JP2003179530A - Receiver device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver device capable of setting the signal power of an added intermediate frequency signal to a maximum immediately after a power supply is turned on, when a plurality of receiving systems 1-3 are provided, and the receiving systems 1-3 comprise PLL circuits 19, 25, 31. <P>SOLUTION: There are provided an adder 4 for output intermediate frequency signals from the receiving systems 1-3, a demodulator 5 for the added intermediate frequency signal, adjustable reference signal generating means 8-11 for supplying a phase-shifted reference signal to the PLL circuits 19, 25, 31 of the receiving systems 1-3, and a plurality of switches 12-14. Respective switching-on times of the switches 12-14 are controlled so that split reference signals in respective PLL circuits 19, 25, 31 are in-phase, and the adjustable reference signal generating means 8-11 are set upon the turning-on of the power supply to a stored phase-shift adjusted state immediately before the turning-off of the power supply. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving device, and more particularly, to an electric field by receiving the same radio signal in each of a plurality of receiving systems and synthesizing the received output signals of the plurality of receiving systems in the same phase. The present invention relates to a receiving device that can receive a wireless signal whose intensity constantly fluctuates in a good state.

[0002]

2. Description of the Related Art Generally, a receiving device that receives a wireless signal under a condition where the radio field strength of the wireless signal constantly changes, such as a vehicle-mounted receiving device, has a plurality of receiving systems such as a diversity receiver. Used by the receiving device having. In this type of receiving apparatus, each receiving system has an antenna, a high frequency amplifier for amplifying the received high frequency signal, a frequency mixer for frequency mixing the high frequency signal and the local oscillation signal, and an output frequency mixing signal of the frequency mixer. A plurality of receiving systems each having an intermediate frequency circuit for extracting an intermediate frequency signal from among the receiving systems are connected in parallel, and an adder for adding the intermediate frequency signals output from the plurality of receiving systems. , A demodulator that demodulates the added intermediate frequency signal, a common local oscillator that supplies a local oscillation signal to each frequency mixer, and a connection between each frequency mixer and a common local oscillator. And a plurality of phase shifters for individually shifting the phase of the local oscillation signal supplied to the mixer.

FIG. 5 is a block diagram showing an example of the main configuration of a receiving apparatus having a plurality of known reception systems, and shows an example in which the plurality of reception systems is three systems.

As shown in FIG. 5, this receiving device is
First receiving system 50, second receiving system 51, third receiving system 52, adder (ADD) 53, demodulator (DET)
54, a demodulation signal output terminal 55, a local oscillator 56,
It is provided with three phase shifters 57, 58 and 59. In this case, the first reception system 50 includes the antenna 60, the high frequency amplifier 61, the frequency mixer 62, and the intermediate frequency filter (F
IL) 63, and the second reception system 52 includes the antenna 6
4, a high frequency amplifier 65, a frequency mixer 66, and an intermediate frequency filter (FIL) 67.
2 has an antenna 68, a high frequency amplifier 69, a frequency mixer 70, and an intermediate frequency filter (FIL) 71. The three antennas 60, 64, 68 are arranged at relatively distant locations.

In the first receiving system 50, the high frequency amplifier 61 has an input end connected to the antenna 60 and an output end connected to the first input end of the frequency mixer 62. The frequency mixer 62 has a second input end connected to the output end of the phase shifter 57 and an output end connected to the input end of the intermediate frequency filter 63. The output terminal of the intermediate frequency filter 63 is the adder 5
3 is connected to the first input terminal. In the second reception system 51, the high frequency amplifier 65 has an input end connected to the antenna 64 and an output end connected to the first input end of the frequency mixer 66. The frequency mixer 66 has a second input end connected to the output end of the phase shifter 58 and an output end connected to the input end of the intermediate frequency filter 67. The output terminal of the intermediate frequency filter 67 is connected to the second input terminal of the adder 53. Third receiving system 5
2, the high frequency amplifier 69 has an antenna 6 at the input end.
8 and the output end is connected to the first input end of the frequency mixer 70. The frequency mixer 70 has a second input end connected to the output end of the phase shifter 59, and an output end connected to the input end of the intermediate frequency filter 71. The intermediate frequency filter 71 is
The output terminal is connected to the third input terminal of the adder 53.

The output end of the adder 53 is a demodulator 54.
Of the demodulator 54, and the output end of the demodulator 54 is connected to the demodulation signal output terminal 55. Phase shifters 57, 58, 59
Has their respective inputs connected to the outputs of the local oscillator 56. Further, the phase shifters 57, 58 and 59 each have a control input end coupled to a control output end of the demodulator 54.

A receiving device having a plurality of receiving systems having the above-described structure operates generally as follows.

When the same radio signals are received by the three antennas 60, 64 and 68, the received signals are amplified by the high frequency amplifiers 61, 65 and 69 and supplied to the frequency mixers 62, 66 and 70. To be done. Frequency mixer 62,
66 and 70 frequency-mix this received signal and the local oscillation signal supplied from the local oscillator 56 through the phase shifters 57, 58 and 59, and respectively generate frequency mixing signals.
The intermediate frequency filters 63, 67, 71 include the frequency mixer 6
The intermediate frequency signal is selected from the frequency mixed signals output from the circuits 2, 66 and 70, and the selected intermediate frequency signal is added to the adder 53.
Supply to. The adder 53 adds and synthesizes the three supplied intermediate frequency signals in the in-phase state to form an added intermediate frequency signal, and the added intermediate frequency signal is demodulated by the demodulator 54.
Supply to. The demodulator 54 demodulates the added intermediate frequency signal and supplies the demodulated signal to a utilization circuit (not shown) through the demodulated signal output terminal 55.

At this time, the demodulator 54 individually adjusts the amount of phase shift of each of the phase shifters 57, 58 and 59, whereby the phase of the local oscillation signal output from the phase shifters 57, 58 and 59 is adjusted. Is adjusted so that the signal power of the added intermediate frequency signal to be supplied is maximized, that is, the phases of the intermediate frequency signals added and synthesized by the adder 53 are the same. By performing such adjustment, the signal power of the addition intermediate frequency signal becomes maximum, and the radio signal can be received in a good state.

[0010]

The above-mentioned known receiver having a plurality of receiving systems can realize a relatively good reception state when applied to a vehicle, but it is not applicable to a mobile phone system or a ground. When it is applied to a system having a large number of channels such as a wave television broadcast, the frequency range of the local oscillation signal becomes considerably wide so that the local oscillator 56 can support a large number of channels, and the phase shifter 5
Since 7, 58 and 59 also need to obtain the required amount of phase shift over such a wide frequency change range, the manufacturing costs of the local oscillator 56 and the phase shifters 57, 58 and 59 increase.

Further, in this type of receiving apparatus, the wiring from the local oscillator 56 to the frequency mixers 62, 66 and 70 through the phase shifters 57, 58 and 59 is made as short as possible at the time of manufacturing the receiving apparatus. However, the frequency of the local oscillation signal is high, and the phase shifters 57, 5
8 and 59 are inserted and connected, the phase shifters 57 and 58,
It becomes impossible to ignore the signal loss due to the insertion and connection of 59, and as a result, the carrier-to-noise ratio (C /
N) becomes deteriorated.

A receiving apparatus designed to solve such a problem has already been proposed by the same applicant as the present applicant.

FIG. 6 is a block diagram showing an example of the main configuration of the receiving apparatus according to the above-mentioned proposal, in which a plurality of receiving systems are provided.
An example of a system is shown.

As shown in FIG. 6, this receiving device is
First reception system 72, second reception system 73, third reception system 74, adder (ADD) 75, demodulator (DET)
76, a demodulation signal output terminal 77, and a reference signal oscillator 78.
And three phase shifters 79, 80, 81. In this case, the first reception system 72 includes an antenna 82, a high frequency amplifier 83, a frequency mixer 84, and a local oscillator 85.
And a PLL circuit (PLL) 86 and an intermediate frequency filter (FIL) 87, and the second reception system 73 includes an antenna 88, a high frequency amplifier 89, a frequency mixer 90,
The third receiving system 7 includes a local oscillator 91, a PLL circuit (PLL) 92, and an intermediate frequency filter (FIL) 93.
Reference numeral 4 denotes an antenna 94, a high frequency amplifier 95, a frequency mixer 96, a local oscillator 97, and a PLL circuit (PLL).
98 and an intermediate frequency filter (FIL) 99.

In the first reception system 72, the high frequency amplifier 83 has an input end connected to the antenna 82 and an output end connected to the first input end of the frequency mixer 84. The frequency mixer 84 has a second input end connected to the output end of the local oscillator 85 and an output end connected to the input end of the intermediate frequency filter 87. The input end of the local oscillator 85 is connected to the output end of the PLL circuit 86, and the output end is connected to the input end of the PLL circuit 86. The PLL circuit 86 has a control input terminal connected to the output terminal of the phase shifter 79, and has an intermediate frequency filter 87.
Has an output end connected to a first input end of the adder 75.

In the second receiving system 73, the high frequency amplifier 89 has an input end connected to the antenna 88 and an output end connected to the first input end of the frequency mixer 90. The frequency mixer 90 has a second input end connected to the output end of the local oscillator 91 and an output end connected to the input end of the intermediate frequency filter 93. The local oscillator 91 has an input end connected to the output end of the PLL circuit 92 and an output end connected to the input end of the PLL circuit 92. In the PLL circuit 92, the control input terminal is the phase shifter 80.
The output terminal of the intermediate frequency filter 93 is connected to the second input terminal of the adder 75.

In the third reception system 74, the high frequency amplifier 95 has an input end connected to the antenna 94 and an output end connected to the first input end of the frequency mixer 96. The frequency mixer 96 has a second input end connected to the output end of the local oscillator 97 and an output end connected to the input end of the intermediate frequency filter 99. The input end of the local oscillator 97 is connected to the output end of the PLL circuit 98, and the output end is connected to the input end of the PLL circuit 98. In the PLL circuit 98, the control input terminal is the phase shifter 81.
Of the intermediate frequency filter 99, the output end of the intermediate frequency filter 99 is connected to the third input end of the adder 75.

The output terminal of the adder 75 is a demodulator 76.
Of the demodulator 76, and the output end of the demodulator 76 is connected to the demodulation signal output terminal 77. Phase shifters 79, 80, 81
Has an input end connected to the output end of the reference signal oscillator 78. The phase shifters 79, 80, 81 each have a control input coupled to a control output of the demodulator 76.

The receiving device according to the above-mentioned proposal generally operates as follows.

When the same radio signal is received by the three antennas 82, 88 and 94, the received signals are amplified by the high frequency amplifiers 83, 89 and 95, respectively, and supplied to the frequency mixers 84, 90 and 96. To be done. Frequency mixer 84,
Reference numerals 90 and 96 denote received signals and local oscillators 85, 91 and 97.
A frequency mixed signal is generated by mixing the frequency of the local oscillation signal supplied from the device. At this time, the PLL circuit 8
Reference numerals 6, 92 and 98 denote local oscillation signals generated by the local oscillators 85, 91 and 97 from the reference signal oscillator 78 to the phase shifter 7.
Phase control is performed by the reference signal supplied through the reference numerals 9, 80, 81, and the local oscillators 85, 9
The frequencies of the local oscillation signals of 1, 97 are set. The intermediate frequency filters 87, 93, 99 include frequency mixers 84, 9
The intermediate frequency signal is selected from the frequency mixed signals output by 0 and 96, and the selected intermediate frequency signal is supplied to the adder 75. The adder 75 adds and synthesizes the three supplied intermediate frequency signals in the in-phase state to form an added intermediate frequency signal, and supplies the added intermediate frequency signal to the demodulator 76. Demodulator 76
Demodulates the added intermediate frequency signal and supplies the demodulated signal to a utilization circuit (not shown) through the demodulated signal output terminal 77.

Also at this time, the demodulator 76 individually adjusts the amount of phase shift of each of the phase shifters 79, 80, 81, and thereby the reference signals output from the phase shifters 79, 80, 81 are adjusted. While changing the phase, the local oscillator 8
5, 91, and 97 so as to change the phase of the local oscillation signal so that the signal power of the addition intermediate frequency signal supplied to the adder 75 becomes maximum, that is, each intermediate added and synthesized by the adder 75. Adjust so that the phases of the frequency signals are the same. By performing such adjustment, the signal power of the added intermediate frequency signal becomes maximum, and the radio signal can be received in a good state. Further, since the signal to be phase-shifted by the phase shifters 79, 80, 81 is a reference signal whose frequency is considerably lower than that of the local oscillation signal, the manufacturing cost of the phase shifters 79, 80, 81 may increase. Without the phase shifters 79, 80,
The signal loss due to the insertion and connection of 81 can be ignored.

By the way, the receiving device according to the above-mentioned proposal can solve various problems in the conventional receiving device of this type, but the first to third receiving systems 7 are used.
2, 73 and 74 have PLL circuits 86, 92 and 98, respectively.
Therefore, the operation of the PLL circuits 86, 92, 98 for setting the oscillation frequencies of the local oscillators 85, 91, 97 is not stabilized immediately after the power is turned on, and the local oscillators 85, 91, 97 are not stabilized. Since the phase state of the local oscillation signal is not fixed, the signal power of the added intermediate frequency signal is not maximized. Then, in order to maximize the signal power of the added intermediate frequency signal, it is necessary to optimally adjust the phase shift amount of the reference signal for each of the first to third reception systems 72, 73, 74, and the power is turned on. During the later period in which such optimum adjustment is performed, the signal cannot be received properly.

The present invention has been made in view of the above technical background, and an object thereof is to have a plurality of receiving systems,
When each of the plurality of receiving systems has a PLL circuit,
It is an object of the present invention to provide a receiving device that can be set immediately after the power is turned on to maximize the signal power of the added intermediate frequency signal.

[0024]

In order to achieve the above-mentioned object, the present invention provides an antenna, a frequency mixer for frequency-converting a received signal received by the antenna, and a local oscillator signal for the frequency mixer. A plurality of receiving systems having a local oscillator for supplying a plurality of signals, a PLL circuit for setting an oscillation frequency of the local oscillator, an intermediate frequency circuit for selecting an intermediate frequency signal from an output frequency mixing signal of a frequency mixer, and an output signal of the plurality of receiving systems , An adder that adds the output signals of the adder, a reproduction processing unit that reproduces the added signal output from the adder, an adjustable reference signal generating unit that supplies the phase-shifted reference signals to the PLL circuits of the plurality of receiving systems, and the PLL circuits. And a plurality of switches respectively connected between the adjustable reference signal generating means and the adjustable reference signal generating means.
The switch-on times are controlled so that the reference signals divided by the circuits have the same phase, and the adjustable reference signal generating means uses the respective PLL circuits so that the output signals of the plurality of receiving systems have the same phase during the steady operation. Means for adjusting the phase of each of the reference signals supplied to each of the power supplies and setting the stored phase shift adjustment state immediately before the power is turned off when the power is turned on.

According to the above means, when the power of the receiving device is turned off, the phase shift adjustment state in the adjustable reference signal generating means immediately before the power is turned off is stored, and when the power of the receiving device is turned on, In each of the plurality of switches, each switch ON time is controlled so that the reference signals divided by each PLL circuit are set to have the same phase. In the adjustable reference signal generating means, immediately before the power is turned off. Since the stored phase shift adjustment state is set, it is not necessary to optimally adjust the phase shift amount of the reference signal for each of a plurality of reception systems in order to maximize the signal power of the added intermediate frequency signal, and the power supply Immediately after it is turned on, the receiving device can perform regular signal reception.

In this case, the adjustable reference signal generating means in the means comprises a reference signal oscillator common to a plurality of receiving systems for generating a reference signal, and a plurality of phase shifters for individually shifting the reference signals. Can be configured.

With such a structure, the structure of the adjustable reference signal generating means can be simplified and the signal loss due to the provision of a plurality of phase shifters can be reduced.

Further, the adjustable reference signal generating means in the above means may be constituted by a plurality of digital synthesizers for generating reference signals which are individually phase-shifted by supplying phase data.

With such a configuration, the phase and frequency of the reference signal can be digitally controlled, so that not only the configuration of the adjustable reference signal generating means is simplified but also the control processing is simplified. Can be achieved.

Further, the reproduction processing means in the above means is configured to control the switch-on time of each of the plurality of switches on the basis of the phase comparison signal supplied from each PLL circuit when the power is turned on. .

With such a configuration, the reproduction processing means supplies the phase comparison signals obtained by the respective PLL circuits and compares the phase states of the supplied phase comparison signals, so that the plurality of switches respectively. Since the switch-on time of is determined, the required switch-on time can be controlled without complicating the configuration of this type of control system.

The reproduction processing means in the above means is
A memory for storing the phase shift adjustment state in the adjustable reference signal generating means immediately before the power is turned off is connected, and the phase shift adjustment state in the adjustable reference signal generating means stored in the memory when the power is turned on is read. The configuration is such that the adjustable reference signal generating means is set in the read phase shift adjustment state.

With such a configuration, the reproduction processing means stores the phase shift adjustment state in the adjustable reference signal generating means immediately before the power is turned off in the memory, and the memory is stored when the power is turned on. It becomes easy to set the adjustable reference signal generation means to the phase shift adjustment state by using the phase shift adjustment state in the adjustable reference signal generation means stored in It is possible to accurately reproduce the phase shift adjustment state in the reference signal generating means.

In this case, it is preferable that the reproduction processing means in the above means is configured to update and store the phase shift adjustment state in the adjustable reference signal generating means in the memory every time a fixed time elapses during the steady operation.

With such a configuration, since the memory contents of the memory are updated at regular time intervals, it is possible to select a memory having a small memory capacity as the memory to be used.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a receiving apparatus according to the present invention, and is a block diagram showing a main configuration of a receiving apparatus having a plurality of receiving systems. An example is shown.

As shown in FIG. 1, the receiving apparatus according to this embodiment has a first receiving system 1 and a second receiving system 2.
, Third receiving system 3, adder (ADD) 4, reproduction processing unit (DET) 5, memory 6, and demodulation signal output terminal 7
, Reference signal oscillator 8 and three phase shifters 9, 10, 11
And three one-circuit two-contact switches 12, 13, and 14. In this case, the first reception system 1 includes the antenna 1
5, a high frequency amplifier 16, a frequency mixer 17, a local oscillator 18, a PLL circuit (PLL) 19, and an intermediate frequency filter (FIL) 20, and the second receiving system 2
Antenna 21, high frequency amplifier 22, and frequency mixer 2
3, a local oscillator 24, and a PLL circuit (PLL) 25
And an intermediate frequency filter (FIL) 26, the third reception system 3 includes an antenna 27, a high frequency amplifier 28, a frequency mixer 29, a local oscillator 30, and a PLL circuit (P
LL) 31 and an intermediate frequency filter (FIL) 32.

In the first receiving system 1, the high frequency amplifier 16 has an input end connected to the antenna 15 and an output end connected to the first input end of the frequency mixer 17. The frequency mixer 17 has a second input end connected to the output end of the local oscillator 18 and an output end connected to the input end of the intermediate frequency filter 20. The input terminal of the local oscillator 18 is the PLL circuit 1
9 is connected to the output end, and the output end is connected to the input end of the PLL circuit 19. The PLL circuit 19 has a control input end connected to the movable contact of the switch 12, and a divided signal output end connected to the first control end of the demodulator 5. Intermediate frequency filter 20
Has an output connected to the first input of the adder 4.

In the second receiving system 2, the high frequency amplifier 2
The input end of 2 is connected to the antenna 21, and the output end is connected to the first input end of the frequency mixer 23. The frequency mixer 23 has a second input end connected to the output end of the local oscillator 24 and an output end connected to the input end of the intermediate frequency filter 26. The input end of the local oscillator 24 is connected to the output end of the PLL circuit 25, and the output end is connected to the input end of the PLL circuit 25. The PLL circuit 25 has a switch 13 at the control input end.
Of the demodulator 5 and the divided signal output end is connected to the second control end of the demodulator 5. The output terminal of the intermediate frequency filter 26 is connected to the second input terminal of the adder 4.

In the third receiving system 3, the high frequency amplifier 2
8, the input end is connected to the antenna 27, and the output end is connected to the first input end of the frequency mixer 29. The frequency mixer 29 has a second input end connected to the output end of the local oscillator 30 and an output end connected to the input end of the intermediate frequency filter 32. The local oscillator 30 has an input end connected to the output end of the PLL circuit 31, and an output end connected to the input end of the PLL circuit 31. In the PLL circuit 31, the control input terminal is the switch 14
Of the demodulator 5 and the divided signal output end is connected to the movable control contact of the demodulator 5. The output terminal of the intermediate frequency filter 32 is connected to the third input terminal of the adder 4.

The output end of the adder 4 is a reproduction processing unit 5
Connected to the input end of. The reproduction processing unit 5 is connected to the memory 6, and the output end thereof is connected to the demodulation signal output terminal 7. In the switches 12, 13, and 14, one fixed contact is connected to the output ends of the phase shifters 9, 10 and 11, respectively, and the other fixed contact is grounded. Phase shifters 9, 10, 11
Has an input terminal connected to the output terminal of the reference signal oscillator 8 and a control input terminal coupled to the control output terminal of the reproduction processing unit 5, respectively.

Next, FIG. 2 is a block diagram showing the internal structure of each of the PLL circuits 19, 25 and 31 used in the receiver shown in FIG.

The PLL circuits 19, 25 and 31 are
Since both have the same configuration and perform the same operation, in the following description, only the configuration and operation of the PLL circuit 19 will be described, and the configuration and operation of the other PLL circuits 25 and 31 will be described. Omit it.

As shown in FIG. 2, the PLL circuit 19
Is a local oscillation signal frequency divider (RF DIV) 33, a phase comparator (P.COM) 34, and a reference signal frequency divider (REF).
DIV) 35, charge pump (CP) 36,
A control signal driver (DR) 37, a local oscillation signal input terminal 38, a reference signal input terminal 39, a phase comparison signal output terminal 40, and a control signal output terminal 41 are provided.

The local oscillation signal frequency divider 33 has an input terminal connected to the local oscillation signal input terminal 38 and an output terminal connected to the first input terminal of the phase comparator 34. Phase comparator 3
4, the second input terminal is connected to the output terminal of the reference signal frequency divider 35, and the output terminal is connected to the input terminal of the charge pump 36. The reference signal frequency divider 35 has an input end connected to the reference signal input terminal 39 and an output end connected to the phase comparison signal output terminal 40. The output end of the charge pump 36 is connected to the input end of the control signal driver 36, and the control signal driver 37
Has an output end connected to the control signal output terminal 41. The local oscillation signal input terminal 38 is connected to the output terminal of the local oscillator 18, and the reference signal input terminal 39 is connected to the switch 1
2 movable contacts. Phase comparison signal output terminal 40
Is connected to the first control end of the reproduction processing unit 5, and the control signal output terminal 41 is connected to the control end of the local oscillator 18.

In this case, the reference signal frequency divider 35 frequency-divides the local oscillation signal supplied from the local oscillator 18 via the local oscillation signal input terminal 38 and supplies the frequency-divided local oscillation signal to the phase comparator 34. . The reference signal frequency divider 35 frequency-divides the reference signal supplied from the reference signal oscillator 8 through the phase shifter 9 and the switch 12 and the reference signal input terminal 39, and outputs the frequency-divided reference signal to the phase comparator 34. Supply. Phase comparator 34
Respectively compares the frequency-divided local oscillation signal and the frequency-divided reference signal, which are respectively supplied, to detect a phase difference signal between them, and supplies the detected phase difference signal to the charge pump 36. The charge pump 36 converts the supplied phase difference signal into an electric charge amount, generates a control signal having a voltage value corresponding to the electric charge amount, and outputs the obtained control signal to the control signal driver 3
Supply to 7. The control signal driver 37 supplies the supplied control signal to the local oscillator 18 through the control signal output terminal 41, and controls the phase of the local oscillation signal oscillated by the local oscillator 18. The frequency division reference signal output from the reference signal frequency divider 35 is partially converted into a phase comparison signal through the phase comparison signal output terminal 40, as will be described later.
Is supplied to.

Next, FIG. 3 shows each PLL circuit 19 in the receiving device shown in FIG. 1 when the receiving device is powered on.
It is a signal waveform diagram which shows an example of the state of the phase comparison signal supplied to the reproduction | regeneration process part 5 from 25,31.

Further, FIG. 4 shows that in the receiving apparatus shown in FIG. 1, the switches 12, 1 are turned on when the receiving apparatus is powered on.
It is a signal waveform diagram which shows an example of the state of the reference signal supplied to each PLL circuit 19,25,31 when controlling the switch-on time of 3,14.

In FIGS. 3 and 4, the horizontal axis represents time, the vertical axis represents signal amplitude, and the upper signal waveform is PLL.
Signal waveforms related to the circuit 19 and signal waveforms in the middle stage are PLL
The signal waveforms related to the circuit 25 and the lower signal waveform are PLL.
3 is a signal waveform related to the circuit 31.

The operation of the receiving apparatus according to this embodiment having the above configuration will be described with reference to the block diagrams shown in FIGS. 1 and 2 and the signal waveform diagrams shown in FIGS. 3 and 4.

First, the operation when the receiving apparatus is in the steady operation state will be described. In this steady operation state, the movable contacts of the switches 12, 13, 14 are switched to one fixed contact side (non-grounded connection side), and each switch 1
2, 13, and 14 are turned on.

Now, when the same radio signal is received by the three antennas 15, 21, and 27, the received signals are amplified by the high-frequency amplifiers 16, 22, and 28, respectively, and the frequency mixers 17, 23, and 29. Is supplied to. At this time, the frequency mixer 17 frequency-mixes the reception signal supplied from the high-frequency amplifier 16 and the local oscillation signal supplied from the local oscillator 18, and generates these frequency mixing signals.
Further, the frequency mixer 23 frequency-mixes the received signal supplied from the high-frequency amplifier 22 and the local oscillation signal supplied from the local oscillator 24, and generates these frequency-mixed signals. Similarly, the frequency mixer 29 frequency-mixes the reception signal supplied from the high-frequency amplifier 28 and the local oscillation signal supplied from the local oscillator 30, and generates these frequency mixing signals. Intermediate frequency filters 20, 26,
The reference numeral 32 selects an intermediate frequency signal from the frequency mixed signals output by the frequency mixers 17, 23 and 29, and supplies the selected intermediate frequency signal to the adder 4. Adder 4
Supplies the three intermediate frequency signals supplied thereto in the in-phase state to form an added intermediate frequency signal, and supplies the added intermediate frequency signal to the reproduction processing section 5. The reproduction processing unit 5 demodulates the added intermediate frequency signal and supplies the demodulated signal to a utilization circuit (not shown) through the demodulated signal output terminal 7.

At this time, the reproduction processing section 5 includes the phase shifters 9 to which the reference signal from the reference signal oscillator 8 is supplied,
The phase shift amounts of 10, 11 are individually adjusted, and the phase shifters 9, 10,
The phase of the reference signal output from 11 is changed to change the phase of the reference signal supplied to the corresponding PLL circuit 19, 25, 31, and the PLL circuit 19, 25, 31 is changed.
By changing the phase of the local oscillation signals of the local oscillators 18, 24, 30 whose phases are controlled by, the signal power of the addition intermediate frequency signal is maximized, that is, each intermediate frequency added and synthesized by the adder 4 Adjust so that the signal phases are the same. By performing such adjustment in the reproduction processing unit 5, the signal power of the added intermediate frequency signal is maximized, and the radio signal can be received in a good state.

In this case, when the receiving device is in such a steady operation state, the reproduction processing section 5 sets the phase shift adjustment state set in the phase shifters 9, 10 and 11 at regular time intervals, for example, every second. Are stored in the memory 6 connected to the demodulator 5, and the stored contents in the memory 6 are updated by storing the next phase shift adjustment state. For this reason,
In the memory 6, the latest phase shift adjustment states of the phase shifters 9, 10, 11 are stored. Therefore, when the use of the receiving device is finished and the power is turned off, the phase shift adjustment state of the phase shifters 9, 10, 11 immediately before the power is turned off is stored in the memory 6.
Memorized in.

Next, in order to reuse the receiving device when the receiving device is powered off, the operation state when the power is turned on when the power is turned on will be described. In the operation state when the power is turned on, initially, the movable contacts of the switches 12, 13, 14 are switched to one fixed contact side (non-grounded connection side), and the switches 12, 13, 14 are turned on. ing.

Immediately after the power of the receiving device is turned on, the reproduction processing section 5 supplies a reset signal to each of the phase shifters 9, 10 and 11 to set them in each of the phase shifters 9, 10 and 11. Reset the phase shift adjustment status. After that, when the reference signal oscillator 8 starts to generate the reference signal, the reference signal is reset through the phase shifters 9, 10, 11 and the switches 12, 13, 14 which are in the ON state. It is supplied to the PLL circuits 19, 25 and 31. The PLL circuit 19 divides the supplied reference signal by the reference signal divider 35, and the obtained divided reference signal is output to the phase comparison signal output terminal 4
The first phase comparison signal from 0 is supplied to the first control end of the reproduction processing section 5. The other PLL circuits 25 and 31 operate in the same manner as the PLL circuit 19, and the second phase comparison signal is supplied to the second control end of the demodulator 5 and the third phase comparison signal is supplied to the third control end of the reproduction processing unit 5, respectively. Supply to.

At this time, the reproduction processing section 5 performs phase comparison of the supplied first to third phase comparison signals, and the phase comparison signal having the most delayed phase among the first to third phase comparison signals, For example, the first phase comparison signal shown in the upper part of FIG. 3 is used as a reference phase comparison signal, and the phase delay (phase difference) of the second phase comparison signal with respect to this reference phase comparison signal, for example, the phase difference shown in the middle part of FIG. TB or a phase delay (phase difference) of the third phase comparison signal with respect to the reference phase comparison signal, for example, the phase difference TC shown in the lower part of FIG. 3 is obtained.

When the reproduction processing section 5 obtains the phase difference TB of the second phase comparison signal and the phase difference TC of the third phase comparison signal,
By supplying different switch control signals to the switches 12, 13 and 14, and keeping the switch 12 in the ON state, the movable contact of the switch 13 is connected to the other fixed contact side (ground connection) for a time corresponding to the phase difference TB. Side) and switch 1
3 is turned off, and similarly, the switch 14 is set to the phase difference TC.
The movable contact is switched to the other fixed contact side (ground connection side) only for a time corresponding to, and the switch 14 is turned off. At this time, the reference signal supplied to the PLL circuit 19 is supplied in the state of the reference signal having no discontinuity as shown in the upper part of FIG. 4, and the reference signal supplied to the PLL circuit 25 is the reference signal of FIG. As shown in the middle row, it is supplied with the signal stop portion for the time corresponding to the phase difference TB,
The reference signal supplied to the PLL circuit 31 is supplied with a signal stop portion for a time corresponding to the phase difference TC as shown in the lower part of FIG. Such a switch 1
When the on / off state of 2, 13, 14 is switched, each P
The first output from each of the LL circuits 19, 25 and 31
Therefore, the third phase comparison signal becomes in-phase.

Next, the reproduction processing section 5 causes the phase shifters 9, 10, which are stored in the memory 6 just before the power is turned off,
The phase shift adjustment state of 11 is read out, and each phase shifter 9, 10, 1
Each of the 1 is set to the same adjustment state as the corresponding read phase shift adjustment state. And each phase shifter 9,
When the setting state of 10 and 11 is set as described above, the operating state when the power is turned on ends, and subsequently, the above-mentioned steady operating state is entered.

As described above, according to the receiving apparatus of this embodiment, when the power is turned off, the phase shift adjustment state in each phase shifter 9, 10, 11 immediately before the power is turned off is stored, When the power is turned on, each switch 12, 1
Each PLL is controlled by controlling the switch-on time in 3 and 14
The reference signals (phase comparison signals) divided by the circuits 19, 25, 31 are set to have the same phase, and the phase shifters 9, 10,
In No. 11, the stored phase shift adjustment state immediately before the power is turned off is set. It is not necessary to perform the optimum adjustment of the phase shift amount, and the receiving apparatus can perform regular signal reception immediately after the power is turned on.

In the receiving device according to the above-mentioned embodiment, an example in which a common reference signal oscillator 8 and a plurality (three) of phase shifters 9, 10, 11 are used as the adjustable reference signal generating means. As described above, in the receiving device according to the present invention, the reference signal oscillator 8 having the common adjustable reference signal generating means is used.
The reference signal is not limited to the example in which a plurality of (three) phase shifters 9 and 10 are used, and the reference signal individually shifted by another means, for example, the phase data supplied from the reproduction processing unit 5. A plurality of (three) digital synthesizers that generate

Each of the three digital synthesizers used in this case is a ROM in which data of one cycle of a sine wave is discretized and stored together with its amplitude and phase.
A clock signal and frequency data are commonly input, and sine wave data of the same frequency synchronized with the clock signal is generated from each ROM. In addition to this, digital phase data is individually input to the three digital synthesizers, and the phase of the sine wave data output based on these phase data is set. Three
The respective sine wave data output from the three digital synthesizers are individually converted into analog sine wave signals by the three analog-digital converters, and then unnecessary signal components are individually removed by the three band pass filters. It is supplied to the corresponding PLL circuits 19, 25 and 31 as three reference signals which are individually phase-shifted. When such a digital synthesizer is used, the control process is simplified.

In the receiving apparatus according to the above-described embodiment, an example in which the receiving system has three systems 1 to 3 has been described. However, the receiving device according to the present invention has three receiving systems. It is not limited, and even if it is 2 systems, 4
It may be systematic or more.

Further, in the receiver according to the above-mentioned embodiment, the phase shifters 9, 10, 1 stored in the memory 6 are stored.
Although the phase shift adjustment state in 1 has been described by taking an example in which the phase shift adjustment state is obtained at regular time intervals, the receiving device according to the present invention is
The phase shift adjustment state in each of the phase shifters 9, 10 and 11 stored in the memory 6 is not limited to that obtained at regular time intervals,
It may be obtained at any time, for example, obtained when the phase shift adjustment state changes, or may be obtained continuously if the memory 6 has a sufficient storage capacity.

Further, in the receiving apparatus according to the above-described embodiment, the example in which the memory 6 is an independent memory connected to the demodulator 5 has been described, but in the receiving apparatus according to the present invention, the memory 6 is independent. The memory is not limited to the example, and may be a built-in memory of the demodulator 5.

[0067]

As described above, according to the invention described in claim 1, when the power of the receiving device is turned off, the phase shift adjustment state in the adjustable reference signal generating means immediately before the power is turned off is stored. When the power of the receiving device is turned on, the switch-on time of each of the plurality of switches is controlled so that the reference signals divided by the PLL circuits are set to have the same phase, and the adjustable reference signal is set. Since the generator is set to the stored phase shift adjustment state immediately before the power is turned off, in order to maximize the signal power of the added intermediate frequency signal, the phase shift of the reference signal is performed for each of a plurality of reception systems. There is no need to perform optimum adjustment of the amount, and there is an effect that the receiving device can perform regular signal reception immediately after the power is turned on.

According to the second aspect of the invention, the structure of the adjustable reference signal generating means can be simplified.
There is an effect that the signal loss due to the provision of the plurality of phase shifters can be reduced.

Further, according to the invention described in claim 3,
Since the phase and frequency of the reference signal can be digitally controlled, there is an effect that not only the configuration of the adjustable reference signal generating means can be simplified but also the control processing can be simplified.

According to the fourth aspect of the invention, the demodulator supplies the phase comparison signals obtained by the respective PLL circuits and compares the phase states of the supplied phase comparison signals to obtain a plurality of phase comparison signals. Since the switch-on time of each of the switches is determined, it is possible to control the required switch-on time without complicating the configuration of this type of control system.

Further, according to the invention of claim 5,
The demodulator stores the phase shift adjustment state in the adjustable reference signal generating means immediately before the power is turned off in the memory,
It becomes easy to set the adjustable reference signal generation means to the phase shift adjustment state by using the phase shift adjustment state in the adjustable reference signal generation means stored in the memory when the power is turned on. There is an effect that it is possible to accurately reproduce the phase shift adjustment state in the adjustable reference signal generating means immediately before the switch is turned off.

In this case, according to the sixth aspect of the invention, since the stored contents of the memory are updated at regular time intervals,
As a memory to be used, it is possible to select a memory having a small storage capacity.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a receiving device according to the present invention and showing a main configuration of a receiving device having a plurality of receiving systems.

2 is each PL used in the receiving apparatus shown in FIG.
It is a block diagram showing an internal configuration of an L circuit.

3 is a signal waveform diagram showing an example of a state of a phase comparison signal supplied from each PLL circuit to a demodulator when the power of the receiving device shown in FIG. 1 is turned on.

4 is a signal waveform diagram showing an example of a state of a reference signal supplied to each PLL circuit when the switch-on time of each switch is controlled when the receiver is powered on in the receiver illustrated in FIG. 1. FIG. .

FIG. 5 is a block diagram showing an example of a main configuration of a receiving device having a plurality of known receiving systems.

[Fig. 6] Fig. 6 is a block diagram illustrating an example of a main configuration of a receiving device already proposed.

[Explanation of symbols]

1st receiving system 2 Second receiving system 3 Third receiving system 4 Adder (ADD) 5 Playback processing unit (DET) 6 memory 7 Demodulation signal output terminal 8 Reference signal oscillator 9,10,11 Phase shifter 12, 13, 14 switch 15, 21, 27 antennas 16, 22, 28 High frequency amplifier 17,23,29 frequency mixer 18, 24, 30 Local oscillator 19, 25, 31 PLL circuit (PLL) 20, 26, 32 Intermediate frequency filter (FIL) 33 Local oscillator signal frequency divider (RF DIV) 34 Phase Comparator (P.COM) 35 Reference Signal Divider (REF DIV) 36 Charge pump (CP) 37 Control signal driver (DR) 38 Local oscillation signal input terminal 39 Reference signal input terminal 40 Phase comparison signal output terminal 41 Control signal output terminal

Claims (6)

[Claims] 1. Each receiving system sets an antenna, a frequency mixer that frequency-converts a received signal received by the antenna, a local oscillator that supplies a local oscillation signal to the frequency mixer, and an oscillation frequency of the local oscillator. PLL
Circuit, a plurality of receiving systems having an intermediate frequency circuit for selecting an intermediate frequency signal from the output frequency mixed signals of the frequency mixer, an adder for adding the output signals of the plurality of receiving systems, and an output addition of the adder A reproduction processing means for reproducing a signal; an adjustable reference signal generating means for supplying a reference signal having a phase shifted to each PLL circuit of the plurality of receiving systems; and each of the PLL circuits and the adjustable reference signal generating means. A plurality of switches respectively connected between the plurality of switches, each of the plurality of switches has a switch-on time controlled so that a reference signal divided by each of the PLL circuits has the same phase when a power source is turned on. The adjustable reference signal generating means is
The reference signals supplied to the respective PLL circuits are phase-shifted and adjusted so that the output signals of the plurality of reception systems are in phase during steady operation, and the stored shifts immediately before the power supply is turned off are turned on when the power supply is turned on. A receiver set in a phase adjustment state. 2. The adjustable reference signal generating means comprises a reference signal oscillator common to the plurality of receiving systems for generating a reference signal, and a plurality of phase shifters for individually shifting the reference signal. The receiving device according to claim 1, wherein: 3. The receiving apparatus according to claim 1, wherein the adjustable reference signal generating means comprises a plurality of digital synthesizers for generating reference signals which are individually phase-shifted by supplying phase data. 4. The reproduction processing means controls the switch-on time of each of the plurality of switches based on a phase comparison signal supplied from each of the PLL circuits when the power source is turned on. The receiving device according to claim 1. 5. The reproduction processing means is connected to a memory for storing a phase shift adjustment state in the adjustable reference signal generating means immediately before the power supply is turned off, and is stored in the memory when the power supply is turned on. 4. The receiving apparatus according to claim 1, wherein a phase shift adjustment state of the adjustable reference signal generating means is read out, and the adjustable reference signal generating means is set to the read phase shift adjustment state. 6. The reproduction processing means updates and stores the phase shift adjustment state in the adjustable reference signal generating means in the memory every time a fixed time elapses during a steady operation. The receiver described.