JP2003179171A - Method for fabricating floating gate memory array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating a contactless flash EPROM cell. <P>SOLUTION: Extended first and second drain diffusion regions and a source diffusion region are formed on a semiconductor substrate along substantially parallel lines. A field oxide region is created on the side opposite to the first and second drain diffusion regions. Floating gate and control gate word lines (WL<SB>0</SB>through WLN) are formed orthogonally in a drain-source-drain structure and two arrays (13, 15 and 14, 16) of storage cells having a shared source region are set. The source region being shared is coupled with global bit lines (17, 18) by bottom block select transistors (19, 21). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and more particularly to a floating gate.
The present invention relates to a flash EPROM cell using a transistor, an array device, and a manufacturing method thereof.

[0002]

Flash EPROM is a growing field of non-volatile charge storage type semiconductor integrated circuits. These flash EPRQMs have the ability to electrically erase, program and read memory cells within the chip. The memory cells of a flash EPROM are formed using so-called floating gate transistors in which data is stored in the cells by charging or discharging the floating gate. The floating gate is made of a conductive material, typically poly-Si, is insulated from the channel of the transistor by an oxide film or other insulating thin film, and a second insulating film of the transistor. Insulated from control gates or word lines.

The act of charging the floating gate is referred to as the "program" step for flash EPROMs. This step is performed by applying a positive voltage of about 12 volts between the gate and the source and a positive voltage between the drain and the source, for example, 7 volts, which is a so-called hot voltage.・ Made by injection of electrons. The operation to discharge the floating gate is a flash EPROM.
Called the "erase" function. This erase function is typically accomplished by the mechanism of an FN tunnel between the floating gate and the source of the transistor (source erase) or between the floating gate and the semiconductor substrate (channel erase). For example, the source erase action is accomplished by applying a large positive voltage from the source to the gate while floating the drain of each memory cell. This positive voltage can be as high as 12 volts.

For further details regarding the structure and function of conventional flash EPROMs, see U.S. Pat. S. You can know by patent. Mukherjee, et al., US Patent No. 4,698,787 i
ssued October 6, 1987; Holler, et al., US Patent
No. 4,780,423 issued October 25, 1988. More advanced techniques for ICs in flash EPROMs are described in the following references. Woo, et al., "A Novel Memory Cel
l Using Flash Array Contactless EPROM (FACE) Techno
logy ", IEDM 1990, Published by the IEEE, Pages 91-
94 and Woo, et al., "A Poly-Buffered" FACE "Technol
ogy for High Density Memories "1991 SYMPOSIUM ON V
LS1 TECHNOLOGY, page 73-74 Contactless Array E
An example of the prior art PROM device is described below. Kazerounian et al. "Alternate Metal Virtual Gr
sound EPROM Array Implemented In A 0.8 (M Process f
or Very High Density Applications "IEDM, Published
by IEEE 1991, pages 11.5.1-11.5.4.

[0005]

[Patent Document 1] Mukherjee, et al., US Patent No.
4,698,787 issued October6, 1987

[Patent Document 2] Holler, et al., US Patent NO. 4,78
0,423 issued October 25,1988.

[Non-Patent Document 1] Woo, et al., "A Novel Memory Cell
Using Flash Array Contactless EPROM (FACE) Technol
ogy ", IEDM 1990, Published by the IEEE, Pages 91-9
Four

[Non-Patent Document 2] Woo, et al., "A Poly-Buffered" FAC
E "Technology for High Density Memories" 1991 SYMP
OSIUM ON VLS1 TECHNOLOGY, page 73-74

[Non-Patent Document 3] Kazerounian et al. "Alternate Metal
Virtual Ground EPROM Array Implemented In A 0.8
(M Process for Very High Density Applications "IED
M, Published by IEEE 1991, pages 11.5.1-11.5.4

[0006]

[Problems to be Solved by the Invention] Woo et al. And Kaze
There is growing interest in the design of contactless array non-volatile memory, as evidenced by the publication of rounian et al. The so-called contactless array is
It is formed by an array of storage cells coupled together by buried diffusion layers, which are only intermittently coupled to the metal bit lines by contacts. Mukherjee et al.
Early flash EPROM designs, such as those systems, required "half" metal contacts for each memory cell. Because the metal contacts occupy a considerable area in a semiconductor integrated circuit, they are a great obstacle in designing a high density memory. In addition, the device is even smaller,
Attempts to reduce area will be limited by the metal covering the adjacent drain and source bit line contacts used to access the storage cells in the array.

The present invention has been made in view of the above,
The present invention relates to an improvement of a non-volatile memory cell composed of a floating gate transistor, and in particular, to a flash EPROM cell which can be integrated at high density, an array device for the flash EPROM cell, and a manufacturing method thereof. It is intended. Another object is to provide a memory circuit using the improved flash EPROM cell.

[0008]

According to the present invention, a non-volatile memory cell (flash EPROM cell) has a unique drain-source-drain configuration in which one source diffusion layer is shared by two floating gate transistors. Based on, and extending! The second drain diffusion region and the source diffusion region are formed along the semiconductor substrate. Field oxide regions are formed outside the first and second drain diffusion regions. The floating gate and the control gate word line are formed so as to be orthogonal to a drain-source-drain structure formed of two rows of storage cells having a shared source region. The shared source region is coupled to the virtual ground terminal by the block select transistor below. Each drain diffusion region is coupled to the global bit line by an upper block select transistor. The cell structure according to the present invention provides a virtual ground supply coupling multiple column transistors to a virtual ground terminal via horizontal conductors such as drain, source and drain diffusions, and buried diffusion lines. , Using two global bit lines extending substantially in parallel. Thus, for a cell of two transistors, only two metal contact pitches are needed.

According to another aspect of the present invention, these multiple drain-source-so-drain structures form one large IC.
A high-density nonvolatile charge storage type semiconductor integrated circuit is obtained. This non-volatile charge storage type semiconductor integrated circuit can be divided along the block boundary by using the block select transistors in the upper and lower parts, and enables individual erasing action. Also,
The block select feature couples a single block of memory cells to a global bit line at a time. This provides an improvement to leakage current into the transistors along a given row of the array.

Thus, one memory circuit has N
It is provided as K sub-arrays with storage cells of columns, M rows. Each storage cell in the storage cell array has a first terminal, a second terminal and a control terminal. There are multiple word lines coupled to the control terminals of the storage cells corresponding to each row. N global bit lines consisting of bit lines corresponding to each column of storage cells, and a number of each coupled to the first terminal of M storage cells in each column within each sub-array. There are local bit lines. The upper block select transistor selectively connects the local bit line in the sub-array of the storage cell to the corresponding wide area bit line in response to the sub-array select signal. In addition, a number of local virtual ground lines and means for connecting the local virtual ground lines in the sub-array to the local virtual ground terminals are included. Each of the local virtual ground lines is coupled in its respective sub-array to a second evening of storage cells in the column. A column select transistor, coupled to the global bit line, allows selective access to the N columns of storage cells.

In addition to the memory cell and its array arrangement as described above, a method of making an array of floating gate devices is provided. The first method is configured as follows. Defining a plurality of drain diffusion regions extending in the first direction; doping the drain diffusion regions; forming a tunnel insulating film on at least the semiconductor substrate major surface in a region adjacent to the drain diffusion regions; Providing a floating gate conductive material on the tunnel insulating film at least in the region adjacent to the drain diffusion region;
Forming on the floating gate conductive film; exposing the extending source diffusion region in alignment with the floating gate conductive material by the floating gate conductive material formed on the main surface of the semiconductor substrate; Doping the source diffusion region; providing an insulating layer also on the source diffusion region and the exposed floating gate conductive material; and forming a row of multiple conductive materials with the control insulating material and the floating gate conductive material. Form to cover a substance. The second method is constructed as follows: a tunnel insulating material,
Forming at least an extended channel region over the major surface of the semiconductor substrate; providing a floating gate conductive material over at least the tunnel insulating material in the extended channel region; control gate Providing an insulating material over the floating gate conductive material; exposing the source diffusion region and the drain diffusion region extending to the semiconductor substrate by aligning them with the floating gate conductive material; drain diffusion region Doping the source with a first distribution; doping the source diffusion with a second distribution; the insulating layer covering the source and drain diffusions and exposing the exposed floating'gate conductive material. Grow also on top; and rows of many conductive materials, Form to cover control insulating material and floating gate conductive material.

[0012]

The floating gate transistor and non-volatile memory of the present invention have several distinct features. First, the metal pitch of adjacent drain and source bit lines is relaxed by having a structure that shares the source (virtual ground) bit line. The bit line passes through the transistors 16 and the like in parallel and is coupled to one metal source line together with a metal drain contact line or a wide area bit line. This makes it possible to obtain a very compact core array. Second, the flash EPROM array will be able to perform sector erase and memory cell failure while the flash EPROM array is divided into sub-arrays while being selected by the fully decoded block select lines. Occurs only while its corresponding subarray is selected. This greatly improves the operation and reliability of the product. Third,
In the first cell type, the source side of the cell does not undergo many oxidation processes, so the source junction ends retain very good integrity. What is more characteristic is that the source junction is not affected by dopant depletion and thickening of the oxide edge that is typical of cells designed by the prior art. In the prior art, there is a more extensive oxidation process after source implantation. For this reason, the new cell can be expected to have a good source erasing effect. In addition, significantly higher gated coupling ratios can be achieved with a unique cell layout. In the above layout, a floating gate poly-Si layer can extend over the drain and field oxide regions to significantly increase the coupling area of the control gate to the floating'gate poly-Si.

Further, according to the first manufacturing method, the source diffusion region in the cell structure is self-contained in the floating gate transistor in the adjacent transistor row.
To be aligned. Similarly, the drain diffusion region is self-aligned to the opposite isolation region of each block. Further, according to the second manufacturing method, both the drain and source diffusion regions are self-aligned with the floating gate. Thus, the drain-source-drain configuration can create a substantially uniform channel length for all memory cell transistors in the array.
The source is also made by ion implantation with a distribution of dopants that provides a graded junction, facilitating tunneling during the source erase operation.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to FIGS. 1 and 2 show circuit diagrams of a flash EPROM device according to the present invention. Figure 3
FIG. 3 shows a block diagram of a memory circuit of a flash EPROM device according to the present invention. 4, 5, 6 and 7 are sectional views showing a method of manufacturing a flash EPROM cell according to the present invention. FIG. 8 is a plan view thereof. FIG. 1 illustrates a drain-source-drain circuit configuration (a configuration including a pair of transistors having a common source) of a flash EPROM according to the present invention. This circuit configuration has a first local bit line 10 and a second local bit line 1.
Have one. The first and second local bit lines 10 and 11 are obtained by means of buried diffusion layer conductors as described below. In addition, the local virtual ground line 12
Is also obtained by a buried diffusion layer. Many floating gates with gate, drain and source
The transistors are coupled to the local bit lines 10, 11 and the local virtual ground line 12. The sources of most transistors are coupled to the local virtual ground line 12. The drain of the transistor in the first column, indicated by 13, is the first! Of the transistors in the second column shown at 14 are coupled to the second local bit line 11. The gates of the floating'gate transistors are coupled to word lines WL _{0 to} WL _N. It should be noted that each word line (eg, WL ₁ ) here is coupled to the gates of a first column transistor (eg, transistor 5) and a second column transistor (eg, transistor 16). Thus, transistors 15 and 16
Can be thought of as a cell consisting of two transistors sharing a source diffusion layer.

The operation of charging the floating gate is called the program step of the flash EPROM cell. This allows a large positive voltage of about 12 volts between the gate and the source, and 6 between the drain and the source.
This can be done by injecting hot electrons by applying a positive voltage of Volts. floating·
The operation for discharging the gate is the flash EPR.
This is called an OM cell erase step. This is done by an FN tunneling mechanism between the floating gate and the source (source erase) or an FN tunneling mechanism between the floating gate and the semiconductor substrate (channel erase). Source erase can be done by grounding the gate or biasing it negatively to the extent of -8 volt and applying 12 volts or 8 volts to the source.
This is done by applying a positive bias on the order of volts. Channel erasure is performed by applying a negative bias to the gate and / or a positive bias to the semiconductor substrate.

As shown in FIG. 1, a first global bit line 17 and a second global bit line 18 are associated with each drain-source-drain circuit configuration cell. The first global bit line 17 is coupled to the source of the upper block select transistor 19 via a metal diffusion contact 20. Similarly, the second global bit line 18 is coupled to the source of the upper block select transistor 21 via a metal diffusion contact 22. The drains of the upper block select transistors 19, 21 are coupled to the first and second local bit lines 10 and 11, respectively. The gates of the upper block select transistors 19 and 21 have block select signals T applied to the line 23.
Controlled by BSEL.

The local virtual ground line 12 is connected to the conductor 2 via the lower block select transistor 25.
4 to a virtual ground terminal. The drain of the lower block select transistor 25 is coupled to the local virtual ground line 12. The source of the lower block select transistor 25 is coupled to the conductor 24. The gate of the lower block select transistor 25 is controlled by the lower block select signal BBSEL applied to line 26. In the system proposed by the present invention, the conductor 24
Is a conductor with a buried diffusion layer, which extends horizontally through the array to the metal-diffusion contact. This metal-diffusion contact makes contact with a vertically extending metal virtual ground bus.

The wide area bit lines 17, 18 are arranged vertically through the array in respective column select transistors 27, 2.
It extends to 8. Transistors 27, 28 couple the select global bit line to a sense amplifier and program data circuit (not shown). Thus, the source of column select transistor 27 is coupled to global bit line 17 and is connected to column select transistor 2
The gate of 7 is supplied with the column decode signal Yl, and the drain of the column select transistor 27 is coupled to the conductor 29.

The many subarrays shown in FIG. 2 are made up of blocks of the flash EPROM cells shown in FIG. FIG. 2 illustrates two subarrays of the overall IC. The sub-array is sectioned along the alternate long and short dash line 50, and the sub-array 51 is located above the alternate long and short dash line 50.
A has a sub-array 51B at the bottom. The first block 52 includes bit lines (eg, bit lines 70, 7).
The second block 53 is arranged along the line 1). These memory sub-arrays are formed on the upper and lower portions of the pair of bit lines 70 and 71 by the metal-diffusion contact 5.
5, 56, 57 and 58 are common and are divided like virtual ground conductors 54A and 54B (embedded diffusion layers). Virtual ground conductors 54A, 5
4B extends horizontally across the array to the virtual ground'metal line 59, which is arranged vertically through the metal-diffusion contacts 60A, 60B. The sub array is formed on the opposite side of the metal / virtual ground line 59 so that the adjacent sub arrays share the metal virtual ground line 59. The metal virtual ground line 59 is a virtual ground select transistor 79 controlled by the decode signal ZN.
Coupled to array ground and erase high voltage circuitry via. The virtual ground select transistor 79 is
It can be used to isolate the array area sharing metal lines 59 from high voltage erase. Thus, the layout of the sub-array has two metal contact pitches per column of two-transistor cells for the wide area bit line and one metal contact pitch per sub-array for the metal virtual ground line 59. Pitch is needed.

In addition, the two sub-arrays shown in FIG. 2 have additional decoding at the top and bottom of them, respectively, with block select signals TBSELA, TBSEL.
Being provided by B, BBSELA and BBSELB, the word line signals can be shared. In one proposed system, each subarray consists of 8 blocks, consisting of 32 pairs of transistor cells and word lines in each column, 512 cell subarrays, for a total of 16 global bits. There are lines and 32 word lines. As will be appreciated, the device according to the invention can form a sector flash EPROM array. this is,
Advantageously, during a read, program or erase cycle, the sources and drains of the transistors in the unselected sub-array are isolated from the currents and voltages applied to the bit lines and virtual ground lines. Thus, during the read operation,
The read operation is improved because the leakage current from the unselected sub-array does not contribute to the current applied to the bit line.
During programming and erasing operations, the high voltage on the virtual ground lines and the bit lines are isolated from the unselected blocks.
This allows a sector erase operation. The lower block select transistor (eg, transistor 6
5A, 65B) may not be necessary in some implementations. Also, these block select transistors can share a lower block select signal with an adjacent sub-array, as illustrated at the bottom with respect to FIG. Alternatively, the lower block select transistor (eg,
65A, 65B) can replace the adjacent virtual ground terminal 60A, 60B by a single isolation transistor.

FIG. 3 shows a flash EPRO according to the present invention.
It is a block diagram which shows the outline of MIC. Flash EP
The ROMIC has the memory array 100 shown in FIG. 2 and a large number of extra cells 101 are provided in the system so that a damaged memory array can be replaced.
In addition, this circuit includes a number of reference cells 102, a sense amplifier, a program data input circuit, a block 103 which includes array ground and erase high voltage circuits, and a block 1 which includes a word line and a block select decoder.
04, and a block 105 containing a column decoder and a virtual ground decoder. The reference cell 102 is
Coupled to the sense amplifier of block 103 to count changes in channel length, such as those that occur during fabrication or reflected in the voltage and current applied to the bit line being read. The reference cell 102 can also be used to generate programming and erase voltages. This redundant cell arrangement was made possible by the split construction of the flash EPROM array as discussed above. The word line and block select decoder 104 row and virtual ground decoder 105 can be programmed after testing the redundant cells to replace dead cells in the memory array 100. In addition, the circuit has a mode control circuit 106 for controlling the voltages of the virtual ground, drain and word lines used during erase, program and read operations, and various operations.

The method of fabricating the flash EPROM cell according to the present invention and the cell used in the above-described circuit is shown in FIGS. 4A to 4D, 5A to 5D, and 6A to 6C.
D and a cross section according to Figures 7A to 7C. FIG. 8 is a plan view thereof. An example of the first cell type is illustrated in FIGS. 4A-4D and 5A-5D. The manufacturing process of the cell shown in this sectional view shows the outline thereof. FIG. 4A illustrates the process of the first step. To make an N-channel cell, a P ^- type Si semiconductor substrate 100 is prepared and a relatively thick field oxide region 10 grown vertically in a well-known LOCOS field oxidation process.
1 and 102 are generated. Further, a thin oxide film 103 is formed on the main surface of the semiconductor substrate on the outer periphery of the field oxides 101 and 102. In the next step, as shown in FIG. 4B, a photoresist mask 104 is deposited between the field oxides 101, 102, the mask essentially parallel to the field oxide regions 101, 102. Extends along. As a result, the drain diffusion region is covered with the field oxide 101 and the photoresist mask 1.
04 and between the field oxide 102 and the photoresist mask 04. An N-type dopant is ion-implanted into the semiconductor substrate 100 through the thin oxide film 103, as shown schematically by the arrow. Thus, the drain diffusion region is self-aligned with the isolation field oxides 101 and 102.

In the next step, as shown in FIG. 4C, the photoresist mask 104 is removed and the N-type dopant implanted in the semiconductor substrate 100 is annealed to form local bit lines 105 and 106. And activate. In addition, drain oxides 107 and 108 are formed so as to cover the diffusion bit lines 105 and 106. Figure 4
D illustrates the next step in cell fabrication. In particular,
The thin oxide 103 is removed by a blank wet etch, and a tunnel oxide 110 is created between the drain diffusion bit lines 105,106. The thickness of the tunnel oxide film 110 is approximately 100 angstroms in the system of this embodiment. However, the tunnel oxide 110 is about 120 in a flash EPROM cell.
Below Angstrom. Thicker oxide film is UV
It may be used in non-volatile cells such as EPROM cells, but tunnel oxides for erase operations do not use such thick oxides. The oxide films 107, 108 above the bit lines 105, 106 by the buried diffusion layer are
This step is about 1000 angstroms thick.

The next step shown in FIG. 5A is poly S.
This is a step of depositing the first layer of the i layer 111 and doping an impurity element to make the poly-Si a conductor. Then, the oxide / nitride / oxide (ONO) layer 112 is formed as the first layer.
Is formed to provide a control gate insulating film on the poly-Si layer 111. The poly-Si layer 111 layer by this step is about 1500 angstroms thick and the ONO layer is about 250 angstroms thick. In FIG. 5B, self-aligned source diffusion regions are defined using a photomask process. After the photo mask process, poly-Si layer 111 and O
The NO insulating layer 112 is etched to expose the source diffusion region. In addition, the floating gate poly-Si layer 111 and the ONO layer 112 are floating.
Etched to define the width of the gate. Thus, one of the etched poly-Si layers 111 defines the source diffusion region and the other defines the width of the floating'gate. In this embodiment, the latter is located on top of field oxide region 101 or 102. afterwards,
Source diffusion region, N ⁺ / N extending parallel to the drain diffusion region 105, 106 ^- N-type dopant to form a double diffused diffusion region is ion-implanted.
The dopant used is to form a double diffusion.
It is a combination of phosphorus and arsenic.

The photoresist is removed and the semiconductor substrate is annealed, as shown in FIG. 5C. N ⁺
By diffusing the dopant annealing, - the N ^- de
The source diffusion region 115 is activated. Also, a source oxide film 116 is formed and an oxide film 117 separates the floating gate from the word line poly-Si layer that is subsequently defined.
It is generated along the side surface of the i layer 111. FIG. 5D illustrates the next step in the process of manufacturing a flash EPROM cell. This involves depositing a second poly layer 118 and using a photomask process to define the word lines. In the photomask process, the word line defining etch is continued to the floating gate poly-Si layer 111 to define the floating gate of each transistor. Word line 118 is approximately 4,500 angstroms thick. Finally, a passivation and metallization layer (not shown) is deposited on top of the cell.

As shown in FIG. 5D, the first transistor has a drain diffusion line 105 and a source diffusion line 1.
A cell structure in which a second transistor is formed between the drain diffusion line 106 and the source diffusion line 115 is obtained. The floating gate is from the source diffusion line 115 to the drain diffusion line 1
05, and extends over the field oxide 101. In this embodiment, these floating
The gate oxide is about 2.4 microns long and 0.8 microns wide. On the other hand, the width of the tunnel oxide film 110 from one end of the drain oxide film 107 to one end of the source oxide film 116 above the transistor is about 1.2 μm. A redundant region over the drain diffusion line 105 and the field oxide 102 is used to increase the coupling ratio by the floating gate up to about 50% or more. Because it is ON
Because the O layer is about 250 Å thick and the tunnel oxide is about 100 Å thick, the coupling ratio must be improved by increasing the area of the floating gate. Alternatively, the ONO layer may be made thinner to reduce the area required for the floating gate. As can be seen, the source diffusion is performed in a step independent of the drain diffusion, and ion implantation with a dopant with a different distribution is used to create a graded junction in the channel of each transistor to facilitate the source erase function. To be done. No graded junctions and sources or diffusions are required for channel erased or UV erased floating gates.

Next, FIGS. 6A to 6D and FIGS. 7A to 7
C shows in cross-section a second cell type embodiment according to the invention. As shown in FIG. 6A, the first
The step is to produce field oxides 201, 202 as described in Figure 4A. In addition, the unnecessary oxide film is purified, and this oxide film is removed to prepare the semiconductor substrate 200 for forming the tunnel oxide film. As shown in FIG. 6B, a thin tunnel oxide film 203 is formed to a thickness of about 100 Å. In the next step of FIG. 6C, a poly-Si layer is deposited and a dopant is doped, and the coupling ratio is about 5.
An ONO layer 205 having a thickness of 120 angstrom is formed so as to be 0% or more. Thicker oxide thin film 203
And ONO layer 205 is used for UV-EPROM cells. In FIG. 6D, a photomask process is used to define the floating gate and source and drain diffusions of the N ⁺ layer. Thus, photomask layers 206 and 207 are defined to protect the floating gate region. 20 of poly-Si layer
A layer of 4 and ONO 205 is etched except where covered by masks 206 and 207, exposing the drain, source and drain regions. Next, an N-type dopant is ion-implanted into the exposed area as shown by arrow 208. These regions are formed by self-alignment of the floating gate and field isolation regions. The flash EPROM array is illustrated in the next step, FIG. 7A. According to this step, the photo mask process uses masks 210, 211 that cover the drain and isolation regions. In this step, the N-type dopant is arrow 21.
Implanted as represented by 2, the source region will have N ⁺ and N ^- type dopants to form a graded junction. The steps in FIG. 7A are U
It can be omitted in the description of the method for manufacturing the V-erasable EPROM cell.

As shown in FIG. 7B, the semiconductor substrate is annealed to activate the dopants and defines drain diffusion regions 213 and 214 and source diffusion region 215. In addition, the drain oxide film 2
The oxide film 217 and the source oxide film 218 are formed so as to cover the side surfaces of the floating gate poly-Si. Finally, as shown in Figure 7C, a second poly-Si layer 219 is deposited and etched to define the transistor. In this embodiment, ONO
The sandwich 205 has a tunnel oxide film thickness of ± 20.
%, The coupling ratio is high (in the range of about 40% to 60%, preferably about 50%), and the floating gate extended on the drain and field isolation regions is used. No need. Finally, passivation and metallization layers (not shown) are deposited on the device of Figure 7C. Thus, as seen in FIG. 7C, the cell structure according to the second type is such that the first transistor has a buried drain diffusion region 2
The second transistor is formed between the embedded drain diffusion region 214 and the embedded source diffusion region 215 between the embedded drain diffusion region 214 and the embedded source diffusion region 215. Each transistor has a floating gate made of the first poly-Si layer 204. floating·
The gate is insulated from the channel region of each transistor by the tunnel oxide film 203, and the ONO layer 205 is isolated from the control gate in the word line / poly-Si layer 219.
Is insulated by. The ONO layer 205 has a tunnel oxide film 203 with a thickness of about ± 2 in order to ensure a sufficiently high coupling ratio for flash EPROM operation.
The thickness is within the range of 0%.

The ONO layer 205 in the cell types shown in FIGS. 6A-6D and 7A-7C is thin enough that the surface area of the floating gate is similar to that of FIGS. 4A-4D. It need not extend as it did in the first type of cell structure illustrated in FIGS. 5A-5D. Furthermore, in the structure shown in FIG. 7C, all of the first and second drain diffusion regions 213 and 214 and the source diffusion region 215 are formed in the first poly-Si layer 2.
04 and the ONO insulating layer 205 are self-aligned with the floating gate structure. This demonstrates that the channel lengths of each transistor are substantially equal.

FIG. 8 shows the EPROM shown in FIGS. 4 and 5.
A sub-array layout of the cell IC is shown. Obviously, this arrangement is also substantially the same for the cell shown in FIG. 7C except for the size of the floating gate. As seen in FIG. 8, the IC has a number of isolation regions 300 that extend vertically through the sub-array.
Through 302. These isolation regions correspond to the thick oxide film 10L102 shown in FIG. 5D. These field oxides 300, 301 define isolation regions with a region 303 between them. In the element-isolated region, there are a band-shaped first buried diffusion line 304 and a second buried diffusion line 305 corresponding to the diffusion line 105 and unit 06 in FIG. 5D. There is a source diffusion line 306 corresponding to the diffusion line 115 in FIG. 5D between the strip-shaped buried diffusion lines. A number of word lines 307-309 traverse the isolation regions that define the control gates of the floating gate transistors of the array device. A floating'gate (see, eg, notch 310) covers the semiconductor substrate between the tunnel oxide and the respective word line.

The top select transistor is a buried diffusion line 304 defined by a local bit line,
Associated with each of the 305. For example, the block select transistor in the cutout area 311 is
It has a drain 312 coupled to the extending buried diffusion region 304 and a source 313 coupled to a metal line (not shown) by a metal-diffusion contact 314. The metal lines extend parallel to the isolation region 300 above the sub-array. Similarly, the second buried diffusion line 305 is coupled to the drain 315 of the upper select transistor. This transistor is coupled to metal-diffused contact 317,
And having a source 316 coupled through the contact to a vertically extending metal line (not shown) that acts as a wide area bit line. The gate of the upper block select transistor is set by the upper select word line 318 which extends horizontally across the array. The upper block select transistor coupling the local bit line 304 to the metal-diffusion contact 314 is connected to the block select transistor coupling the local bit line 305 to the metal-diffusion contact 317.
Separated from the transistor by field oxide region 319. In this way, the transistors in each column can be independently selected for read and program operations.

Local source diffusion 306 is coupled to the underlying block select transistor having a buried diffusion source 320 and a buried diffusion drain 321. The buried diffused drain is a conductor of a strip of buried diffused layer that extends horizontally across the array to metal-diffused contacts 322. The metal-diffusion contacts, in turn, are coupled to metal lines 323 which provide a virtual ground voltage to the array. The lower block select transistor is controlled by the select line 324 in the poly-Si layer. As will be appreciated, the select lines 324 of the poly-Si layer are shared with the subarray depicted in the figure and the subarray 325 below the figure.
Subarray 325 has a block select source region 326 that shares a buried diffused drain 321 that connects the subarray to a virtual ground bus. Thus, the bottom block select signal of the poly-Si layer traverses the wide structure 324 extending from the source region 320 of the first sub-array and the second sub-array 325.
In a manner such as to be supplied to the source region 326 within
Bottom block select signal is local virtual ground diffusion 3
06 acts on the sub-arrays on both sides of the drain diffusion region 321.

Of course, other implementations may be implemented in which the bottom block select signal is individually controlled for each subarray that requires a separate block select signal for word line 324. In the above embodiments, the lower block select transistors may also be implemented in a manner similar to the upper block select transistors, one for each buried diffusion line. In another embodiment, the lower block select transistor has metal-diffusion contacts 322 that control multiple local virtual ground bit lines.
Can be replaced by a conductor with one isolated transistor near. Element isolation regions, eg, element isolation regions 301, extend periodically through lower block select source regions 320 and drain regions 321, and lower block select regions of adjacent sub-arrays.
Separate the transistors. As can be seen, the virtual ground metal bus 323 extends vertically across the figure. The bus 323 has metal-diffusion contacts 322.
Is connected to the lower block select transistor.

The element isolation region 301 separates the subarray on both sides of the field oxide 301 by isolating the underlying block select transistor.
As shown in FIG. 6, the sub-array thus has four (as an example) columns of transistors 350, 351, 352, 353, which generally share the lower block select transistors in region 354. A preferred system has 16 columns of transistors (2
8 blocks with individual transistor cells). The transistors formed by diffusion regions 304, 305 will thus be in a sub-array separate from the transistors in columns 350 and 351. The transistors to the right of virtual ground metal line 323 will also be in separate subarrays. The lower block select transistor that was shared is
Since it is controlled by the block signal applied to the line 324, four sub-arrays (two on each side of the metal 324) are used.
Have their source diffusion regions, eg, 359, coupled to a virtual ground bus 323 responsive to the signal on line 324. This results in sector erase for four subarrays at a time.

In the present invention, the N channel of the flash EPROM array has been described, but it is obvious that the P channel can be easily realized. Further, the embodiments and the description thereof disclosed in the present invention are for explaining the present invention, and do not disclose all the gist of the present invention. Therefore, the present invention is not limited to the disclosed embodiments, which were chosen in order to best explain the principles of the invention and its practical application, and to numerous modi? Cations. It is clear that cations and variations can be made by experienced technicians.

[0036]

As described above, the nonvolatile memory of the present invention
The cell and array device is a new floating gate
A flash EPROM cell including a transistor, an array device thereof, and a memory circuit thereof can be provided, and the main features thereof are as follows. 1. Two adjacent local drain bit lines share one source bit line and one metal source
The bit lines are formed in parallel with all sub-arrays of the cell, and the contactless structure has an effect of obtaining a very dense core array of a nonvolatile memory. 2. Sector erase is a floating
There are advantages that can be realized by using a partitionable array device composed of gate transistors. 3. A nonvolatile memory cell using the novel floating gate transistor of the present invention provides a flash memory array having high operation and high reliability,
Also, there is an advantage that a memory circuit can be obtained.

Further, the non-volatile memory cell, array device of the present invention can provide a flash EPROM cell and the device can be adapted to an array of various memory circuits. Thus, the storage cells in the memory array are ROM, PROM, EPROM, UV erase E
Clearly, a PROM, or other EPROM, could be applied. Furthermore, the flash EPRO disclosed in the present application
It goes without saying that M is for the purpose of the source erase operation and can be adapted to the channel erase operation if desired.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a nonvolatile memory cell according to the present invention.

FIG. 2 is a schematic diagram of an array device including nonvolatile memory cells according to the present invention, and is a circuit diagram showing two sub-arrays.

FIG. 3 is a block diagram showing an embodiment of a semiconductor integrated circuit using a nonvolatile memory cell according to the present invention.

4A to 4D illustrate a method of manufacturing a non-volatile memory cell according to an embodiment of the present invention, which is a cross-section taken along a word line of an array device using the non-volatile memory cell according to the present invention. It is a figure.

5A to 5D are diagrams of FIGS. 4A to 4D.
FIG. 6 is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory cell, which is continued from FIG.

6A to 6D illustrate a manufacturing method of another embodiment of a non-volatile memory cell along a word line of an array device with the non-volatile memory cell according to the present invention. FIG.

7A to 7C are diagrams of FIGS. 6A to 6D.
FIG. 6 is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory cell, which is continued from FIG.

8A to 4D and FIGS. 5A to 5D.
FIG. 6 is a plan view of an array device including a nonvolatile memory cell obtained by the manufacturing method of FIG.

[Explanation of symbols]

10 First Local Bit Line 11 Second Local Bit Line 12 Local Virtual Ground Lines 13, 15 First Row Transistors 14, 16 Second Row Transistors 17 First Wide Area Bit Line 18 Second Wide Area Bit Line 19 , 21 Upper block select transistors 20, 22 Metal-diffused contacts 23, 26 Lines 24, 29 Conductor 25 Lower block select transistors 27, 28 Column select transistors WL _{0 to} WL _N Word line

Continued front page    (72) Inventor Hayashi Tenraku             United States California 95104,             Santa Clara, Capertino, Maderad             Live 10501 (72) Inventor             United States California 94087,             Santa Clara, Sunnyvale, March             N'Avenue 1640 F term (reference) 5F083 EP13 EP23 EP55 EP62 EP67                       EP75 ER02 ER14 ER16 ER19                       ER22 ER23 GA09 KA08 KA13                       LA12 LA16 LA20 NA02 PR29                       ZA10                 5F101 BA05 BA23 BA29 BA36 BB05                       BC11 BD05 BD09 BD31 BD32                       BD37 BE05 BE07 BH19

Claims (11)

[Claims] 1. A plurality of drain diffusion regions extending in a first direction are defined; a drain diffusion region is doped; and a first surface of the semiconductor substrate is at least in a region adjacent to the drain diffusion region. Providing an insulating material, and providing at least a floating gate conductive material covering the first insulating material in a region adjacent to the drain diffusion region, and a control gate insulating covering the floating gate conductive material. A conductive material, exposing the extended source diffusion region by aligning the floating gate conductive substance of the semiconductor substrate with the floating gate conductive substance, and doping the source diffusion region; Insulation over the source diffusion and any exposed floating gate conductive material And forming a row of multiple conductive materials overlying the control gate insulating material and the floating gate conductive material, a contactless floating gate memory array. Device manufacturing method. 2. A step of exposing a number of elongated source diffusion regions is stepped from the first side to define one side of the source diffusion region and a width of the floating gate region. An elongated floating gate region having a second side provided therein, and etching the floating gate conductive material such that the floating gate region overlies at least a portion of the adjacent drain diffusion region. The method of manufacturing a contactless floating gate memory array device according to claim 1, further comprising: 3. The method of claim 2, wherein the second side of the floating gate region is defined to overlie the adjacent drain diffusion region. 4. The method for manufacturing a contactless floating gate memory array device according to claim 1, wherein the first insulating material is silicon dioxide. 5. The control gate insulating material is O
The method for manufacturing a contactless floating'gate memory array device according to claim 4, wherein the contactless floating 'gate memory array device is made of NO. 6. The contactless floating gate of claim 1, wherein the first insulative material comprises silicon dioxide having a thickness that does not reach the floating gate material below about 120 angstroms.
Method of manufacturing memory array device. 7. The first insulating material is a floating
2. From silicon dioxide having a thickness not reaching the gate conductive material, the costrol gate insulating material comprises ONO having a thickness substantially greater than the thickness of the tunnel insulating material. A method for manufacturing the contactless floating gate memory array device described. 8. The method of manufacturing a contactless floating gate memory array device of claim 1, wherein the step of doping the source diffusion region sets the dopant distribution to have a graded junction. 9. Forming a large number of insulating regions extending in a first direction on a main surface of a semiconductor substrate, and forming a large number of insulating regions extending in the first direction and spaced apart from each other. Defining a plurality of drain diffusion regions extending in the first direction, the drain diffusion regions having at least one drain diffusion region inside each of the isolation regions in the plurality of isolation regions; Doping, providing a first insulating material on the semiconductor substrate at least in a region adjacent to the drain diffusion region, and floating at least in a region adjacent to the drain diffusion region to cover the first insulating material. Providing a gate conductive material, providing a control gate insulating material covering the floating gate conductive material, and expanding the source extending to the semiconductor substrate. Aligning and exposing the region with a floating gate conductive material, doping the source diffusion region, and providing an insulating layer over the source diffusion region and any exposed floating gate conductive material. And forming a number of rows of conductive material overlying the control gate insulating material and the floating gate conductive material, a method of manufacturing a floating gate memory array. 10. At least providing an insulating material on the semiconductor substrate in the extended channel region, and providing at least a floating gate conductive material covering the first insulating material in the extended channel region. Providing a control gate insulating material covering the floating gate conductive material, and exposing the source diffusion region and the drain diffusion region extending to the semiconductor substrate by aligning with the floating gate conductive material. , Doping the drain diffusion region with a dopant having a first distribution, doping the source diffusion region with a dopant having a second distribution, the source and drain diffusion regions, and any exposed floating・ Providing an insulating layer covering the gate conductive material, and controlling A floating gate characterized in that it comprises forming a number of rows of conductive material overlying the edge material and the floating gate conductive material.
Method of manufacturing gate memory array. 11. A semiconductor substrate extending in a first direction is provided with a plurality of isolation regions spaced apart from each other, and a plurality of insulating regions extending in the first direction are formed on the semiconductor substrate. Depositing a first insulative material on at least the semiconductor substrate in a channel region extending into the isolation region; floating gate conduction covering at least the insulative substance in the extended channel region. A conductive material, at least a floating gate conductive material covering the first insulating material in the channel region, and a control gate covering the floating gate conductive material. Depositing a conductive material, exposing the source and drain diffusion regions extending to the semiconductor substrate with a floating gate conductive material, and exposing the source; And doping the drain diffusion region, creating an insulating layer over the source and drain diffusion regions and any exposed floating gate conductive material, and providing a control insulating material and a floating gate conductive material. A method of manufacturing a floating gate memory array comprising forming a number of rows of conductive material overlying.