JP2003179163A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To suppress an increase in chip area as compared with the case of using a diffusion resistor on an active region of a field without increasing the number of wirings and the number of mask superpositions (the number of steps) A semiconductor device capable of reducing variation in resistance value and a method for manufacturing the same are obtained. SOLUTION: In a semiconductor memory device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit portion, doped amorphous silicon or doped polysilicon of a storage node 12 which is a capacitor lower electrode of the semiconductor memory device is provided in the peripheral circuit portion. And a resistance element formed by using the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a CONCAVE type capacitor or a DRAM-embedded semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 is a cross-sectional view showing a semiconductor device having a conventional CONCAVE type capacitor and a DRAM embedded therein. In the figure, 1 is a silicon substrate, 2 is a well portion, 3 is a diffusion layer, 4 is an element isolation insulating film, 5 is a gate electrode, 6 is a sidewall, 7 is a doped amorphous silicon plug (hereinafter referred to as a BS plug), 8 is a first interlayer silicon oxide film, 9 is a bit line line, 10 is a storage node contact, 11 is a third interlayer silicon oxide film, 12 is a storage node (capacitor lower electrode),
Reference numeral 13 is a capacitive insulating film, 14 is a cell plate (capacitor upper electrode), 15 is aluminum wiring, 16 is a fourth interlayer silicon oxide film, 17 is a fifth interlayer silicon oxide film, and 18 is a first W film.
A plug, 19 is a second W plug, 20 is a second interlayer silicon oxide film, and 21 is a bit line contact.

[0003]

By the way, in the conventional semiconductor device in which the DRAM is embedded as shown in FIG.
At present, the resistance element of the GIC portion uses the diffusion resistance on the activation region of the field, that is, the diffusion layer 3. Therefore, using the diffusion resistance on the active region of the field, LOGIC
It is necessary to secure a pattern serving as a resistance element of the LOGIC section in the macro cell which is the minimum unit of the section (see FIG.
There are problems such as an increase in the chip area of the GIC section (resistive element section) and the chip area.

Further, when the diffusion resistance on the active region of the field is used, the resistance may vary due to variations in the finish in the field step (step of forming the element isolation insulating film), variations in the implantation step, variations in the heat treatment step, etc. There were problems such as large variations in values.

The present invention has been made in order to solve the above problems, and utilizes doped amorphous silicon or doped polysilicon such as a storage node in a DRAM mixed device having a CONCAVE type capacitor. An object of the present invention is to provide a semiconductor device capable of suppressing an increase in chip area and suppressing variation in resistance value by forming a resistance element by using the resistance element, and a manufacturing method thereof.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device including a semiconductor memory device having a CONCAVE type capacitor and a peripheral circuit portion, wherein the peripheral circuit portion includes the semiconductor memory device. The resistance element is formed by using the conductive film of the lower electrode of the capacitor.

A semiconductor device according to a second aspect of the present invention is a CO device.
A semiconductor device having an NCAVE-type capacitor and a semiconductor device having a peripheral circuit portion, wherein the peripheral circuit portion is provided with a resistance element formed by using a conductive film of a capacitor upper electrode of the semiconductor memory device. .

The semiconductor device according to the invention of claim 3 is a CO
In a semiconductor memory device having an NCAVE type capacitor and a semiconductor device having a peripheral circuit portion, a resistance element formed by using a conductive film of a capacitor lower electrode and a capacitor lower electrode contact of the semiconductor memory device is provided in the peripheral circuit portion. Be prepared.

According to another aspect of the semiconductor device of the present invention, the semiconductor memory device is a DRAM or a DRAM mixed LSI.
Is.

A semiconductor device according to a fifth aspect of the present invention uses doped amorphous silicon or doped polysilicon as the conductive film.

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention is a method of manufacturing a semiconductor device having a semiconductor memory device having a CONCAVE type capacitor and a peripheral circuit portion, wherein the peripheral circuit portion is formed on an interlayer film on a semiconductor substrate. A step of opening a portion to be a resistance element, a step of depositing a conductive film used for forming a capacitor lower electrode of the semiconductor memory device in the opening to form a resistance element, the resistance element and an upper wiring. And a step of forming a joint portion for connecting the two.

A method of manufacturing a semiconductor device according to a seventh aspect of the present invention is a method of manufacturing a semiconductor device having a semiconductor memory device having a CONCAVE type capacitor and a peripheral circuit portion, wherein the peripheral circuit portion is formed on an interlayer film on a semiconductor substrate. A step of opening a portion to be a resistance element, a step of depositing a conductive film used for forming a capacitor upper electrode of the semiconductor memory device to form a resistance element in the opening, and the resistance element and the upper wiring. And a step of forming a joint portion for connecting the two.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a semiconductor memory device having a CONCAVE type capacitor; and a semiconductor device having a peripheral circuit portion. A step of opening a portion of the peripheral circuit portion to be a resistance element; a step of depositing a first conductive film used for forming a capacitor lower electrode contact of the semiconductor memory device in the opening portion; Forming a second interlayer film thereon; opening a portion of the peripheral circuit portion that reaches the first conductive film and serving as a resistance element in the second interlayer film; and opening the semiconductor portion in the opening portion. A step of depositing a second conductive film used for forming a capacitor lower electrode of a memory device to form a resistance element composed of the first and second conductive films, and connecting the resistance element and an upper wiring It is obtained and forming a junction.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the semiconductor memory device is a DRAM or a DRAM.
It is an embedded LSI.

According to a tenth aspect of the present invention, a method of manufacturing a semiconductor device uses doped amorphous silicon or doped polysilicon as the conductive film.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
It will be described with reference to the drawings. Embodiment 1. 1 to 5 show Embodiment 1 of the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing process in FIG. In this embodiment, as an example, a 0.18 μm class semiconductor memory device having a CONCAVE type capacitor, for example, a DRAM embedded L
In SI, for example, doped amorphous silicon (D-α) or doped polysilicon (D-pol) is used as a conductive film of a storage node that is a capacitor lower electrode.
The case of forming a resistance element using y) will be described as an example with reference to FIGS. In each drawing, 1 is a silicon substrate, 2 is a well portion, 3 is a diffusion layer, 4 is an element isolation insulating film, 5 is a gate electrode, 6 is a sidewall, and 7 is a doped amorphous silicon plug (hereinafter referred to as a BS plug). , 8 is a first interlayer silicon oxide film, 9 is a bit line line, 10 is a storage node (capacitor lower electrode)
A contact, 11 is a third interlayer silicon oxide film, 12 is a storage node (capacitor lower electrode), 13 is a capacitive insulating film, 14 is a cell plate (capacitor upper electrode), 1
5 is aluminum wiring, 16 is a fourth interlayer silicon oxide film, 17
Is a fifth interlayer silicon oxide film, 18 is a first W plug, 19
Is a second W plug, 20 is a second interlayer silicon oxide film, 21
Is a bit line contact.

Next, the manufacturing method will be described. Here, when forming the region of the element isolation insulating film 4, it is not necessary to secure a portion to be a resistance element on the activation region, that is, the diffusion layer 3. Therefore, other patterns may be present in the current diffusion resistance pattern (FIG. 1 is an example in which a gate pattern exists).

First, the gate electrode 5 and the source / drain portions of the diffusion layer 3 are formed. Next, a first interlayer silicon oxide film 8 which is an interlayer film of the BS plug 7 (bit line contact plug) is deposited. A hole is opened in the memory cell portion, that is, the DRAM portion by dry etching, doped amorphous silicon is deposited, and then this doped amorphous silicon is etched back.

Next, the bit line contact (BC) 2
The second interlayer silicon oxide film 20 which is the first interlayer film (BP TEOS) is deposited. Next, a hole is formed by dry etching on the poly pad of the memory cell part and in the peripheral circuit part, for example, the LOGIC part, and Ti / TiN and W are deposited and etched back to form the first W plug 18. Next, the bit line line 9 is formed by photolithography. Next, the interlayer film (BP) of the storage node contact (SC) 10
A third interlayer silicon oxide film 11 which is TEOS) is deposited.

Next, the memory cell portion is dry-etched to open a hole, doped amorphous silicon is deposited, and then this doped amorphous silicon is etched back. (See Figure 1)

Next, following the SiN film serving as a stopper,
As the interlayer film (BP TEOS), for example, a fourth interlayer silicon oxide film 16 of 15000Å is deposited. Next, the CONC of the storage node (capacitor lower electrode) 12 of the DRAM memory cell is subjected to photolithography and oxide film dry etching.
The AVE portion is opened, and the portion of the LOGIC portion that becomes the resistance element portion is also opened. (See Figure 2)

Next, 2000 Å of doped amorphous silicon, which is the base of the storage node (SN) 12 which is the lower electrode of the capacitor, is deposited, and non-doped amorphous silicon is deposited, followed by roughening treatment (this roughening treatment). Does not have to be done). Next, a resist is embedded inside SNCONCAVE by photolithography. At this time, the resistance element portion is patterned so that the amorphous silicon remains on the upper portion of the interlayer film in order to form a junction with the upper layer wiring, and the amorphous silicon is etched back. (See Figure 3)

Next, a capacitor insulating film 13 and doped amorphous silicon (or doped polysilicon) are deposited, and a cell plate 14 as a capacitor upper electrode is formed by photolithography and dry etching. At this time, the joint portion with the upper wiring of the resistance element portion is connected to the above SNC.
Patterning is performed so that the pattern of the upper layer doped amorphous silicon is located inside the pattern formed by the photoengraving process in which the resist is embedded inside the ONCAVE.
(See Figure 4)

Next, a fifth interlayer silicon oxide film 17 is deposited as an interlayer film, and contact holes are opened by photolithography and oxide film dry etching. On this occasion,
The contact hole is also made to drop at the junction with the upper wiring of the resistance element section. Next, Ti / TiN and W are deposited and then etched back to form the second W plug 19.
Next, aluminum (Al) is deposited, and aluminum wiring 15 is formed by photolithography and Al dry etching. (Refer to FIG. 5) Actually, the sheet resistance of the doped amorphous silicon 2000Å is about 120Ω / □, the resistance of the N-type well portion is about 850Ω / □, and the SN aspect is 7.5. Applicable to structure.

Thus, in the present embodiment, CO
Since the resistance element is formed by effectively utilizing the side surface of the NCAVE portion, the pattern can be arranged to some extent in the SN layer having substantially no LOGIC, and the distance between the resistance elements on the side surface of the CONCAVE portion can be increased, thereby activating the field. It is possible to suppress an increase in the chip area as compared with the case of using the diffusion resistance of the region portion.

If tantalum oxide is used for the capacitance insulating film, in order to prevent reactivity with tantalum oxide,
Since TiN or the like must be used for the electrode in the CP step (step of making a cell plate), it is difficult to form a resistance element with the CP electrode. However, in the present embodiment, since the electrode in the CP step is not used, the capacitive insulating film It can also be applied by using tantalum oxide.

Embodiment 2. 6 to 7 are cross-sectional views showing the manufacturing process in the second embodiment of the present invention. In the present embodiment, a 0.18 μm class semiconductor memory device having a CONCAVE type capacitor, for example, a DRAM embedded L
In SI, a case where a resistance element is formed by using a conductive film of a cell plate which is a capacitor upper electrode, for example, doped amorphous silicon or doped polysilicon will be described with reference to FIGS. 6 to 7.

It is to be noted that 2000 Å of doped amorphous silicon, which is a base of SN of the manufacturing process of FIG. 1 to the manufacturing process of FIG. 3 of the first embodiment, is deposited, and non-doped amorphous silicon is deposited, followed by roughening treatment. The operation is the same as in the first embodiment. First, a resist is embedded in the side surface of the CONCAVE portion by photolithography, and the amorphous silicon is etched back. (See Figure 6)

Next, a capacitance insulating film 13 and doped amorphous silicon (or doped polysilicon) are deposited, and a cell plate (CP) 14 as a capacitor upper electrode is formed by photolithography and dry etching. Next, an interlayer film is deposited, and contact holes are opened by photoengraving and oxide film dry etching. At this time, the contact hole is also made to drop at the junction of the LOGIC portion as the peripheral circuit portion with the upper wiring of the resistance element portion. Next, Ti / TiN and W are deposited and then etched back to form the second W plug 19. next,
Al is deposited, and aluminum wiring 15 is formed by photoengraving and Al dry etching. (See Figure 7)

Thus, in the present embodiment, CO
Since the resistance element is formed by effectively utilizing the side surface of the NCAVE portion, the pattern can be arranged to some extent in the CP layer having substantially no LOGIC, and the distance between the resistance elements on the side surface of the CONCAVE portion can be increased, thereby activating the field. It is possible to suppress an increase in the chip area as compared with the case of using the diffusion resistance of the region portion.

Embodiment 3. 8 to 12 are sectional views showing manufacturing steps in the third embodiment of the present invention.
In a 0.18 μm class semiconductor memory device having a CONCAVE type capacitor, for example, a DRAM embedded LSI, a case where a resistance element is formed by using, for example, doped amorphous silicon or doped polysilicon as a conductive film of a storage node contact and a storage node, An example will be described with reference to FIGS. The steps up to the deposition of the third interlayer silicon oxide film 11 which is the interlayer film (BP TEOS) of the storage node contact 10 in the manufacturing process of FIG.
This is the same as in the first embodiment.

First, the capacitive insulating film 13 and the doped amorphous silicon (or doped polysilicon) memory cell portion are dry-etched to open holes, and doped amorphous silicon is deposited. Next, photolithography is performed to pattern the resistive element portion. afterwards,
The doped amorphous silicon in the memory cell section is etched back, and the resistive element section in the LOGIC section as the peripheral circuit section is dry-etched. Next, holes are opened in the memory cell portion by dry etching, doped amorphous silicon is deposited, and then this doped amorphous silicon is etched back. (See Figure 8)

Next, following the SiN film serving as a stopper,
As the interlayer film (BP TEOS), for example, a fourth interlayer silicon oxide film 16 of 15000Å is deposited. Next, the CONCAVE portion of the storage node 12 of the DRAM memory cell is opened by photolithography and the dry etching of the oxide film, and the portion of the LOGIC portion that will be the resistance element portion is also opened. (See Figure 9)

Next, doped amorphous silicon 2000Å which is the base of the storage node 12 is deposited, and non-doped amorphous silicon is deposited, and then roughening treatment is performed (the roughening treatment may not be performed). next,
A resist is embedded inside SNCONCAVE by photoengraving. At this time, the resistance element portion is patterned so that the amorphous silicon remains on the upper portion of the interlayer film in order to form a junction with the upper layer wiring, and the amorphous silicon is etched back. (See FIG. 10) Next, the capacitive insulating film 1
3. Doped amorphous silicon (or doped polysilicon) is deposited, and the cell plate 14 as a capacitor upper electrode is formed by photolithography and dry etching.
To form. At this time, the resistance element portion is patterned so that the junction portion with the upper layer wiring has the pattern of the upper layer doped amorphous silicon inside the pattern formed by the photoengraving process in which the resist is embedded in the SNCONCAVE described above. (See Figure 11)

Next, a fifth interlayer silicon oxide film 17 is deposited as an interlayer film, and contact holes are opened by photolithography and oxide film dry etching. On this occasion,
The contact hole is also made to drop at the junction with the upper wiring of the resistance element section. Next, Ti / TiN and W are deposited and then etched back to form the second W plug 19.
Next, Al is deposited, and aluminum wiring 15 is formed by photoengraving and Al dry etching. (Fig. 12
reference)

Thus, in this embodiment, the SN
And the internal side surface of the SN contact CONCAVE is effectively used to form the resistance element, so that the
Since the pattern can be arranged to some extent in the SN and SN contact layers having no C and the distance between the resistance elements can be lengthened on the side surfaces of the SN and SN contact holes, the chip area is larger than that in the case of using the diffusion resistance of the active region of the field. Can be suppressed.

When tantalum oxide is used for the capacitance insulating film, in order to prevent reactivity with tantalum oxide,
Since TiN or the like must be used for the electrode in the CP step, it is difficult to form a resistance element with the CP electrode. However, in the present embodiment, since the electrode in the CP step is not used, even if tantalum oxide is used for the capacitive insulating film. Applicable.

[0038]

As described above, according to the invention of claim 1, in the semiconductor memory device having the CONCAVE type capacitor and the semiconductor device having the peripheral circuit portion, the semiconductor memory device is provided in the peripheral circuit portion. Since the resistance element formed by using the conductive film of the lower electrode of the capacitor is provided, the number of wirings and the number of mask overlays (the number of steps)
It is possible to suppress the increase of the chip area compared with the case of using the diffusion resistance on the active region of the field without increasing the
Further, since the diffusion resistance is not used, variations in resistance value can be reduced, and there is an effect that the product can be downsized and the quality can be improved.

According to the invention of claim 2, the CONC
In a semiconductor device having an AVE type capacitor and a semiconductor device having a peripheral circuit portion, a wiring is provided because a resistance element formed by using a conductive film of a capacitor upper electrode of the semiconductor memory device is provided in the peripheral circuit portion. The number of masks and the number of mask overlays (number of steps) can be suppressed without increasing the chip area compared to the case of using the diffusion resistance on the active region of the field. Also, since the diffusion resistance is not used, the resistance value varies. It is possible to reduce the above-mentioned problem, and it is possible to reduce the size of the product and improve the quality.

According to the invention of claim 3, the CONC
In a semiconductor device having an AVE type capacitor and a semiconductor device having a peripheral circuit section, a resistance element formed by using a conductive film of a capacitor lower electrode and a capacitor lower electrode contact of the semiconductor memory device is provided in the peripheral circuit section. Since it is provided, it is possible to suppress an increase in the chip area as compared with the case where the diffusion resistance on the field activation region is used without increasing the number of wirings and the number of times of mask overlapping (the number of steps), and the diffusion resistance is not used. Therefore, variations in resistance value can be reduced, and the product can be downsized and the quality can be improved.

According to the inventions of claims 4 and 9,
Since the semiconductor memory device is a DRAM, there is an effect that it is possible to obtain a small-sized device having excellent quality and high reliability and in which a DRAM is embedded.

According to the fifth and tenth aspects of the present invention, since doped amorphous silicon or doped polysilicon is used as the conductive film, the number of wirings and the number of mask overlays (number of steps) can be easily increased without increasing the number of wirings. There is an effect that an increase in chip area can be suppressed and a variation in resistance value can be reduced.

Further, according to the invention of claim 6, CON
In a method of manufacturing a semiconductor memory device having a CAVE-type capacitor and a semiconductor device having a peripheral circuit portion, a step of opening a portion of the peripheral circuit portion to be a resistance element in an interlayer film on a semiconductor substrate, and the opening portion Since the method includes the step of depositing a conductive film used for forming a capacitor lower electrode of a semiconductor memory device to form a resistance element and the step of forming a joint connecting the resistance element and an upper layer wiring, Also, it is possible to suppress the increase in the chip area compared to the case of using the diffusion resistance on the active region of the field without increasing the number of mask overlays (the number of steps), and reduce the variation in the resistance value because the diffusion resistance is not used. Therefore, there is an effect that the product can be downsized and the quality can be improved, and the product yield and the production efficiency can be improved.

According to the invention of claim 7, the CONC
In a method of manufacturing a semiconductor device having an AVE type capacitor and a semiconductor device having a peripheral circuit section, a step of opening a portion of the peripheral circuit section to be a resistance element in an interlayer film on a semiconductor substrate, and the opening section Since the step of depositing a conductive film used for forming a capacitor upper electrode of a semiconductor memory device to form a resistance element and the step of forming a joint connecting the resistance element and the upper layer wiring are provided, the number of wirings is increased. Also, it is possible to suppress the increase in the chip area compared to the case of using the diffusion resistance on the active region of the field without increasing the number of mask overlays (the number of steps), and reduce the variation in the resistance value because the diffusion resistance is not used. Therefore, there is an effect that the product can be downsized and the quality can be improved, and the product yield and the production efficiency can be improved.

According to the invention of claim 8, the CONC
In a method of manufacturing a semiconductor memory device having an AVE type capacitor and a semiconductor device having a peripheral circuit section, a step of opening a portion of the peripheral circuit section to be a resistance element in the first interlayer film, and the opening. A step of depositing a first conductive film used for forming a capacitor lower electrode contact of the semiconductor memory device, a step of forming a second interlayer film on the first conductive film, and a step of forming the second interlayer film on the first conductive film. A step of forming an opening in the interlayer film, which becomes the resistance element of the peripheral circuit portion reaching the first conductive film, and a second conductive film used for forming a capacitor lower electrode of the semiconductor memory device in the opening. Since the step of depositing and forming the resistance element composed of the first and second conductive films and the step of forming the joint connecting the resistance element and the upper layer wiring are performed, the number of wirings and the mask overlapping are provided. Without increasing the number of times (the number of steps), it is possible to suppress the increase of the chip area compared to the case where the diffusion resistance on the active area of the field is used, and since the diffusion resistance is not used, the variation of the resistance value can be reduced. In addition to being able to reduce the size and improve the quality of the product, the yield of products and the production efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process for the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process for the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process for the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

1 silicon substrate, 3 diffusion layer, 4 element isolation insulating film, 7 doped amorphous silicon plug (BS plug), 8 first interlayer silicon oxide film,
10 storage node contact, 11 third interlayer silicon oxide film, 12 storage node (capacitor lower electrode), 13 capacitive insulating film, 14
Cell plate (capacitor upper electrode), 15 aluminum wiring, 16 fourth interlayer silicon oxide film, 1
7 Fifth interlayer silicon oxide film, 18 1st W plug,
19 Second W plug, 20 Second interlayer silicon oxide film.

Claims (10)

[Claims] 1. A semiconductor device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit section, wherein a resistance element formed by using a conductive film of a capacitor lower electrode of the semiconductor memory device is provided in the peripheral circuit section. A semiconductor device characterized by being provided. 2. A semiconductor device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit section, wherein a resistance element formed by using a conductive film of a capacitor upper electrode of the semiconductor memory device is provided in the peripheral circuit section. A semiconductor device characterized by being provided. 3. A semiconductor memory device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit portion, wherein the peripheral circuit portion is formed by using a conductive film for a capacitor lower electrode and a capacitor lower electrode contact of the semiconductor memory device. A semiconductor device comprising: 4. The semiconductor memory device is a DRAM or a DRAM embedded LSI.
3. The semiconductor device according to any one of 3 above. 5. The semiconductor device according to claim 1, wherein doped amorphous silicon or doped polysilicon is used as the conductive film. 6. A method of manufacturing a semiconductor memory device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit section, wherein a step of opening a portion of the peripheral circuit section to be a resistance element in an interlayer film on the semiconductor substrate, A step of depositing a conductive film used for forming a capacitor lower electrode of the semiconductor memory device to form a resistance element in the opening portion, and a step of forming a bonding portion connecting the resistance element and an upper layer wiring are provided. A method for manufacturing a semiconductor device, comprising: 7. A method of manufacturing a semiconductor memory device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit section, wherein a step of opening a portion of the peripheral circuit section to be a resistance element in an interlayer film on the semiconductor substrate, A step of depositing a conductive film used for forming a capacitor upper electrode of the semiconductor memory device to form a resistance element in the opening portion; and a step of forming a junction connecting the resistance element and the upper wiring. A method for manufacturing a semiconductor device, comprising: 8. A method for manufacturing a semiconductor memory device having a CONCAVE type capacitor and a semiconductor device having a peripheral circuit section, wherein a portion of the peripheral circuit section, which will be a resistance element, is opened in a first interlayer film. A step of depositing a first conductive film used for forming a capacitor lower electrode contact of the semiconductor memory device in the opening, and a step of forming a second interlayer film on the first conductive film. A step of opening a portion of the peripheral circuit portion that will be a resistance element reaching the first conductive film in the second interlayer film, and a step of forming a capacitor lower electrode of the semiconductor memory device in the opening portion. The method further comprises the steps of depositing a second conductive film to form a resistance element composed of the first and second conductive films, and forming a junction connecting the resistance element and the upper wiring. Manufacturing method of semiconductor device. 9. The semiconductor memory device according to claim 6, wherein the semiconductor memory device is a DRAM or a DRAM embedded LSI.
9. The method for manufacturing a semiconductor device according to any one of 8. 10. The method of manufacturing a semiconductor device according to claim 6, wherein doped amorphous silicon or doped polysilicon is used as the conductive film.