JP2003168973A - Clock recovery circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a voltage control oscillator is made up of, e.g. many differential inverters mutually connected to each other in series, multiplicity-phase clocks usable as reproduction clocks can be generated, but an increased number of such differential inverters involves increase of a circuit scale and current consumption. <P>SOLUTION: A plurality of first clocks higher in frequency than a clock to be reproduced are generated by an oscillator, and the first clocks are frequency-divided into second clocks of multiplicity phases usable as reproduction clocks. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for recovering a clock so as to be synchronized with received data, and a clock / data recovery circuit equipped with this clock recovery circuit.

[0002]

2. Description of the Related Art Today, with the spread of local area networks and the Internet, the transmission capacity and transmission speed in data communication are increasing.

Equipment for data communication (hereinafter referred to as "node")
Say. Data is exchanged between each other according to a predetermined interface standard. USB (un
iversal serial bus), SSA (serial storage archi
tecture), Ethernet (trademark name), IE
EE (institute of electrical and electronics engi
neers) 1394, fiber channel
Various interface standards are known.

In many interface standards, data is transmitted under a predetermined frequency. A node that has received the transmission data can theoretically decode the reception data by synchronizing with the reception data using a clock having the same frequency as the frequency predetermined by the interface standard.

However, the frequency of the internal clock of each node has a unique value for each node. For example, even between nodes having the same nominal clock frequency, there is a maximum error of about ± 100 ppm in the frequency of the clock generated by these nodes. Also, the received data inevitably contains jitter.

Therefore, particularly in a node which transmits and receives data at a high speed, a process for decoding the content of the received data at its own clock frequency is performed prior to the decoding of the received data. This process depends on what standard the transmitted data is encoded under.

For example, Gigabit Ethernet, IEEE
According to standards such as E1394b and Fiber Channel, 8B1
Data is encoded under the 0B encoding method and transmitted serially. In this encoding method, 2-bit redundant data is added to continuous 8-bit data and converted into 10-bit data.

The node that receives the data created under the 8B10B encoding system first removes the jitter in the received data by using the clock / data recovery circuit.

FIG. 11 schematically shows an example of a clock / data recovery circuit (hereinafter abbreviated as "CDR circuit"). A CDR circuit 200 shown in the figure is a phase locked loop circuit (hereinafter, abbreviated as “PLL circuit”) 10.
And one of the first clocks Φ1 to Φn (n is an integer of 2 or more) supplied from the PLL circuit 10, one first clock Φx (x is an integer of 1 to n). (Represented.) As a reproduction clock Cr, a feedback circuit 30 for the multiplexer 20, and a reproduction data generator 50 that receives the supply of the reproduction clock Cr and the received data D to generate reproduction data.

The PLL circuit 10 includes a voltage controlled oscillator (VC
O) 11 generates a plurality of first clocks Φ1 to Φn having the same frequency and deviated by a constant phase, for example, ten phase first clocks Φ1 to Φ10 deviated by 1/10 of one cycle. First clock Φ1 to Φn
In order to maintain each frequency at a predetermined frequency, a part of the output from the voltage controlled oscillator 11 is supplied to the frequency divider 12 and is frequency-divided under a predetermined frequency division ratio to obtain a phase / frequency detector. 13 is supplied.

The phase / frequency detector 13 detects, for example, the phase and frequency of the reference clock Cf supplied from the original oscillation and the phase and frequency of the signal supplied from the frequency divider 12, and based on these differences. To generate a predetermined signal. This signal is supplied to the loop filter 14 having a charge pump and converted into a DC voltage signal. This DC voltage signal becomes a control signal for the voltage controlled oscillator 11.

Each of the first clocks Φ1 to Φn generated by the voltage controlled oscillator 11 is a multiplexer 20
Is supplied to. The multiplexer 20 receives the first signal based on the control signal Sc supplied from the feedback circuit 30.
Select one of the clocks Φ1 to Φn,
This is output as the reproduction clock Cr.

The feedback circuit 30 includes a phase detector 3
3 and a controller 36 having a digital filter.

The phase detector 33 is, for example, a reproduction clock C.
An output signal is generated by detecting a time difference between the rising edge of r and the change in the state of the received data D (rise or fall of the signal), that is, the phase difference between the recovered clock CR and the received data D. In the data created under the 8B10B encoding method, the same bit information does not continue five or more times, so that the phase of the received data D can be easily detected.

Controller 36 with digital filter
The digital filter integrates the output signal of the phase detector 33. When this integrated value exceeds a predetermined value, the control device 3
6 generates the control signal Sc, and the multiplexer 2 moves in the direction in which the phase of the reproduction clock Cr matches the phase of the received data D.
0 is feedback-controlled.

For example, when the phase of the reproduction clock Cr is behind the phase of the received data D, the control device 36 supplies the control signal Sc indicating that the phase of the reproduction clock Cr is behind to the multiplexer 20, and The multiplexer 20 is controlled so that the first clock having the advanced phase is output as the reproduction clock Cr. The frequency of the reproduction clock Cr is adjusted to the frequency of the received data D by sequentially changing the phase of the reproduction clock Cr stepwise.

The PLL circuit 10, the multiplexer 20, and the feedback circuit 30 form a clock recovery circuit 140.

The reproduction data generator 50 has a reproduction clock C.
By receiving r and the received data D and latching the received data D according to the reproduced clock Cr, reproduced data (retimed data) Dr is generated.

The first clock itself generated in the PLL circuit 10 in the CDR circuit 200 described above has a clock frequency specific to the node itself that has received the data. As described above, the maximum clock frequency and the clock frequency of the node on the data transmitting side differ from each other by about ± 100 ppm.

However, by matching the phase of the reproduced clock Cr with the phase of the received data D by the clock recovery operation, the reproduced clock CR has a frequency that matches the clock frequency of the other party (the node on the data transmitting side). Become. Therefore, the received data D can be accurately latched by the reproduced data generator 50, and the jitter can be removed from the received data D.

The received data D from which the jitter has been removed, that is, the reproduction data Dr, is then synchronized with the reproduction clock Cr, for example, first-in first-out (FI).
FO) buffer.

The receiving side node reads the reproduced data Dr written in the FIFO buffer in synchronization with its own internal clock and decodes it.

[0023]

For example, a five-stage differential inverter array having five differential inverters connected in series with each other, and a differential output of each stage in the differential inverter array is first provided. A voltage-controlled oscillator is configured by using 10 conversion circuits for converting into clocks, and the voltage-controlled oscillator generates 10-phase first clocks whose phases are shifted by 1/10 of one cycle. The reproduced clock Cr can be obtained with a phase resolution of 1 unit interval (UI; unit interval of the received data D).

However, as the transmission capacity has increased in recent years, the jitter tolerance required for the clock / data recovery circuit has become more severe. For example, 0.7U
There is also an application in which a jitter tolerance of I is required.

In order to cope with the jitter tolerance of 0.7 UI, it is advantageous to use a clock recovery circuit having a smaller phase resolution than using a clock recovery circuit having a phase resolution of 0.1 UI.

For example, a nine-stage differential inverter array and one
If the 18-phase first clock is generated using eight conversion circuits, a clock recovery circuit with a phase resolution of about 0.05 UI can be obtained. However, as the number of differential inverters and conversion circuits increases, the circuit scale and current consumption of the voltage controlled oscillator increase.

An object of the present invention is to provide a clock recovery circuit which can generate a multi-phase clock that can be used as a recovered clock with a relatively small circuit scale and current consumption.

Another object of the present invention is to provide a clock / data recovery circuit which can generate a multi-phase clock that can be used as a recovered clock with a relatively small circuit scale and current consumption.

[0029]

According to one aspect of the present invention, (i) a plurality of phases having mutually different phases, each having a first frequency N times higher than the frequency of the clock to be reproduced. An oscillator capable of generating a first clock and outputting the plurality of first clocks in parallel; and (ii) receiving the supply of each of the first clocks, the number of phases is greater than the number of phases of the first clocks. Many, each one of the first frequencies
Clock generated by generating a plurality of second clocks having a second frequency of / N and having mutually different phases, selecting one of the second clocks according to a control signal, and outputting the selected clock as a reproduced clock. Generator and (i
ii) Upon receiving the received data and the reproduction clock,
A clock recovery circuit having a feedback circuit that compares the phase of the received data with the phase of the recovered clock and feedback-controls the recovered clock generator in a direction in which the phase of the recovered clock matches the phase of the received data. Provided.

According to another aspect of the present invention, (i) generating a plurality of first clocks having different phases, each having a first frequency N times higher than the frequency of the clock to be reproduced. An oscillator capable of outputting the plurality of first clocks in parallel, and (ii) the supply of each of the first clocks, the number of phases is greater than the number of phases of the first clocks, each of which is A plurality of second frequencies having a second frequency of 1 / N of the first frequency and having different phases from each other.
A regenerated clock generator capable of generating a clock and selecting one of the second clocks according to a control signal to output as a regenerated clock; (iii) receiving a supply of received data and the regenerated clock A feedback circuit that compares the phase of the received data with the phase of the recovered clock and feedback controls the recovered clock generator in a direction in which the phase of the recovered clock matches the phase of the received data; and (iv) There is provided a clock / data recovery circuit having a reproduction data generator capable of receiving reception data and the reproduction clock and outputting the reception data in synchronization with the reproduction clock.

By making the frequency of each of the first clocks N times higher than the frequency of the reproduction clock, these first clocks are divided into multiple phases, and the second multi-phase clock having the same frequency as the reproduction clock. It will be possible to obtain.

For example, if the frequency of the first clock is doubled the frequency of the reproduction clock, even if the oscillator generates the first clock of 10 phases, it has the same frequency as the reproduction clock and is 1/20 of one cycle. 20-phase second with each phase shifted
The clock can be easily generated with a recovered clock generator.

The circuit for obtaining the second clock can be composed of, for example, a logic circuit using a plurality of flip-flops. Even if the number of stages of the differential inverter array of the voltage controlled oscillator is set to, for example, 9 stages, the circuit scale and the current consumption of the clock recovery circuit can be significantly reduced even when compared with the case of generating a clock of 18 phases. .

[0034]

FIG. 1 schematically shows a clock recovery circuit and a CDR circuit according to a first embodiment.

In the illustrated clock recovery circuit 40, the multiplexer 20 includes a frequency divider 21 and a multi-phase frequency divider 2.
3 and the recovered clock generator 25 are configured, which is a significant difference in configuration from the clock recovery circuit 140 shown in FIG. The CDR circuit 100 shown has the same configuration as the CDR circuit 200 shown in FIG. 11 except for the presence or absence of the frequency divider 21 and the multiphase frequency divider 23. Among the constituent elements shown in FIG. 1, those common to the constituent elements shown in FIG. 11 are designated by the same reference numerals as those used in FIG. 11, and the description thereof will be omitted.

In the illustrated CDR circuit 100, the voltage controlled oscillator 11 constituting the PLL circuit 10 generates the first clocks φ1 to φn (n represents an integer of 2 or more) of a predetermined number of phases. The frequencies of the first clocks φ1 to φn are the first clocks generated by the CDR circuit 200 shown in FIG.
Unlike the frequencies of the clocks Φ1 to Φn, it is N times, for example, twice as high as the frequency of the reproduction clock Cr. The frequency divider 12 shown in FIG. 1 and the frequency divider 12 shown in FIG. 11 have different frequency division rates.

One clock φx of the first clocks φ1 to φn (x represents one integer of 1 to n).
Is supplied to the frequency divider 21. Also, the first clock φ1
Each of ~ φn is supplied to the multi-phase divider 23.

The frequency divider 21 divides the first clock φx to generate a clock χ0 and supplies it to the multi-phase frequency divider 23. The frequency of the clock χ0 is the same as the frequency of the reproduction clock Cr.

The multi-phase frequency divider receives the clock χ0 and the first clocks Φ1 to Φn to generate the 2n-phase second clocks χ1 to χ2n and supplies them to the multiplexer 20. Each of the second clocks χ1 to χ2n has the same frequency as the reproduction clock Cr to be generated.

The multiplexer 20 is controlled by the feedback circuit 30 and has a predetermined second clock χx.
(X represents one integer of 1 to 2n) is selected and output as the reproduction clock Cr.

PLL circuit 10, recovered clock generator 2
5, and the feedback circuit 30 constitutes a clock recovery circuit 40.

The CDR circuit 100 is the CD shown in FIG.
Like the R circuit 200, it has a reproduction data generator 50.
The reproduced data generator 50 latches the received data D in accordance with the reproduced clock Cr to generate reproduced data (retimed data) Dr.

For example, if the frequency of each of the first clocks φ1 to φn is doubled the frequency of the reproduction clock Cr, the voltage-controlled oscillator 11 causes the 10-phase first clocks φ1 to φ10.
Even if is generated, the phase is shifted by 1/20 of one cycle by halving the frequency division ratio of the frequency divider 21.
The second phase clocks χ1 to χ20 can be easily generated by the multiphase divider 23.

The frequency divider 21 and the multi-phase frequency divider 23 can be constituted by a logic circuit using a flip-flop, for example. Even if the number of stages of the differential inverter array IA of the voltage controlled oscillator 11 is set to, for example, 9 to generate 18-phase clocks and the reproduction clock CR is selected from these 18-phase clocks, clock recovery is performed. The circuit scale and current consumption of the circuit 40 and the CDR circuit 100 can be significantly reduced.

Hereinafter, the voltage controlled oscillator 11, the frequency divider 21,
And the multi-phase divider 23, the second clock χ of 20 phases that are out of phase by 1/20 of one cycle
This will be described more specifically by taking the case of generating 1 to χ20 as an example.

FIG. 2 schematically shows the voltage controlled oscillator 11. In the voltage controlled oscillator 11 shown in the figure, the five differential inverters 11A to 11E form a five-stage differential inverter array IA. Individual differential inverters 11A-11E
Receives a control signal (DC voltage signal) CV from the loop filter 14 having the charge pump shown in FIG.

The first-stage differential inverter 11A receives the inverted output Os5 and the non-inverted output Es5 from the final-stage differential inverter 11E, and supplies the inverted output Os1 and the non-inverted output Es1 to the second-stage differential inverter 11B. Supply. The differential inverter 11B supplies the inverting output Os2 and the non-inverting output Es2 to the third-stage differential inverter 11C, and the differential inverter 11C supplies the inverting output Os3 and the non-inverting output Es3 to the fourth-stage differential inverter 11D. Supply. The final stage differential inverter 11E receives the inverted output Os4 and the non-inverted output Es4 from the fourth stage differential inverter 11D, and generates the above-described inverted output Os5 and the non-inverted output Es5.

Two differential inverters 11A to 11E are provided in each stage.
A total of ten conversion circuits 11a to 11j are arranged corresponding to each one.

One of the two conversion circuits corresponding to one differential inverter receives the inverting output from the corresponding differential inverter at the inverting input terminal (-) and the non-inverting output at the non-inverting input terminal. In response to (+), a predetermined first clock is generated. The other conversion circuit receives the inverting output from the corresponding differential inverter at the non-inverting input terminal (+) and the non-inverting output at the inverting input terminal (−) to generate a predetermined first clock.

Since the illustrated voltage controlled oscillator 11 has ten conversion circuits 11a to 11j, it has a first phase of 10 phases.
It is possible to generate the clocks φ1 to φ10 and output the first clocks φ1 to φ10 in parallel. The phases of the first clocks generated by the two conversion circuits corresponding to one differential inverter are shifted from each other by ½ of one cycle.

The configuration of the differential inverter and the conversion circuit is
A more specific description will be given with reference to FIGS. 3 and 4.

FIG. 3 is a circuit diagram showing an example of the differential inverter. The differential inverter shown in the figure corresponds to the differential inverter 11A shown in FIG. The other differential inverters 11B to 11E shown in FIG. 2 can also have the same configuration as the differential inverter 11A described below.

The illustrated differential inverter 11A has a pair of transistors Q1 and Q2 whose sources are commonly connected and connected to the current source CS1. The gate of the transistor Q1 has a differential inverter 11 at the final stage shown in FIG.
The inverted output Os5 is supplied from E. Transistor Q2
The gate of the differential inverter 11E has a non-inverted output E
s5 is supplied.

A variable current source CS3 and a diode-connected load transistor Q3 are connected to the drain of the transistor Q1. A variable current source CS5 and a diode-connected load transistor Q5 are connected to the drain of the transistor Q2. Load transistor Q3
Potential at the drain side junction point N1 of the load transistor Q5 becomes the inverted output Os1, and the drain side junction point N2 of the load transistor Q5
Potential becomes the non-inverting output Es1.

Each of the variable current sources CS3 and CS5 is controlled by a control signal (DC voltage signal) CV supplied from the loop filter 14 having the charge pump shown in FIG. 1, and outputs a current of a predetermined value. For example, the current source CS1
Is a variable current source CS
Each of 3 and CS5 sends a standard current of 700 μA in a predetermined direction.

When the gate potential of the transistor Q1 is higher than that of the transistor Q2, the transistor Q1
1 is turned on and the transistor Q2 is turned off.

At this time, 6 output from the current source CS1
All the current of 00 μA flows through the transistor Q1. On the other hand, a standard current of 700 μA flows from the variable current source CS3 connected to the drain of the transistor Q1. Therefore, the current of 100 μA is subtracted from the load transistor Q.
Pour into 3. Moreover, since the transistor Q2 is in the off state, all the current of 700 μA from the variable current source CS5 connected to the drain of the transistor Q2 flows into the load transistor Q5.

Since the load transistor Q3 is diode-connected, the drain potential of the load transistor Q3 changes from the ground level according to the current supplied to the drain. The greater the current drawn, the higher the drain potential will be above ground level. The same applies to the load transistor Q5.

As described above, the load transistor Q3 has 10
A current of 0 μA flows and 700 μ is applied to the load transistor Q5.
When the current A flows, the potential at the junction point N1 shown in the figure becomes lower than the potential at the junction point N2. The inverted output Os1 that is the potential of the junction point N1 becomes smaller than the non-inverted output Es1 that is the potential of the junction point N2.

That is, Os5 is applied to the differential inverter 11A.
When a differential input> Es5 is given, the differential inverter 11A produces a differential output Es1> Os1. The phase of the input differential input signal is inverted and a differential output signal is output.

When the state of the differential input signal is switched, the state of the differential output signal is switched accordingly. At this time, a signal transmission is delayed, and this delay time determines the oscillation frequency of the voltage controlled oscillator 11. The delay time is determined by the current value passed through the load transistors Q3 and Q5. The larger this current value, the shorter the delay time and the higher the oscillation frequency.

The value of the current flowing through the load transistors Q3 and Q5 is controlled by the control signal CV. For example, when the currents from the variable current sources CS3 and CS5, which are 700 μA as standard, respectively become 800 μA, the current flowing to the load transistor Q3 increases from 100 μA to 200 μA when Os5> Es5, and the current flowing to the load transistor Q5 becomes Increase from 700 μA to 800 μA. As a result, the voltage controlled oscillator 11 oscillates at a higher frequency than the standard.

FIG. 4 shows a first output from the differential inverter.
It is a circuit diagram which shows an example of the conversion circuit which converts into a clock. The conversion circuit shown in the figure is the same as the conversion circuit 11 shown in FIG.
It corresponds to a. Other conversion circuits 11b to 11 shown in FIG.
j can also have the same configuration as that of the conversion circuit 11a described below.

The illustrated conversion circuit 11a has a transistor Q10 whose gate receives the inverted output Os1 from the differential inverter 11A, and a transistor Q11 whose gate receives the non-inverted output Es1. .

The drain of the transistor Q10 is connected to the drain of the transistor Q12.
Is connected to the drain of the transistor Q13.

The transistor Q12 is diode-connected, and the gate of the transistor Q12 and the transistor Q12 are connected to each other.
The gate of 13 is connected to each other to form a current mirror circuit.

An inverting input terminal (not shown) is connected to the gate of the transistor Q10, and a non-inverting input terminal (not shown) is connected to the gate of the transistor Q11. The output terminal Out is connected to a wiring L connecting the drain of the transistor Q13 and the drain of the transistor Q11.

The potential of the non-inverted output Es1 is the inverted output Os1.
When the potential is higher than the potential of the transistor Q10, the current flowing through the transistor Q10 is Ineg and the current flowing through the transistor Q11 is Ipos.
Then, the current Ineg tends to flow into the output terminal Out, and the current Ipos tends to flow out from the output terminal Out.
However, the current Ipos at this time is larger than the current Ineg. As a result, the potential of the output terminal Out is lowered to the ground potential. The first clock φ1 at the ground potential is output from the output terminal Out.

On the other hand, when the potential of the non-inverting output Es1 is lower than the potential of the inverting output Os1, the current Ineg is the current Ieg.
Since it is larger than pos, the potential of the output terminal Out is raised. The first clock φ1 having the raised potential is output from the output terminal Out.

In the voltage controlled oscillator 11 having the differential inverter and the conversion circuit configured as described above, the output from each differential inverter can be shifted by ⅕ of one cycle. Two conversion circuits corresponding to one differential inverter can generate two first clocks that are out of phase with each other. As a result of the above, ten first clocks φ1 to φ1 whose phases are shifted by 1/10 of one cycle
φ10 can be obtained.

FIG. 5 shows the differential inverters 11A, 11B,
And the differential output from 11E and each conversion circuit 11a-1
It is a timing chart which shows the relationship with the output from 1j.

As shown in the figure, the differential inverter 11A
The non-inverted output Es1 and the inverted output Os1 from the
It has a cycle T corresponding to the time difference between 2 and time t1. The differential outputs from the other differential inverters 11B to 11E also have the same cycle T. From the differential inverter 11A to the differential inverter 11E, the phase of each differential output lags behind the differential output from the preceding differential inverter by T / 5.

Since the differential output from the differential inverter has the period T, each of the first clocks φ1 to φ10 output from the conversion circuits 11a to 11j also has the period T.

From one conversion circuit, one clock which rises under the period T in synchronization with the time when the waveforms of the differential outputs from the differential inverters to which the conversion circuit corresponds intersects, and this clock. Clocks of opposite phase to and are output. In FIG. 3, the time at which the waveforms of the differential outputs Os2 and Es2 from the differential inverter 11B cross each other is t3.
, The differential output Os5 from the differential inverter 11E,
The time when the waveforms of Es5 intersect each other is shown by t4.

Since the phase of the differential output of each of the differential inverters 11A to 11E is delayed by T / 5 with respect to the differential output from the differential inverter in the preceding stage, the two clocks output from the individual conversion circuits. The phase also lags behind the clock output from the conversion circuit at the preceding stage by T / 5.

When the clocks φ1 to φ10 shown in FIG. 2 are arranged in this order, the respective phases are shifted by T / 10 from the clock φ1 to the clock φ10. That is, the voltage-controlled oscillator 11 shown in FIG. 2 can generate 10-phase clocks φ1 to φ10 whose phases are shifted by T / 10.

Next, these first clocks φ1 to φ10
With reference to FIGS. 6 and 7, the configuration of the regenerated clock generator 25 for generating the 20-phase second clocks χ1 to χ20 using explain.

As shown in FIG. 6, the frequency divider 21 has one D
-A flip-flop (hereinafter, the D-flip-flop is abbreviated as "DFF").

A predetermined first clock selected from the 10-phase first clocks φ1 to φ10 is supplied to the clock input terminal CK of the frequency divider 21, and the complement output q of the frequency divider 21 is supplied to the frequency divider 21. Becomes the input D of. As the first clock supplied to the frequency divider 21, the output Q from the frequency divider 21 is at a high level when the first clock supplied to the first-stage frequency divider (DFF) of the multi-phase frequency divider 23 rises. It is desirable to have a phase that will be settled at either the low level or the low level. In the illustrated example, the first clock φ6 is supplied to the frequency divider 21.

The frequency divider 21 is constructed so that its output Q becomes a clock χ0 corresponding to a clock obtained by dividing the first clock φ6 by 1/2.

The multi-phase divider 23 can be composed of the same number of DFFs as the number of phases of the second clock to be generated, that is, 20 DFFs 23a to 23t.
These DFFs 23a to 23t are connected in series with each other, and the first-stage DFF 23a is connected to the frequency divider 21 in series. In FIG. 6, for convenience, seven DFFs 23a to 23c,
23j, 23k, 24s, and 23t are shown.

In the illustrated multi-phase divider 23, the DF of the first stage is
The first clock φ1 is supplied to the clock input terminal CK of the F23a, and the clock input terminals CK of the second and subsequent DFFs 23b to 23t are delayed by T / 10 in phase from the first clock supplied to the DFF of the previous stage. The first clock is also supplied. One 1st clock every DF
Supplied to F.

The clock χ0 output from the frequency divider 21 is supplied to the D input terminal of the DFF 23a in the first stage, and the output Q of the DFF in the previous stage is supplied to the D input terminals of the DFFs 23b to 23t in the second and subsequent stages. . DFF 23a-23
Each t latches the first clock input to the clock input terminal CK with the output Q supplied to the D input terminal from the previous DFF to generate the output Q.

The output Q of each of the DFFs 23a to 23t becomes the second clock. Twenty-phase second clocks χ1 to χ20 having a phase difference of 1/20 of one cycle are generated. From the first DFF 23a to the last DFF 23t,
The second clocks χ1 to χ20 are generated in this order.

FIG. 7 is a timing chart schematically showing the first clocks φ1 to φ20, the clock χ0, and the second clocks χ1 to χ20.

As shown in the figure, the clock χ0 has a cycle twice that of each of the first clocks φ1 to φ10, and
Each of the clocks χ1 to χ20 is also the first clock Φ1 to Φ
It has twice as many cycles as 10 each.

When one of the first clocks rises at a certain time, after a lapse of a predetermined delay time, the second clock generated by one of the two DFFs supplied with the first clock rises. At this time, the second clock generated by the other of the two DFFs falls. After a lapse of a predetermined delay time from the time when the first clock rises next,
The second clock generated by one of the two DFFs falls, and the second clock generated by the other of the two DFFs rises.

The above delay time is determined by the propagation delay time of the DFF. D using a transistor with a short gate length
When the FF is configured, this delay time becomes short.

For example, when the first clock φ1 rises at time t10, the second clock χ1 generated in the DFF 23a receiving the supply of the first clock φ1 rises with a slight delay. At this time, the second clock χ11 generated in the DFF 23k receiving the supply of the first clock φ1 falls. Time t11 when the first clock φ1 next rises
After a slight delay, the second clock χ1 falls and the second
The clock χ11 rises.

When the first clock φ2 rises at time t12, the second clock χ2 generated in the DFF 23b receiving the supply of the first clock φ2 rises with a slight delay. At this time, D receiving the supply of the first clock φ2
The second clock χ12 (not shown in FIG. 7) generated by the FF 23l falls. The second clock χ2 falls and the second clock χ12 rises with a slight delay at time t13 when the first clock φ2 next rises.

Similarly, at time t14, the first clock φ10
Rises, the second clock χ generated in the DFF 23k receiving the first clock φ10 is slightly delayed.
10 stands up. At this time, the second clock χ20 generated by the DFF 23t receiving the supply of the first clock φ10 falls. The second clock χ10 falls and the second clock χ20 rises with a slight delay at time t15 when the first clock φ10 next rises.

The second clock χ thus generated
1 to χ20 are supplied to the multiplexer 20 (see FIG. 1). The multiplexer 20 includes a feedback circuit 30.
Controlled by a predetermined second clock χx (x is 1
Represents an integer of 1 to 20. ) Is selected and is output as the reproduction clock Cr.

Next, the operation of the clock recovery circuit 40 provided with the recovered clock generator 25 configured as described above will be described with reference to FIG.

FIG. 8 shows received data D and reproduced clock C.
r, the control signals Sc1 and Sc2 from the control device 36 having a digital filter, and the second clocks χn and χm (n and m, which are selected as the reproduction clock Cr, each represent an integer of 1 to 20). Is a schematic timing chart.

In the illustrated example, from time t20 to time 23, the rising edge of the received data D and the rising edge of the reproduction clock Cr are synchronized. The second clock χn selected by the control signal Sc1 generated by the control device 36 is
It is output as the reproduction clock Cr from the reproduction clock generator 25.

At time t24, the phase difference between the reproduced clock Cr and the received data D becomes a predetermined value or more, and the control device 36 generates the control signal Sc2. This control signal Sc2
Accordingly, the multiplexer 20 is set to the second position after the time t25.
The clock χm is output as the reproduction clock.

As the second clock χm, the phase of the reproduction clock Cr lags behind the phase of the reproduction data D at the time t24. Therefore, a clock whose phase is advanced by 1/20 of one cycle from the second clock χn. Is selected.

As a result, at times t26 and t27, the rising edge of the received data D and the reproduced clock Cr
The rising edge of is synchronized again.

The controller 36 controls the reproduction clock Cr.
The control signal Sc is generated when the phase shift between the received data D and the received data D occurs a plurality of times in the same direction, that is, when it is determined that the phase of the reproduction clock Cr and the phase of the received data D are truly deviated. Is composed of. Received data D
Since jitter is superimposed on, the phase of the recovered clock Cr and the phase of the received data D do not actually deviate,
There is a case where these phases are deviated and detected. This erroneous determination randomly occurs at random. By smoothing the phase shift using a digital filter, the cause of erroneous determination can be eliminated.

The multiplexer 20 uses the new control signal S
When the supply of c is received, a predetermined second clock whose phase is one stage, that is, 1/20 of one cycle in the example shown in the figure, which is ahead or behind, is selected as the reproduction clock in response to the control signal Sc. And output.

By constructing the clock recovery circuit 40 using the reproduced clock generator 25 described above, even if the 10-phase first clocks φ1 to φ10 are generated by the voltage controlled oscillator 11, as described above, 20-phase second clocks χ1 to χ2 that can be used as clocks
You can get 0. By setting the number of stages of the differential inverter array IA of the voltage controlled oscillator 11 to nine, for example, 18
Even if the clocks of the number of phases are generated and the reproduction clock CR is selected from the 18-phase clocks, the circuit scale and current consumption of the clock recovery circuit 40 and the CDR circuit 100 can be significantly reduced.

For example, even when it is used for an application where a jitter tolerance of 0.7 UI is required, a large number of second clocks whose phases are slightly shifted are generated without increasing the circuit scale and current consumption, and reproduced from them. Since the clock can be selected, it becomes easy to accurately reproduce the received data D.

The reproduction data (retimed data) Dr is
The received data D and the reproduction clock are reproduced data generator 50.
And latch the received data D in accordance with the reproduction clock Cr.

Next, a clock recovery circuit and a CDR circuit according to the second embodiment will be described with reference to FIGS. 9 and 10.

The clock recovery circuit and the CDR circuit according to the present embodiment are the same as the first embodiment except for the configuration of the multiphase divider.
Clock recovery circuit 40 or CD according to the embodiment of
It has the same configuration as the R circuit 100. Here, only the configuration of the multi-phase divider will be described in detail, and the description of the other configurations will be omitted.

FIG. 9 schematically shows the configuration of a frequency divider and a multi-phase frequency divider connected to this frequency divider. The frequency divider is shown in Figure 6.
Since it has the same configuration as the frequency divider 21 shown in FIG. 6, the same reference numeral 21 as that used in FIG. 6 is given and its description is omitted. The frequency divider 21 shown in FIG.
4 is being supplied.

The configuration itself of the illustrated multiphase divider 123 is
It is similar to the multiphase divider 23 shown in FIG. Individual D
The first clock supplied to the FFs 123a to 123t is
It is different from the multiphase divider 23 shown in FIG. In Figure 9,
For convenience, seven DFFs 123a to 123c, 123j,
123k, 124s, and 123t are shown.

In this multiphase divider 123, the DF of the first stage is
First clock φ1 at the clock input terminal CK of F123a
Is supplied to the clock input terminal CK of each of the second and subsequent DFFs 123b to 123t, and the first clock whose phase is delayed by 3/10 of one cycle from the first clock supplied to the DFF in the previous stage is supplied. . One first clock is supplied to every 9th DFF.

The output Q of each of the DFFs 123a to 123t becomes the second clock. Twenty-phase second clocks χ1 to χ20 having a phase difference of 1/20 of one cycle are generated. From the first DFF 123a to the last DFF 123t
The second clock whose phase is delayed by 3/20 of one cycle is generated over the period.

FIG. 10 is a timing chart schematically showing the first clocks φ1 to φ20, the clock χ0, and the second clocks χ1 to χ20.

As shown in the figure, the clock χ0 has a period twice that of each of the first clocks φ1 to φ10, and
Each of the clocks χ1 to χ20 is also the first clock Φ1 to Φ
It has twice as many cycles as 10 each.

When one first clock rises at a certain time, after a lapse of a predetermined delay time, the second clock generated by one of the two DFFs supplied with the first clock rises. At this time, the second clock generated by the other of the two DFFs falls. After a lapse of a predetermined delay time from the time when the first clock rises next, the second clock generated by one of the two DFFs falls and the second clock generated by the other DFF rises.

For example, when the first clock φ1 rises at the time t30, the first clock φ1 is passed after the elapse of a predetermined delay time.
The second clock χ1 generated in the DFF 123a receiving the supply of 1 rises. At this time, the second clock χ11 generated in the DFF 123k receiving the supply of the first clock φ1 falls. The second clock χ1 falls after a lapse of a predetermined delay time from time t31 when the first clock φ1 next rises. At this time, the second clock χ11
Stands up.

When the first clock φ4 rises at time t32, after the elapse of a predetermined delay time, the second clock χ4 generated in the DFF 123b receiving the supply of the first clock φ4.
Stands up. At this time, the second clock χ14 generated in the DFF 123l receiving the supply of the first clock φ4 falls. Time t at which the first clock φ4 rises next
After a lapse of a predetermined delay time from 33, the second clock χ4 falls and the second clock χ14 rises.

When the first clock φ7 rises at time t34, the second clock χ7 generated by the DFF 123c receiving the supply of the first clock φ7 after the elapse of a predetermined delay time.
Stands up. At this time, the second clock χ17 generated in the DFF 123m receiving the supply of the first clock φ7 falls. Time t when the first clock φ7 next rises
After a lapse of a predetermined delay time from 35, the second clock χ7 falls and the second clock χ17 rises.

Thereafter, similarly, each DFF 123d-12d
A predetermined second clock is also generated at 3t. When the second clocks χ1 to χ20 are generated in this manner, the circuit scale and current consumption of the clock recovery circuit and the CDR circuit can be significantly reduced, and also the data transmission speed can be easily increased. It also becomes possible.

For example, the CDR circuit 2 according to the first embodiment
00, a DFF of a stage in the multi-phase divider 23
The phase of the first clock supplied to the
1/1 of one cycle than the phase of the first clock supplied to
Only 0 is late. As a result, when the frequency of the first clock itself is increased to cope with the increase in the data transmission speed, in other words, when the cycle of the first clock itself is shortened, one cycle of the first clock A reversal phenomenon may occur in which the delay time in each of the DFFs 23a to 23e becomes longer than 1/10.

When this inversion phenomenon occurs, for example, the rising time of the second clock generated by the DFF in the preceding stage is later than the rising time of the first clock supplied to the DFF in a certain stage. Therefore, it becomes impossible to latch the predetermined first clock by the DFF in the next stage using the second clock. As a result, it becomes impossible for the multiphase divider 23 to generate the desired second clock of 20 phases.

On the other hand, in the CDR circuit according to the second embodiment, the phase of the first clock supplied to the DFF in a certain stage is one cycle longer than the phase of the first clock supplied to the DFF in the preceding stage. It is 3/10 late. Therefore, compared with the CDR circuit 200 according to the first embodiment,
Even if the frequency of the first clock is increased, the above-mentioned inversion phenomenon hardly occurs. After the output of the second clock from the DFF of a certain stage is confirmed, the DCK of the next stage is used by using this second clock.
The FF facilitates surely latching the predetermined first clock. As a result, the desired 20-phase second
Easy to get a clock. It is easy to deal with higher data transmission speeds.

Although the clock recovery circuit and the CDR circuit according to the embodiments have been described above, the present invention is not limited to the above embodiments.

For example, the oscillator for generating the first clock is preferably a voltage controlled oscillator forming a PLL circuit, but is not limited to this voltage controlled oscillator. When a PLL circuit is used, this PLL circuit can also be configured to be able to generate a plurality of types of first clocks having different frequencies.

The frequency divider and the multi-phase frequency divider constituting the regenerated clock generator are preferably constituted by logic circuits from the viewpoint of reducing the circuit scale and current consumption. The configurations of these frequency dividers and multi-phase frequency dividers can be changed as appropriate.

The relationship between the frequency of the first clock and the frequency of the second clock, and the relationship between the number of phases of the first clock and the number of phases of the second clock are as follows. It is N times the frequency of the clock (reproduced clock) (N represents a rational number), and the number of phases of the second clock is the first.
It is preferable to select an integer corresponding to N times the number of clock phases. Particularly, N is preferably an integer of 2 or more.

For example, if the 6-phase first clock having a frequency four times the frequency of the reproduction clock is generated, it is possible to generate the 24-phase second clock. The number of phases of the second clock is the clock recovery circuit or CDR.
It can be appropriately selected according to the application of the circuit.

As in the multi-phase divider 123 shown in FIG. 9, the period of the first clock is the number of phases of the first clock from the DFF in the first stage to the DFF in the final stage, which constitutes this multi-phase divider. The first phase shifted by an integer multiple of the divided value
When a clock is supplied, this phase shift is not limited to three times the above value. It can be an integer multiple that is relatively prime to the number of phases of the first clock.

It will be apparent to those skilled in the art that other various modifications, improvements, combinations and the like are possible.

[0127]

As described above, according to the present invention,
A multi-phase clock that can be used as a reproduction clock can be generated with a relatively small circuit scale and current consumption. It becomes easy to provide a highly accurate clock recovery circuit or clock / data recovery circuit that is small in size and consumes less current.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a clock recovery circuit and a clock / data recovery circuit according to a first embodiment.

FIG. 2 is a schematic diagram showing an example of the voltage controlled oscillator shown in FIG.

FIG. 3 is a circuit diagram showing an example of the differential inverter shown in FIG.

FIG. 4 shows the output from the differential inverter shown in FIG.
It is a circuit diagram which shows an example of the conversion circuit which converts into a clock.

5 is a timing chart showing the relationship between the output from the differential inverter shown in FIG. 2 and the output from each conversion circuit shown in FIG.

FIG. 6 is a schematic diagram showing an example of each of a frequency divider and a multi-phase frequency divider constituting a recovered clock generator.

7 is a diagram illustrating a first clock supplied to the multi-phase divider shown in FIG. 6, a clock output from the divider in the regenerated clock generator, and a multi-phase divider shown in FIG. 6 is a timing chart schematically showing an output second clock.

8 is a timing chart schematically showing received data, a reproduction clock, a control signal, and a second clock selected as a reproduction clock in the clock / data recovery circuit shown in FIG.

FIG. 9 is a schematic diagram showing a frequency divider and a multi-phase frequency divider constituting a recovered clock generator in the clock recovery circuit and the clock / data recovery circuit according to the second embodiment.

FIG. 10 is a diagram illustrating a first phase supplied to the multi-phase divider shown in FIG.
10 is a timing chart schematically showing a clock, a clock output from a frequency divider in the recovered clock generator, and a second clock output from the multi-phase frequency divider shown in FIG. 9.

FIG. 11 is a block diagram schematically showing a conventional clock recovery circuit and clock / data recovery circuit.

[Explanation of symbols]

10 ... PLL circuit, 11 ... Voltage controlled oscillator, 20 ...
Multiplexer, 21 ... Divider, 23 ... Multi-phase divider, 25 ... Regenerated clock generator, 30 ... Feedback circuit, 40 ... Clock recovery circuit, 50 ...
Reproduction data generator, 100 ... Clock / data recovery circuit, φ1 to φn ... First clock, χ0 ... Clock, χ1 to χ2n ... Second clock, Cr ... Reproduction clock, Dr ... Reproduction data.

Continued front page    F term (reference) 5J039 EE16 EE24 KK01 KK09 KK10                       KK27 KK29 MM04 MM16 NN01                 5J106 AA04 BB01 CC03 CC20 CC24                       CC30 CC43 CC46 CC52 DD10                       FF04 FF09 KK38 KK39 KK40                       LL01                 5K047 AA05 AA16 GG08 MM11 MM28                       MM33 MM50 MM53 MM55 MM60

Claims (6)

[Claims] 1. A plurality of first clocks having different phases, each having a first frequency N times higher than the frequency of the clock to be reproduced, are generated.
An oscillator capable of outputting clocks in parallel, and a number of phases which is supplied with each of the first clocks and is greater than that of the first clocks, each of which is 1 / Nth of the first frequency. A regenerated clock generator capable of generating a plurality of second clocks having two frequencies and different phases, selecting one of the second clocks according to a control signal, and outputting the regenerated clock. The phase of the received data is compared with the phase of the recovered clock by receiving the received data and the recovered clock, and the recovered clock generator is oriented in a direction in which the phase of the recovered clock matches the phase of the received data. A clock recovery circuit having a feedback circuit for performing feedback control. 2. A frequency divider that divides one of the first clocks to generate a third clock having the same frequency as the reproduced clock; and the second clock of the second clock. The same number of D-flip-flops as the number of phases are connected in series with each other and in series with the frequency divider, and each of the D-flip-flops corresponds to each of the first clocks in a plurality. While being supplied with the first clock, the first stage D-flip-flops supply the third clock as viewed from the frequency divider, and the second-stage and subsequent D-flip-flops supply the output of the preceding stage D-flip-flop. The clock recover unit according to claim 1, further comprising a multi-phase divider having a flip-flop array that receives each of the second clocks and that generates the second clocks each having a different phase. Over circuit. 3. A phase angle of each of the first clocks, which corresponds to a quotient obtained by dividing 2π by the number of phases of the first clock from the D-flip-flop of the first stage to the D-flip-flop of the final stage. The clock recovery circuit according to claim 2, which is offset. 4. The phase of each of the first clocks is the quotient obtained by dividing 2π by the number of phases of the first clock from the D-flip-flop of the first stage to the D-flip-flop of the final stage, and the first clock. 3. The clock recovery circuit according to claim 2, wherein the clock recovery circuit is deviated by a phase angle corresponding to a product obtained by multiplying the number of phases by a number that is relatively prime to the number of phases. 5. The first frequency is an integer multiple of the second frequency, and the number of phases of the second clock is the quotient of the first frequency divided by the second frequency and the first frequency. The clock recovery circuit according to any one of claims 1 to 4, which corresponds to a product of the number of clock phases. 6. A plurality of first clocks having different phases, each having a first frequency N times higher than the frequency of the clock to be reproduced, are generated.
An oscillator capable of outputting clocks in parallel, and a number of phases which is supplied with each of the first clocks and is greater than that of the first clocks, each of which is 1 / Nth of the first frequency. A regenerated clock generator capable of generating a plurality of second clocks having two frequencies and different phases, selecting one of the second clocks according to a control signal, and outputting the regenerated clock. The phase of the received data is compared with the phase of the recovered clock by receiving the received data and the recovered clock, and the recovered clock generator is oriented in a direction in which the phase of the recovered clock matches the phase of the received data. A feedback circuit for performing feedback control of the received data and the received data and the reproduction clock, and synchronizes the received data with the reproduction clock. Clock data recovery circuit having a playback data generator capable of outputting by.