JP2003167030A - Semiconductor integrated circuit - Google Patents

Abstract

(57) Abstract: In a semiconductor integrated circuit, a hold error during a scan test in which a scan chain is configured by a plurality of flip-flops is suppressed. SOLUTION: A scan data input circuit unit 601, a master unit 604S, and a slave unit 605S in a scan flip-flop circuit region 10 other than a unit that performs high impedance control by a clock signal, and a data output buffer unit 606. The substrate potential of a transistor (target transistor) in a portion including any of the above is separated from the source potential of the transistor and the source and substrate potentials of non-target transistors other than the transistor. During normal operation, the substrate potential of the target transistor is used with the same potential as the substrate potential of the non-target transistor.
A test is performed by applying a back bias to the side where the threshold value of the transistor increases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test and test design technique for a semiconductor integrated circuit, and more particularly, in a test mode, a data holding circuit such as a flip-flop is continuously connected in a chain to perform a shift operation. In addition, the present invention relates to a semiconductor integrated circuit that performs a scan shift test for determining whether the pattern processing of the target circuit portion is good or bad.

[0002]

2. Description of the Related Art In recent digital circuit design, a functional description design technique is often used in order to improve design efficiency in response to the increase in circuit scale. The circuit that is logically synthesized from the functional description design is a synchronous design, and many flip-flops that are data holding circuits are used. Since the flip-flop has a large cell area as compared with other logically configured cells such as NAND / NOR, it is common that the flip-flop occupies almost half of the area of the logic portion in terms of area ratio. Further, in the future, in order to realize high speed of LSI in the trend that the fine process becomes low voltage specification and the speed improvement tends to be slowed down, there is a tendency that the number of designs in which the number of logic stages between pipelines and flip-flops is reduced increases in order to realize the high speed of LSI. From the above situation, the flip-flop area ratio in the logic circuit is high, and it is increasing in the future.

The non-defective inspection of the LSI is also important for ensuring the market quality. Since the flip-flop is a sequential circuit,
In order to test efficiently, it is necessary to have a circuit configuration that can arbitrarily control the flip-flop during the test. For that reason,
Although the circuit area increases to some extent, a scan flip-flop circuit whose conceptual diagram is shown in FIG. 21A is used with priority given to the improvement of testability. The scan type flip-flop has a selector 21 that can switch an input to a data flip-flop 22 (hereinafter, simply referred to as a flip-flop) in a test mode and a normal operation mode. In the test mode, the selector 21 responds to the test data D in response to the mode switching signal NT.
T is selected, and in the normal operation mode, normal operation data D is selected and output to the flip-flop 22.

Since the area occupancy of the flip-flop is high as described above, various techniques for efficiently testing the flip-flop have been studied. As a typical method,
In the test mode, scan flip-flops are continuously connected in a chain as shown in FIG.
Call it a scan chain. ), There is a scan shift test (hereinafter, simply referred to as a scan test) for determining pass / fail of pattern processing by causing the scan chain to perform a shift register operation.

Here, a circuit example of a conventional scan flip-flop is shown in FIG. In FIG. 22, 6
Reference numeral 01 is a scan data input circuit unit, 602 is a normal data input circuit unit, 603 is a mode switching circuit unit, 604 is a master unit, 605 is a slave unit, 606 is a data output buffer unit, and 607 is a clock input unit. The clocks CK and / CK (inversion of CK) shown in the clock input unit 607 are the master unit 604 and the slave unit 6 respectively.
05 clocks CK and / CK. According to the mode switching signal NT, the normal operation data D is input to the master unit 604 through the normal data input circuit unit 602 in the normal operation mode, and the test data DT passes through the scan data input circuit unit 601 in the test mode. It is input to 604.

[0006]

The conventional scan test has the following problems.

Since the synchronous clocks are usually the same, in a circuit in which the output of the flip-flop is directly input to the next-stage flip-flop, the scan shift operation can be accurately performed due to the clock timing skew caused by the wiring length difference and the like. There can be no glitches. For example, rather than the clock signal 103 input to the scan flip-flop 101 of FIG.
When the clock signal 104 input to the 2 has a longer wiring length or a larger parasitic capacitance, the data transition of the flip-flop 101 is faster and the flip-flop 1
No data can be captured in 02, and a scan shift operation failure may occur.

The wiring delay difference that causes the scan shift operation failure can be verified to some extent by simulation. However, there are simulation error factors as shown in 1 to 4 below between the actual LSI and the simulation. Since it always exists, it is currently difficult to completely guarantee and partition by simulation.

1. Difference in finish of gate length due to pattern distribution of transistor gate 2. 2. Difference in finish of wiring width and wiring film thickness due to wiring distribution density Difference in finish for each wiring layer 4. In the case of a defect due to insufficient wiring crosstalk setup time, it is possible to avoid the error by lowering the operating frequency during inspection, but in the case of a defective operation due to insufficient hold time, it is not possible to avoid it by changing the operation timing from the outside. It is possible, and as a result, mask correction and re-trial production are required. The hold error in the scan test is a problem to be avoided as much as possible from the viewpoint of the design period rather than the mask cost.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a semiconductor integrated circuit capable of suppressing a hold error (operation failure due to insufficient hold time) during a scan test.

[0011]

A semiconductor integrated circuit according to claim 1 of the present invention comprises a plurality of scan type flip-flop circuits each having a scan data input circuit section and a normal data input circuit section, and a plurality of scans during a scan test. A semiconductor integrated circuit that causes a type flip-flop circuit to function as a shift register, characterized in that a delay element that delays the transmission of scan data is provided in the scan data input circuit unit.

A semiconductor integrated circuit according to a second aspect of the present invention comprises a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit functioning as a register, wherein the scan data input circuit unit has a transistor having a logically redundant conductive state inserted in series with respect to a data input transistor circuit connected between power supply voltages. Is characterized by.

A semiconductor integrated circuit according to a third aspect of the present invention is provided with a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit that functions as a register, wherein a scan data input circuit section includes a data input transistor circuit connected between a first power supply voltage and a second power supply voltage, and the first power supply voltage and the data input transistor circuit. And a diode is inserted in the forward direction between the data input transistor circuit and the second power supply voltage.

A semiconductor integrated circuit according to a fourth aspect of the present invention comprises a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit that functions as a register, wherein a scan data input circuit unit has a load capacitance element provided between an inverter that inputs scan data and a circuit that is connected to the output of the inverter and performs high impedance control. Is characterized by.

According to the first, second, third, and fourth aspects of the invention, the hold time required to latch the scan input data of the scan flip-flop circuit can be improved. Further, when the scan chain is configured by using the normal output terminal, the problem that the normal output cannot be tested which occurs when the scan-dedicated output terminal having the delay element is not generated. Further, the scan chains can be used in combination even when the scan chains are formed using the scan-dedicated output terminals having the delay elements, in which case the margin for the hold error is further increased.

A semiconductor integrated circuit according to a fifth aspect of the present invention is provided with a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit that functions as a register, and scans a transistor that configures a scan-dedicated circuit portion in the scan flip-flop circuit in which data does not pass in the normal operation mode but only scan data in the scan test mode passes. In order to increase the threshold voltage of the transistors forming the other circuit parts except the dedicated circuit part, the impurity concentration of the well region in which the transistors forming the scan-dedicated circuit part are formed is changed by the transistor forming the other circuit part. Impurity concentration of formed well region Characterized in that the remote was high.

According to the fifth aspect of the present invention, in the scan type flip-flop circuit, the threshold value of the transistor forming the scan-dedicated circuit portion through which data does not pass in the normal operation mode but only the scan data passes is another circuit. The threshold value is higher than that of some transistors, and the operation speed becomes slower. As a result, the change in scan data can be made slower than when a delay circuit is configured with the same gate length, gate width, and number of logic stages using low threshold voltage transistors used in other circuit parts. Therefore, it is possible to improve the data hold specification of how much data should be held with respect to the change of the clock so that it cannot be taken into the slave unit side with a smaller area than that of the one configured with the low threshold voltage transistor. Further, since the portion constituted by the high threshold voltage transistor is a region which is not used in the normal operation, the problem of the operation speed in the actual use does not occur. Further, although the portion configured by the high threshold voltage transistor is present even in actual use, the transistor off-leak current can be suppressed smaller than that in the low threshold voltage transistor configuration.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the scan-dedicated circuit portion configured by using a transistor having a high threshold voltage is a scan data input circuit portion. Is characterized in that.

According to the sixth aspect of the present invention, in the scan flip-flop circuit, the scan data input circuit section has a higher threshold than the transistors in other circuit sections. As a result, the data hold specification of how much data should be held with respect to the change of the clock before the data can be fetched to the slave side can be improved in a smaller area than that of the one configured by the low threshold voltage transistor. Since the scan data input circuit section composed of high threshold voltage transistors is a region that is not used in normal operation, the problem of operating speed in actual use does not occur. Also,
By using a high threshold voltage transistor, the transistor off-leakage current can be suppressed smaller than that of the low threshold voltage transistor configuration.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the scan type flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section, and has a high threshold value. The scan-dedicated circuit portion configured by using the voltage-converted transistor is a scan-data-dedicated output circuit portion.

According to the seventh aspect of the present invention, in the scan flip-flop circuit, the threshold value of the transistor forming the scan-dedicated output circuit section becomes higher than the threshold value of the transistor of the other circuit section. As a result, the data output hold time, which is how long the previous data continues to be output after the clock changes, can be made longer than that formed by the low threshold voltage transistor. Also,
Since the scan-dedicated output circuit unit configured by the high threshold voltage transistor is not used in the normal operation, the problem of the operation speed in actual use does not occur. Further, the transistor off-leakage current can be suppressed to be smaller than that of the low threshold voltage transistor configuration by using the high threshold voltage transistor configuration.

A semiconductor integrated circuit according to claim 8 of the present invention comprises a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit that functions as a register, in which the data does not pass in the normal operation mode in the scan flip-flop circuit, and the gate insulation of the transistor that constitutes the scan-dedicated circuit portion through which only the scan data in the scan test mode passes It is characterized in that the film thickness is made thicker than the gate insulating film of the transistors constituting the other circuit portion excluding the scan-dedicated circuit portion.

A semiconductor integrated circuit according to a ninth aspect of the present invention is the semiconductor integrated circuit according to the eighth aspect, wherein the scan-dedicated circuit portion configured by using a transistor having a thick gate insulating film is a scan data input circuit portion. It is characterized by being.

A semiconductor integrated circuit according to a tenth aspect of the present invention is the semiconductor integrated circuit according to the eighth aspect, wherein the scan flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section, and gate insulation. The scan-dedicated circuit portion configured by using a thick-film transistor is a scan-data-dedicated output circuit portion.

According to the eighth, ninth and tenth aspects of the present invention, in the scan flip-flop circuit, the hold characteristic in the scan test can be improved while suppressing the gate leak current. When the threshold voltage of the transistor forming the scan-dedicated circuit portion is the same as that of the transistors in the other circuit portions when the threshold voltage is set and injected, the driving capability can be lowered. This is because the driving current is proportional to the gate oxide film capacitance and the threshold voltage is inversely proportional to the gate oxide film capacitance, so that a transistor having a thick gate oxide film has a high threshold voltage and a low driving capability. Further, even if an optimal transistor is manufactured under the condition that the source and drain have the same off leak between the thick and thin gate oxide films, the transistor having a thick gate oxide film also has a lower driving capability. In addition, since the gate oxide film is thick, it is possible to suppress the gate leak current generated in the extremely thin gate oxide film.

A semiconductor integrated circuit according to claim 11 of the present invention comprises a plurality of scan type flip-flop circuits having a scan data input circuit section and a normal data input circuit section, and shifts the plurality of scan type flip-flop circuits during a scan test. A semiconductor integrated circuit that functions as a register, in which the data does not pass in the scan flip-flop circuit in the normal operation mode, but only the scan data in the scan test mode passes through. Is electrically separated from the substrate potential of the transistors forming the other circuit parts excluding the scan-dedicated circuit part, and the back bias is set on the side where the threshold voltage of the transistor forming the scan-dedicated circuit part becomes higher. And

A semiconductor integrated circuit according to a twelfth aspect of the present invention is the semiconductor integrated circuit according to the eleventh aspect, wherein the scan-dedicated circuit portion in which the back bias is set on the side where the threshold voltage of the transistor is high is the scan data input circuit. It is characterized by being a part.

A semiconductor integrated circuit according to a thirteenth aspect of the present invention is the semiconductor integrated circuit according to the eleventh aspect, wherein the scan type flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section. The scan-dedicated circuit portion in which the back bias is set on the side where the threshold voltage is high is characterized in that it is a scan-data-dedicated output circuit portion.

According to the eleventh, twelfth and thirteenth aspects of the present invention, in the scan flip-flop circuit, the scan-dedicated circuit portion through which only the scan data does not pass in the normal operation mode separates the substrate potential. Since the back bias is applied, the threshold voltage of the transistor becomes high. As a result, the same data hold characteristic improvement and leakage current suppression effect as those of the fifth aspect can be obtained without a process threshold adjustment process step.

A semiconductor integrated circuit according to a fourteenth aspect of the present invention is the semiconductor integrated circuit according to any one of the eleventh to thirteenth aspects, in which the substrate potential of a transistor forming a circuit portion other than the scan-dedicated circuit portion is It is characterized in that a bias generation circuit for supplying a substrate potential of a transistor which forms a scan-dedicated circuit portion in which a back bias is set to the side where the input voltage is increased is provided.

According to the fourteenth aspect of the present invention, in the configuration of the eleventh to thirteenth aspects, the back bias applying potential is supplied by the internal bias generating circuit.
It becomes unnecessary to supply the back bias application potential from the outside.

A semiconductor integrated circuit according to a fifteenth aspect of the present invention is the semiconductor integrated circuit according to any one of the second, third, and fifth to fifteenth aspects, wherein the power supply voltage in the scan test mode is the power supply voltage in the normal operation mode. It is characterized in that the voltage is lower than the voltage.

According to the fifteenth aspect of the present invention, by setting the power supply voltage in the scan test mode lower than the power supply voltage in the normal operation mode, the low threshold voltage transistor and the high threshold voltage transistor when the power supply voltage becomes low are provided. By utilizing the difference in speed reduction rate from the threshold voltage transistor, the part where the threshold voltage is raised for the purpose of slowing the change of data,
It is possible to further widen the speed difference from other portions and further improve the hold characteristic during the scan shift operation.

A semiconductor integrated circuit according to a sixteenth aspect of the present invention is a scan having a scan data input circuit section and a normal data input circuit section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. Is a semiconductor integrated circuit having a plurality of flip-flop circuits each of which functions as a shift register at the time of a scan test, wherein the data output circuit section is a parallel circuit having at least a part through which data passes through two paths. A first buffer unit for transmitting data in the scan test mode and the normal operation mode is provided in one path, data is transmitted in the normal operation mode in the other path, and a high impedance output is provided in the scan test mode. The second buffer part that becomes And wherein the door.

According to the sixteenth aspect of the invention, both the first and second buffer sections function as a data output buffer in the normal operation mode, and during the scan test,
Since the first buffer unit functions but the second buffer unit does not function, the driving capability of the data output buffer can be made lower than that during normal operation. As a result, the transition time of the output data can be delayed only during the scan test, and the hold characteristic during the scan shift operation can be improved.

A semiconductor integrated circuit according to a seventeenth aspect of the present invention is a scan having a scan data input circuit section and a normal data input circuit section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit that includes a plurality of flip-flop circuits, and that functions as a shift register in a scan test, and has one end connected to a node on a scan data passage in the scan flip-flop circuit. A switch circuit that is conductive in the scan test mode and non-conductive in the normal operation mode, and a load capacitance element connected between the other end of the switch circuit and a fixed potential are provided.

According to the seventeenth aspect of the present invention, by making the switch circuit conductive in the scan test mode, the load capacitance required to be charged and discharged is provided on the path through which the scan data passes only during the scan test. Can be given. As a result, the transition time of the output data can be delayed only during the scan test, and the hold characteristic during the scan shift operation can be improved.

A semiconductor integrated circuit according to claim 18 of the present invention is a scan having a scan data input circuit section and a normal data input circuit section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. Is a semiconductor integrated circuit having a plurality of flip-flop circuits each of which functions as a shift register at the time of a scan test, wherein a node on a data passage path of a data output circuit unit is in a conductive state in a scan test mode. It is characterized in that it is connected to a fixed potential through a switch circuit having a low drive capability that is in a non-conduction state in the normal operation mode.

According to the invention of claim 18, High
If one of the transitions from (high) data to low (low) data and transition from low data to high data is faster, the hold error in the scan shift operation is faster in data transition. Since it occurs on the side, the node on the data passage path of the data output circuit section is connected to the fixed potential via the switch circuit with low drive capability to prevent the change of the scan data only during the scan test. By making the transition on the fast side slow, the hold characteristic during the scan shift operation can be improved.

A semiconductor integrated circuit according to a nineteenth aspect of the present invention is a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output for outputting data in the scan test mode and the normal operation mode. What is claimed is: 1. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits having a circuit section, wherein the scan type flip-flop circuits function as shift registers during a scan test. , The substrate potential of the first transistor forming at least a part of the portion other than the portion for performing high impedance control by the clock system signals in the master portion and the slave portion, and the source potential of the first transistor. And the first tran Is electrically separated from the substrate potential of the second transistor forming the other portion except the portion formed by the transistor, and the substrate potential of the first transistor is set to the source potential of the first transistor and the first transistor in the normal operation mode. The substrate potential of the first transistor is set to the same potential as the substrate potential of the second transistor, and the substrate potential of the first transistor is set to the back bias so that the threshold voltage of the first transistor is higher than that of the second transistor in the scan test mode. It is characterized by

According to the nineteenth aspect of the invention, in the normal operation, since the substrate potential of the scan data path is the same as the peripheral substrate potential, the conditions are not changed at all in the normal operation, and the data rises from the clock rising edge. The characteristics are not deteriorated until is output. However, since the threshold voltage of the transistor in the scan data path becomes high during the scan test, both the change in the output data from the rising edge of the clock and the change in the input data taken in are delayed, and a hold error countermeasure is taken during the shift register operation. be able to. Further, by using the normal output terminal as a scan chain without providing the scan-dedicated output terminal, it becomes possible to evaluate the performance of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal. Since no new element is added, there is no factor of yield reduction, and the input capacitance of the clock system is unchanged, so it is possible to take measures against scan hold without degrading performance during normal operation.

According to a twentieth aspect of the present invention, in the semiconductor integrated circuit according to the nineteenth aspect, the power supply voltage in the scan test mode is lower than the power supply voltage in the normal operation mode. It is characterized by

According to the twentieth aspect of the invention, in the nineteenth aspect of the invention, the threshold voltage of the transistor in the scan data path is made higher than the threshold voltage of the peripheral transistor by applying the back bias during the scan test. Furthermore, by lowering the power supply voltage, there is a difference due to the difference between the threshold voltage and the power supply voltage that determines the transistor drive current and circuit operation speed.Therefore, the speed decrease of the high threshold voltage transistor is smaller than that of the low threshold voltage transistor. Is relatively large, and it is possible to obtain a larger effect of improving the measure against the hold error during the shift register operation.

A semiconductor integrated circuit according to claim 21 of the present invention is a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output for outputting data in the scan test mode and the normal operation mode. What is claimed is: 1. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits having a circuit section, wherein the scan type flip-flop circuits function as shift registers during a scan test. , The power supply potential of at least a part of the part other than the part that performs high impedance control by the clock system signals in the master part and the slave part and the data output circuit part is electrically separated from the power supply potential of other parts, In operating mode, part of the power supply potential and other And a power supply potential of the portion is set to the same potential, the scan in the test mode, characterized in that so as to set the power supply potential of a portion to a lower potential than the power supply potential of the other portions.

According to the twenty-first aspect of the present invention, during the scan test, the power supply voltage to the circuit portion for which the speed of the scan data path is desired to be lowered becomes low, and the operation speed becomes slow. As a result, it is possible to take measures against a hold error when the shift register operates. In normal operation, the potential of the separated power supply is set to the same potential as the peripheral circuits,
There is no deterioration in circuit performance during normal operation. Further, by passing the normal output terminal instead of the scan-dedicated output terminal, it becomes possible to evaluate the quality of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal.
Since no new element is added, there is no factor of yield reduction, and the input capacitance of the clock system is completely unchanged, so that a measure for scan hold can be taken.

A semiconductor integrated circuit according to a twenty-second aspect of the present invention is a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output for outputting data in the scan test mode and the normal operation mode. What is claimed is: 1. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits having a circuit portion, wherein the plurality of scan type flip-flop circuits function as shift registers during a scan test. The source of the transistor in the first circuit portion, which includes at least a part of the scan data input circuit portion, the portion other than the portion that performs high impedance control by the clock system signals in the master portion and the slave portion, and the data output circuit portion. Contact The power supply potential to be electrically separated from the substrate potential of the transistor and the power supply potential of the other circuit parts except the first circuit part, and the power supply potential connected to the source of the transistor in the normal operation mode is the substrate potential of the transistor. And set to the same potential as the power supply potential of other circuit parts,
In the scan test mode, the power supply potential connected to the source of the transistor is set to a potential lower than the substrate potential of the transistor and the power supply potential of other circuit parts.

According to the invention of claim 22, in addition to the same effect as that of the invention of claim 21,
In the scan test, in addition to lowering the power supply voltage to the circuit part where you want to reduce the speed of the scan data path, back bias is applied to the substrate potential,
Further, the threshold voltage is increased and a large amount of speed reduction can be obtained. Since the power supply potential in the area where the power supply potential is dropped and the power supply potential in the area that receives the output can be made only at a level that allows high / low signal transmission, a larger amount of speed reduction is required under such restrictions. Obtainable.

A semiconductor integrated circuit according to a twenty-third aspect of the present invention is a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output for outputting data in the scan test mode and the normal operation mode. What is claimed is: 1. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits having a circuit section, wherein the scan type flip-flop circuits function as shift registers during a scan test. , The ground potential of at least a part of the data output circuit part other than the part that performs high impedance control by the clock system signals in the master part and the slave part is electrically separated from the ground potential of other parts, In operating mode, some graphs A ground potential of the de potential and the other part is set to the same potential, the scan in the test mode, characterized in that so as to set the ground potential of a portion to a potential higher than the ground potential of the other portions.

According to the twenty-third aspect of the present invention, during the scan test, the ground potential of the circuit portion for which the speed of the scan data path is desired to be lowered is raised, so that the voltage applied between the source and drain is reduced, and the operating speed is reduced. Will be late. As a result, it is possible to take measures against a hold error when the shift register operates. In the normal operation, the separated ground potential is set to be the same as the ground potential of the peripheral circuit, so that there is no deterioration in circuit performance during normal operation. Further, by passing the normal output terminal instead of the scan-dedicated output terminal, it becomes possible to evaluate the quality of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal. Since there is no addition of new elements,
There is no factor of yield reduction, and the input capacitance of the clock system is completely unchanged, so that a measure for scan hold can be taken.

A semiconductor integrated circuit according to a twenty-fourth aspect of the present invention is a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output for outputting data in the scan test mode and the normal operation mode. What is claimed is: 1. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits having a circuit section, wherein the scan type flip-flop circuits function as shift registers during a scan test. A ground potential connected to the source of the transistor in the first circuit portion, which includes at least a portion of the data output circuit portion, and a portion other than the portion for performing high impedance control in the master portion and the slave portion by the clock system signal, Board electric And a ground potential that is electrically separated from the ground potentials of the other circuit parts other than the first circuit part and is connected to the source of the transistor in the normal operation mode are the substrate potential of the transistor and the ground potential of the other circuit part. It is characterized in that the same potential is set, and the ground potential connected to the source of the transistor in the scan test mode is set to a potential higher than the substrate potential of the transistor and the ground potential of other circuit portions.

According to the invention as set forth in claim 24, in addition to obtaining the same effect as that of the invention as set forth in claim 23,
During the scan test, the ground potential of the circuit part where you want to reduce the speed of the scan data path rises, the voltage applied between the source and drain decreases, and the back bias is applied to the substrate potential, further increasing the threshold voltage. It is possible to increase and obtain a large amount of speed reduction.
The power supply potential in the region that raises the source potential and the power supply potential in the region that receives the output can be differentiated only at a level that allows high / low signal transmission. Obtainable.

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION Prior to the description of the embodiments of the present invention, comparative examples will be described first, and the advantages of the comparative examples will be clarified in the respective embodiments described below.

As a comparative example, a description will be given below of an example in which a measure against a hold time shortage defect at the time of scan shift, which has been a conventional problem, is taken. However, the flip-flop will be described as a positive edge type that operates synchronously at the rising edge of the clock.

(Comparative Example 1) The setting margin of the hold time specification is increased. In this case, there is a problem that the number of timing errors increases and the design period is extended for debugging the timing errors.

(Comparative Example 2) A delay element is inserted in the scan data output portion to increase the data holding time from the rise of the clock to the change of the data. In this case, if a delay element is inserted in the normal output terminal, there will be an adverse effect that the time from the rise of the clock to the output of data will be delayed during actual operation. There is a coping method in which an output terminal is provided and a delay element is inserted in the scan-dedicated output terminal (Japanese Patent No. 2139223). In this case, there are the following problems. Since the buffer part of the normal output is not included in the scan chain, the performance of that part cannot be inspected and the testability deteriorates. Further, since the scan-dedicated output terminal is separately added, the area is increased. If the number of stages is increased or the gate length is increased to delay, the area is further increased. Also, in terms of power consumption, the power consumption during operation increases due to the addition of an extra circuit, and the drain leakage current, which has been a concern in recent low-voltage fine processes, also increases.

(Comparative Example 3) All clock groups are operated by a one-phase clock during normal operation, and the odd number and even number of scan chain flip-flops are used during the scan test.
There is a method of dividing a clock into a positive phase and a negative phase (Japanese Patent No. 2130898). This measure is ideal in that the hold time error can be almost completely eliminated.
However, there are the following problems. In order to distribute the odd-numbered flip-flops to the normal phase operation and the even-numbered flip-flops to the negative phase operation during the scan test, an exclusive OR circuit (hereinafter referred to as EXOR) is provided on the input side of the clock signal of each flip-flop. ) Must be added. The EXOR is usually 6 to 1 depending on the circuit configuration.
A large number of transistors, about 0, is required. Since the number of additional transistors is large, an increase in area, current consumption, and off-leakage current occurs as in Comparative Example 2. Even in the normal operation, the clock signal passes through the EXOR composed of vertically stacked transistors, so that the time from the rise of the clock to the output of data is delayed. Further, the clock input load capacity is more than doubled as compared with the case where the clock signal is received by a simple inverter, which causes disadvantages such as increase in delay of the clock system itself and increase in power consumption.

Examples in the respective embodiments described below are as follows:
The semiconductor integrated circuit includes a plurality of scan-type flip-flop circuits that form a scan chain at the time of a scan test, but the main part (scan-type flip-flop circuit) will be mainly described below. Further, in the following example, when the scan flip-flop circuit does not have a scan-dedicated output circuit section, each scan flip-flop circuit has a normal data output terminal (Q) as shown in FIG. 21B, for example. A scan chain is formed by connecting the scan data input terminal (DT). When the scan flip-flop circuit has a scan-dedicated output circuit section, each scan flip-flop circuit has a scan-dedicated output terminal (SQ) and a scan-data input terminal (instead of the normal data output terminal (Q) described above. DT) is connected to form a scan chain.

(First Embodiment) The first embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 1 to 4, and an element such as a delay element is added to the scan data input section to suppress a hold error during scan shift.

FIG. 1 shows a first example of the scan flip-flop in this embodiment. Reference numerals 601 to 607 are the same as those in FIG. 22, and a description thereof will be omitted. This example corresponds to claim 1, and as shown in FIG. 1A, a delay element 110 is inserted between the scan data input terminal (DT) and the scan data input circuit unit 601. The insertion of the delay element 110 slows down the speed at which the potential change of the scan data input terminal (DT) to the scan flip-flop is transmitted to the master unit 604 of the scan flip-flop. The specification value of the input data hold time, which defines how long the data cannot be fetched until it is held, becomes small. Even if it is a negative value, it will be a smaller negative value. This makes it possible to take hold error measures during the scan shift operation.

The simplest delay element 110 is shown in FIG.
111 is a multi-stage inverter circuit. In general, a smaller gate width and a longer gate length give a slower delay. However, increasing the gate length leads to an increase in area and current consumption.

As the second to fourth examples, the delay element 1
By configuring the scan data input circuit portion as shown in FIGS. 2A, 2B, and 2C without providing 10 (111), it is possible to take hold error countermeasures during the scan shift operation. This will be described below.

In the second example, the scan data input circuit unit 601 which is a tri-state buffer for performing high impedance control of scan input data without providing the delay element 110 in FIG. As shown in (a), an on-state Pch (P-channel) transistor 1
12 and Nch (N channel) transistor 1 in ON state
By inserting 13, the drive capability of scan data input can be weakened. This corresponds to claim 2 of the present invention.

The third example is as shown in FIG.
As shown in FIG. 2B, the delay element 110 is not provided, and the diode 115 is connected to the power supply and the scan data input circuit unit 6 as shown in FIG.
By inserting in the forward direction between 01 and 0.4, it is possible to set 0.4 to 0.
Scan data input circuit unit 6 with a voltage lowered by about 7V
01 can be operated to weaken the drive capability of scan data input. This corresponds to claim 3 of the present invention.

The fourth example is as shown in FIG.
Even if the capacitive element 118 is added to the scan data input circuit unit 601 as shown in FIG. 2C without providing the delay element 110, the change in scan data can be delayed.
However, attention must be paid to the location where the capacitance is inserted, and the load capacitance element 118 is arranged between the inverter 116 that receives scan data (DT) at its gate and the transfer gate 117 that performs high impedance control. This is,
It corresponds to claim 4 of the present invention.

When the capacitive element 118 is provided at the outermost scan data input terminal portion as a flip-flop, not only the scan-dedicated output but also the normal output terminal is connected to the scan data input terminal (DT). In some cases, the drive load on the connected normal output terminal is increased, causing performance deterioration such as speed reduction and current consumption increase. Further, even when the transfer gate 117 is arranged on the right side (on the master unit 604 side), the load capacitance can be seen from the normal data input terminal (D), which causes a deterioration in performance during normal operation.

The capacitance element 118 is a transistor gate capacitance, a diffusion capacitance, a DMOS capacitance for analog, a capacitance made of polysilicon or a metal electrode, and a gate made of a nitride film as an insulator and a diffusion upper contact in the self-align contact technique with respect to the gate. And the like, and there is no particular limiting factor in the forming process and the structure.

As described above, according to this embodiment, by adding the delay element 110, the transistors 112 and 113 in the ON state, the diode 115 or the load capacitance element 118 to the scan data input section, the scan flip-flop can be realized. The hold time required to latch the scan input data can be improved, and the hold error can be suppressed.

In this embodiment, the problem in Comparative Example 1 can be avoided. Further, since the scan chain is configured using the normal output terminal (Q), there is a problem that the normal output circuit portion cannot be tested, which occurs when the scan-dedicated output terminal having the delay element is used as in Comparative Example 2. do not do. Further, unlike Comparative Example 3, there is no adverse effect such as an increase in delay during normal operation or an increase in current consumption.

In the structure of each example of the present embodiment, a scan-dedicated output section having a delay element (see FIG. 4B).
(Refer to the part 205 of No. 2), and a scan chain can be configured by using the scan-dedicated output terminal,
In that case, although there is a problem that the normal output circuit portion cannot be tested as in Comparative Example 2, the margin for a hold error is further increased.

(Second Embodiment) A second embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 5 to 10.

In this embodiment, the scan data input circuit unit 601 of the scan flip-flop shown in FIG.
On the other hand, the impurity ion implantation for increasing the threshold voltage is higher than the transistors used in the other normal data input circuit unit 602, mode switching circuit unit 603, master unit 604, slave unit 605, data output buffer unit 606, and the like. Apply (related to claims 5 and 6). Compared to the case of using a low threshold voltage transistor used in other regions, the change of scan data can be slower than that of configuring a delay circuit with the same gate length, gate width, and number of logic stages. Hold error during scan shift can be improved.

The specific procedure of the high threshold voltage (high Vt) processing will be described below.

FIG. 3A shows a schematic layout image diagram of the scan type flip-flop before the threshold voltage raising process. As shown in FIG. 3B, on the scan data input section,
The high Vt region definition layer 203 defines a region for performing a process of increasing the threshold value. Although there are various process-based methods, generally, the overlapping portion of the high Vt region defining layer 203 and the N well region 201 and the overlapping portion of the high Vt region defining layer 203 and the P well region 202 are masked, The threshold voltage is increased by additionally implanting impurity ions having the same polarity as the well. Therefore, the N well region 2 in the high Vt region definition layer 203 is
01 is an N-type impurity region having a higher concentration than the N well region 201 in the other region, and the P well region 202 in the high Vt region defining layer 203 is the P region in the other region.
The P-type impurity region has a higher concentration than the well region 202. A MOS type Pch transistor is provided in the N well region 201, and a MOS type Nch is provided in the P well region 202.
A transistor is formed. As a result, FIG.
A scan data input circuit section using a high threshold voltage transistor is formed in the portion indicated by 204 in (a).

A transistor having a high threshold voltage has a smaller difference from the power supply voltage than a transistor having a low threshold voltage, so that the current driving capability is lowered. This enables the scan data input terminal to the scan flip-flop.
Since the speed at which the potential change of (DT) is transmitted to the master unit 604 of the scan type flip-flop becomes slow, the input data that determines how long the scan data DT must be held with respect to the clock change. The specifications of the hold time are reduced, and since the portion configured by the high threshold voltage transistor is the area that is not used in normal operation, it does not affect the operation speed in actual use.

Further, by configuring the scan data input circuit section 204 with a high threshold voltage transistor, the off-leakage current between the source and drain of the transistor during actual use can be suppressed to a smaller value than when it is configured with a low threshold voltage transistor. it can.

In the above example, the problem in Comparative Example 1 can be avoided. Further, since the scan chain is configured using the normal output terminal (Q), there is a problem that the normal output circuit portion cannot be tested, which occurs when the scan-dedicated output terminal having the delay element is used as in Comparative Example 2. do not do. Further, unlike Comparative Example 3, there is no adverse effect such as an increase in delay during normal operation or an increase in current consumption.

For the same reason, as shown in FIG. 4B, even when the scan-dedicated output circuit unit 205 is provided and the scan-dedicated output circuit unit 205 is subjected to the high threshold voltage processing, The change in the data output to the scan flip-flop in the next stage is delayed, and as a result, the effect of improving the hold timing in the scan shift operation is similar to the high threshold voltage of the scan data input circuit unit 204 in FIG. 4A. can get. However, there is a problem that the normal output circuit portion cannot be tested as in Comparative Example 2. This is the embodiment relating to claims 5 and 7.

From the 0.10 μm generation fine process, in addition to the source-drain off-leakage current of the transistor described above, the gate leakage current caused by the tunnel current passing through the thin gate oxide film becomes a problem. Have begun. Although a transistor having a thick gate oxide film has an effect of suppressing a gate leak current as compared with a transistor having a thin gate oxide film, if the threshold voltage is about the same, the current capability itself is inferior. This thick film transistor is connected to the scan data input circuit section 204 described above.
When used in the position of the scan-dedicated output circuit unit 205, it is possible to obtain an effect of improving the hold time characteristic and reducing the gate leak current due to the delay of data change.

When the same threshold voltage adjustment injection as that of the low threshold voltage transistor is made to the scan data input circuit section 204 and the scan dedicated output circuit section 205, the thicker the gate oxide film and the smaller the oxide film capacitance are, the more the threshold value is. Since the voltage becomes higher, the same effect as that obtained when the above-mentioned transistor to which the high threshold voltage is injected is used is obtained (claims 8 to 9).
10 related).

(Third Embodiment) A third embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 11 to 14.

In the above second embodiment, additional process steps are required for increasing the transistor threshold voltage (Vt) Vt and increasing the gate oxide film thickness. Although the multi-Vt and multi-gate oxide films are being adopted in order to improve the LSI performance under the limit of miniaturization, in the third embodiment, the same improvement is made without additional process steps. A method for obtaining the effect will be described.

FIG. 5A is a gate level circuit diagram of the scan type flip-flop circuit according to this embodiment, and FIG. 5B is a transistor level circuit diagram thereof. In this embodiment, a scan flip-flop with a set / reset function is used. That is, FIG.
Of the master unit 604S and the slave unit 60
The difference is that the set signal SET and the reset signal RSET are input to 5S. Furthermore, the present embodiment is characterized in that the power supply configuration of the scan input circuit section 300 is different.

In the scan flip-flop circuit according to the present embodiment, as shown in FIG. 5B, in the scan data input circuit section 300, the source power supply (VDD1) of the Pch transistor is separated from the substrate power supply (VDD2). In addition, the source power of the Nch transistor (VS
S1) and the substrate power supply (VSS2) are separated, and VDD2 is set to a higher potential than VDD1 and VSS2 is set to a lower potential than VSS1 (related to claim 11). In this case, Pch
In the transistor, since P-type source and drain regions are formed in the N well region 201 (see FIG. 3), P
Scan input circuit section 3 which is a ch transistor formation region
The N-well region 201 (see FIG. 3) of No. 00 and the N-well region 201 (see FIG. 3) in other regions are separated, and the substrate potential VDD is applied to the N-well region of the scan input circuit section 300.
2 is applied, and the potential VDD1 is applied to the other N well regions. Also, the Nch transistor is P
Since the N-type source region and the drain region are formed in the well region 202 (see FIG. 3), the P-well region 202 (see FIG. 3) of the scan input circuit unit 300, which is an Nch transistor forming region, and the other regions are formed. The scan input circuit unit 3 is separated from the P-well region 202 (see FIG. 3).
The substrate potential VSS2 is applied to the P-well region of No. 00, and the potential VSS1 is applied to the P-well regions of the other regions.

By setting the bias conditions as described above, a back bias is applied to the transistor, and the absolute value of the threshold voltage increases. As a result, the same effect as in the case of adopting the high threshold voltage transistor as in the second embodiment can be obtained without additional process steps. However, although it depends on the degree of wiring congestion, separating the wells may cause a disadvantage in area.

In the case of a flip-flop provided with the scan-dedicated output circuit section 301 as shown in FIG. 6A, the scan-dedicated output circuit section 301 is provided with the scan of FIG. 5 as shown in FIG. 6B. By a back bias applying method similar to the input circuit unit 300, it is possible to improve the hold characteristic without causing a speed decrease during normal operation (claim 1).
1 and 13).

The scan flip-flop circuit is shown in FIG.
FIG. 7 shows a power supply configuration example of the scan flip-flop group and the other logic groups which configure the semiconductor integrated circuit in the case of the configuration of FIG. Since a back bias is applied to VDD2 and VSS2, VDD2 is set to a higher potential than VDD1 and VSS2 is set to a lower potential than VSS1. VDD of scan flip-flops
1 is VDD of the other logic group and VSS of the scan flip-flop group is 1 of VSS of the other logic group
You can connect with. Further, the design in which the source and the substrate are separated tends to be adopted also for the purpose of the VTCMOS technology for the countermeasure against the off-leakage problem in the recent fine process, the IDDQ test correspondence, and the like. Easy to adopt.

Further, how to supply power to the block shown in FIG. 7 at the one-chip level will be described. FIG. 8 is the easiest example from the standpoint of chip development in which VSS2 and VDD2 are supplied from the outside in addition to VSS and VDD even at the one-chip level. On the other hand, as shown in FIG. 9, internal bias generation circuits 302 and 303 are provided inside the chip, and the internal bias generation circuit 302 generates the potential VDD2 from the potential VDD1 supplied from the outside. The potential VSS2 is generated from the potential VSS1 supplied from the outside (related to claim 14). This makes it possible to implement the scan shift countermeasure without increasing the apparent number of power sources as a chip. In FIGS. 8 and 9, 30
4 is a power supply terminal.

(Fourth Embodiment) The fourth embodiment will be described with reference to FIG. The present embodiment mainly relates to claim 15.

In the second embodiment, the method of improving the hold characteristic of scan shift using the high threshold voltage transistor has been described. The speed difference between the high threshold voltage transistor and the low threshold voltage transistor becomes larger as the voltage becomes lower. The qualitative analysis is shown below.

The charge Q has a relationship of Q = CV with the capacitance C and the voltage V. Further, the relationship between the charge Q, the delay time ΔT, and the current I is Q = I × ΔT. Therefore, ΔT = C
It becomes V / I.

The saturation current Ids of the transistor which is dominant with respect to the delay time can be expressed as Ids = A (Vgs-Vt) α (where A and α are constants, Vt is a threshold voltage).
In the fine process, α = 1, and if the capacitors C and A are regarded as constants related to voltage, ΔT = VDD / (VDD−
Vt).

If low Vt = 0.3V and high Vt = 0.5V, the delay ratio between high Vt and low Vt is high Vt delay / low Vt.
t delay ∝ (VDD-0.3) / (VDD-0.5). The results are graphed in FIG.

As can be seen from FIG. 10, the high threshold voltage transistor is slower than the low threshold voltage transistor in the low voltage region.

Therefore, in the present embodiment, in consideration of the voltage dependence difference between the operating speeds of the low threshold voltage transistor and the high threshold voltage transistor, in each example of the second embodiment, the operating power supply during the scan test is used. By setting the voltage to be lower than that during normal operation, the hold characteristic of scan shift is further improved.

Also in the third embodiment in which a back bias is applied to increase the threshold voltage, the operating power supply voltage (voltage between VDD1 and VSS1) during the scan test is higher than that during the normal operation. By setting a low voltage,
The hold characteristic of the scan shift is further improved.

Further, as shown in FIG. 2A, the scan data input circuit section 601 has an on-state transistor inserted therein, and as shown in FIG. 2B, the scan data input circuit section 601 has a diode in the forward direction. In the inserted configuration as well, similarly, by setting the operating power supply voltage at the time of the scan test to be lower than that at the normal operation, the hold characteristic of the scan shift is further improved. this is,
This is because the on-state transistor or diode is inserted because the voltage applied to the transistor (transistor forming the scan data input circuit unit 601) contributing to the operation is lowered to some extent. For example, assuming that the voltage drops by 0.6V when the diode is inserted, VDD-
For the transistor having Vt = 1.0 (V), VDD-0.6-Vt = 0.4 by inserting the diode.
It only takes (V). From here, the power supply voltage VDD
If lowering by 0.2 (V), VDD-Vt = 0.8
(V), VDD-0.6-Vt = 0.2 (V),
The current values are 0.8 / 1.0 = 80% and 0.2 /
It becomes 0.4 = 50%, and the one in which the diode or the transistor in the ON state is inserted has a lower voltage and tends to have a lower speed.

(Fifth Embodiment) A fifth embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 16 to 18.

In the fifth embodiment, the circuit for delaying the transition time of output data only in the scan test mode is used by using the mode switching signal NT for switching between the scan test mode and the normal operation mode. This is different from the first to fourth embodiments.

FIG. 11 is a gate level circuit diagram of a scan type flip-flop circuit showing a first example (related to claim 16) of the present embodiment. The configuration of the data output buffer section 606 is different from that of FIG. , Other configurations are the same. A buffer unit 501 has a function of changing the buffer capacity between the scan test mode and the normal operation mode.

In the configuration of FIG. 11, as shown in the buffer unit 501, at least a part of the data output buffer unit 606 is divided into two series, the input and the output are the same, but the inverter 502 is provided in one path and the other is provided. A tri-state buffer 503 that is in a high impedance state in the scan test mode that can be controlled by the mode switching signals NT and / NT is provided on the path. This is not limited to the tri-state buffer, as long as it is an element capable of controlling high impedance such as a transfer gate.

In the normal operation mode (NT = High level), the tri-state buffer 503 operates as the inverter 502.
, And also functions as a data output buffer, but in the scan test mode (NT = Low level), the tri-state buffer 503 has a high impedance output, and only the inverter 502 drives a load.

As a result, it is possible to suppress an increase in delay in the normal operation mode and improve the hold timing in the scan test mode.

12A and 12B are gate-level circuit diagrams of the scan type flip-flop circuit showing the second example (related to claim 17) of the present embodiment, which are a switch and a load, respectively. Capacitance circuit 701, 70
22 is different in that 4 is added, and other configurations are the same.

The structure of FIG. 12A has a switch 702 which is controlled by the mode switching signals NT and / NT and is in a conductive state in the scan test mode and a non-conductive state in the normal operation mode, and a load capacitance 703. In the scan test mode, the node on the scan output is connected to the load capacitor 703 having one end connected to the fixed potential via the switch 702. As a result, the load capacitance 703 needs to be charged / discharged only in the scan test mode, and the data change is delayed accordingly, and the scan shift hold characteristic is improved.

Further, although the switch and load capacitance circuit 701 are added to the scan output side in FIG. 12A, they are similar to the circuit 701 in the scan input section and the master section as shown in FIG. 12B. Even if the circuit 704 is added, the hold characteristic of the scan flip-flop is improved and the scan shift is facilitated.

In addition, the switch 7 shown in FIGS.
Reference numeral 02 is a complementary type having both Pch and Nch transistors, and the charge / discharge potential is completely oscillated by the power supply potential, but the number of elements is reduced to only one Nch transistor, and the charge / discharge of the capacitance is less by the threshold voltage VDD. Even if it becomes −Vt, it is possible to obtain the effect of causing the delay.

FIG. 13 is a gate level circuit diagram of a scan type flip-flop circuit showing a third example (related to claim 18) of the present embodiment, and a switch 705 connected to a fixed potential in the data output buffer section 606. 22 is different from the configuration of FIG. 22, and the other configurations are the same.

In this embodiment, as shown in FIG. 13, the source side is set to a fixed potential (VDD) which is controlled by the mode switching signal NT and is in the conducting state in the scan test mode and is in the non-conducting state in the normal operation mode. A switch 705 including a connected transistor is provided, and the drain side thereof is connected to the data output signal line. This switch 705
The drive capability is lowered by narrowing the gate width, increasing the gate length, or increasing the Vt. As a result, the VDD power source collides with the output data only during the scan operation. On the other hand, when transitioning to the High side, on the contrary, it works in the direction of helping the transition and shortening the delay time, but the hold error of the scan determines the operation failure at the faster speed of the High / Low data transitions. In such a case, the present invention that delays the transition on the faster side is effective. Further, in the scan test, although the power of the switch 705 is narrowed down, the current consumption slightly increases due to a signal collision, but the switch 705 is turned off in the normal operation, which causes an increase in standby current. Does not reach.

Further, in addition to the switch 705 having a high resistance ON transistor, a switch and a high resistance element may be used and connected to a fixed power source via the high resistance element, which is different from the gist of the present invention. Absent.

As described above, in the present embodiment, as shown in FIG.
In both configurations of FIG. 12 and FIG. 13, the problem in Comparative Example 1 can be avoided. Further, since the scan chain is configured using the normal output terminal (Q), there is a problem that the normal output circuit portion cannot be tested, which occurs when the scan-dedicated output terminal having the delay element is used as in Comparative Example 2. do not do. Further, unlike Comparative Example 3, there is no adverse effect such as an increase in delay during normal operation or an increase in current consumption.

In the configurations of FIGS. 11 and 13, the NQ output side, which does not form the scan chain, is provided with the same buffer section 501 and the switch 705 as the Q output side in the present embodiment, but this is not always the case. Not necessary. For example, if the NQ output is not used in normal operation, then N
If the scan chain is configured using the Q output, the load at the time of actual operation becomes smaller, and in order to cope with such a case, the same buffer unit is provided on both the NQ output side and the Q output side in FIGS. 11 and 13. An example in which 501 and a switch 705 are provided is shown.

(Sixth Embodiment) A sixth embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 19 to 20.

FIG. 14 is a gate level circuit diagram of the scan flip-flop circuit according to the present embodiment, and FIG. 15 is its transistor level circuit diagram.

In the present embodiment, the scan data input circuit section 60 in the area 10 shown in FIG. 14 is provided for the flip-flop with the set / reset function similar to that shown in FIG.
1. Substrate of transistors (hereinafter referred to as “target transistors”) in a portion other than a portion for performing high impedance control by a clock system signal in the master portion 604S and the slave portion 605S, and a portion including any of the data output buffer portions 606 Source potential of the same target transistor (source potential of the target Pch transistor is VDD
1, the source potential of the target Nch transistor is VSS1)
And source and substrate potentials of surrounding transistors (hereinafter referred to as “non-target transistors”) other than the target transistor (source and substrate potential of the non-target Pch transistor are V
The source and substrate potential of DD1, the non-target Nch transistor are separated from VSS1). In this case, since the P-type source region and the drain region are formed in the N-well region 201 (see FIG. 3) in the Pch transistor, the target Pch
The N-well region 201 (see FIG. 3) in the transistor formation region and the N-well region 201 (see FIG. 3) in the other non-target Pch transistor formation region are separated, and the respective substrate potentials are applied to the respective N-well regions. To be done. In addition, since the N-type source region and the drain region are formed in the P-well region 202 (see FIG. 3) of the Nch transistor, the P-well region 202 (see FIG. 3) of the target Nch transistor forming region and other non-target regions are formed. The P-well region 202 (see FIG. 3) in the Nch transistor formation region is separated and each substrate potential is applied to each P-well region.

During normal operation, the substrate potential of the target transistor is set to the substrate potential (Pc) of the non-target transistor.
h transistor is VDD1, Nch transistor is VS
Use the same potential as S1). When the scan test is performed, the substrate potential of the target transistor is tested by applying a back bias to the side where the threshold value of the transistor rises. That is, the substrate potential of the target Pch transistor is set to VDD2, which is higher than VDD1, and the substrate potential of the target Nch transistor is set to VSS2, which is lower potential than VSS1. By applying the back bias in this way, the threshold voltage can be increased as described in the third embodiment.

In the third embodiment, it is assumed that the back bias is applied even in the normal operation, and the data does not pass in the normal operation such as the scan data input circuit section and the scan data dedicated output section. The back bias could be applied only to the portion through which the data passes in the scan test mode, but in the case of the present embodiment,
Since the back bias is not applied during the normal operation, the back bias can be applied to part of the data output buffer unit 606, the master unit 604S, and the slave unit 605S, and a larger hold data characteristic improving effect can be obtained.

Incidentally, in the areas of the master section 604S and the slave section 605S, the part for performing high impedance control is removed from the back bias applicable area 10.
This is because the faster the part changes, the shorter the time for holding the data.

According to this embodiment, the problem in Comparative Example 1 can be avoided. In the normal operation, the potential of the separated power supply is set to the same potential as that of the peripheral circuit, so that the circuit performance does not deteriorate during the normal operation. Further, by passing the normal output terminal instead of the scan-dedicated output terminal, it becomes possible to evaluate the quality of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal. Since there is no addition of a new element or increase in the input capacity of the clock system, it is possible to take hold measures for the scan shift operation without deterioration in performance during normal operation.

Further, in the present embodiment, at the same time as applying the back bias during the scan test, and further lowering the power supply voltage from that during the normal operation, the same effect as described in the fourth embodiment is obtained. , The scan hold characteristic can be further improved (related to claim 20).

(Seventh Embodiment) A seventh embodiment will be described with reference to the drawings. The present embodiment mainly relates to claims 21 to 24.

FIG. 16 is a gate level circuit diagram of the scan flip-flop circuit according to the present embodiment.

In this embodiment, a flip-flop with a set / reset function similar to that of FIG. 5A is used, but a scan data input circuit section in the region 10 shown in FIG. 14 similar to that of the sixth embodiment is provided. 601, the master unit 604S and the slave unit 605S, other than the portion other than the portion that performs high impedance control by the clock system signal, and the portion including any of the data output buffer unit 606, the data delay time only in the scan test mode. Take a method to increase. However, in FIG. 16, FIG. 17, FIG. 18, and FIG. 19 showing the seventh embodiment, the improvement measures of the present invention have not been implemented for the master portion portion having a small hold time improvement effect. Please note.
It is assumed that the area 11 shown in FIG. 16 is an area where countermeasures are taken in the seventh embodiment.

The first example of the present embodiment is Claim 2
FIG. 17 shows a transistor-level circuit diagram of the scan flip-flop circuit corresponding to the first aspect of the invention. As shown in FIG. 17, the circuit portion (FIG.
The power supply potential VDD2 in the region 11) is electrically separated from the power supply potential VDD1 of the peripheral circuits. Then, in normal operation, VDD1 and VDD2 are used with the same potential, and when a scan test is performed, VDD2 is made lower than VDD1 for testing, thereby delaying the delay time of the circuit in the region 11 and performing scan shift. Improves hold characteristics.

The second example of the present embodiment is Claim 2
FIG. 18 shows a transistor-level circuit diagram of the scan flip-flop circuit corresponding to the third aspect of the invention. As shown in FIG. 18, a circuit portion whose delay is desired to be delayed (see FIG.
The ground potential VSS2 of the area 11) is electrically separated from the ground potential VSS1 of the surrounding circuits. Then, during normal operation, VSS1 and VSS2 are used with the same potential, and when performing a scan test, VSS2 is set to a potential higher than VSS1 for testing, thereby delaying the delay time of the circuit in the area 11 and performing scanning. Improves hold characteristics during shift.

Also in the case of the first and second examples of the present embodiment corresponding to the inventions of claims 21 and 23, as in the sixth embodiment corresponding to the invention of claim 19, Comparative Example 1 In the normal operation, the potential of the separated power supply is set to the same potential as that of the peripheral circuit, so that the circuit performance does not deteriorate during the normal operation. Also, by passing the normal output terminal instead of the scan-dedicated output terminal, it is possible to evaluate the appearance of the normal output terminal, which is not seen in the hold measure by adding the scan-dedicated output terminal, and to add new elements or input clock signals. Measures for scan hold can be taken without any increase in capacity.

Further, FIG. 19 shows a transistor level circuit diagram of the scan type flip-flop circuit of the third example in the present embodiment relating to claims 22 and 24 for improving the scan hold characteristic.

In the third example, the source potential and the substrate potential are further separated for the transistors of the circuit in the region 11 of FIG. In the case of FIG. 19, the source of the Pch transistor is VDD2, the substrate is VDD1, the source of the Nch transistor is VSS2, and the substrate is VSS1. Further, as shown in FIG. Connected to the power supplies VDD and VSS of the logic group other than the logic group.

In normal operation, VDD2 is set to VDD (= V
DD1) and set VSS2 to VSS (= VSS)
Use the same potential as 1). During the scan test, the source potential V of the circuit in the region 11 where the delay is desired to be delayed
For DD2 and VSS2, VDD2 is lower than VDD,
VSS2 should be higher than VSS. As a result, not only the voltage applied between the source and drain lines during the scan test is lowered, but also the back bias is applied, which makes it possible to further improve the scan hold characteristic.

In the example of FIG. 19, the present invention is applied to both the Pch transistor side and the Nch transistor side, but it may be applied to only one side.

[0130]

As described above, according to the present invention, it becomes possible to suppress the hold error in the scan test. The details are given below.

According to the invention described in claims 1, 2, 3, and 4, the hold time required for latching scan input data of the scan flip-flop circuit can be improved. Further, when the scan chain is configured by using the normal output terminal, the problem that the normal output cannot be tested which occurs when the scan-dedicated output terminal having the delay element is not generated. Further, the scan chains can be used in combination even when the scan chains are formed using the scan-dedicated output terminals having the delay elements, in which case the margin for the hold error is further increased.

According to the fifth aspect of the present invention, in the scan flip-flop circuit, the threshold value of the transistor forming the scan-dedicated circuit portion through which the data does not pass in the normal operation mode but only the scan data passes is another circuit. The threshold value is higher than that of some transistors, and the operation speed becomes slower. As a result, the change in scan data can be made slower than when a delay circuit is configured with the same gate length, gate width, and number of logic stages using low threshold voltage transistors used in other circuit parts. Therefore, it is possible to improve the data hold specification of how much data should be held with respect to the change of the clock so that it cannot be taken into the slave unit side with a smaller area than that of the one configured with the low threshold voltage transistor. Further, since the portion constituted by the high threshold voltage transistor is a region which is not used in the normal operation, the problem of the operation speed in the actual use does not occur. Further, although the portion configured by the high threshold voltage transistor is present even in actual use, the transistor off-leak current can be suppressed smaller than that in the low threshold voltage transistor configuration.

According to the sixth aspect of the invention, in the scan type flip-flop circuit, the scan data input circuit section has a higher threshold value than the transistors in other circuit sections. As a result, the data hold specification of how much data should be held with respect to the change of the clock before the data can be fetched to the slave side can be improved in a smaller area than that of the one configured by the low threshold voltage transistor. Since the scan data input circuit section composed of high threshold voltage transistors is a region that is not used in normal operation, the problem of operating speed in actual use does not occur. Also,
By using a high threshold voltage transistor, the transistor off-leakage current can be suppressed smaller than that of the low threshold voltage transistor configuration.

According to the seventh aspect of the present invention, in the scan flip-flop circuit, the threshold value of the transistor forming the scan-dedicated output circuit section becomes higher than the threshold value of the transistor of the other circuit section. As a result, the data output hold time, which is how long the previous data continues to be output after the clock changes, can be made longer than that formed by the low threshold voltage transistor. Also,
Since the scan-dedicated output circuit unit configured by the high threshold voltage transistor is not used in the normal operation, the problem of the operation speed in actual use does not occur. Further, the transistor off-leakage current can be suppressed to be smaller than that of the low threshold voltage transistor configuration by using the high threshold voltage transistor configuration.

According to the eighth, ninth and tenth aspects of the present invention, in the scan flip-flop circuit, the hold characteristic in the scan test can be improved while suppressing the gate leak current. When the threshold voltage of the transistor forming the scan-dedicated circuit portion is the same as that of the transistors in the other circuit portions when the threshold voltage is set and injected, the driving capability can be lowered. This is because the driving current is proportional to the gate oxide film capacitance and the threshold voltage is inversely proportional to the gate oxide film capacitance, so that a transistor having a thick gate oxide film has a high threshold voltage and a low driving capability. Further, even if an optimal transistor is manufactured under the condition that the source and drain have the same off leak between the thick and thin gate oxide films, the transistor having a thick gate oxide film also has a lower driving capability. In addition, since the gate oxide film is thick, it is possible to suppress the gate leak current generated in the extremely thin gate oxide film.

According to the eleventh, twelfth and thirteenth aspects of the present invention, in the scan flip-flop circuit, the scan-dedicated circuit portion through which only scan data does not pass in the normal operation mode separates the substrate potential. Since the back bias is applied, the threshold voltage of the transistor becomes high. As a result, the same data hold characteristic improvement and leakage current suppression effect as those of the fifth aspect can be obtained without a process threshold adjustment process step.

According to the fourteenth aspect of the invention, in the configuration of the eleventh to thirteenth aspects, the back bias applying potential is supplied by the internal bias generating circuit.
It becomes unnecessary to supply the back bias application potential from the outside.

According to the fifteenth aspect of the present invention, by setting the power supply voltage in the scan test mode lower than the power supply voltage in the normal operation mode, the low threshold voltage transistor and the high threshold voltage transistor when the power supply voltage becomes low are provided. By utilizing the difference in speed reduction rate from the threshold voltage transistor, the part where the threshold voltage is raised for the purpose of slowing the change of data,
It is possible to further widen the speed difference from other portions and further improve the hold characteristic during the scan shift operation.

According to the sixteenth aspect of the present invention, both the first and second buffer sections function as data output buffers in the normal operation mode, and during the scan test,
Since the first buffer unit functions but the second buffer unit does not function, the driving capability of the data output buffer can be made lower than that during normal operation. As a result, the transition time of the output data can be delayed only during the scan test, and the hold characteristic during the scan shift operation can be improved.

According to the seventeenth aspect of the present invention, by making the switch circuit conductive in the scan test mode, the load capacitance that needs to be charged and discharged is provided on the path through which the scan data passes only during the scan test. Can be given. As a result, the transition time of the output data can be delayed only during the scan test, and the hold characteristic during the scan shift operation can be improved.

According to the invention of claim 18, High
If one of the transitions from (high) data to low (low) data and transition from low data to high data is faster, the hold error in the scan shift operation is faster in data transition. Since it occurs on the side, the node on the data passage path of the data output circuit section is connected to the fixed potential via the switch circuit with low drive capability to prevent the change of the scan data only during the scan test. By making the transition on the fast side slow, the hold characteristic during the scan shift operation can be improved.

According to the nineteenth aspect of the invention, in the normal operation, since the substrate potential of the scan data path is the same as the peripheral substrate potential, the condition does not change at all in the normal operation, and the data rises from the clock rising edge. The characteristics are not deteriorated until is output. However, since the threshold voltage of the transistor in the scan data path becomes high during the scan test, both the change in the output data from the rising edge of the clock and the change in the input data taken in are delayed, and a hold error countermeasure is taken during the shift register operation. be able to. Further, by using the normal output terminal as a scan chain without providing the scan-dedicated output terminal, it becomes possible to evaluate the performance of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal. Since no new element is added, there is no factor of yield reduction, and the input capacitance of the clock system is unchanged, so it is possible to take measures against scan hold without degrading performance during normal operation.

According to the invention of claim 20, in the invention of claim 19, the threshold voltage of the transistor of the scan data path is made higher than the threshold voltage of the peripheral transistor thereof by applying the back bias during the scan test. Furthermore, by lowering the power supply voltage, there is a difference due to the difference between the threshold voltage and the power supply voltage that determines the transistor drive current and circuit operation speed.Therefore, the speed decrease of the high threshold voltage transistor is smaller than that of the low threshold voltage transistor. Is relatively large, and it is possible to obtain a larger effect of improving the measure against the hold error during the shift register operation.

According to the twenty-first aspect of the present invention, during the scan test, the power supply voltage to the circuit portion for which the speed of the scan data path is desired to be lowered becomes low, and the operation speed becomes slow. As a result, it is possible to take measures against a hold error when the shift register operates. In normal operation, the potential of the separated power supply is set to the same potential as the peripheral circuits,
There is no deterioration in circuit performance during normal operation. Further, by passing the normal output terminal instead of the scan-dedicated output terminal, it becomes possible to evaluate the quality of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal.
Since no new element is added, there is no factor of yield reduction, and the input capacitance of the clock system is completely unchanged, so that a measure for scan hold can be taken.

According to the invention described in Item 22, in addition to the same effect as the invention described in Item 21, is obtained.
In the scan test, in addition to lowering the power supply voltage to the circuit part where you want to reduce the speed of the scan data path, back bias is applied to the substrate potential,
Further, the threshold voltage is increased and a large amount of speed reduction can be obtained. Since the power supply potential in the area where the power supply potential is dropped and the power supply potential in the area that receives the output can be made only at a level that allows high / low signal transmission, a larger amount of speed reduction is required under such restrictions. Obtainable.

According to the twenty-third aspect of the present invention, the voltage applied between the source and the drain is reduced by raising the ground potential of the circuit portion for which the speed of the scan data path is desired to be reduced during the scan test. Will be late. As a result, it is possible to take measures against a hold error when the shift register operates. In the normal operation, the separated ground potential is set to be the same as the ground potential of the peripheral circuit, so that there is no deterioration in circuit performance during normal operation. Further, by passing the normal output terminal instead of the scan-dedicated output terminal, it becomes possible to evaluate the quality of the normal output terminal which is not seen in the hold countermeasure by adding the scan-dedicated output terminal. Since there is no addition of new elements,
There is no factor of yield reduction, and the input capacitance of the clock system is completely unchanged, so that a measure for scan hold can be taken.

According to the invention described in Item 24, in addition to obtaining the same effect as that of the invention described in Item 23,
During the scan test, the ground potential of the circuit part where you want to reduce the speed of the scan data path rises, the voltage applied between the source and drain decreases, and the back bias is applied to the substrate potential, further increasing the threshold voltage. It is possible to increase and obtain a large amount of speed reduction.
The power supply potential in the region that raises the source potential and the power supply potential in the region that receives the output can be differentiated only at a level that allows high / low signal transmission. Obtainable.

[Brief description of drawings]

FIG. 1A is a gate level circuit diagram of a scan flip-flop circuit in which a delay element is inserted in a scan input section of a first example according to a first embodiment of the present invention, and FIG.
FIG. 3 is a gate level circuit diagram showing a specific example of the delay element.

FIG. 2A is a circuit diagram in which an ON transistor is inserted in a scan input section of a second example according to the first embodiment of the present invention, and FIG. 2B is a third example according to the same embodiment. FIG. 6C is a circuit diagram in which a diode is inserted in the scan input section, and FIG. 7C is a circuit diagram in which a capacitance is added to the scan input section of the fourth example according to the embodiment.

FIGS. 3 (a) and 3 (b) are layout image diagrams for explaining a high threshold voltage increasing method according to a second embodiment of the present invention.

FIG. 4A and FIG. 4B are gate level circuit diagrams showing an example of a scan flip-flop circuit according to a second embodiment of the invention.

FIG. 5A is a gate level circuit diagram of a scan type flip-flop circuit according to a first example of the third embodiment of the present invention, and FIG. 5B is a transistor level circuit diagram thereof.

6A is a gate level circuit diagram of a scan type flip-flop circuit according to a second example of the third embodiment of the present invention, and FIG. 6B is a transistor level circuit diagram thereof.

FIG. 7 is an explanatory diagram of a block level according to a third embodiment of the present invention.

FIG. 8 is a chip image diagram in the case where a substrate bias potential according to a third embodiment of the present invention is supplied from the outside.

FIG. 9 is a chip image diagram in the case where a substrate bias potential according to the third embodiment of the present invention is created inside the chip.

FIG. 10 is a diagram showing a delay voltage dependency between a high threshold voltage transistor and a low threshold voltage transistor according to a fourth embodiment of the present invention.

FIG. 11 is a gate-level circuit diagram of a scan flip-flop circuit showing a first example according to the fifth embodiment of the present invention.

12A and 12B are gate level circuit diagrams of a scan type flip-flop circuit showing a second example according to the fifth embodiment of the present invention.

FIG. 13 is a gate-level circuit diagram of a scan flip-flop circuit showing a third example according to the fifth embodiment of the present invention.

FIG. 14 is a gate level circuit diagram of a scan flip-flop circuit according to a sixth embodiment of the present invention.

FIG. 15 is a transistor level circuit diagram of a scan flip-flop circuit according to a sixth embodiment of the present invention.

FIG. 16 is a gate level circuit diagram of a scan flip-flop circuit according to a seventh embodiment of the present invention.

FIG. 17 is a transistor level circuit diagram of a scan flip-flop circuit showing a first example according to the seventh embodiment of the invention.

FIG. 18 is a transistor level circuit diagram of a scan flip-flop circuit showing a second example according to the seventh embodiment of the invention.

FIG. 19 is a transistor level circuit diagram of a scan flip-flop circuit showing a third example according to the seventh embodiment of the invention.

FIG. 20 is an explanatory diagram of a block level in a third example according to the seventh embodiment of the present invention.

21A is a conceptual explanatory diagram of a scan flip-flop, and FIG. 21B is a scan shift scan chain configuration diagram.

FIG. 22 is a gate level circuit diagram of a conventional scan flip-flop circuit.

[Explanation of symbols]

10 Region for Applying Substrate Bias in Scan Test Mode 11 Region for Reducing Power Supply Voltage in Scan Test Mode 101 Flip-Flop 102 on Scan Chain Flip-Flop 103 on Scan Chain Clock Input Wiring 104 of Flip-Flop 101 Clock Input of Flip-Flop 102 Wiring 110 Delay element 111 Delay element 112 composed of multistage gates Pch transistor 113 in conduction state Nch transistor 115 in conduction state Diode 116 Scan data input receiving inverter 117 Scan data high impedance control transfer gate 118 Capacitance element 201 N well region 202 P well region 203 High Vt region definition layer 204 Scan input circuit unit 205 using high threshold voltage transistor High threshold Scan-only output circuit unit 300 that uses a value-voltage transistor Scan input circuit unit 301 that uses a transistor whose threshold voltage is increased by applying back bias 301 Scan-only output circuit unit 302 that uses a transistor whose threshold voltage is increased by applying a back bias Bias generation circuit 303 Internal bias generation circuit 501 Buffer unit 502 having a function of changing buffer capacity Inverter 503 Tri-state buffer 601 that is in a high impedance output state in scan test mode Scan data input circuit unit 602 Normal data input circuit unit 603 Mode switching Circuit unit 604 Master unit 605 Slave unit 606 Data output buffer unit 607 Clock input unit 701 Switch and load capacitance circuit 702 mode applied to data output unit Switch 703 for switching conduction / non-conduction with a switching signal 703 Load capacitance 704 Switch and load capacitance circuit provided to master unit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA01 AA03 AA05 AA06 AA17                       AB01 AC14 AD07 AK07 AK12                       AK14 AK15 AK23 AK27 AL11                       AL16                 5J043 AA09 EE01 HH06 JJ04 KK06                       KK07                 5J056 AA03 BB60 CC05 CC14 DD12                       DD29 EE00 FF01 FF08 GG14                       KK02

Claims (24)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits having a scan data input circuit portion and a normal data input circuit portion, wherein the plurality of scan flip-flop circuits function as a shift register during a scan test. A semiconductor integrated circuit comprising a delay element for delaying the transmission of scan data in the scan data input circuit section. 2. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits having a scan data input circuit portion and a normal data input circuit portion, wherein the plurality of scan flip-flop circuits function as a shift register during a scan test. The semiconductor integrated circuit is characterized in that the scan data input circuit unit has a transistor for data input, which is connected between power supply voltages, in series with a transistor in a redundant conductive state as a logical configuration. 3. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits having a scan data input circuit portion and a normal data input circuit portion, wherein the plurality of scan flip-flop circuits function as a shift register during a scan test. The scan data input circuit unit includes a data input transistor circuit connected between first and second power supply voltages, and is provided between the first power supply voltage and the data input transistor circuit or the data input transistor circuit. A semiconductor integrated circuit in which a diode is inserted in a forward direction between the input transistor circuit and the second power supply voltage. 4. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits having a scan data input circuit portion and a normal data input circuit portion, the scan integrated flip-flop circuits functioning as shift registers during a scan test. The scan data input circuit unit is characterized in that a load capacitance element is provided between an inverter for inputting scan data and a circuit connected to the output of the inverter for performing high impedance control. 5. A semiconductor integrated circuit comprising a plurality of scan type flip-flop circuits each having a scan data input circuit section and a normal data input circuit section, the plurality of scan type flip-flop circuits functioning as a shift register during a scan test. In the scan-type flip-flop circuit, transistors that constitute a scan-dedicated circuit portion through which data does not pass in the normal operation mode but only scan data in the scan test mode pass through circuits other than the scan-dedicated circuit portion. In order to increase the threshold voltage of the transistor forming the portion, the impurity concentration of the well region in which the transistor forming the scan-dedicated circuit portion is formed is adjusted to that of the well region in which the transistor forming the other circuit portion is formed. Higher than impurity concentration The semiconductor integrated circuit according to claim. 6. The semiconductor integrated circuit according to claim 5, wherein the scan-dedicated circuit portion configured by using a transistor having a high threshold voltage is a scan data input circuit portion. 7. A scan flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section, and the scan dedicated circuit section configured by using a transistor having a high threshold voltage is dedicated to the scan data. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is an output circuit section. 8. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits each having a scan data input circuit portion and a normal data input circuit portion, wherein the plurality of scan flip-flop circuits function as a shift register during a scan test. In the scan flip-flop circuit, the film thickness of the gate insulating film of the transistor forming the scan-dedicated circuit portion where the data does not pass in the normal operation mode but only the scan data in the scan test mode passes A semiconductor integrated circuit characterized in that it is thicker than a gate insulating film of a transistor constituting other circuit parts excluding the circuit part. 9. The semiconductor integrated circuit according to claim 8, wherein the scan-dedicated circuit portion configured by using a transistor having a thick gate insulating film is a scan data input circuit portion. 10. A scan flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section, and the scan dedicated circuit section configured by using a transistor having a thick gate insulating film outputs the scan data dedicated output. 9. The semiconductor integrated circuit according to claim 8, which is a circuit unit. 11. A semiconductor integrated circuit comprising a plurality of scan flip-flop circuits each having a scan data input circuit portion and a normal data input circuit portion, the plurality of scan flip-flop circuits functioning as a shift register during a scan test. In the scan type flip-flop circuit, the substrate potential of a transistor forming a scan dedicated circuit portion through which data does not pass in the normal operation mode but only scan data in the scan test mode passes, excluding the scan dedicated circuit portion, A semiconductor integrated circuit characterized by being electrically isolated from a substrate potential of a transistor constituting another circuit portion and having a back bias set on a side where a threshold voltage of a transistor constituting the scan-dedicated circuit portion becomes higher. 12. A scan-dedicated circuit portion in which a back bias is set on the side where the threshold voltage of a transistor is high,
12. The semiconductor integrated circuit according to claim 11, which is a scan data input circuit unit. 13. A scan type flip-flop circuit has a scan data dedicated output circuit section and a normal data output circuit section, and the scan dedicated circuit section in which back bias is set on the side where the threshold voltage of the transistor becomes high is the scan data. The semiconductor integrated circuit according to claim 11, wherein the semiconductor integrated circuit is a dedicated output circuit section. 14. A substrate potential of a transistor constituting a circuit portion other than the scan-dedicated circuit portion is inputted, and a substrate potential of a transistor constituting the scan-dedicated circuit portion whose back bias is set on the side where the threshold voltage becomes higher is set. 14. The semiconductor integrated circuit according to claim 11, further comprising a bias generating circuit for supplying the bias. 15. The semiconductor according to claim 2, wherein the power supply voltage in the scan test mode is lower than the power supply voltage in the normal operation mode. Integrated circuit. 16. A plurality of scan-type flip-flop circuits having a scan data input circuit section and a normal data input circuit section and having a data output circuit section for outputting data in a scan test mode and a normal operation mode are provided. A semiconductor integrated circuit that causes the plurality of scan-type flip-flop circuits to function as a shift register, wherein the data output circuit unit has a parallel circuit configuration of two paths in at least a part through which data passes, and one of the paths has a parallel circuit configuration. A second buffer unit is provided which transmits data in the scan test mode and the normal operation mode, and transmits the data to the other path in the normal operation mode and which has a high impedance output in the scan test mode. Semiconductor provided with Product circuit. 17. A plurality of scan flip-flop circuits each having a scan data input circuit section and a normal data input circuit section and having a data output circuit section for outputting data in a scan test mode and a normal operation mode are provided, and a scan type flip-flop circuit is provided. A semiconductor integrated circuit that causes the plurality of scan-type flip-flop circuits to function as shift registers, wherein one end is connected to a node on a scan data passage in the scan-type flip-flop circuit, which is in a conductive state in a scan test mode. A semiconductor integrated circuit comprising: a switch circuit that is turned off in an operation mode; and a load capacitance element connected between the other end of the switch circuit and a fixed potential. 18. A plurality of scan-type flip-flop circuits having a scan data input circuit section and a normal data input circuit section and having a data output circuit section for outputting data in a scan test mode and a normal operation mode are provided. A semiconductor integrated circuit that causes the plurality of scan flip-flop circuits to function as a shift register, wherein a node on a data passage path of the data output circuit unit is
A semiconductor integrated circuit characterized in that it is connected to a fixed potential through a switch circuit having a low drive capability that is conductive in a scan test mode and nonconductive in a normal operation mode. 19. A scan type flip-flop circuit having a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit having a plurality of scan type flip-flop circuits as a shift register at the time of a scan test, wherein the scan data input circuit section, the master section and the slave section are provided in the scan type flip-flop circuit. The substrate potential of the first transistor, which constitutes at least a part of the data output circuit section other than the section for performing high impedance control by a clock signal, is set to the source potential of the first transistor and the first transistor. Structure with transistor Electrically separated from the substrate potential of the second transistor that constitutes the other portion except the above-mentioned portion, and the substrate potential of the first transistor is set to the source potential of the first transistor and the first transistor in the normal operation mode. The substrate potential of the first transistor is set to the same potential as the substrate potential of the second transistor, and the substrate potential of the first transistor is back-biased so that the threshold voltage of the first transistor is higher than that of the second transistor in the scan test mode. A semiconductor integrated circuit characterized by the above. 20. The semiconductor integrated circuit according to claim 19, wherein the power supply voltage in the scan test mode is set to be lower than the power supply voltage in the normal operation mode. 21. A scan type flip-flop circuit having a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit having a plurality of scan type flip-flop circuits as a shift register at the time of a scan test, wherein the scan data input circuit section, the master section and the slave section are provided in the scan type flip-flop circuit. A power supply potential of a portion other than a portion for performing high impedance control by a clock signal and at least a portion of the data output circuit portion is electrically separated from a power supply potential of another portion, and in the normal operation mode, the power The power supply potential and the voltage of the other parts The semiconductor integrated circuit, characterized in that the potential is set to the same potential, the scan test mode and to set the power supply potential of said portion to a lower potential than the power supply potential of the other portion. 22. A scan type flip-flop circuit having a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit having a plurality of scan type flip-flop circuits as a shift register at the time of a scan test, wherein the scan data input circuit section, the master section and the slave section are provided in the scan type flip-flop circuit. A power supply potential connected to a source other than a portion for performing high impedance control by a clock system signal and a source of a transistor in a first circuit portion including at least a part of the data output circuit portion is set to the substrate potential of the transistor and the source potential of the transistor. First The power supply potential that is electrically separated from the power supply potentials of the other circuit parts except the path part and is connected to the source of the transistor in the normal operation mode is the same as the substrate potential of the transistor and the power supply potential of the other circuit part. And a power supply potential connected to the source of the transistor in the scan test mode is set to a potential lower than the substrate potential of the transistor and the power supply potential of the other circuit portion. Integrated circuit. 23. A scan-type flip-flop circuit having a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit having a plurality of scan type flip-flop circuits as a shift register at the time of a scan test, wherein the scan data input circuit section, the master section and the slave section are provided in the scan type flip-flop circuit. The ground potential of at least a portion of the portion other than the portion for performing high impedance control by a clock system signal and the data output circuit portion is electrically separated from the ground potential of the other portion, and in the normal operation mode, the ground potential of the portion is Ground potential and above The semiconductor integrated circuit of a ground potential portion is set to the same potential, the scan in the test mode, characterized in that so as to set the ground potential of the portion to a potential higher than the ground potential of the other portion. 24. A scan-type flip-flop circuit having a scan data input circuit section, a normal data input circuit section, a master section, a slave section, and a data output circuit section for outputting data in a scan test mode and a normal operation mode. A semiconductor integrated circuit having a plurality of scan type flip-flop circuits as a shift register at the time of a scan test, wherein the scan data input circuit section, the master section and the slave section are provided in the scan type flip-flop circuit. A ground potential connected to the source of the transistor in the first circuit section, which is formed of at least a part of the data output circuit section other than the section for performing high impedance control by a clock signal, is set to the substrate potential of the transistor and the ground potential. First Electrically separated from the ground potential of the other circuit portion except the circuit portion, the ground potential connected to the source of the transistor in the normal operation mode, the substrate potential of the transistor and the ground potential of the other circuit portion. The same potential is set, and in the scan test mode, the ground potential connected to the source of the transistor is set to a potential higher than the substrate potential of the transistor and the ground potential of the other circuit section. Semiconductor integrated circuit.