JP2003158269A - Insulated gate bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IGBT that can prevent the IGBT from being out of control and destruction and has superior turn-off characteristic with reduced tail current 95. SOLUTION: This insulated gate bipolar transistor 1 is provided with a collector area having a conductivity modulation function, an emitter area, and a gate electrode that is formed on a channel area between the collector area and emitter area, and it is also provided with an insulated gate control electrode G2 formed between the gate electrode and collector area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor suitable for use as a single semiconductor device such as a power converter of various power capacities, a power supply, a power amplifier, and an analog switch, or in an integrated manner. .

[0002]

2. Description of the Related Art In a conventional insulated gate bipolar transistor, in order to reduce tail current and ON voltage,
An insulated gate bipolar transistor (IGBT: characterized by having a control gate forcibly extracting carriers such as holes between the channel region and the collector region as follows.
Insulated Gate Bipolar Transistor). The present applicant has applied for an insulated gate bipolar transistor having a four-terminal structure in Japanese Patent Application No. 2001-248473. Hereinafter, a brief description will be given with reference to the drawings. In FIG. 6, the IGBT 7 includes a p ⁺ type semiconductor substrate 72a which is a part of the collector region, an Al collector electrode 71 formed by a sputtering method on the back surface side thereof, and a part of the collector region epitaxially formed on the surface side thereof. Is
n ^- type conductivity modulation layer 72b and this n ^- type conductivity modulation layer 72b
P doped with B, Al or Ga by ion implantation
Type channel region 73 and n ⁺ type emitter region 74 formed on the surface side thereof, emitter electrode 75 formed on p type channel region 73, n ⁺ type emitter region 74 p type channel region 73 and n ⁻ type conductivity A silicon oxide film 76a formed over the surface layer of the modulation layer 72b, a polysilicon gate 76b formed on the silicon oxide film 76a, a gate electrode 76c formed on the polysilicon gate 76b, and an n ^- type conductivity modulation layer. It has a control electrode 77b formed on 72b, and an n ⁺ layer 77a for making ohmic contact with the control electrode 77b and the conductivity modulation layer 72b.

Therefore, the IGBT 7 of this example has a control terminal G1 conductively connected to the control electrode 77b, a gate terminal G2 conductively connected to the gate electrode 76c, and a collector terminal C conductively connected to the collector electrode 71. A four-terminal structure having an emitter terminal E conductively connected to the emitter electrode 75 is provided. Here, the IGBT 7 has an n channel type field effect transistor (MOSFET: Metal Oxide Semicide) composed of an n ⁺ type emitter region 74, ap type channel region 73, and an n ⁻ type conductivity modulation layer 72b.
on-ductor field effect transistor), n ⁺ -type emitter region 74, p-type channel region 73, and n ⁻ -type conductivity modulation layer 7
Npn type bipolar transistor (BJT: Bi
polar Junction Transistor) and p-type channel region 73,
An n ⁻ type conductivity modulation layer 72b and a pnp type BJT composed of ap ⁺ type semiconductor substrate 72a which is a collector region are parasitically formed, and n ⁻ which corresponds to the n base of this pnp type parasitic transistor. The control electrode 77b is electrically connected to the type conductivity modulation layer 72b. Further, the control electrode 77b can also be regarded as a gate electrode of an npnp structure parasitic thyristor constituted by the n ⁺ type emitter region 74, the p type channel region 73, the n ⁻ type conductivity modulation layer 72b and the collector region 71.

Next, an equivalent circuit of the IGBT 7 will be described with reference to FIG. As shown in this figure, the p-type channel region 73
N-channel MOSFET 81 with n-channel and conductivity modulation layer
Pnp type BJT83 with 72b as n base and channel region 73 with p
And an npn-type BJT82 as a base. Where resistance 84
Is the short-circuit resistance of the p-type channel region 73 immediately below the n ⁺ -type emitter region 74. Next, the dynamic characteristics of the IGBT 7 will be described with reference to the timing chart shown in FIG. here,
The solid line 91 represents the gate drive signal V _G2 applied to the gate terminal G ₂ of the IGBT 7, the solid line 92 represents the control signal V _G1 applied to the control terminal G ₁ of the IGBT 7, and the solid line 93 represents the emitter terminal E and collector terminal C of the IGBT 7. the voltage waveform V _CE between the solid line 94 the current waveform I _CE between the emitter terminal E and the collector terminal C of the IGBT 7, respectively. First, on the IGBT7 side, the emitter electrode 75,
The gate electrode 76c and the control electrode 77b are set to the ground state as the lowest potential, and the collector electrode 71 is set to the positive potential. In this state, the IGBT 7, the MOSFET 81, and the parasitic BJT 82 (parasitic thyristor) are in the OFF state, so that the current I _CE between the emitter electrode 75 and the collector electrode 71 does not flow.

Next, at time t ₉₁ , the gate drive signal V
The application of a pulse of _G2 to the gate terminal G _2, in IGBT 7, begins an inversion layer is formed on the surface side of the p-type channel region 73 where the gate electrode 76c is opposed through the silicon oxide film 76a becomes a positive potential, the inversion layer Electrons start to be injected into the n ⁻ -type conductivity modulation layer 72b through the, and holes are started to be injected into the n ⁻ -type conductivity modulation layer 72b from the p ⁺ -type semiconductor substrate 72a. As a result, the collector current I _CE begins to flow between the collector electrode 71 and the emitter electrode 75 from time t ₉₃ , and is saturated at t ₉₄ . When turning off, when the pulse of the gate drive signal V _G2 is set to the ground state at time t ₉₅ , the IGBT 7
The polysilicon gate 76b becomes zero potential and the silicon oxide film 7
Inversion layer formed on the surface side of the p-type channel region 73 which faces through 6a starts to disappear, n via the inversion layer ^-
Since the holes injected from the p ⁺ type semiconductor substrate 72a to the n ⁻ type conductivity modulation layer 72b are not injected together with the electrons injected into the type conductivity modulation layer 72b, the collector current I _CE
Begins to decrease. At this time, the MOSFET 81 in the gate region is turned off and the base of the BJT 83 becomes floating. As a result, at the time of off n ^- for outflow route of holes which are minority carriers accumulated in the mold conductivity modulation layer 72b is interrupted, would occur is the tail current 95, as shown in FIG. 8, the time t ₉₉ Up to, the holes remain in the n ⁻ -type conductivity modulation layer 72b, so that the collector current becomes 0 for the first time at this point and the turn-off time is increased.

Therefore, at time t ₉₅ , the control terminal G ₁
A pulse of the control signal V _G1 that is a negative voltage is applied to the control electrode 77b to apply a negative potential to the holes remaining in the n ⁻ -type conductivity modulation layer 72b that causes the tail current 95. To start pulling out forcibly and reduce the current. As a result, time t
_{At 98} , the collector-emitter current becomes 0, and at time t
_{At 9 8} it is completely turned off. According to this embodiment, at the time of turn-off, the holes accumulated in the n ⁻ -type conductivity modulation layer 72b can be forcibly pulled out by the control terminal G ₁ and the generation of a tail current can be prevented. As a result, the turn-off time can be reduced as much as MOSFET, and the operating frequency can be increased.

[0007]

However, in the above-mentioned conventional insulated gate bipolar transistor, the holes accumulated in the n ⁻ type conductivity modulation layer 72b are controlled by the control electrode 77b arranged between the channel region and the collector region. I forcibly pulled it out. In this case, since the emitter electrode 75 and the collector electrode 71, through which a large current flows, are directly conductively connected to the control gate 77b, there is a risk that a large current will flow to the control electrode 77b and disable or destroy the control of the IGBT element. However, it cannot be said that the turn-off characteristic can be sufficiently improved. Therefore, it is an object of the present invention to provide an IGBT having good turn-off characteristics in which the uncontrollability and destruction of the IGBT are prevented and the tail current 95 is reduced.

[0008]

[Means for Solving the Problems] The invention according to claim 1 is
A collector region having a conductivity modulation effect, an emitter region,
A gate electrode formed on the channel region existing between the collector region and the emitter region, and a gate electrode
The present invention is characterized by having an insulated gate type control electrode provided between the collector regions. Due to the conductivity modulation effect, holes, which are minority carriers accumulated in the conductivity modulation layer at turn-off, are transferred to the gate electrode / collector. The insulated gate type control electrode provided between the electrodes causes a tunnel effect or an avalanche effect to forcefully pull out the tail current, thereby reducing the tail current and shortening the turn-off time. Therefore, the present invention is a four-terminal IGBT having an insulated gate type control electrode, a gate electrode, a collector electrode, and an emitter electrode. The invention according to claim 2 provides an emitter region, a gate electrode, and a channel region on a main surface of a semiconductor crystal having a pair of main surfaces, and a collector region and an insulated gate control electrode on one main surface. The insulated gate bipolar transistor according to claim 1, characterized in that
According to the IGBT described in claim 2, the tail current can be reduced and the turn-off time can be shortened.

According to the third aspect of the invention, an emitter region, a gate electrode, an insulated gate type control electrode and a channel region are formed on the main surface of a semiconductor crystal having a pair of main surfaces, and a collector region and an insulated gate type are formed on one main surface. 2. The insulated gate bipolar transistor according to claim 1, further comprising a control electrode. According to the IGBT described in claim 3, the turn-off time can be shortened by reducing the tail current. The invention according to claim 4 is characterized in that a collector region, a gate electrode, an emitter region and a channel region are provided on the main surface of a semiconductor crystal having a pair of main surfaces, and an insulated gate type control electrode is provided on one main surface. The insulated gate bipolar transistor according to claim 1. Claim
According to the IGBT described in 4, the tail current can be reduced and the turn-off time can be shortened.

The invention according to claim 5 is the insulated gate bipolar transistor according to any one of claims 2 to 4, wherein the gate electrode and the channel region have a trench structure. That is, a collector region, an emitter region, a gate electrode, an insulated gate type control electrode and a channel region are provided on the surface of the semiconductor crystal.
The insulated gate bipolar transistor described in 1. According to the invention of claim 5, the tail current can be reduced and the turn-off time can be shortened. The invention according to claim 6 is the insulated gate bipolar transistor according to any one of claims 2 to 5, characterized in that SiC is used for the semiconductor crystal. According to the invention described in claim 6, the turn-off time can be shortened by reducing the tail current.
Moreover, the loss can be reduced by using SiC. The invention according to claim 7 is the insulated gate bipolar transistor according to any one of claims 1 to 6, characterized in that the insulated gate bipolar transistor is integrated. According to the invention of claim 7, the tail current can be reduced and the turn-off time can be shortened. Also, by integrating, it can be used as a large capacity switching element.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION I of the first embodiment of the present invention
The GBT will be described based on FIGS. 1 and 2. In FIG. 1, the IGBT 1 includes a p ⁺ type semiconductor substrate 12a which is a part of the collector region, an Al collector electrode 11 formed by a sputtering method on the back surface side thereof, and a part of the collector region epitaxially formed on the front surface side thereof. And the n ^- type conductivity modulation layer 12b
A p-type channel region 13 in which B, Al or Ga is added to the ⁻ type conductivity modulation layer 12b by an ion implantation method, an n ⁺ type emitter region 14 formed on the surface side thereof, and a p-type channel region 1
3 and the emitter electrode 15 and the n ⁺ -type emitter region 14 formed on
A silicon oxide film 16a formed over the surface layers of the p-type channel region 13 and the n ⁻ -type conductivity modulation layer 12b, a polysilicon gate 16b formed on the silicon oxide film 16a, and a gate formed on the polysilicon gate 16b. It has an electrode 16c, a silicon oxide film 17a formed on the n ⁻ type conductivity modulation layer 12b, a polysilicon gate 17b formed on the silicon oxide film 17a, and an insulated gate control electrode 17c formed on the polysilicon gate 17b.

Therefore, the IGBT 1 of this example includes a control terminal G1 conductively connected to the insulated gate type control electrode 17c and a gate electrode 1
The four-terminal structure has a gate terminal G2 conductively connected to 6c, a collector terminal C conductively connected to the collector electrode 11, and an emitter terminal E conductively connected to the emitter electrode 15. Here, the IGBT 1 has an n ⁺ type emitter region 14, p
An n-channel MOSFET composed of a n ^- type conductivity modulation layer 12b and an n ^- type conductivity modulation layer 12b, and an n ⁺ type emitter region 14, a p-type channel region 13 and an n ^- type conductivity modulation layer 12b The npn-type BJT and the p-type channel region 13, the n ⁻ -type conductivity modulation layer 12b, and the pnp-type BJT composed of the p ⁺ -type semiconductor substrate 12a that is the collector region are parasitically formed. The insulated gate control electrode 17c is formed on the n ⁻ type conductivity modulation layer 12b corresponding to the n base of the pnp type parasitic transistor. Further, the insulated gate control electrode 17c includes an n ⁺ type emitter region 15, ap type channel region 14, and an n ⁻ type conductivity modulation layer 13.
It can also be regarded as the gate electrode of the parasitic thyristor having the npnp structure constituted by the collector region 11.

Next, an equivalent circuit of the IGBT 1 will be described with reference to FIG. As shown in this figure, the p-type channel region 13
N-channel MOSFET 21 with n-channel and conductivity modulation layer
Pnp type BJT23 with 12b as n base and channel region 13 with p
And an npn-type BJT22 serving as a base. Where resistance 24
Is the short-circuit resistance of the p-type channel region 13 immediately below the n ⁺ -type emitter region 14. According to this embodiment, a silicon oxide film is formed by dry oxidation so that a tunnel phenomenon or an avalanche phenomenon occurs with respect to the voltage applied to G1.
When 17a is manufactured by controlling the film thickness to about 5 nm to 30 nm, the holes accumulated in the n ⁻ -type conductivity modulation layer 13 at the time of turn-off are controlled by the control terminal G1 to form the silicon oxide film 17a by the tunnel effect or the avalanche effect. Through this, holes remaining in the n ⁻ -type conductivity modulation layer 12b can be forcibly drawn out and the generation of tail current can be prevented.

Therefore, the dynamic characteristic of the IGBT 1 becomes a timing chart almost equal to that of FIG. 3 shown in the conventional example. Also, G
Since 1 can be controlled by the voltage, it is possible to reduce the power consumption without causing the uncontrollability or destruction of the IGBT. As a result, the reliability can be improved, the turn-off time can be reduced as much as the MOSFET, and the operating frequency can be increased. The IGBT according to the second embodiment of the present invention is a vertical IGBT in which an insulated gate type control electrode is arranged on one main surface, as shown in FIG. According to this embodiment, holes remaining in the conductivity modulation layer are tunneled or
Since the avalanche effect is used to forcibly pull out through the silicon oxide film, the generation of tail current can be prevented. The IGBT according to the third embodiment of the present invention is a vertical IGBT in which an insulating gate type control electrode is arranged on the main surface and one main surface as shown in FIG. According to this embodiment, holes remaining in the conductivity modulation layer are forcibly pulled through the silicon oxide film by using the tunnel effect or the avalanche effect, so that the tail current is not generated. It can be prevented.

The IGBT according to the fourth embodiment of the present invention is
As shown in FIG. 5, it is a lateral IGBT in which an insulated gate type control electrode is arranged on one main surface. According to this embodiment, holes remaining in the conductivity modulation layer are forcibly pulled through the silicon oxide film by using the tunnel effect or the avalanche effect, so that the tail current is not generated. It can be prevented. The IGBT of the fifth embodiment of the present invention is
1. This is an IGBT in which the lateral MOSFET shown in FIGS. 3 to 5 is replaced with a trench structure MOSFET. Further, in the case where the IGBT of the sixth embodiment of the present invention uses SiC for the semiconductor substrate, the IGBT of the seventh embodiment integrates the IGBTs of the examples from the first example to the sixth example. In all cases, the same effect as that of the first embodiment can be expected.

[0016]

According to the invention of claim 1, a collector region having a conductivity modulation action, an emitter region, a gate electrode formed on a channel region existing between the collector region and the emitter region, and a gate It is characterized by having an insulated gate type control electrode provided between the electrode collector regions, and due to the conductivity modulation effect, holes that are minority carriers accumulated in the conductivity modulation layer at the time of turn-off,
The insulated gate type control electrode provided between the gate electrode and the collector electrode is forcibly pulled out to reduce the tail current and shorten the turn-off time. As a result,
The turn-off time can be reduced as much as MOSFET and the operating frequency can be increased. As a result, the operating frequency can be increased without impairing the on-voltage, the SOA, the applicable range, and without causing the element breakdown of the IGBT. From these, the IGBT of the present invention
Is used for a power semiconductor main circuit of a power control device such as a servo control device and an inverter, it has effects such as high reliability, high speed operation, high precision control, and reduction of switching loss. Claims 2, 3, 4, and 5 have the same effect as the above effect. According to the invention of claim 6, SiC
Therefore, the loss can be reduced. According to the invention of claim 7, by integrating the IGBT, it can be used as a large capacity switching element.

[Brief description of drawings]

FIG. 1 is a sectional view of an IGBT according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit of the IGBT according to the first embodiment of the present invention.

FIG. 3 is a sectional view of an IGBT according to a second embodiment of the present invention.

FIG. 4 is a sectional view of an IGBT according to a third embodiment of the present invention.

FIG. 5 is a sectional view of an IGBT according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional IGBT.

FIG. 7 is an equivalent circuit of a conventional IGBT.

FIG. 8 is a timing chart showing an operation state of a conventional IGBT.

[Explanation of symbols]

11,31,41,51 Collector electrode 12a, 32a, 42a, 52a p + type semiconductor substrate 12b, 32b, 42b, 52b n ^- type conductivity modulation layer 13,33,43,53 p type channel region 14,34,44 , 54 n ⁺ type emitter region 15,35,45,55 Emitter electrode 16a, 36a, 46a, 56a Silicon oxide film 16b, 36b, 46b, 56b Polysilicon gate 16c, 36c, 46c, 56c Gate electrode 17,37,47 , 57 n ⁺ layer 21 MOSFET 22 BJT 23 BJT 24 short-circuit resistance 71 collector electrode 72a p + type semiconductor substrate 72b n ⁻ type conductivity modulation layer 73 p type channel region 74 n ⁺ type emitter region 75 emitter electrode 76a silicon oxide film 76b poly Silicon gate 76c Gate electrode 77a n ⁺ layer 77b Control electrode 81 MOSFET 82 BJT 83 BJT 84 Short circuit resistance 91 Gate drive signal 92 Control signal 93 Voltage waveform between collector region and emitter region 94 Current waveform between collector region and emitter region 95 Tail current

Claims (7)

[Claims] 1. A collector region having a conductivity modulation effect,
An insulated gate bipolar transistor comprising an emitter region and a gate electrode formed on a channel region existing between the collector region and the emitter region, having an insulated gate type control electrode provided between the gate electrode and the collector region An insulated gate bipolar transistor characterized in that. 2. The emitter region, the gate electrode, and the channel region are provided on a main surface of a semiconductor crystal having a pair of main surfaces, and the collector region and the insulated gate control electrode are provided on one main surface. The insulated gate bipolar transistor according to claim 1, characterized in that 3. The emitter region, the gate electrode, the insulated gate type control electrode and the channel region on the main surface of a semiconductor crystal having a pair of main surfaces, and the collector region and the insulated gate type control on one main surface. 2. The insulated gate bipolar transistor according to claim 1, wherein an electrode is provided. 4. The collector region, the gate electrode, the emitter region and the channel region are provided on a main surface of a semiconductor crystal having a pair of main surfaces, and the insulated gate control electrode is provided on one main surface. The insulated gate bipolar transistor according to claim 1. 5. The insulated gate bipolar transistor according to claim 2, wherein the gate electrode and the channel region have a trench structure. 6. The insulated gate bipolar transistor according to claim 2, wherein SiC is used as a semiconductor crystal. 7. The integrated gate bipolar transistor according to claim 1, wherein the insulated gate bipolar transistor is integrated.
Insulated gate bipolar transistor according to paragraph.