JP2003150949A - Image processor and image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing method capable of easily altering or adding an image processing function and having excellent processing speed. SOLUTION: This image processing method has steps S7 and S12 for selecting a combination of a circuit module and a program module required for performing an applied image processing function, steps S8 and S13 for forming the circuit module by reconfiguring a reloadable hardware area of a semiconductor element according to the reload information including the information of the selected circuit module, and steps S9, S14 for performing the selected program module in the semiconductor element in which the circuit module is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device and an image processing method.

[0002]

2. Description of the Related Art Conventionally, a circuit provided in an image processing apparatus such as a scanner is an ASIC (Application Specific I) which is a custom IC optimally designed for a specific application.
ntegrated Circuit), the main part is made up. And when changing or adding features,
It is designed to be handled by software.

[0003]

However, although software is compatible with various image processes, it has a problem in processing speed, so that the range in which the functions of the image processing apparatus can be changed or added is extremely limited. Has been done.

On the other hand, a hardware circuit composed of an ASIC or the like is excellent in terms of processing speed, but is poor in flexibility and requires hardware development in order to change or add a function. Further, although it is possible to design an image processing apparatus capable of coping with a wide range of function changes, there is a problem in terms of manufacturing cost and development man-hours.

The present invention has been made to solve such a conventional problem, and an image processing apparatus and an image processing which can easily change or add an image processing function and are excellent in processing speed. The purpose is to provide a method.

[0006]

Means for Solving the Problems The present invention for achieving the above object is configured as follows.

(1) A semiconductor device having a rewritable hardware area, and a selection unit for selecting a combination of a circuit module and a program module required to execute an applied image processing function. Reconfiguring means for forming the circuit module by reconfiguring the rewritable hardware area based on rewriting information including information of the selected circuit module, the circuit An image processing apparatus, wherein a selected program module is executed in the semiconductor element having a module formed therein.

(2) The semiconductor element is a field
The image processing device according to (1) above, which comprises a programmable gate array.

(3) The image processing apparatus according to (1), further comprising a storage unit in which the information of the circuit module and the program module are stored.

(4) The image processing apparatus as described in (1) above, further comprising receiving means for receiving the information of the circuit module and the program module transmitted from an external device.

(5) A step for selecting a combination of a circuit module and a program module required to execute the applied image processing function, and a rewrite including information of the selected circuit module. Reconfiguring the rewritable hardware area of the semiconductor device based on the information to form the circuit module, and execute the selected program module in the semiconductor device in which the circuit module is formed. An image processing method, comprising:

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the scanner 20 which is the image processing apparatus according to the first embodiment of the present invention is connected to a computer 30 and a printer 40 via cables 61 and 62. The scanner 20 also has a slot for a memory card 50 which is a removable recording medium.

The computer 30 has a display device composed of a CRT monitor or a liquid crystal monitor, and an input device composed of a mouse and a keyboard.

Further, the computer 30 includes a scanner 20.
The driver software for controlling the display is installed, and the screen 31 as shown in FIG. 2 is displayed on the display device. Therefore, by using the mouse to click the command buttons 33 to 36, it is possible to request the scanner 20 to perform an operation or visually check the image data 32 generated by the scanner 20.

For example, the command button 33 "scan"
When is clicked, the image of the document is read by the scanner 20 and image data is generated. When the command button 34 “Save” is clicked, the image data is compressed and stored in the memory card 50.

When the command button 35 "print" is clicked, print data is created from the image data and sent to the printer 40. Further, when the command button 36 “transfer” is clicked, the image data is transmitted to the computer 30.

Next, the configuration of the scanner 20 will be described in detail with reference to FIG.

The scanner 20, as shown in FIG.
It has a control unit 21, memories 11 and 22, an image reading unit 23, an operation panel 24, an FPGA 10, a memory card unit 25, and interfaces 26 and 27, which are interconnected via a system bus 28.

The control section 21 is a control circuit composed of a microprocessor and the like, and each section 10, 11, 22, 2-2.
Control eight.

The memory 22 comprises a read-only memory such as a ROM and a high speed random access memory such as a RAM, and is used by the control unit 21.

The image reading section 23 is a CCD (Charge Coupl).
ed Device) has an image sensor and an A / D converter, reads an image of a document set at a predetermined reading position, generates an analog signal, and converts the analog signal into a digital signal. Output image data. The image reading unit 23 can also sequentially read images of a plurality of documents by including an ADF (automatic document feeder).

The operation panel 24 has a liquid crystal display used to display various messages and an input section used to input various items. The input unit has, for example, a touch panel arranged on the liquid crystal display, and a plurality of keys such as a numeric keypad arranged on the outside of the liquid crystal display, a start button, and a pause button.

The FPGA 10 is a field programmable gate array which is a semiconductor device having a rewritable hardware area. The FPGA 10 can appropriately form various circuit modules by reconfiguring the rewritable hardware area.

The memory 11 is a spare storage device used by the FPGA 10 and composed of a high speed random access memory such as a RAM.

The memory card section 25 includes a memory card 50.
Has a slot for storing data in the memory card 50
It is used to store data in the memory and read data stored in the memory card 50. The memory card 50 has a non-volatile memory such as a flash memory.

The interface 26 is a computer 30.
The interface 27 is for connection with the printer 4
For connection with 0.

Specific examples of the interfaces 26 and 27 include RS-232C, RS-422, and IEEE139.
4, serial interface such as USB (Universal Serial Bus), IEEE1284, SCSI (Small)
Computer System Interface) and other parallel interfaces.

IrDA that does not use a connection cable
It is also possible to apply a serial interface such as (Infrared Data Association). In addition, Blu
It is also possible to apply short-distance wireless communication based on standards such as etoth (registered trademark) and HomeRF.

The system bus 28 includes blocks 10 and 2
It has a data line connecting 1 to 17, an address line, and a control line.

Next, the structure of the memory card 50 will be described.

The memory card 50, as shown in FIG. 4, is hardware (HW) information 51, software information 52, which is rewriting information necessary for reconfiguring the rewritable hardware area of the FPGA 10. It has a code library table 53 and a page memory area 54 which is an area for storing image data.

The hardware information 51 is information for forming various circuit modules by reconfiguring the rewritable hardware area of the FPGA 10, for example, JEDEC (Joint Electron Device Engi).
neering) format.

As the circuit module, for example, a rotation processing hardware core (Rotater), a scaling processing hardware core (Scaler), a DMAC (direct access memory controller) hardware core, a DCT (Discrete Cosine Transformation). Hardware core, 8/16/32 bit RISC (Reduce
d Instruction Set Computer) MPU (Micro Processi)
ng Unit) hardware core, 32-bit DSP (Digit
al Signal Processor) hardware core, JPEG (j
oint photographic experts Group) Hardware core, JBIG (Joint Bi-level Image coding experts)
Group) hardware core, SRAM (Static RAM) hardware code, DRAM (Dynamic RAM) hardware code.

The software information 52 is information on a program module that can be executed in the FPGA 10 in which a circuit module is formed, and is described by, for example, an object code. Specifically, the program module is a program code for executing a rotation process, an enlargement / reduction process, a print data creation process, a JPEG process, a JBIG process, etc. using the circuit module.

The code library table 53 holds the specification information of the image processing function. The item of specification information is
As shown in FIG. 5, it includes the type, hardware, number of gates, program size, storage area size, and processing speed.

The type item is a list of applicable image processing functions. In the present embodiment, there are 5 types of JPEG compression, 4 types of JBIG compression, and 3 enlargement / reduction processes.
There are four types, four types of rotation processing, and one type of print sequence.

The hardware item indicates a configuration for realizing the above function. For example, JPEG-4 has 3
A 2-bit RISCMPU hardware core and a DCT hardware core are used, and a Scaler-1 uses an 8-bit RISCMPU hardware core and a Scaler is used.
er-2 uses a 32-bit DSP hardware core and Scaler-3 uses a rotation processing hardware core.

The number of gates item indicates the number of gates required to configure the hardware having the above function.

The program size item indicates the size of the software part of the above function. For example, using an 8-bit RISCMPU hardware core,
In order to execute the -1 processing, a program of 150 kilobytes is required. Note that the processing that uses a dedicated hardware core such as the DCT hardware core does not require a software part, so the program size is
It is indicated by "-".

The storage area size item indicates the storage capacity required as a storage area when the above function is executed.

The processing speed item indicates the processing speed of the above function. The unit is MIPS (Mega Instruction Per Se
cond). JPEG-4 is a 32-bit RI.
Since it is a combination of the SCMPU hardware core and the DCT hardware core, the processing speed as a whole is shown, and the individual processing speed is not shown (indicated by "-"). In addition, the processing speed of the print sequence is
Since it is inappropriate to represent by S, it is indicated by "-".

Therefore, from the rewriting information stored in the memory card 50, it is possible to select the optimum data required to execute the applied image processing function and read it as appropriate.

The rewriting information may be stored in advance in the memory 22 incorporated in the scanner 20. In this case, the memory card 50 is dedicated to storing image data. Further, the rewriting information can be stored in the storage device of the computer 30 in advance. In this case, the rewriting information is transferred from the computer 30 to the scanner 20 via the cable 61 in response to the request from the scanner 20.

Next, the image data of the original is transferred to the memory card 5
A case in which JPEG compression is performed to save 0 will be described. First, the JPEG compression algorithm will be described with reference to FIG.

R consisting of 8 bits for each color forming the original image
When the image data in the GB format is input, it is converted into the image data in the YCrCb format including the luminance signal Y and the color difference signal CrCb (color conversion). The color difference signal CrCb is subjected to thinning processing to compress the data amount (subsampling).

Then, the image data is divided into blocks of 8 × 8 pixels. Each divided block is D
CT is applied to obtain the DCT coefficients.

Next, DC which is the two-dimensional frequency component of the image
The T coefficient is divided by a quantization table that determines the resolution, and the quotient is used as the quantized value. The quantized values are grouped and sequentially connected and rearranged by zigzag scanning.

Huffman coding, which is a kind of arithmetic coding, is applied to the rearranged quantized values (Huffman coding). As a result, the obtained output image data becomes JPEG format storage data having a size of about 1/10 to 1/50 as compared with the input image data.

Next, referring to FIG. 7, the JPEG formed in the rewritable hardware area 100 of the FPGA 10.
The circuit module for compression will be described by taking the case of JPEG-4 as an example.

The DCT processing in the above algorithm is
Since the amount of calculation is the largest, there is a noticeable difference in performance between execution in software and execution in hardware. Therefore, for DCT processing, D
A circuit module 101 of the CT hardware core is formed.

Further, the circuit module 102 in which the JPEG processing program code for controlling the whole process including other processing is stored is formed. Then, a 32-bit RISCMPU as a microprocessor for executing the JPEG processing program code
The circuit module 103 of the hardware core and the SRAM hardware which is a storage area required for execution of the program, which is used as a work area of the program, a temporary storage area of intermediate results of calculations, and a storage area of the conversion table. An Accord circuit module 104 is formed.

The rewritable hardware area 10
When the storage area size available at 0 is insufficient, the storage area of the memory 11 can be used.

Further, the circuit module 105 of the DMAC hardware core is formed in order to execute the data transfer with the system bus 28 and the data transfer between the circuit modules efficiently and at high speed.

Therefore, by executing the selected program module in the FPGA 10 in which the selected circuit module is formed, the applied image processing function JPEG compression can be executed at high speed. The FPGA 10 has an interface 106 for receiving rewrite information for reconfiguring the rewritable hardware area 100 transferred from the memory card 50.

Next, a case in which print data creation is executed in order to print the image data by the printer 40 will be described.
First, an algorithm for creating print data will be described with reference to FIG.

R consisting of 8 bits for each color forming the original image
When the GB format image data is input, it is converted into YMCK format image data which is a color space printable by the printer 40 (colorimetric conversion).

The image data is rotated so as to match the direction of the paper set in the printer 40.
Further, the image data is enlarged or reduced according to the size of the paper.

Next, in order to improve the data transfer efficiency to the printer 40, JBI is applied to the image data.
G compression is applied. As a result, the obtained print data becomes compressed data having a size of about 1/10 to 1/50 of the size of the input image data.

Next, a circuit module for creating print data formed in the rewritable hardware area 100 will be described with reference to FIG.

Since the JBIG compression processing in the above algorithm has the largest amount of calculation, there is a significant difference in performance between the case where it is executed by software and the case where it is executed by hardware. Therefore, the circuit module 111 of the JBIG hardware core is formed for the JBIG compression process.

Since a large amount of calculation is required for the rotation processing and the scaling processing, the circuit module 11 of the rotation processing hardware core and the scaling processing hardware core is used.
2,113 are formed.

Further, the circuit module 114 in which the print data creation processing program code for controlling the whole process including other processing is stored is formed. A circuit module 115 of a 16-bit RISCMPU hardware core as a microprocessor for sequence control of the circuit modules 111 to 113, and a circuit module of a DRAM hardware code which is a storage area required for executing a program. 116 is formed.

As in the case of JPEG compression, DM
The circuit module 105 and the interface 106 of the AC hardware core are formed.

Therefore, as in the case of JPEG compression, print data creation, which is the image processing function to be applied,
It can be executed at high speed.

Next, the operation of the scanner 20 will be described with reference to FIG.

Immediately after the power is turned on, various parameters are initialized and circuit operations are checked (step S1).

Then, the command button 33 "scan" displayed on the screen of the display device of the computer 30.
Is clicked by the mouse (step S2:
YES), the image of the document set at the predetermined reading position of the image reading unit 23 is read, and the image data is generated (step S3).

Specifically, the CCD image sensor generates an analog signal corresponding to the image of the original, and the A / D converter converts the analog signal into a digital signal. The digital signal is temporarily stored in the memory 22 as image data.

Then, the image data 32 generated by executing the thinning-out process is displayed on the screen of the display device of the computer 30 in order to reduce the number of displayable pixels of the display device (step). S4).

Next, it is determined whether or not the command button 33 "scan" displayed on the screen is clicked by the mouse (step S5). If the determination in step S5 is affirmative, the process returns to step S3.

When the determination in step S5 is negative, it is further determined whether or not the command button 34 "save" displayed on the screen is clicked by the mouse (step S6).

If the determination in step S6 is affirmative, J
A process for receiving the rewrite information for executing the PEG compression (data storage reception process) is executed (step S7).

After that, the rewritable hardware area 100 is reconfigured based on the rewriting information to form a circuit module as shown in FIG. 7 (step S8). In addition, the JPEG compression is executed by executing the selected program module in the FPGA 10 (step S9).

Then, the JPEG format compressed data is stored in the page memory area 54 of the memory card 50 (step S10).

The memory card 50 is a removable recording medium. Therefore, for example, a portable computer having a memory card slot or a desktop computer to which a memory card reader is connected is used to read the image data stored in the memory card 50 and display the image data on the screen. It is also possible to edit with various applications.

On the other hand, when the determination in step S6 is negative, the command button 35 displayed on the screen is further added.
It is determined whether or not "print" is clicked by the mouse (step S11).

If the determination in step S11 is negative,
The process ends. On the other hand, if the determination in step S11 is affirmative, the process for receiving the rewrite information for executing the print data creation (data print reception process)
Is executed (step S12).

Then, based on the rewriting information, the FPGA
By reconfiguring the rewritable hardware area 100 of 10, the circuit module as shown in FIG. 9 is formed (step S13). In addition, FPGA10
In, the print data creation is executed by executing the selected program module (step S14).

Then, the print data is output to the printer 40 (step S15).

In addition to the above-described configuration in which the operation of the scanner 20 is indirectly instructed by the computer 30 in which the driver software is installed, the operation panel 24 of the scanner 20 is used to directly instruct the operation of the scanner 20. It is also possible to adopt.

Next, the data storage receiving process will be described in detail with reference to FIG.

First, as the device conditions, the maximum number of gates that can be configured in the FPGA 10 and the maximum available storage area size are set (step S101). For example, the maximum number of gates and the maximum storage area size are 150K gates and 512K bytes, respectively.

As an applied image processing function, J
PEG compression is set (step S102).

Next, the specification information held in the code library table 53 stored in the memory card 50 is referred to, and the hardware information 51 and software information 52 required for JPEG compression are selected (( Step S103).

For example, JPEG-5 has the maximum processing speed, but since it requires 200K as the number of gates, it does not satisfy the device condition. Next, JPEG-4, which has the next highest processing speed, requires 100K as the number of gates and 192K bytes as the storage area size, which satisfies the device conditions. Therefore, JPEG-4 is selected.

That is, the algorithm for selecting the type having the maximum processing speed satisfying the device condition is applied.

After that, the rewriting information consisting of the hardware information 51 and the software information 52 corresponding to the selected JPEG-4 is read from the memory card 50 (step S104).

Next, the data print reception process will be described in detail with reference to FIG.

First, as the device conditions, the maximum number of gates that can be configured in the FPGA 10 and the maximum available storage area size are set (step S111). For example, the maximum number of gates and the maximum storage area size are 150K gates and 512K bytes, respectively.

As an applied image processing function, J
Print data creation including BIG compression processing, rotation processing, and enlargement / reduction processing is set (step S112).

Next, the specification information held in the code library table 53 stored in the memory card 50 is referred to, and the hardware information 51 and software information 52 required for creating print data are selected. (Step S113).

For example, JBIG-4 and Scaler-3
And Rotator-4 combination has the highest processing speed. However, regarding the number of gates and storage area size,
JBIG-4, Scaler-3 and Rotator
-4 is 100 K and 128 K bytes, 5 K and 16 K bytes, and 5 K and 1024 K bytes, respectively, and the total storage area size does not satisfy the device condition.
That is, the storage area size required for Rotator-4 for rotation processing exceeds 512 Kbytes, which is a device condition.

On the other hand, Rota has the next highest processing speed.
The tor-3 requires 5K as the number of gates and 16K bytes as the storage area size. Therefore, the number of gates is 20K and the storage area size is 32K.
Even considering a 16-bit RISCMPU that executes a sequence control that requires bytes, the number of gates and the storage area size required for creating print data are 130K and 208K bytes, which satisfies the device condition. That is, JBIG-4, Scaler-3, and Rot
A combination of attor-3 is selected.

After that, the rewriting information consisting of the hardware information 51 and the software information 52 corresponding to the selected combination is read from the memory card 50 (step S114).

As described above, the image processing function can be easily changed or added, and the processing speed is excellent.

Next, a digital camera according to the second embodiment of the present invention will be described. It should be noted that members having the same functions as those in the first embodiment are denoted by similar reference numerals, and the description thereof will be omitted to avoid duplication.

As shown in FIG. 13, the digital camera 220, which is an image processing apparatus, includes cables 261 and 262.
The computer 230 and the printer 240 are connected via. The digital camera 220 also has a slot for a memory card 250, which is a removable recording medium.

As shown in FIG. 14, the digital camera 220 has a control section 221, memories 211 and 222, an image pickup section 223, an operation panel 224, an FPGA 210, a memory card section 225, and interfaces 226 and 227. , Are connected to each other via a system bus 228.

The image pickup section 223 is a CCD (Charge Coupled).
Device) image sensor and an A / D converter, which generates an analog signal from an optical image of a subject and digitally converts the analog signal to output digital image data.

As shown in FIG. 15, the operation panel 224 includes a liquid crystal display 231 used for displaying a photographed image 232 and various messages, and various keys 233.
˜236 and a power switch 237, the photographing key 233 is used to generate image data of an optical image of a subject. The save key 234 is used to compress the image data and store it in the memory card 250.
The print key 235 is used to create print data from image data and send the print data to the printer 240 for printing. The transfer key 236 is used to send the image data stored in the memory card 250 to the computer 230.

Next, referring to FIG. 16, the digital camera 2
The operation of 20 will be described.

First, when the power switch 237 is pressed, initialization such as initialization of various parameters and circuit operation check is executed (step S201).

Then, the photographing key 23 on the operation panel 224
When 3 is pressed (step S202: YES), the image capturing unit 223 generates image data of the subject (step S203). The digital signal is temporarily stored in the memory 222 as image data.

The image data is displayed on the screen of the liquid crystal display 231 of the operation panel 224 (step S20).
4). The image data 232 is generated by executing a thinning process in order to reduce the number of pixels that can be displayed by the liquid crystal display 231.

Next, it is determined whether or not the photographing key 233 has been pressed (step S205). Step S20
If the determination in 5 is affirmative, the process proceeds to step S2.
Return to 03.

If the determination in step S205 is negative, the save key 234 displayed on the screen is
It is determined whether or not it has been pressed (step S206).

When the determination in step S206 is affirmative, the process for receiving the rewriting information for executing the JPEG compression (data storage receiving process) is executed (step S207).

Then, based on the rewriting information, the FPGA
A circuit module is formed by reconfiguring the rewritable hardware area 100 of 210 (step S208). In addition, the JPEG compression is executed by executing the selected program module in the FPGA 210 (step S209).

Then, the compressed data in the JPEG format is stored in the page memory area of the memory card 250 (step S210).

On the other hand, if the determination in step S206 is negative, it is further determined whether or not the print key 235 has been pressed (step S211).

If the determination in step S211 is negative, the process ends. On the other hand, if the determination in step S211 is affirmative, the process for receiving the rewriting information for executing the print data creation process (data printing reception process) is executed (step S212).

After that, based on the rewriting information, the FPGA
A circuit module is formed by reconfiguring the rewritable hardware area of 210 (step S).
213). In addition, print data creation is executed by executing the selected program module in the FPGA 210 (step S214).

Then, the print data is output to the printer 40 (step S215).

As described above, the digital camera 220 according to the second embodiment, like the scanner 20 according to the first embodiment, can easily change or add the image processing function and is excellent in processing speed. There is.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the claims.

For example, as shown in FIG. 17, the rewriting information can be held in the storage device of the external server 370. In this case, the image processing device 320 has a communication interface composed of a network interface card (NIC), and the rewriting information held in the storage device of the external server 370 is stored in the network in response to a request from the image processing device 320. It is transferred to the image processing device 320 via 380.

The network 380 is, for example, TCP /
IP (Transmission Control Protocol / Internet Proto)
col) based protocol, a local area network (LAN), a wide area information network (WAN), the Internet, or a combination thereof.

The data link relating to the network 380 is, for example, Ethernet (registered trademark) or F
DDI (Fiber Distributed Data Interface).
Further, as a physical layer related to the network 380, the IE
It is also possible to apply a wireless LAN such as EE802.11.

The image data generated by the image processing device 320 is transmitted to the client computer 330 for storage, or the printer 34 for printing.
Sent to 0.

Further, the image processing apparatus is not limited to the form of a scanner or a digital camera, and may have the form of a mobile phone or a computer, for example.

For example, the mobile phone 420 shown in FIG.
In this case, the rewriting information stored in the storage device of the external server 470 includes the network 480, the access server 481, the mobile phone network, the general phone network, and the ISDN phone network in response to the request from the mobile phone 420. Mobile phone 420 via telephone network 482 and base station 483
Transferred to.

Further, as in the first and second embodiments, it is possible to provide a cell phone with a slot for a memory card and an interface for connecting to an external device with a cable.

Further, in the above-described embodiment of the present invention,
In addition to the inventions described in claims 1 to 5 of the claims, inventions as shown in the following supplementary notes 1 to 10 are included.

[Supplementary Note 1] The image processing apparatus according to claim 4, wherein the receiving unit has a network interface card, and the external device is connected via a network.

[Supplementary Note 2] The image processing apparatus according to claim 1, further comprising a reading unit for reading the information of the circuit module and the program module stored in a removable recording medium.

[Supplementary Note 3] The combination of the circuit module and the program module is based on the number of rewritable gates in the rewritable hardware area and / or the storage area size available for storing the program module. The image processing apparatus according to claim 1, wherein the image processing apparatus is selected.

[Supplementary Note 4] The image processing apparatus according to claim 1, wherein the image processing function is applied to create print data from image data.

[Supplementary Note 5] The image processing apparatus according to claim 1, wherein the image processing function is applied to compress and store image data.

[Supplementary Note 6] The rewriting information includes information on a circuit module for storing the selected program module and information on a circuit module for use as a storage area for executing the selected program module. The image processing apparatus according to claim 1, further comprising:

[Supplementary Note 7] The image processing apparatus according to claim 4, wherein the receiving unit has a serial interface, and the external device is serially connected.

[Supplementary Note 8] The image processing apparatus according to claim 4, wherein the recording medium is a memory card.

[Supplementary Note 9] An image reading unit for reading an image on a document to generate image data is further provided.
The image processing apparatus according to claim 1, wherein the image processing is applied to the image data.

[Supplementary Note 10] An image pickup device for generating image data from an optical image of a subject is further provided, and the image processing is applied to the image data. Image processing device.

[0135]

According to the present invention described above, the image processing function can be easily changed or added, and the image processing function is excellent in processing speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image processing system for explaining a scanner according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a display screen of a computer according to the image processing system.

FIG. 3 is a block diagram of a scanner.

FIG. 4 is a block diagram for explaining the configuration of a memory card inserted into a slot provided in the scanner.

5 is a diagram for explaining a code library table shown in FIG. 4. FIG.

FIG. 6 is a block diagram for explaining an algorithm of JPEG compression executed in a scanner.

FIG. 7 is a diagram illustrating a circuit module for JPEG compression formed in a rewritable hardware area of an FPGA included in a scanner.

FIG. 8 is a block diagram for explaining an algorithm for creating print data executed by the scanner.

FIG. 9 is a block diagram illustrating a circuit module for creating print data, which is formed in a rewritable hardware area of an FPGA included in a scanner.

FIG. 10 is a flowchart for explaining the operation of the scanner.

FIG. 11 is a flowchart for explaining the data storage reception process shown in FIG.

FIG. 12 is a flowchart for explaining the data print reception process shown in FIG.

FIG. 13 is a configuration diagram of an image processing system for explaining a digital camera according to a second embodiment of the present invention.

FIG. 14 is a block diagram of a digital camera.

FIG. 15 is a diagram showing an example of an operation panel of a digital camera.

FIG. 16 is a flowchart for explaining the operation of the digital camera.

FIG. 17 is a configuration diagram for explaining an image processing apparatus according to a third embodiment of the present invention.

FIG. 18 is a configuration diagram for explaining a mobile phone according to a fourth embodiment of the present invention.

[Explanation of symbols]

10, 210 ... FPGA, 11 ... memory, 20 ... Scanner, 21 ... Control unit, 11, 22 ... Memory, 23 ... Image reading unit, 24 ... Operation panel, 25 ... Memory card section, 26, 27 ... Interface, 28 ... system bus, 30, 230, 330 ... Computer, 31 ... Display screen, 33-35 ... command buttons, 40, 240, 340 ... Printer, 50,250 ... memory card, 51 ... Hardware information, 52 ... Software information, 53 ... Code library table, 54 ... page memory area, 61, 62, 261, 261 ... Cable, 220 ... digital camera, 221 ... Control unit, 211, 222 ... memory, 223 ... Imaging unit, 224 ... Operation panel, 225 ... a memory card section, 226, 227 ... Interface, 228 ... system bus, 320 ... Image processing device, 370, 470 ... Server, 380, 480 ... Network, 420 ... cell phone, 481 ... access server, 482 ... telephone network, 483 ... Base station.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshiyuki Mitsuhori             2-3-3 Azuchi-cho, Chuo-ku, Osaka             Kokusai Building Minolta Co., Ltd. F term (reference) 5B057 AA01 CH01 CH11 CH16 CH18

Claims (5)

[Claims] 1. A combination of a semiconductor device having a rewritable hardware area and a circuit module and a program module required to execute an applied image processing function,
Reconfiguring means for forming the circuit module by reconfiguring the rewritable hardware area based on reselecting means for selecting and rewriting information including information on the selected circuit module. And a selected program module is executed in the semiconductor element in which the circuit module is formed. 2. The image processing apparatus according to claim 1, wherein the semiconductor element comprises a field programmable gate array. 3. The image processing apparatus according to claim 1, further comprising a storage unit that stores information on the circuit module and a program module. 4. The image processing apparatus according to claim 1, further comprising a receiving unit for receiving the information of the circuit module and the program module transmitted from an external device. 5. A step for selecting a combination of a circuit module and a program module required to execute an applied image processing function, and rewriting information including information on the selected circuit module. Based on, by reconfiguring the rewritable hardware area of the semiconductor element, a step for forming the circuit module, in the semiconductor element in which the circuit module is formed,
And a step of executing the selected program module.