JP2003150082A - EL display device driving method, EL display device, manufacturing method thereof, and information display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EL (electroluminescence) display device having a satisfactory contrast. SOLUTION: In this EL display device, two lines of pixel rows are selected by applying an ON-voltage to gate signal lines. Programmed currents are outputted from a source signal line 18 to be programmed in selected write pixel rows 871a, 871b. Then, a picture is written in an entire display area by successively shifting write pixel rows. A dummy pixel row 2471 is selected at the low side part of a display area 21. Since EL film screens are not formed in the dummy pixel row, the row does not emit rays of light. Moreover, since the dummy pixel row is selected at the lower side of the picture, a current flowing through the source line 18 can be made constant. As a result, the black float of the picture is not generated in the device and a satisfactory contrast can be realized in the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to an EL display panel that displays an image by self-luminous display, an information display device such as a mobile phone using the EL display panel, and the like.

[0002]

2. Description of the Related Art Liquid crystal display panels are widely used in portable devices and the like because of their thinness and low power consumption. Therefore, devices such as word processors, personal computers, TVs, viewfinders and monitors for video cameras, etc. It is also used in.

[0003]

However, since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to form the backlight, there is a problem that the thickness of the display module becomes large. Further, in order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. for that reason,
There is a problem that the light utilization efficiency is low.

[0004]

In order to solve this problem, the present invention provides, firstly, an EL display device, which is an active matrix type EL display device, wherein at least one of an upper side and a lower side of the display area is provided. A pixel row that does not emit light or that shields emitted light is formed or arranged.

Secondly, in the EL display device driving method, the first operation is the driving method of the EL display device, in which a plurality of pixel rows are simultaneously selected and the same image data is applied to the selected pixel rows. And a second operation of sequentially shifting the selection positions of the pixel rows, and selecting the final pixel row,
It is characterized in that a third operation of selecting a pixel row formed or arranged in a region other than the image display region is performed.

Thirdly, the EL display device comprises pixels arranged in a matrix, a gate driver circuit for selecting the pixels, and a current output type source driver circuit for outputting image data applied to the pixels. The gate driver circuit sequentially selects the pixel rows, and when the gate driver circuit does not select the pixel rows, the source driver circuit outputs a write current in black display.

Fourth, in the EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, and a current output type source driver circuit for outputting image data applied to the pixels, A second pixel formed outside the display area, the gate driver circuit sequentially selects pixel rows, and when the gate driver circuit does not select a pixel row in the display area, the source driver circuit is An output current is written in a pixel formed outside the display area, or a current is absorbed from the pixel.

Fifth, in an EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, and a current output type source driver circuit for outputting image data applied to the pixels, A second pixel formed outside the display region, wherein a pixel electrode of the second pixel is electrically short-circuited with a cathode electrode or an anode electrode of the EL element.

Sixth, in an EL display device, pixels arranged in a matrix, a gate driver circuit for selecting the pixels, and a current output type source driver circuit for outputting image data applied to the pixels, A second pixel formed outside the display region, wherein the second pixel is not formed with an EL element or has a light-shielding unit for shielding light emitted from the EL element. And

Seventh, in the information display device, an EL display panel having pixels arranged in a matrix and second pixels formed outside the display area, a down converter, an up converter, and a receiver. , And a speaker.

Eighth, in the EL display device, an image memory, a counter circuit for counting the number of image data having a predetermined size or more, and a count value of the counter circuit being a predetermined value or more And a data conversion circuit for converting data so that the read data becomes small.

Ninth, in the EL display device, the pixels formed in a matrix and the EL formed in the pixels.
An element, a drive transistor element that supplies a current to the EL element, a switching element that controls that the current from the driving transistor element flows to the EL element, a gate driver circuit that sequentially selects the pixels, and a predetermined element And a control circuit that controls the switching element when the count value of the counter circuit is a predetermined value or more.

Tenth, in an EL display device, pixels formed in a matrix and E formed in the pixels.
An L element, a drive transistor element that supplies a current to the EL element, a gate driver circuit that sequentially selects the pixels, an electrode formed on the gate driver circuit, and an EL film formed on the electrode And is provided.

Eleventh, in the EL display device, the EL device is an active matrix type EL display device, in which the EL element formed in each pixel, a drive transistor element for supplying a current to the EL element, and the drive transistor element. A first capacitor for holding a potential of a gate terminal for a predetermined period, a second capacitor connected to one terminal of the first capacitor, and a control signal connected to another terminal of the second capacitor Line, and the potential of the gate terminal is shifted by the voltage applied to the control signal line.

Twelfth, the EL display device is an active matrix type EL display device, wherein an EL element formed in each pixel, a drive transistor element for supplying a current to the EL element, a switching transistor element, A first capacitor arranged between the gate terminal and the voltage terminal of the drive transistor element, and a second capacitor arranged between the gate terminal of the drive transistor element and the drain terminal of the switching transistor element, The drain terminal of the switching transistor element and the source terminal of the driving transistor are arranged to be short-circuited by selecting the switching element.

Thirteenth, the EL display device is an active matrix type EL display device, wherein a first EL element that emits red light, a second EL element that emits green light, and a third EL element that emits blue light. Element and a first drive transistor element that supplies a current to the first EL element, a second drive transistor element that supplies a current to the second EL element, and a current supply to the third EL element A third drive transistor element, a first switching element disposed between the first drive transistor element and the first EL element, and a second drive transistor element and the second EL element. The second switching element, the third driving transistor element, and the third EL element arranged in
A third switching element arranged between elements, a first gate signal line for simultaneously selecting the first drive transistor element, the second drive transistor element, and the third drive transistor element; A first control signal line for controlling on / off of the first switching element, a second control signal line for controlling on / off of the second switching element, and a third control signal line for controlling on / off of the third switching element. And a control signal line.

Fourteenth, in the driving method of the EL display device, there is provided a driving method of the active matrix EL display device, wherein at least one of a period for turning on and off the first EL element emitting red light and a time for turning on the first EL element is set. , Which is at least one of a cycle for turning on and off the second EL element that emits green light and an on time, and at least one of a cycle for turning on and off the third EL element that emits blue light and at least one time Is different from other EL elements.

Fifteenth, the EL display device is an EL display device, wherein an EL element formed in each pixel, a drive transistor element for supplying a current to the EL element, and an EL film formed in the pixel. An electrode formed on the EL film, a sealing film for preventing water from flowing into the EL film, and a light bending unit formed on the sealing film in correspondence with the pixel shape. It is characterized in that the light bending means is formed or arranged in a hexagonal shape.

Sixteenth, in the EL display device, the EL display device has pixels arranged in a matrix,
A current output circuit formed or arranged on each source signal line that outputs a current applied to the pixel; an analog current conversion circuit that converts digital image data into an analog current;
A current sampling circuit for sampling the current output from the analog current conversion circuit and holding the sampled current in the current output circuit.

Seventeenth, in the method of manufacturing an EL display device, the method of manufacturing an EL display device, wherein an EL film and a sealing film for preventing water from flowing into the EL film are formed on a substrate. And a second step of applying a transparent resin on the sealing film, and a roller having an uneven shape corresponding to the shape of the light bending means is pressed against the transparent resin to form the uneven shape. Is performed, and a fourth step of curing the transparent resin is performed.

Eighteenth, in the method of manufacturing an EL display device, the method of manufacturing an EL display device, wherein an EL film and a sealing film for preventing water from flowing into the EL film are formed on a substrate. A second step of forming a convex portion corresponding to a pixel shape on the sealing film, a third step of applying a transparent resin on the convex portion and the sealing film, and The method is characterized by performing a fourth step of curing the transparent resin.

Nineteenth, in the method of manufacturing an EL display device, the method of manufacturing an EL display device, wherein an EL film and a sealing film for preventing water from flowing into the EL film are formed on a substrate. And a second step of disposing a mask having an opening corresponding to the pixel shape at a predetermined distance from the sealing film, and a transparent material is sealed through the mask. And a third step of vapor-depositing on the stop film.

20th, in the method of manufacturing an EL display device, the method of manufacturing an EL display device, wherein an EL film and a sealing film for preventing water from flowing into the EL film are formed on a substrate. First step, a second step of applying a transparent resin on the sealing film, and a third step of pressing a press plate having an uneven shape corresponding to the shape of the light bending means against the transparent resin. And irradiating the transparent resin with light through the press plate to cure the transparent resin, thereby performing a fourth step.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION In the present specification, each drawing is omitted or enlarged or reduced in order to facilitate understanding or drawing. For example, in the cross-sectional view of the display panel shown in FIG. 5, the sealing film 73 and the like are shown sufficiently thick. In addition, FIG.
Etc., a thin film transistor (T
FT) etc. are omitted. Further, in the display panel and the like of the present invention, a phase film or the like for phase compensation is omitted, but it is desirable to add it at a proper time. The above also applies to the other drawings. Further, the parts having the same numbers or symbols have the same material, function or operation.

The contents described in the drawings and the like can be combined with other embodiments, etc., unless otherwise specified. For example, a touch panel or the like may be added to the display panel of FIG. 6 to provide the information display device as shown in FIGS. 232 and 243. In addition, a magnifying lens is attached to a viewfinder (see FIG. 23) such as a video camera (see FIG. 162).
9) can be configured. Also, FIG. 49 and FIG.
The driving method of the present invention described with reference to FIG. 97, FIG. 50, FIG. 60, etc. can be applied to any of the display device or display panel of the present invention. Further, although the present invention is mainly described with respect to an active matrix type display panel in which a TFT is formed in each pixel, it is needless to say that the present invention can be applied to a simple matrix type.

As described above, the matters, contents, and specifications described in the specification and drawings can be applied in combination with each other even if not specifically exemplified.

(Embodiment 1) At present, a plurality of organic electroluminescence (EL) elements are arranged in a matrix as a display panel which has low power consumption and high display quality and can be further thinned. Organic EL display panels have been attracting attention.

As shown in FIG. 2, the organic EL display panel has at least one layer including an electron transport layer, a light emitting layer, a hole transport layer, etc. on an array substrate 49 on which a transparent electrode as a pixel electrode 48 is formed. Organic EL layer 47 and reflective film 4
6 is laminated. Transparent electrode (pixel electrode) 48
By applying a positive voltage to the anode (anode) and a negative voltage to the cathode of the reflective film 46 and applying a direct current between them, the organic EL layer 47 emits light. As described above, by using an organic compound, which can be expected to have good light emitting characteristics, in the organic EL layer, the EL display panel can be put to practical use.

The cathode electrode, the anode electrode or the reflection film may be formed by forming an optical interference film made of a dielectric multilayer film on the ITO electrode. The dielectric multilayer film is a film (dielectric mirror) in which a low refractive index dielectric film and a high refractive index dielectric film are alternately formed in multiple layers. This dielectric multilayer film has a function (filter effect) of improving the color tone of light emitted from the organic EL structure.

A large current flows through the wirings 63 and 51 for supplying a current to the anode or the cathode. For example, E
1 when the screen size of the L display device becomes 40 inches
A current of about 00A flows. Therefore, the resistance value of these wirings needs to be sufficiently low. With respect to this problem, in the present invention, first, the wiring such as the anode is formed of a thin film. Then, a thick conductor is formed on the thin film wiring by an electrolytic plating technique. Also, if necessary,
The wiring itself or metal wiring made of thin copper is added to the wiring.

Further, in order to supply a large current to the anode or cathode wiring, a high-voltage, small-current power wiring is used from the current supply means to wire up to the vicinity of the anode wiring and the like, and a DCDC converter or the like is used to reduce the current. Voltage,
The power is converted into a high current and supplied. In other words, use the high-voltage, small-current wiring from the power supply to connect to the power consumption
Converts to large current and low voltage near the power consumption target. Examples of such devices include DCDC converters and transformers.

For the reflective film 46, it is preferable to use a material having a small work function such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy of each, particularly an Al--Li alloy. For the transparent electrode (pixel electrode) 48, a conductive material having a large work function such as ITO (tin-doped indium oxide) or gold can be used. When gold is used as the electrode material, the electrode becomes semitransparent. The ITO may be another material such as IZO. The same applies to the pixel electrode.

When depositing a thin film on the pixel electrode 48 or the like, it is advisable to form an organic EL film in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 nm or more and 50 nm or less on the ITO as the pixel electrode 48, the stability of the interface is improved, and the emission brightness and the emission efficiency are also improved.

Further, it goes without saying that the organic EL film is not limited to being formed by vapor deposition and may be formed by ink jet.

(Embodiment 2) Hereinafter, in order to facilitate understanding of the structure of the EL display panel of the present invention, first, a method of manufacturing the organic EL display panel of the present invention will be described.

The array substrate 49 may be formed of sapphire glass in order to improve heat dissipation. Alternatively, a thin film or a thick film having good thermal conductivity may be formed. For example, it is exemplified to use a substrate on which a diamond thin film is formed. Of course, a quartz glass substrate or a soda glass substrate may be used. Alternatively, a ceramic substrate made of alumina or the like, a metal plate made of copper or the like may be used, or an insulating film coated with a metal film by vapor deposition or coating may be used. When the pixel electrode is of a reflective type, since light is emitted from the surface direction of the substrate, a transparent or semi-transparent material such as glass, quartz or resin, or a non-transmissive material such as stainless steel may be used as the substrate material. it can. This configuration is shown in FIG. In FIG. 5, the cathode electrode is formed of a transparent electrode 72 such as ITO.

In the embodiment of the present invention, the cathode and the like are formed of a metal film, but the present invention is not limited to this, and may be formed of a transparent film such as ITO or IZO. In this way, by making both the anode and cathode electrodes of the EL element 15 transparent electrodes, a transparent EL display panel can be constructed. In other words, by increasing the transmittance to about 80% without using a metal film, it is possible to display a character or a picture while allowing the other side of the display panel to be almost transparent.

A plastic substrate may be used as the array substrate 49. Since the plastic substrate is hard to break and is lightweight, it is optimal as a substrate for display panels of mobile phones. The plastic substrate is preferably used as a laminated substrate by adhering an auxiliary substrate to one surface of a base substrate which is a core material with an adhesive. Of course, these substrates are not limited to plates, and films having a thickness of 0.05 mm or more and 0.3 mm or less may be used.

An alicyclic polyolefin resin is preferably used as the material of the base substrate. As such an alicyclic polyolefin resin, ARTO manufactured by Japan Synthetic Rubber Co., Ltd.
N (one plate having a thickness of 200 μm) is exemplified. From a polyester resin, polyethylene resin or polyether sulfone resin, etc., on one surface of the base substrate, a hard coat layer having heat resistance, solvent resistance or moisture permeation resistance function and a gas barrier layer having air permeation resistance function are formed. An auxiliary substrate (or film or film) is placed.

As described above, when the array substrate 49 is made of plastic, since the array substrate 49 is composed of the base substrate and the two auxiliary substrates, the other surface of the base substrate is also hard-coated as described above. An auxiliary substrate (or film or membrane) made of polyethersulfone resin or the like on which the layer and the gas barrier layer are formed is arranged. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.

As the adhesive, it is preferable to use a UV (ultraviolet) curing type acrylic resin and an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Also,
It is preferable that the difference in refractive index from the refractive index of the array substrate 49 be 0.03 or less. In particular, it is preferable to add a light diffusing material such as titanium oxide to the adhesive so that the adhesive functions as a light scattering layer.

When the respective auxiliary substrates are bonded to the base substrate, the angle formed by the optical slow axes of the respective auxiliary substrates is 45 degrees or more and 120 degrees or less, and more preferably 80 degrees or more and 100 degrees or less (approximately). 90 degrees) is preferable. Within this range, the phase difference generated in the auxiliary substrate and the auxiliary substrate, such as polyethersulfone resin, can be completely canceled in the laminated substrate. Therefore,
The plastic substrate for the organic EL display panel can be treated as an isotropic substrate having no phase difference.

With this structure, versatility is remarkably widened as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining with a retardation film, linearly polarized light can be converted into elliptically polarized light as designed. When the array substrate 49 or the like has a phase difference, this phase difference causes an error from the design value.

The hard coat layer in the auxiliary substrate can be made of epoxy resin, urethane resin, acrylic resin or the like as a material, and is used as the first undercoat layer of the transparent conductive film having the stripe electrodes or the pixel electrodes. Doubles as Further, as the gas barrier layer, Si
An inorganic material such as O ₂ or SiOx, or an organic material such as polyvinyl alcohol or polyimide can be used. As the pressure-sensitive adhesive, the adhesive or the like, an epoxy-based adhesive, a polyester-based adhesive, or the like can be used in addition to the acrylic-based adhesive described above. The thickness of the adhesive layer is 100 μm or less, but it is preferably 10 μm or more in order to smooth the surface irregularities such as the substrate.

Further, it is preferable to use, as the auxiliary substrate and the auxiliary substrate constituting the array substrate 49, those having a thickness of 40 μm or more and 400 μm or less. Further, by setting the thickness of each auxiliary substrate to 120 μm or less, it is possible to suppress unevenness or phase difference at the time of melt extrusion molding called die line of polyethersulfone resin. Therefore, the thickness is preferably 50 μm or more and 80 μm or less. And

Next, on this laminated substrate, SiOx is formed as an auxiliary undercoat layer of a transparent conductive film, and a transparent conductive film made of ITO to be a pixel electrode is formed by a sputtering technique. The transparent conductive film of the plastic substrate for an organic EL display panel manufactured as described above can realize a sheet resistance value of 25Ω / □ and a transmittance of 80% as its film characteristics.

The thickness of the base substrate is 50 μm to 100 μm
When the organic EL display panel is manufactured as described above, the plastic substrate for the organic EL display panel curls due to the heat treatment in the manufacturing process of the organic EL display panel. In addition, a crack is generated in the ITO forming the striped electrodes and the like, making it impossible to carry it thereafter. Also, good results cannot be obtained when connecting circuit components. However, when the thickness of the base substrate is 200 μm or more and 500 μm or less, the substrate is not deformed, the smoothness is excellent, the transportability is good, and the transparent conductive film characteristics are stable. Moreover, the connection of the circuit components can be performed without any problem. Further, since it has appropriate flexibility and flatness, it is considered preferable to set the thickness to 250 μm or more and 450 μm or less.

When an organic material such as the aforementioned plastic substrate is used as the array substrate 49, it is preferable to form a thin film made of an inorganic material as a barrier layer also on the surface in contact with the liquid crystal layer. The barrier layer made of this inorganic material is preferably formed of the same material as the AIR coat. The sealing lid 41 can also be manufactured by the same technique or configuration as the array substrate 49.

When the barrier layer is formed on the pixel electrode or the stripe electrode, it is preferable to use a low dielectric constant material in order to reduce the loss of the voltage applied to the light modulation layer as much as possible. For example, an amorphous carbon film containing fluorine (relative dielectric constant of 2.0 to 2.5) is exemplified. In addition, the LKD series (LKD-T200 series (dielectric constant 2.5-
2.7)), LKD-T400 series (relative permittivity 2.
0-2.2)) are exemplified. LKD series is MSQ
(Methy-silsesquioxane) based spin coating type, with a relative dielectric constant of 2.0-2.
It is as low as 7, which is preferable. In addition, an organic material such as polyimide, urethane, or acrylic, or an inorganic material such as SiNx or SiO ₂ may be used. There is no problem in using these barrier layer materials for the auxiliary substrate.

By using the array substrate 49 or the sealing lid 41 made of plastic, not only the advantages of not cracking and the weight reduction but also the advantage of press working can be obtained. That is, it is possible to manufacture a substrate having an arbitrary shape by pressing or cutting (see FIG. 3). Further, it can be processed into any shape and thickness by melting or chemical treatment. For example, a circular shape, a spherical shape (curved surface or the like), or a conical shape is exemplified. Further, by pressing, at the same time as manufacturing the substrate, the uneven portion 252 can be formed on the surface of one substrate to form a scattering surface or embossing.

It is also easy to form the positioning pins of the backlight or the cover substrate into the holes of the array substrate 49 formed by pressing the plastic. Further, an electric circuit such as a capacitor or a resistor formed by a thick film technique or a thin film technique may be formed in the array substrate 49 and the sealing lid 41.
Further, a concave portion (not shown) is formed in the sealing lid 41, a convex portion 251 is formed in the array substrate 49, and the concave portion and the convex portion are formed so that they can be fitted into each other. The array substrate 49 may be configured so that it can be integrated by fitting.

When a glass substrate is used, a bank used for vapor deposition of an EL element is formed around the pixel 16. The bank (rib) is formed of a resin material in a convex shape with a thickness of 1.0 μm or more and 3.5 μm or less, more preferably 1.5 μm or more and 2.5 μm or less. The bank (convex portion) 251 made of this resin can be produced at the same time when the sealing lid 41 or the array substrate 49 is formed by pressing (see FIG. 3). This is a great effect generated by forming the sealing lid 41 and the array substrate 49 with resin. The bank material may be an SOG material as well as an acrylic resin or a polyimide resin.

As described above, since the resin portion is formed at the same time as the substrate, the manufacturing time can be shortened and the cost can be reduced. Further, when the array substrate 49 or the like is manufactured, the convex portions 251 are formed in a dot shape in the display area portion. This convex part 2
By forming 51 between adjacent pixels, a predetermined space between the sealing lid 41 and the array substrate 49 is held. The bank shape may be a square shape surrounding the pixel electrode or a stripe shape.

In the above embodiments, the convex portion 251 functioning as a bank is formed, but the present invention is not limited to this. For example, the pixel portion may be dug down (recessed portion) by pressing or the like. The uneven portion 252,
The convex portion 251 is formed at the same time as the substrate, and also includes a method of forming a flat substrate first and then pressing by reheating to form irregularities.

Further, a mosaic color filter may be formed by directly coloring the sealing lid 41 and the array substrate 49. Dyes, pigments, etc. are applied and permeated onto the substrate using a technique such as inkjet printing. After penetration,
It may be dried at a high temperature and the surface may be coated with a resin such as a UV resin or an inorganic material such as silicon oxide or nitric oxide. Alternatively, the color filter may be formed by a gravure printing technique, an offset printing technique, a semiconductor pattern forming technique in which a film is applied and developed by a spinner. In addition to the color filter, a similar technique may be used to directly form a black or dark color or a black matrix (BM) having a complementary color relationship with the light to be modulated by coloring. Alternatively, a recess may be formed on the surface of the substrate so as to correspond to the pixel, and a color filter, BM, or TFT may be embedded in the recess. Particularly, it is preferable to coat the surface with an acrylic resin. This structure also has an advantage that the pixel electrode surface and the like are smoothed.

Alternatively, the resin on the substrate surface may be made conductive by a conductive polymer or the like to directly form the pixel electrode or the cathode electrode. Furthermore, make a large hole in the board,
A configuration in which an electronic component such as a capacitor is inserted into this hole is also exemplified. As a result, the advantage that the substrate can be made thin is exhibited.

By cutting the surface of the substrate,
The pattern may be formed freely. Alternatively, it may be formed by melting the peripheral portions of the sealing lid 41 and the array substrate 49. In the case of an organic EL display panel, in order to prevent moisture from entering from the outside, the peripheral portion of the substrate may be melted and sealed.

As described above, by forming the substrate with resin, it is easy to make a hole in the substrate. Further, the substrate shape can be freely configured by pressing or the like.

In order to use the sealing lid 41 and the array substrate 49 as a multi-layer circuit board or a double-sided substrate, holes are formed in the sealing lid 41 and the array substrate 49, and the holes are filled with a conductive resin or the like. It is also possible to electrically connect the front and back of the substrate.

Further, the sealing lid 41 and the array substrate 49 themselves may be a multilayer wiring substrate. For example, you can insert a conductive pin instead of conductive resin, or insert the terminals of electronic parts such as capacitors into the formed holes,
Alternatively, thin film circuit wiring, capacitors, coils, or resistors may be formed in the substrate. Since the multi-layer structure is formed by bonding thin substrates, one or more substrates (films) to be bonded may be colored at this time.

Further, the substrate itself can be colored by adding a dye or pigment to the substrate material, or a filter can be formed. Further, the serial number can be formed at the same time when the substrate is manufactured. Also, by coloring only the portion other than the display area, malfunction can be prevented by irradiating the loaded IC chips with light.

Further, half of the display area of the substrate can be colored with different colors. For this, a resin plate processing technique (injection processing, complexion processing, etc.) may be applied. Further, by using the same processing technique, half of the display area can have different EL layer thicknesses. Further, the display portion and the circuit portion can be formed at the same time. It is also easy to change the substrate thickness between the display area and the driver loading area.

Further, the sealing lid 41 or the array substrate 49
In addition, the microlenses can be formed so as to correspond to the pixels or the display region. Further, the diffraction grating may be formed by processing the sealing lid 41 and the array substrate 49. Further, by forming irregularities that are sufficiently finer than the pixel size, the viewing angle can be improved or the viewing angle dependency can be provided. It should be noted that such arbitrary shape processing and fine processing technology can be realized by a stamper technology developed by OMRON Corporation for forming microlenses.

Striped electrodes (not shown) are formed on the sealing lid 41 and the array substrate 49. In addition, an antireflection film (AIR coat) is provided on the surface of the substrate that comes into contact with air.
When another constituent material such as a polarizing plate (polarizing film) is attached, an antireflection film (AIR coat) is formed on the surface of the constituent material. Further, when a polarizing plate or the like is not attached to the sealing lid 41 or the array substrate 49, the antireflection film (AIR coat) is directly formed on the sealing lid 41 or the array substrate 49.

In the above embodiments, the explanation has been centered on that the sealing lid 41 and the array substrate 49 are made of plastic, but the present invention is not limited to this. For example, even if the sealing lid 41 and the array substrate 49 are a glass substrate or a metal substrate, the uneven portion 252, the convex portion 251, or the like can be formed or configured by pressing or cutting.
Further, it is not limited to the substrate. For example, it may be a film or a sheet.

Further, in order to prevent or suppress the adhesion of dust to the surface of the polarizing plate, it is effective to form a thin film made of fluororesin. Further, in order to prevent static electricity, a thin film having a hydrophilic group, a conductive polymer film, a conductor film such as a metal film may be applied or vapor-deposited.

The polarizing plate (polarizing film) arranged or formed on the light incident surface or the light emitting surface of the display panel 82 is not limited to linearly polarized light, and may be elliptically polarized light. Good. In addition, a plurality of polarizing plates may be stuck together, a polarizing plate and a retardation plate may be combined, or ones that are stuck together may be used.

A TAC film (triacetyl cellulose film) is used as a main material for the polarizing film.
Is the best. This is because the TAC film has excellent optical properties, surface smoothness and processability. For the production of TAC film, it is optimal to produce it by the solution casting film forming technique.

The AIR coat is exemplified by a structure formed of a dielectric single layer film or a multilayer film. Others, 1.35
A resin having a low refractive index of 1.45 may be applied. For example,
Examples include fluorine-based acrylic resins, and those having a refractive index of 1.37 or more and 1.42 or less are particularly preferable.

The AIR coat has a three-layer structure or a two-layer structure. In the case of three layers, it is used to prevent reflection in a wide wavelength band of visible light, and this is called multicoat. In the case of two layers, it is used to prevent reflection in a specific visible light wavelength band, and this is called a V coat. The multi coat and the V coat are used properly according to the use of the display panel. The AIR coat is not limited to two layers or more and may be one layer. In this case, magnesium fluoride (MgF ₂ ) is formed by stacking nd1 = λ / 2.

In the case of multi-coating, aluminum oxide (Al ₂ O ₃ ) has an optical film thickness nd = λ / 4, zirconium (ZrO ₂ ) has nd1 = λ / 2, and magnesium fluoride (MgF ₂ ) has nd1 =. It is formed by laminating λ / 4. Usually, the thin film is formed with a value of λ = 520 nm or a value in the vicinity thereof.

In the case of V coat, silicon monoxide (Si
O) is an optical film thickness nd1 = λ / 4 and magnesium fluoride (MgF ₂ ) is nd1 = λ / 4, or yttrium oxide (Y ₂ O ₃ ) and magnesium fluoride (MgF ₂ ) are n.
d1 = λ / 4 stacked layers are formed. Since SiO has an absorption band on the blue side, it is preferable to use Y ₂ O ₃ when modulating blue light also from the viewpoint of the stability of the substance. Alternatively, a SiO ₂ thin film may be used. Of course, the AIR coat may be made by using a resin having a low refractive index. For example, acrylic resin such as fluorine is exemplified. It is preferable to use an ultraviolet curing type of these.

In order to prevent the display panel from being charged with static electricity, a hydrophilic resin is applied to the surface of the light guide plate such as the cover substrate or the display panel 82, or the substrate material of the panel or the like. It is preferable that the material is composed of a material having good hydrophilicity. In addition, in order to prevent surface reflection, the surface of the polarizing plate 54 may be embossed.

A thin film transistor (TFT) as a plurality of switching elements or current control elements is formed in one pixel. The TFTs to be formed may be TFTs of the same type, or P-channel type and N-channel type TFTs.
Although different types of TFTs may be used, it is desirable that the switching thin film transistor and the driving thin film transistor have the same polarity. Also TFT
The structure is not limited to a planar type TFT, and may be a stagger type or an inverted stagger type, or may be a non-impurity type in which an impurity region (source, drain) is formed by using a self-alignment method. A self-aligned method may be used.

The EL element 15 of the present invention is an EL device in which an ITO serving as a hole injecting electrode (pixel electrode), one or more kinds of organic layers, and an electron injecting electrode are sequentially laminated on an array substrate.
A TFT is provided on the array substrate having a structure.

To manufacture the EL device of the present invention, first,
An array of TFTs is formed in a desired shape on a substrate. Then, ITO, which is a transparent electrode (pixel electrode) on the smoothing film, is formed by a sputtering method and patterned. Then Organic E
An L layer, an electron injection electrode, etc. are laminated.

As the TFT, an ordinary polycrystalline silicon T is used.
FT may be used. The TFT is provided at the end of each pixel of the EL structure and has a size of about 10 to 30 μm.
The size of the pixel at this time is 20 μm × 20 μm to 300 μm.
It is about m × 300 μm.

Wiring electrodes of TFTs are provided on the array substrate. The wiring electrode has a low resistance, and also has a function of electrically connecting the hole injection electrode to keep the resistance value low,
Generally, the wiring electrodes are made of Al, Al and transition metals (excluding Ti), Ti or titanium nitride (Ti
Materials containing any one or more of N) are used, but the present invention is not limited to this material. Hole injection electrode and TF which are the base of EL structure
The total thickness including the wiring electrode of T is not particularly limited, but is usually about 100 to 1000 nm.

An insulating layer is provided between the wiring electrode of the TFT 11 and the organic layer of the EL structure. The insulating layer is formed by depositing an inorganic material such as silicon oxide such as SiO ₂ or silicon nitride by sputtering or vacuum deposition, a silicon oxide layer formed by SOG (spin on glass), photoresist, polyimide, acrylic. Any insulating material such as a coating film of a resin-based material such as a resin may be used, but of these, polyimide is preferable. The insulating layer also plays a role of a corrosion / water resistant film that protects the wiring electrodes from moisture and corrosion.

The EL structure may have two or more emission peaks. For example, the green and blue light emitting portions in the EL device of the present invention are obtained by combining a blue green light emitting EL structure with a green transmission layer or a blue transmission layer. The red light emitting portion is composed of a blue green light emitting EL structure and this E structure.
It can be obtained by a fluorescence conversion layer that converts the blue-green emission of the L structure into a wavelength close to red.

Next, E constituting the EL element 15 of the present invention
The L structure will be described. The EL structure of the present invention has an electron injection electrode which is a transparent electrode, at least one organic layer, and a hole injection electrode. The organic layer has at least one hole transport layer and at least one light emitting layer, for example, an electron injecting and transporting layer, a light emitting layer, a hole transporting layer, and a hole injecting layer in that order. The hole transport layer may be omitted. The organic layer of the EL structure of the present invention can have various configurations,
The electron injecting / transporting layer may be omitted, or the light emitting layer may be integrated, or the hole injecting / transporting layer and the light emitting layer may be mixed.

As the material of the hole injecting electrode, since the light emitted from the hole injecting electrode side is extracted,
Examples thereof include TO (tin-doped indium oxide), IZO (zinc-doped indium oxide), ZnO, SnO ₂ , and In ₂ O ₃ , and ITO and IZO are particularly preferable. The thickness of the hole injecting electrode may be a certain thickness or more at which hole injection can be sufficiently performed, and it is usually preferable to set the thickness to about 10 to 500 nm. The material of the hole injecting electrode is required to have a low driving voltage in order to improve the reliability of the element, but a preferable material is ITO having a resistance of 10 to 30 Ω / □ (a film thickness of 50 to 300 nm). To be In actual use, the film thickness and optical constants of the electrodes may be set so that the interference effect due to reflection at the interface of the hole injecting electrode such as ITO sufficiently satisfies the light extraction efficiency and color purity. The hole injecting electrode can be formed by a vapor deposition method or the like, but is preferably formed by a sputtering method.
The sputtering gas is not particularly limited, and Ar,
An inert gas such as He, Ne, Kr, Xe, or a mixed gas thereof may be used.

The electron injecting electrode is made of a material using a metal, compound or alloy having a small work function, which is formed by sputtering or preferably vapor deposition. For example, K, L
i, Na, Mg, La, Ce, Ca, Sr, Ba, A
Metal element simple substance such as l, Ag, In, Sn, Zn, Zr,
Or two components containing them to improve stability,
Alternatively, it is preferable to use a three-component alloy system. As an alloy system, for example, Ag / Mg (Ag: 1 to 20 at)
%), Al.Li (Li: 0.3 to 14 at%), In
-Mg (Mg: 50-80 at%), Al-Ca (C
a: 5 to 20 at%) and the like are preferable. The thickness of the electron injecting electrode thin film may be a certain thickness or more capable of sufficiently injecting electrons, and may be 0.1 nm or more, preferably 1 nm or more. The upper limit is not particularly limited, but usually
The film thickness may be about 100 to 500 nm.

The hole injecting layer has a function of facilitating the injection of holes from the hole injecting electrode, and the hole transporting layer has a function of transporting holes and a function of hindering electrons, and the charge injection It is also called a layer or a charge transport layer.

The electron injecting and transporting layer is provided when the compound used for the light emitting layer does not have a very high electron injecting and transporting function, and the function of facilitating the injection of electrons from the electron injecting electrode,
It has a function of transporting electrons and a function of hindering holes.

These hole injecting layer, hole transporting layer and electron injecting and transporting layer increase and seal the holes and electrons injected into the light emitting layer, optimize the recombination region and improve the light emitting efficiency. There is a function to do. Note that the electron injecting and transporting layer may be separately provided in a layer having an injecting function and a layer having a transporting function.

The thickness of the light emitting layer, the combined thickness of the hole injecting layer and the hole transporting layer, and the thickness of the electron injecting and transporting layer are not particularly limited, and are usually 5 to 100 n although they vary depending on the forming method.
It is preferably about m.

The thicknesses of the hole injecting layer, the hole transporting layer and the electron injecting and transporting layer are the same as the thickness of the light emitting layer or about 1/10 to 10 times, depending on the design of the recombination / light emitting region. And it is sufficient. The thicknesses of the hole injection layer and the hole transport layer, and the thicknesses of the electron injection layer and the electron transport layer when separated, are preferably 1 nm or more for the injection layer and 20 nm or more for the transport layer. At this time, the upper limit of the thickness of the injection layer and the transport layer is usually about 100 nm in the injection layer and 1 in the transport layer.
It is about 00 nm. Such a film thickness is the same when two injecting and transporting layers are provided.

By controlling the film thickness while considering the carrier mobility and carrier density (determined by the ionization potential / electron affinity) of the light emitting layer, electron injecting and transporting layer and hole injecting and transporting layer to be combined, the recombination region is obtained. -It is possible to freely design the light emitting region, and it is possible to design the light emitting color, control the light emitting luminance and light emitting spectrum by the interference effect of both electrodes, and control the spatial distribution of light emission.

The light emitting layer of the EL element 15 of the present invention contains a fluorescent substance which is a compound having a light emitting function. Examples of the fluorescent substance include, for example, JP-A-63-2646.
92, etc., metal complex dyes such as tris (8-quinolinolato) aluminum (Alq3), JP-A-6-110569 (phenylanthracene derivative), JP-A-6-114456 (tetraaryl). Ethene derivatives), and blue-green light emitting materials as disclosed in JP-A-6-100857 and JP-A-2-247278.

The blue light-emitting EL element 15 is made of a material for the light-emitting layer, such as “DMPhen (Trip
It is preferable to use "hylamine)". At this time, the electron injection layer (Bathocup
It is preferable that the same material as that of the light emitting layer has the same band gap as the hole injection layer and the hole injection layer (m-MTDATXA). It has a band gap of 3.4.
Only using eV and large DMPhen for the light emitting layer,
This is because electrons remain in the electron injection layer and holes remain in the hole injection layer, so that recombination of electrons and holes does not easily occur in the light emitting layer. The problem that the structure of the light emitting material having an amine group such as DMPhen is unstable and it is difficult to prolong the life can be solved by transferring the energy excited in DMPhen to the dopant and causing the dopant to emit light.

The luminous efficiency can be improved by using a phosphorescent material as the EL material. The fluorescent material has an external quantum efficiency of about 2 to 3%. The fluorescent material has an internal quantum efficiency (efficiency of converting energy by excitation into light) of 25%, whereas the phosphorescent material has a quantum efficiency of nearly 100%, and thus the external quantum efficiency is high.

CBP may be used as the host material of the light emitting layer of the EL element. Here, red (R), green (G), and blue (B) phosphorescent materials are doped. All doped materials contain Ir. R material is Btp2Ir (acac), G material is (ppy) 2I
FIrpic is preferably used for the r (acac) and B materials.

The hole injecting layer / hole transporting layer can be formed, for example, in JP-A-63-295695 and JP-A-2-19.
1694, JP 3-792, JP 5-
234681, JP-A-5-239455,
JP-A-5-299174 and JP-A-7-12622
Japanese Patent Laid-Open No. 5-126226, Japanese Patent Laid-Open No. 8-126226
Various organic compounds described in 100172, EP0650955A1 and the like can be used.

It is preferable to use the vacuum deposition method for forming the hole injecting / transporting layer, the light emitting layer and the electron injecting / transporting layer because a uniform thin film can be formed.

(Third Embodiment) The manufacturing method and structure of the EL display panel of the present invention will be described in more detail below. As described above, first, the array substrate 49
Then, the TFT 11 for driving the pixel is formed. One pixel is composed of 4 or 5 TFTs. In addition, the pixel is current-programmed, and the programmed current is the EL element 1.
5 is supplied. Usually, the current programmed value is held in the capacitor 19 as a voltage value. This TFT11
The pixel configuration such as the combination will be described later.
Next, a pixel electrode 48 as a hole injection electrode is formed on the TFT 11.
To form. The pixel electrode 48 is patterned by photolithography. A light-shielding film is formed or placed on the lower layer or the upper layer of the TFT 11 in order to prevent image quality deterioration due to a photoconductor phenomenon (hereinafter referred to as photocon) that occurs when light is incident on the TFT 11.

In order to form a TFT on a plastic substrate, the surface for forming an organic semiconductor may be processed to form an electronic thin film using pentacene molecules composed of carbon and hydrogen. This thin film has a size 20 to 100 times larger than that of a conventional crystal grain, and has sufficient semiconductor characteristics suitable for electronic device manufacturing.

Pentacene molecules tend to adhere to surface impurities as they grow on a silicon substrate. This results in irregular growth and grain sizes that are too small to produce high quality devices. In order to grow the crystal grains larger, a single layer of molecules called cyclohexene "molecular buffer" may be applied first on a silicon substrate. This layer is called "sticky sit" on silicon.
It covers the es (where it sticks easily), resulting in a clean surface and the pentacene molecules growing into very large crystal grains. By applying such a new thin film of pentacene molecules having large crystal grains at a low temperature and using it, it is possible to mass-produce flexible transistors.

Alternatively, a metal thin film to be a gate may be formed in an island shape on a substrate, an amorphous silicon film may be vapor-deposited or applied thereon, and then heated to form a semiconductor film. The semiconductor film is excellently crystallized in the island-shaped portion. Therefore, the mobility becomes good.

As the organic transistor (TFT), it is preferable to adopt a structure called a static induction transistor (SIT), and amorphous pentacene is used. The hole mobility is 1 × 10 cm ² / Vs, which is lower than that of crystallized pentacene. However, the frequency characteristic can be improved by adopting the SIT structure. The thickness of pentacene is preferably 100 nm or more and 300 nm or less.

A P-type field effect transistor may be used as the organic TFT, and the TFT can be formed on a plastic substrate. In this case, since the plastic substrate can be bent together, it is preferable that pentacene, which can form a flexible TFT type display panel, be in a polycrystalline state. Further, it is preferable to use PMMA as the material of the gate insulating film. You may use naphthacene for the active layer of an organic transistor.

If oxygen plasma and an O ₂ asher are used during cleaning, the smoothing film 71 on the peripheral portion of the pixel electrode 48 is also ashed at the same time, and the peripheral portion of the pixel electrode 48 is scooped out. In order to solve this problem, in the present invention, FIG.
As shown by, an edge protection film 81 made of acrylic resin is formed on the peripheral portion of the pixel electrode 48. Examples of the constituent material of the edge protection film 81 include the same materials as organic materials such as acrylic resin and polyimide resin that form the smoothing film 71. In addition, inorganic materials such as SiO ₂ and SiNx, and Al ₂ O _{3 are also used.} Are also exemplified.

The edge protection film 81 is formed so as to fill the space between the pixel electrodes 48 after patterning the pixel electrodes 48.
Of course, the edge protection film 81 may be formed to have a height of 2 μm or more and 4 μm or less to serve as a bank of a metal mask (spacer that prevents the metal mask from directly contacting the pixel electrode 48) when the organic EL materials are separately applied. Needless to say.

(Embodiment 4) A method for improving the extraction efficiency of light generated in the EL display panel will be described below. FIG. 301 illustrates a problem of the conventional EL display device. In FIG. 301, 2791 shows the locus of light.

The light generated in the organic EL layer 47 is reflected by the reflection film 4
The light is reflected at 6 and emitted from the array substrate 49 on which the gate driver 12 (or the source driver 14) is formed. The light 2791a that is incident on the interface between the array substrate 49 and the air at a predetermined angle is emitted from the array substrate 49. However, the light 2791b incident at an angle equal to or greater than the critical angle θ is totally reflected within the array substrate 49. The totally reflected light 2791b is diffusely reflected in the array substrate 49 and reduces the display contrast.

The totally reflected light 2791b becomes a loss, and the ratio of the lost light reaches 2/3 of the total luminous flux amount generated by the EL element 15. Therefore, reducing the generation of the light 2791b directly leads to the improvement of the light utilization rate.

The configuration for solving this problem is the configuration of FIG. A refraction sheet (a light refraction member or a light refraction plate) is attached (arranged or formed) on the sealing film 73 described with reference to FIG. Refraction sheet 2801
A refracting portion 2802 is formed in a triangular shape, a polygonal shape, or an arc so as to correspond to the pixel 16. This refraction part 2802 may be entirely made of a transparent member,
Further, a reflection film may be formed on the portion indicated by a in FIG. 7 (inner surface of the refraction portion 2802). The reflection film may be a metal film such as Al or silver, or may be an interference film formed by forming a multi-layer of a low refractive index dielectric film and a high refractive index dielectric film. Further, the shape may be set so as to be a total reflection area according to Snell's law.

In addition, the refraction sheet 280 is provided with a refraction portion 280.
In addition to the structure in which the layer 2 formed is attached on the sealing film 73, the refraction portion 2802 may be directly formed on the sealing film 73. In the case of taking out the light underneath, the array substrate 4
The refraction portion 2802 may be formed by processing 9 itself. It may also be formed or arranged on the sealing plate.

The shape of the refracting portion 2802 is not limited to the slope shape or the arc shape, but may be a polygonal shape or a vertical shape. Alternatively, a large number of needle-shaped protrusions may be formed. The refracting portion 2802 is basically formed in the peripheral portion of the light emitting portion of the pixel 16.
That is, if the aperture ratio of the pixel 16 is 30%, the pixel 16
Is formed in the non-light emitting portion (that is, 70% portion). Of course, it goes without saying that the formation position of the refraction part 2802 may overlap the light emission position.

Although the refracting portion 2802 is basically formed in the peripheral portion of the light emitting portion of the pixel 16, it is preferable to slightly change it in the peripheral portion of the central portion of the display screen 21. In the central part of the display screen 21, the refraction part 2802 is formed so as to be arranged just around the light emitting part of the pixel 16. In the peripheral portion of the display screen 21, the refraction portion 2802 is formed so as to be arranged so as to be shifted outward from the center position of the light emitting portion of the pixel 16. As described above, by changing the formation position of the refraction part 2802 between the central part and the peripheral part of the display screen, it is possible to suppress the occurrence of moire and also the occurrence of color unevenness. In addition, by forming the position of the refraction portion 2802 at random for each pixel,
It is possible to suppress the occurrence of moire and also suppress the occurrence of color unevenness.

The inside of the refracting portion 2802 is the EL element 1.
The light emitted at 5 may pass through, and may be refracted at the refraction portion 2802 and emitted to the front surface of the panel. That is, the refraction part 2802 functions as a prism. In this case, the refraction part 2802 needs to be made of a light transmitting material.

When the refracting portion 2802 is formed of a light transmitting material, coloring this material is effective. This is because the effect of the color filter that cuts the band of the light emitted from the EL element 15 can be exhibited. Therefore, the color purity of the EL display panel is improved and the white balance is improved. When the EL element 15 emits white light, the refraction portion 2802 can be used as a color filter without providing a color filter. Of course, a color filter may be separately formed, and the colored refraction portion 2802 may be formed or arranged. Further, the refraction section 2802 or the refraction sheet 2801 may be colored directly, or these may be formed of a coloring material.

As the coloring material, a material in which a coloring matter or a pigment is dispersed in a resin may be used, or a material obtained by dyeing gelatin or casein with an acid dye like a color filter may be used. In addition, a fluoran dye can be used by coloring it. Further, the three colors of RGB are not required, and any one or more colors may be used. Further, a natural resin may be dyed with a pigment, or a material in which the pigment is dispersed in a synthetic resin may be used. The selection range of the dye may be an appropriate one selected from azo dyes, anthraquinone dyes, phthalocyanine dyes, triphenylmethane dyes, and the like, or a combination of two or more kinds thereof.

A polymer is preferably used as the constituent material of the refraction section 2802 and the refraction sheet 2801. As the polymer, a photo-curing type resin is preferably used in terms of easiness of manufacturing process, separation from the liquid crystal phase, and the like. As a specific example, an ultraviolet curable acrylic resin is preferable, and a resin containing an acrylic monomer or an acrylic oligomer that is polymerized and cured by ultraviolet irradiation is particularly preferable.

Among them, the photocurable acrylic resin having a fluorine group has little change with time and has good light resistance.

Examples of the polymer-forming monomer constituting the polymer include 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate, neopentyl glycol acrylate, hexanediol diacrylate, diethylene glycol diacrylate, tripropylene glycol diacrylate, polyethylene glycol diacrylate. , Trimethylolpropane triacrylate, pentaerythritol acrylate and the like.

Examples of the oligomer or prepolymer include polyester acrylate, epoxy acrylate and polyurethane acrylate.

A polymerization initiator may be used in order to carry out the polymerization promptly. As an example of this, 2-hydroxy-2-
Methyl-1-phenylpropan-1-one (“Darocur 1173” manufactured by Merck), 1- (4-isopropylphenyl) -2-hydroxy-2-methylpropan-1-
On (Merck "Darocur 1116"), 1-vidroxycyclohexyl phenyl ketone (Ciba-Gaiki "Irgacure 184"), benzyl methyl ketal (Ciba-Geigy "Irgacure 651") and the like. In addition, a chain transfer agent, a photosensitizer, a dye, a cross-linking agent and the like can be appropriately used in combination as optional components.

The above matters relating to the polymer are mainly applied to the manufacturing method shown in FIGS. 13, 14 and 15. In the case of the manufacturing method of FIG. 16, the refraction part 2802 is formed of an inorganic material, but of course, it may be formed of an organic material such as a polymer.

The arrangement of the refracting portion 2802 may be hexagonal as shown in FIG. Of course, it may be octagonal or more. A refraction portion 2802 is provided around the light emitting portion of the pixel 16.
To form. By forming the hexagonal shape in this way, E
When observing the L display panel, the occurrence of color unevenness and color shift can be significantly reduced even when the viewpoint for viewing the display screen is changed. Further, the occurrence of moire due to the displacement between the light emitting position of the pixel 16 and the position of the refracting portion 2802 is small.

Although FIG. 8 shows an example of a constitution in which the same color is arranged in the vertical direction of the display screen 21 (vertical stripe constitution), by forming the color arrangement of pixels in a mosaic pattern as shown in FIG. Even when the number of dots forming the display panel is relatively small, the resolution in the diagonal direction of the image is improved.

Further, as shown in FIG. 10, a plurality of refracting portions 2802 may be formed or arranged in one pixel 16. In the embodiment of FIG. 10, the pixel 16 has one pixel electrode, and three bent portions 2802 (2802a, 2802b, 2802c) are provided for this one pixel electrode.
Are formed (arranged). Of course, one pixel 16
It may have a plurality of pixel electrodes, and the refraction part 2802 may be formed (arranged) for each pixel electrode. A TFT for driving or switching is provided around the pixel electrode.
Since the pixel electrodes are divided into a plurality of pixel electrodes with respect to one pixel electrode, the aperture ratio does not decrease much.

Of course, as shown in FIG. 11, one refraction part 2802 may be arranged (formed) in one pixel 16. Further, as illustrated in FIG. 12A, a plurality of (2 × 6 in FIG. 12A) refracting portions 2802 may be formed in one pixel in two columns. In addition, FIG.
As described above, a plurality of polygonal refraction portions 2802 such as a hexagon (three in FIG. 12B) may be formed on one pixel electrode.

(Fifth Embodiment) Hereinafter, the refracting portion 2802 will be described.
A manufacturing method for forming (may include the refraction sheet 2801) will be described.

FIG. 13 shows the first embodiment of the present invention. First, the organic EL layer 47 is formed on the array substrate 49 on which the TFT 11, the pixel 16, the gate driver 12, the source driver 14 and the like are formed. In this formation, a low molecular weight EL film may be formed by vapor deposition, or a high molecular weight EL film may be formed by an inkjet method. An electrode is formed on the organic EL layer 47, and a sealing film 73 is formed thereon (FIG. 13).
(A)). Moreover, you may attach a sealing plate. These items will be omitted here because they will be described in detail elsewhere.

Further, except for the matters described below, the manufacturing method described in the specification of the present invention is applied. Also, EL
Configuration of element 15, pixel configuration, array configuration, panel configuration,
It goes without saying that the driving method and driving circuit are also applied to the following manufacturing method or manufactured panel. Further, an information display device, a television, a monitor, a camera and the like can be configured by using a panel manufactured by the manufacturing method described below.

Next, as shown in FIG. 13B, an uncured polymer material (transparent film 2861) is applied onto the sealing film 73. The polymer material 2861 is the material of the refraction part 2802 described above. The application may be performed by any method (technology) such as offset printing, screen printing, roller application, and spinner application.

After application of the uncured polymeric material 2861,
Place in oven to pre-dry. Alternatively, weak light (ultraviolet (UV) or visible light may be used) polymer material 2
861 is irradiated to suppress the fluidity of the polymer material 2861. Then, while rotating the roller 2862 having the shape of the refraction portion 2802, the transparent film (polymer material)
Press on 2861. Thus, the roller 2862
The uneven shape of is transferred to the transparent film 2861 (see FIG. 13).
(C)). As a result of this transfer, the refraction part 2 is formed on the transparent film 2861.
An uneven portion (recess) 2863 corresponding to 802 is formed. After forming the uneven portion (recess) 2863, the transparent film 2861 is formed.
The entire surface is irradiated with UV or visible light to completely cure the transparent film 2861.

Temperature control when polymerizing the transparent film 2861
Is important. The heating temperature is 40 degrees or more and about 60 degrees. purple
The outside line (UV) depends on the spectral distribution, but is 20 to 30 mW /
cm ²Irradiate for about 2 to 8 seconds with a certain intensity. these
Temperature and UV irradiation conditions are the addition of transparent film 2861.
It must be decided in consideration of materials. Inappropriate conditions
In that case, the surface becomes cloudy or has fine irregularities. Starting
In the light, using a super high pressure mercury lamp as a light source at a temperature of 50 ° C,
Ultraviolet rays on the transparent film 2861 (irradiation intensity on the substrate surface: 30 m
W / cm²) For 6 seconds to cure the transparent film 2861.
Let

A light source for ultraviolet (UV) 2902 is arranged inside the roller 2862, and the roller 2862 is
The UV may be irradiated to the transparent film 2861 to sequentially cure the transparent film 2861 as the process proceeds. Also, separately from the roller 2862,
A source of UV2902 may be provided, and the transparent film 2861 may be irradiated with UV from this source in accordance with the progress of the roller 2862 to be sequentially cured. Further, a reflective film or the like is formed on a necessary portion of the refraction portion 2802. The structure of the reflective film has been described with reference to FIG.

In addition, according to the manufacturing method of FIG.
802 may be formed. 14 (a) and 14 (b) are shown in FIG.
3 (a) and 3 (b) are the same, so the description will be omitted. In FIG. 14C, a press plate 2901 made of a transparent material is used. The press plate 2901 is provided with unevenness having a shape opposite to that of the bent portion 2802. Press board 2901
Is formed of a transparent material such as quartz glass. By pressing the press plate 2901 against the transparent film 2861, the unevenness of the press plate 2901 is transferred to the transparent film 2861.

In this way, by transferring the uneven shape of the press plate 2901 to the transparent film 2861, the transparent film 286 is formed.
1 is a concave / convex portion (concave portion) 2863 corresponding to the refraction portion 2802.
Is formed. After the uneven portion (recess) 2863 is formed, the entire transparent film 2861 is irradiated with UV or visible light 2902 through the press plate 2901 to completely cure the transparent film 2861.

On the uneven surface of the press plate 2901, it is preferable to form a thin film made of an olefinic material or the like with good releasability. By forming such a thin film having good releasability, the releasability between the transparent film 2861 and the press plate 2901 becomes good, and the manufacturing efficiency is improved. Note that temperature control is important for both the press plate 2901 and the transparent film 2861. The pressing plate 2901 is 5 degrees or more than the transparent film 2861.
It is preferable to keep the temperature low by about 15 degrees. Depending on the type of the transparent film 2861, the releasability and the like may be improved when the temperatures are reversed. Therefore, it is necessary to sufficiently carry out the experiment and determine the conditions.

Examples of the release film include silicone resin films, fluororesin films, olefin resin films such as polyethylene and polypropylene,
Further, a resin film whose surface is coated with silicon resin or fluororesin is exemplified. In addition, any material may be used as long as it transmits ultraviolet light and has some flexibility. For example,
A glass substrate or the like can also be used.

As shown in FIG. 14D, after the press plate 2901 is removed, the entire transparent film 2861 is irradiated with UV (visible light) to completely cure the uncured resin component. This is also the case when the transparent film 2861 is of a thermosetting type or the like.

Although the transparent film 2861 is of the ultraviolet curing type in the manufacturing method described with reference to FIGS. 13 and 14, the present invention is not limited to this. For example, a thermoplastic type resin material, a thermosetting type resin material, or a two-component type room temperature curing type resin material which starts to cure by mixing two liquids can be used. In the above case, the polymer material (transparent film) 286
1 need not be a transparent material. Polymer material 2861
The selection range is expanded, and an epoxy resin, a phenol resin, or the like can be used. In this case, after forming the uneven portion (recess) 2863, the refraction portion 28 is heated or left to stand.
02 is formed. Of course, the press plate 2901 may be cured while being pressed against the transparent film 2861. Also,
A reflective film or the like is formed on a necessary portion of the refraction portion 2802.
The structure of the reflective film has been described with reference to FIG.

FIG. 15 shows another embodiment of the present invention. The description up to FIG. 15A is omitted because it is similar to the other embodiments.

In FIG. 15B, the convex portion 2 is formed on the sealing film 73.
871 is formed. The formation position of the convex portion 2871 is made to coincide with the formation position of the refraction portion 2802. That is,
It is the periphery of the pixel or the periphery of the light emitting portion of the pixel. In the liquid crystal display panel, this is the position where the black matrix (BM) is formed. The convex portion 2871 is formed using an inorganic material such as SiO ₂ or SiNx. Alternatively, an organic material such as the transparent film 2861 may be used. As a method of forming the convex portion 2871, an inorganic thin film or an organic thin film is vapor-deposited or applied on the sealing film 73 or the sealing plate in a thickness of 0.5 to 3 μm. A mask is formed thereon, and negative or positive etching is performed using the mask (FIG. 15B).

Next, as shown in FIG. 15C, a transparent film 2861 is applied to the entire display screen 21. The application may be performed by any method (technology) such as offset printing, screen printing, roller application, and spinner application.

The resin to be applied has a viscosity of 5 cp or more and 40 c or more.
It is preferably p or less. That is, a material having a relatively low viscosity is used. The transparent film 2861 is smoothly formed along the convex portion 2871. As described above, in FIG. 15, the convex portion 2871 and the transparent film 2861 form the refraction portion 2802. Further, a reflective film or the like is formed on a necessary portion of the refraction portion 2802. For the configuration of the reflective film, see FIG.
Since it has been described above, it will be omitted.

Note that in FIG. 15C, the display screen 2
Although the transparent film is applied to the whole of No. 1, it is not limited to this, and a thin film made of an inorganic material may be vapor-deposited. The refraction portion 2802 is formed by the projections and depressions of the projections 2871 by depositing an inorganic material.

FIG. 16 shows another embodiment of the present invention. Up to FIG. 16A, the description is omitted because it is similar to the other embodiments. In FIG. 16B, a metal mask 2881 is placed on the sealing film 73 or the sealing lid. The opening of the metal mask 2881 is wide on the sealing film 73 side and narrow on the other surface side.

The metal mask 2881 described with reference to FIG.
Protects the sealing film 73 from direct contact (or contacts with the sealing film 73 as much as possible). Protrusions having a height of 0.5 to 3 μm are formed. This protrusion is formed at a place where the organic EL layer 47 is not vapor-deposited, for example, between adjacent pixels.

As shown in FIG. 16B, an inorganic material such as SiO ₂ or SiNx is deposited through a metal mask 2881. The deposition location is the location where the bent portion 2802 is formed. Also, a transparent film 2861 is used instead of the inorganic material.
You may use an organic material like this. As described above, the refraction portion 2802 can be formed using the metal mask 2881.

FIG. 7 shows an example of a bent portion (or light reflecting portion) 2802 having a prism shape. However, the present invention is not limited to this. For example, as shown in FIG. 17, a microlens-shaped refracting portion 2802 may be formed corresponding to the pixel 16. It is preferable that the microlenses have a sine curve shape. Further, although it is preferable to form it in an arc shape, the shape is not limited to this, and it may be a kamaboko shape. The height of the micro lens is 1
The thickness is preferably 5 μm or more and 3100 μm or less. The microlens is formed by stamper technology. For this stamper technology, a method adopted by OMRON as a method for forming a microlens, a method used by Matsushita Electric as a method for forming a minute lens in a pickup lens of a CD, and the like are applied. Further, the refraction part 2802 in FIG. 17 can also be formed by a diffraction grating. The other items are the same as those in FIG.

As the vacuum vapor deposition apparatus, an apparatus obtained by modifying a commercially available high vacuum vapor deposition apparatus (EBV-6DA type manufactured by Nippon Vacuum Technology Co., Ltd.) is used. The main evacuation device is a turbo molecular pump (TC1500 manufactured by Osaka Vacuum Co., Ltd.) with an evacuation speed of 1500 liters / min, and the ultimate vacuum is about 1 × 10e.
^-6 Torr (133.322e ^-6 Pa) or less, and all vapor depositions are 2-3 × 10e ^-6 Torr (266.644).
Up to 399.966e ^-6 Pa). In addition, all vapor deposition may be performed by connecting a DC power source (PAK10-70A, manufactured by Kikusui Electronics Co., Ltd.) to a resistance heating type vapor deposition boat made of tungsten.

A carbon film of 20 to 50 nm is formed on the array substrate thus arranged in the vacuum layer. Next, 4- (N, N-bis (p-methylphenyl) amino) -α-phenylstilbene was added as a hole injection layer to 0.3
A film thickness of about 5 nm is formed at a vapor deposition rate of nm / s.

As the hole transport layer, N, N'-bis (4 '
-Diphenylamino-4-biphenylyl) -N, N'-
Diphenylbenzidine (Hodogaya Chemical Co., Ltd.),
4-N, N-diphenylamino-α-phenylstilbene was added to 0.3 nm / s and 0.01 nm / s, respectively.
Is co-deposited at a deposition rate of to form a film thickness of about 80 nm.

As a light emitting layer (electron transport layer), tris (8
-Quinolinolato) Aluminum (made by Dojindo Co., Ltd.)
To a film thickness of about 40 nm at a vapor deposition rate of 0.3 nm / s.

Next, as an electron injection electrode, an Al-Li alloy (manufactured by Kojundo Chemical Co., Ltd., Al / Li weight ratio 99 /
From 1), only Li was formed at a low temperature to a film thickness of about 1 nm at a vapor deposition rate of about 0.1 nm / s, and then the temperature of the Al-Li alloy was further raised to remove only Al from the state where Li was exhausted. , A film thickness of about 100 nm was formed at a vapor deposition rate of about 1.5 nm / s to form a laminated electron injection electrode.

In the organic thin film EL element thus produced, after leaking the inside of the vapor deposition tank with dry nitrogen, the sealing lid 41 made of Corning 7059 glass was sealed with the sealant 45 (produced by Anelva Co., Ltd.) under a dry nitrogen atmosphere. The product name: Super Back Seal 953-7000) was applied to form a display panel. A desiccant 55 is placed in the space between the sealing lid 41 and the array substrate 49. This is because the organic EL film is vulnerable to humidity, so that the desiccant 55 absorbs moisture that permeates the sealant 45 and prevents the deterioration of the organic EL layer 47.

In order to suppress the permeation of water from the sealant 45, it is a good measure to lengthen the path from the outside. For this reason, in the display panel of the present invention, minute concave portions 43 and convex portions 44 are formed in the peripheral portion of the display area. The convex portions 44 formed on the peripheral portion of the array substrate 49 are at least doubled. It is preferable that the interval (formation pitch) between the protrusions is 100 μm or more and 500 μm or less, and the height of the protrusions is 30 μm or more and 300 μm or less. This convex portion is formed by a stamper technique.

On the other hand, the recess 43 is also formed in the sealing lid 41. The formation pitch of the concave portions 43 is the same as the formation pitch of the convex portions 44. In this way, by making the formation pitches the same, the convex portions 44 fit exactly into the concave portions 43, and no positional deviation occurs between the sealing lid 41 and the array substrate 49 during the manufacturing of the display panel. A sealant 45 is arranged between the concave portion 43 and the convex portion 44. The sealing agent 45 adheres the sealing lid 41 and the array substrate 49, and also prevents intrusion of moisture from the outside.

As the sealing agent 45, it is preferable to use a UV (ultraviolet) curable type acrylic resin and an acrylic resin having a fluorine group. Besides, an epoxy adhesive or pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. In particular, as the seal adhesive, fine powder of titanium oxide or fine powder of silicon oxide is added at a ratio of 65% or more and 95% or less by weight, and the average diameter of the fine powder is 20 μm.
It is preferable that the thickness is m or more and 100 μm or less. This is because as the weight ratio of the fine powder increases, the effect of suppressing the entry of humidity from the outside increases. However, if the amount is too large, bubbles and the like tend to enter, and the space becomes rather large and the sealing effect decreases.

The weight of the desiccant is preferably 0.04 g or more and 0.2 g or less, particularly 0.06 g or more and 0.15 g or less per 10 mm length of the seal. This is because if the amount of desiccant is too small, the moisture-preventing effect is weakened and the organic E
This is because the L layer deteriorates. On the other hand, if the amount is too large, the desiccant becomes a hindrance in sealing, and good sealing cannot be performed.

In FIG. 2, the glass sealing lid 41 is used for sealing, but a film may be used as shown in FIG. For example, as the sealing film, a film of an electrolytic capacitor on which DLC (diamond-like carbon) is deposited is used. Since this film has extremely poor moisture permeability (moisture resistance), it can be used as the sealing film 73. Alternatively, the DLC film may be directly deposited on the surface of the transparent electrode 72. The thickness of the thin film is n · d (n is the refractive index of the thin film, and when multiple thin films are stacked, the total refractive index of the thin films (n · d of each thin film is
To calculate). d is a film thickness of a thin film, and when a plurality of thin films are laminated, their refractive indexes are comprehensively calculated. ) Is preferably the emission main wavelength λ of the EL element 15 or less. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case of sealing with a glass substrate. Also, an alloy or mixture of aluminum and silver or a laminate may be formed.

Half of the light emitted from the organic EL layer 47 is
The light is reflected by the reflection film 46, passes through the array substrate 49, and is emitted. However, the reflection film 46 reflects external light, so that reflection occurs and the display contrast is reduced. As a countermeasure, the λ / 4 plate 50 and the polarizing plate 54 are arranged on the array substrate 49. When the pixel is a reflective electrode, the light generated from the organic EL layer 47 is emitted upward. Therefore, the λ / 4 plate 50 and the polarizing plate 54 must be arranged on the light emitting side. The reflective pixel is obtained by forming the pixel electrode 48 with aluminum, chromium, silver, or the like. Further, by providing a convex portion (or a concave-convex portion) on the surface of the pixel electrode 48, the interface with the organic EL layer 47 is widened, the light emitting area is increased, and the luminous efficiency is improved.

Array substrate 49 and polarizing plate (polarizing film)
One or more phase films (phase plate,
A phase rotation means, a retardation plate, a retardation film) are arranged. It is preferable to use polycarbonate as the phase film. This phase film generates a phase difference between the incident light and the emitted light and contributes to efficient light modulation.

In addition, as the phase film, an organic resin plate or an organic resin film of polyester resin, PVA resin, polysulfone resin, vinyl chloride resin, Zeonex resin, acrylic resin, polystyrene resin or the like may be used. Alternatively, crystals such as quartz may be used.
The phase difference of one phase plate is 50 nm or more in the uniaxial direction 350
nm or less, and more preferably 80 nm or more and 220 nm or less.

As shown in FIG. 5, a circularly polarizing plate 74 (circularly polarizing film) in which a phase film and a polarizing plate are integrated may be used.

The λ / 4 plate (phase film) 50 is preferably colored with a dye or a pigment so as to have a function as a color filter. In particular, since the organic EL layer has poor red (R) purity, the colored wavelength is cut by the colored λ / 4 plate 50 to adjust the color temperature. The color filter is generally provided by a pigment dispersion type resin as a dyeing filter, and this pigment absorbs light in a specific wavelength band and transmits light in a wavelength band that is not absorbed.

As described above, a part or the whole of the phase film may be colored, or a part or the whole may have a diffusion function. In addition, the surface may be embossed or an antireflection film may be formed to prevent reflection. In addition, it is preferable to form a light-shielding film or a light-absorbing film at a position that is not effective for image display or a position that does not hinder the display, thereby reducing the black level of the display image and exhibiting a contrast improving effect by preventing halation. Further, by forming irregularities on the surface of the phase film, the microlenses may be formed in a kamaboko shape or a matrix shape. The microlenses are arranged so as to correspond to one pixel electrode or pixels of three primary colors, respectively.

As described above, since the phase difference can be generated by rolling or photopolymerization when forming the color filter, the color filter may have the function of the phase film. Alternatively, the smoothing film 71 of FIG. 5 may be photopolymerized to have a phase difference. According to this structure, there is no need to form or dispose the phase film outside the substrate, the structure of the display panel is simplified, and cost reduction can be expected. The above items are also applicable to the polarizing plate 54.

The polarizing plate 54 is exemplified by a resin film in which iodine or the like is added to polyvinyl alcohol (PVA) resin. The polarizing plates of the pair of polarization separation means perform polarization separation by absorbing a polarization component of the incident light in a direction different from the specific polarization axis direction, and therefore the light utilization efficiency is relatively poor. Therefore, of the incident light, a polarization component (reflective polar) in a direction different from the specific polarization axis direction
Riser: A reflective polarizer for separating polarized light by reflecting the light may be used. According to this structure, the light utilization efficiency is increased by the reflective polarizer, and a brighter display can be performed as compared with the above example using the polarizing plate.

In addition to such a polarizing plate and a reflective polarizer, as the polarized light separating means of the present invention, a combination of a cholesteric liquid crystal layer and a (1/4) λ plate, the Brewster angle is used. It is also possible to use one that separates the reflected polarized light and the transmitted polarized light, one that uses a hologram, a polarized beam splitter (PBS), or the like.

Although not shown in FIG. 2, an AIR coat is applied to the surface of the polarizing plate 54.

Although the TFT is connected to the pixel electrode 48, it is not limited to this. The active matrix includes a thin film transistor (TFT) as a switching element, a diode method (TFD), a varistor, a thyristor, a ring diode, a photodiode,
Phototransistor, FET, MOS transistor, PL
A ZT element or the like is also possible. In other words, any of these constituting the switching element and the driving element can be used.

Further, it is preferable to adopt an LDD (low doping drain) structure for the TFT. In addition,
The TFT generally means all elements such as FETs that perform transistor operations such as switching. Further, the structure of the EL film, the panel structure, etc. can be applied to a simple matrix type display panel. Further, in the present specification, an organic EL element (OEL, PEL, PLED, OLED) is used as an EL element.
However, the present invention is not limited to this and is also applied to an inorganic EL element.

The active matrix system used for the organic EL display panel is (1) capable of selecting a specific pixel and given necessary display information, and (2) capable of supplying a current to the EL element through one frame period. Two conditions must be met.

In order to satisfy these two conditions, the first TFT in the conventional organic EL element structure shown in FIG.
11a is a switching thin film transistor for selecting a pixel, and the second TFT 11b is a driving thin film transistor for supplying a current to the EL element 15.

In comparison with the active matrix system used for liquid crystal, the switching TFT 11a is used.
Is also required for liquid crystal, but the driving TFT 11b is EL
It is necessary to light the element 15. The reason for this is that in the case of liquid crystal, the ON state can be maintained by applying a voltage, but in the case of the EL element 15, the lighting state of the pixel 16 cannot be maintained unless current continues to flow.

Therefore, in the organic EL display panel, the driving TFT 11b must be kept on in order to keep the current flowing. First, when both the scanning line and the data line are turned on, charges are accumulated in the capacitor 19 through the switching TFT 11a. This capacitor 1
Since 9 continues to apply a voltage to the gate of the driving TFT 11b, even if the switching TFT 11a is turned off, current continues to flow from the current supply line 20 and the pixel 16 can be turned on for one frame period.

When displaying gradation using this structure,
It is necessary to apply a voltage according to the gradation as the gate voltage of the driving TFT 11b. Therefore, the driving TFT 1
The on-current variation of 1b appears on the display as it is.

The on-current of a transistor is extremely uniform if it is a transistor formed of a single crystal, but it can be formed on an inexpensive glass substrate by using a low temperature poly-silicon technique formed at a low temperature of 450 ° C. or lower. Since the threshold value of the crystal transistor varies in the range of ± 0.2 V to 0.5 V, the on-current flowing through the driving TFT 11b varies correspondingly, causing uneven display. These irregularities are caused not only by variations in threshold voltage,
It also occurs due to the mobility of the TFT and the thickness of the gate insulating film. The characteristics also change due to deterioration of the TFT 11.

Therefore, in the method of displaying gray scales in an analog manner, it is necessary to strictly control the characteristics of the device in order to obtain a uniform display. In the current low temperature polycrystal polysilicon TFT, this variation is within a predetermined range. We cannot meet the specifications to keep it within. In order to solve this problem, four transistors are provided in one pixel and the variation in threshold voltage is compensated by a capacitor to obtain a uniform current, or a constant current circuit is formed for each pixel to make the current uniform. It is possible to consider a method of

However, in these methods, the current to be programmed is made through the EL element 15, so that the transistor for controlling the drive current is the source follower for the switching transistor connected to the power supply line when the current path changes. Therefore, the driving margin becomes narrow. Therefore, there is a problem that the driving voltage becomes high.

Further, it is necessary to use the switching transistor connected to the power source in the region of low impedance, and there is also a problem that this operating range is affected by the characteristic variation of the EL element 15. In addition, there is a problem that the stored current value fluctuates when a kink current occurs in the voltage-current characteristics in the saturation region or when the threshold voltage of the transistor fluctuates.

The EL device structure of the present invention has the TFT 11 for controlling the current flowing through the EL device 15 to solve the above problems.
However, even if the transistor has a kink current, the influence of the kink current can be minimized and the fluctuation of the stored current value can be reduced.

The EL device structure of the present invention is specifically shown in FIG.
As shown in (a), a unit pixel is formed by a plurality of TFTs 11 and at least four EL elements 15.
Note that the pixel electrode is formed so as to overlap with the source signal line. That is, an insulating film or a smoothing film made of an acrylic material is formed on the source signal line 18 for insulation, and a pixel electrode is formed on this insulating film. In this way, the structure in which the pixel electrode is overlapped on the source signal line 18 is set to the high aperture (H
A) It is called a structure.

First gate signal line (first scanning line) 17
By making a active (applying ON voltage),
A current value to be passed through the EL element 15 is passed through the first TFT (or switching element) 11a and the third TFT (or switching element) 11c so that the gate and drain of the first TFT 11a are short-circuited. The second TFT 11b opens by activating the first gate signal line 17a (applying ON voltage), and
The first TFT 11a is configured so that the current value flows through the capacitor 19 connected between the gate and the source of the first TFT 11a.
The gate voltage (or drain voltage) of 11a is stored.

The capacitor 19, which is the source-gate capacitance of the first TFT 11a, preferably has a capacitance of 0.2 pF or more. As another configuration, there is an example in which the capacitor 19 is separately formed. That is, this is a structure in which the storage capacitor is formed from the capacitor electrode layer, the gate insulating film, and the gate metal. M3 transistor 11c
From the viewpoint of preventing a decrease in luminance due to the leakage of No. 2 and stabilizing the display operation, it is preferable to separately configure the capacitor in this way. The size of the capacitor 19 is 0.2 pF or more and 2 pF or less, and in particular 0.4 pF.
It is preferably not less than 1.2 pF.

Further, it is preferable that the capacitor 19 is formed in a non-display area between adjacent pixels. Generally, when forming a full-color organic EL layer, since the organic EL layer is formed by mask vapor deposition using a metal mask, a mask position shift occurs at the formation position of the organic EL layer, and the organic EL of each color is formed.
There is a risk of overlapping layers. Therefore, the non-display area between adjacent pixels of each color must be separated by 10 μm or more,
Further, this portion does not contribute to light emission. Therefore, forming the capacitor 19 in this region is an effective means for improving the aperture ratio.

Next, the first gate signal line 17a is made inactive (OFF voltage is applied), and the second gate signal line 17 is made.
b is made active, and the path through which the current flows is switched to the path including the fourth TFT 11d connected to the first TFT 11a and the EL element 15 and the EL element 15, so that the stored current flows through the EL element 15. To work.

This circuit has four TFTs 11 in one pixel, the gate of the first transistor M1 is connected to the source of the second transistor M2, and the second transistor M2 and the third transistor M2 are connected. The gate of M3 is connected to the first gate signal line 17a and the second transistor M
The drain of 2 is connected to the source of the third transistor M3 and the source of the fourth transistor M4, and the drain of the third transistor M3 is connected to the source signal line 18. The gate of the fourth transistor M4 is connected to the second gate signal line 17b, and the fourth transistor M4
The drain of No. 4 is connected to the anode electrode of the EL element 15.

Note that, in FIG. 6, all TFTs are composed of P channels. Although the P-channel is somewhat less mobile than the N-channel TFT, it is preferable because it has a large breakdown voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL device having P channels. It may be configured with only N channels (see FIGS. 158, 159, 85, etc.),
Further, both N channel and P channel may be used.

It is preferable that the third and fourth transistors have the same polarity and are N-channel, and the first and second transistors are P-channel. Generally, P-channel transistors are N
Compared with a channel transistor, it has features such as high reliability and low kink current. For the EL element that obtains the desired light emission intensity by controlling the current, the first TFT 11a is used as the P channel. Then, the effect becomes large.

(Embodiment 6) The EL element structure of the present invention will be described below with reference to FIG. The EL element structure of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. At this timing, the TFT 11b and the TFT 11
By turning on c, an equivalent circuit shown in FIG.
Becomes Here, a predetermined current I1 is written from the signal line, the gate and the drain of the TFT 11a are connected, and the current I1 flows through the TFT 11a and the TFT 11c. Therefore, the gate-source voltage of the TFT 11a becomes V1 so that the current I1 flows.

The second timing is TFT 11a and TF.
It is the timing when T11c is closed and the TFT 11d is opened, and the equivalent circuit at that time is shown in FIG. In this case, since the TFT 11a of M1 always operates in the saturation region, the current I1 becomes constant and the source-gate voltage V1 of the TFT 11a remains held.

The gate of the TFT 11a and the TFT 11
The gate of c is connected to the same gate signal line 17a. However, the gate of the TFT 11a and the gate of the TFT 11c may be connected to different gate signal lines 17b (so that SA1 and SA2 can be individually controlled).
That is, the number of gate signal lines for one pixel is three (the configuration of FIG. 6 is two). ON / OF of the gate of the TFT 11a
By individually controlling the F timing and the ON / OFF timing of the gate of the TFT 11c, it is possible to further reduce the variation in the current value of the EL element 15 due to the variation in the TFT 11.

The first gate signal line 17a and the second gate signal line 17b are made common, and the third and fourth transistors have different conductivity types (N channel and P channel).
Then, the driving circuit can be simplified and the aperture ratio of the pixel can be improved. According to this structure, the write path from the signal line is turned off in the operation timing of the present invention. That is, when a predetermined current is stored, if there is a branch in the path through which the current flows, an accurate current value is not stored in the source-gate capacitance (capacitor) of M1. Third transistor M3 and fourth transistor M
By making 4 different conductivity types and controlling the threshold value of each other, it is possible to turn on M4 after turning off M3 without fail at the timing of switching the scanning lines. However, in this case, attention must be paid to the process because it is necessary to accurately control the threshold values of each other.

Although the circuit described above can be realized with at least four transistors, the TFT 11e (M5) is shown in FIG. 6 (b) in order to control the timing more accurately or to reduce the mirror effect, as will be described later. As shown, the operation principle is the same even if the total number of transistors is four or more by cascade connection. In this way, by adding the TFT 11e, the third transistor M3
EL device 1 more accurately programmed current via
It becomes possible to flow to 5.

In the configuration of FIG. 6, the first TFT 11a
It is more preferable that the current value Ids in the saturation region of 1 satisfies the following condition. In the equation below, the value of λ is
The condition of 0.01 or more and 0.06 or less is satisfied between adjacent pixels.

Ids = k * (Vgs-Vth) ² (1 + Vds * λ) In the present invention, the operating range of the TFT 11a is limited to the saturation region, but the transistor characteristic in the saturation region generally deviates from the ideal characteristic. , Affected by source-drain voltage (Miller effect).

Each TFT1 in adjacent pixels
Consider a case where a threshold shift of ΔVt occurs in 1a. In this case, the stored current values are the same. If the shift of the threshold value is ΔL, then about ΔV × λ corresponds to the deviation of the current value of the EL element 15 due to the change of the threshold value of the TFT 11a. Therefore, in order to suppress the current deviation to be x (%) or less, λ must be 0.01 × x / y or less, where the threshold shift allowable amount is y (V) between adjacent pixels. I understand. This tolerance varies depending on the brightness of the application. Brightness is 100 cd / m ² ~ 1
In the luminance region up to 000 cd / m ² , if the variation amount is 2% or more, a person recognizes the varied boundary line. Therefore, it is necessary that the variation amount of the brightness (current amount) is within 2%. When the brightness is higher than 100 cd / cm ² , the brightness change amount of the adjacent pixels is 2% or more. When the EL display element of the present invention is used as a display for a mobile terminal, the required brightness is about 100 cd / m ² . Actually, when the pixel configuration of FIG. 6 was prototyped and the variation of the threshold value was measured, it was found that the maximum value of the variation of the threshold value was 0.3V in the TFT 11a of the adjacent pixel. Therefore,
In order to suppress the fluctuation of the luminance within 2%, λ must be 0.06 or less. However, since it is not possible for humans to recognize the change, it is not necessary to set it to 0.01 or less.
Further, in order to achieve this variation in threshold value, it is necessary to make the transistor size sufficiently large, which is unrealistic.

Further, it is preferable that the current value Ids in the saturation region of the first TFT 11a is configured to satisfy the following expression. The variation of λ is set to 1% or more and 5% or less between adjacent pixels.

Ids = k * (Vgs−Vth) ² (1 + Vds * λ) If there is a change in λ in the above formula between adjacent pixels even if there is no change in the threshold value, the current value flowing through the EL element is fluctuate. In order to suppress the fluctuation within ± 2%, the fluctuation of λ must be suppressed within ± 5%. However, since humans cannot recognize the change, it is not necessary to reduce it to 1% or less. Also, in order to achieve 1% or less, it is necessary to considerably increase the transistor size,
Unrealistic.

According to experiments, array trial manufacture, and studies, the channel length of the first TFT 11a is preferably 10 μm or more and 200 μm or less, and more preferably 15 μm or more and 150 μm or less. This is considered to be because when the channel length L is increased, the grain boundary contained in the channel is increased to relax the electric field and suppress the kink effect to a low level.

Further, the TFTs 11 constituting the pixels are formed of polysilicon TFTs formed by the laser recrystallization method (laser annealing), and the channel directions of all the transistors are the same as the laser irradiation direction. Is preferred.

The object of the present invention is to propose a circuit configuration in which variations in transistor characteristics do not affect the display, and therefore four or more transistors are required.
When the circuit constant is determined based on these transistor characteristics, it is difficult to obtain an appropriate circuit constant unless the four transistors have the same characteristics. When the channel direction is horizontal or vertical with respect to the long-axis direction of laser irradiation, the threshold and mobility of transistor characteristics are different. The degree of variation is the same in both cases. Since the mobility and the average value of the threshold value are different in the horizontal direction and the vertical direction, it is desirable that the channel directions of all the transistors forming the pixel are the same.

When the capacitance value of the capacitor 19 is Cs and the off-current value of the second TFT 11b is Ioff,
It is preferable to satisfy the following formula.

3 <Cs / Ioff <24 More preferably, the following formula is preferably satisfied.

6 <Cs / Ioff <18 By setting the off current of the TFT 11b to 5 pA or less, it is possible to suppress the change in the current value flowing through the EL element to 2% or less. This is because when the leak current increases, the charge stored between the gate and the source (both ends of the capacitor) cannot be retained for one field in the voltage non-writing state. Therefore, the larger the storage capacity of the capacitor 19, the larger the allowable amount of off-current. By satisfying the above equation, the fluctuation of the current value between adjacent pixels can be reduced by 2
% Or less.

It is preferable that the transistors forming the active matrix are formed of p-ch polysilicon thin film transistors, and the TFT 11b has a multi-gate structure having a dual gate structure or more.
Since the TFT 11b acts as a switch between the source and drain of the TFT 11a, it is turned on / off as much as possible.
High ratio characteristics are required. To meet this demand,
By making the gate structure of the TFT 11b a multi-gate structure, it becomes possible to realize characteristics with a high ON / OFF ratio.

It is preferable that the transistors forming the active matrix are polysilicon thin film transistors, and the (channel width W) * (channel length L) of each transistor is 54 μm ² or less. There is a correlation between (channel width W) * (channel length L) and variations in transistor characteristics. Most of the variations in transistor characteristics are caused by variations in energy due to laser irradiation, and in order to absorb this, the laser irradiation pitch (generally 10 and several μm) should be increased as much as possible in the channel. It is desirable to have a structure that includes them. Therefore, the (channel width W) * (channel length L) of each transistor is 54 μm.
^{When the number is 2} or less, there is no variation due to laser irradiation, and a thin film transistor with uniform characteristics can be obtained. If the transistor size becomes too small, the characteristics will vary depending on the area. Therefore, (channel width W) * (channel length L) of each transistor
Is preferably 9 μm ² or more, and more preferably 16 μm ² or more and 45 μm ² or less.

In addition, the first TFT in the adjacent unit pixel
It is preferable that the mobility fluctuation of 11a is 20% or less. This is because the mobility of the switching transistor deteriorates and the charging capability of the switching transistor deteriorates.
This is because the capacity between the sources cannot be charged. Therefore, by suppressing the variation in movement within 20%, the variation in luminance between pixels can be made equal to or lower than the recognition limit.

Although FIG. 6 has been described as a pixel configuration,
These can also be applied to the configurations shown in FIGS. 19 and 20. The pixel configuration shown in FIG. 19 and the like will be described below.

When setting the current flowing through the EL element 15, the signal current flowing through the converting TFT 11a is Iw, and as a result, the gate-source voltage generated in the converting TFT 11a is Vg.
Let s. When writing, use the TFT 11d for conversion T
Since the gate and drain of the FT 11a are short-circuited, the conversion TFT 11a operates in the saturation region. Therefore, the signal current Iw is given by the following equation.

(Equation 1) Iw = μ1 · Cox1 · W1 /
L1 / 2 (Vgs-Vth1) ² where Cox is the gate capacitance per unit area,
It is given by Cox = ε0 · εr / d. Vth is TFT
Threshold, μ is carrier mobility, W is channel width, L
Is the channel length, ε0 is the mobility of vacuum, εr is the relative dielectric constant of the gate insulating film, and d is the thickness of the gate insulating film.

If the current flowing through the EL element 15 is Idd, the current level of Idd is controlled by the driving TFT 11b connected in series with the EL element 15. In the present invention, the gate-source voltage is Vgs of the formula (1).
Therefore, assuming that the driving TFT 11b operates in the saturation region, the following formula is established.

(Equation 2) Idrv = μ2 · Cox2 · W
2 / L2 / 2 (Vgs-Vth2) ² Insulated gate field effect thin film transistor (TFT)
The condition for operating in the saturation region is to drain Vds
The voltage between sources is generally given by the following formula.

(Formula 3) | Vds |> | Vgs−Vth | Here, the conversion TFT 11a and the driving TFT 11b are
Since it is formed close to the inside of a small pixel, approximately μ1 =
μ2 and Cox1 = Cox2, and it is considered that Vth1 = Vth2 unless special measures are taken. Then,
At this time, the following equation is easily derived from the equations (1) and (2).

(Equation 4) Idrv / Iw = (W2 / L
2) / (W1 / L1) The point to be noted here is that in the formulas (1) and (2), the values of μ, Cox, and Vth themselves are different for each pixel, each product, or each manufacturing lot. Although it usually varies, since the equation (4) does not include these parameters,
This means that the value of Idrv / Iw does not depend on these variations. If W1 = W2 and L1 = L2 are designed, Idrv / Iw = 1, that is, Iw and Idrv
Becomes the same value, and the drive current Id flowing through the EL element 15
Since d is exactly the same as the signal current Iw regardless of the TFT characteristic variation, as a result, the emission brightness of the EL element 15 can be accurately controlled.

As described above, since the threshold value Vth1 of the converting TFT 11a and the threshold value Vth2 of the driving TFT 11b are basically the same, a cutoff level signal voltage is applied to the gates at the common potential in both TFTs. Then, both the converting TFT 11a and the driving TFT 11b should be in a non-conducting state. However, in reality, due to factors such as parameter variations within a pixel, Vth
Vth2 may be lower than 1. At this time, since a sub-threshold level leak current flows through the driving TFT 11b, the EL element 15 emits a slight amount of light. This slight light emission lowers the contrast of the screen and impairs the display characteristics.

In the present invention, in particular, the threshold voltage Vth2 of the driving TFT 11b is set so as not to be lower than the threshold voltage Vth1 of the corresponding conversion TFT 11a in the pixel.
For example, if the gate length L2 of the driving TFT 11b is converted to T
Even if the process parameters of these thin film transistors are changed by making the gate length L1 of the FT11a longer than V1.
Th2 is set so as not to be lower than Vth1,
It is possible to suppress a minute current leak. The above items also apply to the relationship between the conversion TFT 11a and the TFT 11d in FIG.

As shown in FIG. 19, in addition to the driving TFT 11b for controlling the driving current flowing through the light emitting element including the converting TFT 11a through which the signal current flows and the EL element 15, the first scanning line scanA (SA) is controlled. The capture T that connects or disconnects the pixel circuit and the data line data by
The gate of the conversion TFT 11a is controlled during the writing period by controlling the FT 11c and the second scanning line scanB (SB).
It is composed of a switching TFT 11d for short-circuiting the drain, a capacitor 19 for holding the gate-source voltage of the conversion TFT 11a after writing is completed, an EL element 15 as a light emitting element and the like. in this way,
Since each pixel has two gate signal lines, the configuration, functions, operations, etc. of the entire specification of the present invention based on FIG. 6 described above can be applied.

The fetch TFT 11c in FIG. 19 is composed of an N channel MOS (NMOS), and the other transistors are composed of a P channel MOS (PMOS).
This is an example, and it does not necessarily have to be the same. One terminal of the capacitor 19 is a conversion TFT
Although it is connected to the gate of 11a and the other terminal is connected to Vdd (power supply potential), it is not limited to Vdd and may be any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential. Therefore, the above items are
It goes without saying that it also applies to such cases.

The terminal voltage of the EL element 15 also changes with temperature. Usually, it is high when the temperature is low, and is low when the temperature is high. This tendency has a linear relationship. Therefore, the Vdd voltage depends on the external temperature (to be exact, E
It is preferable to adjust (by the temperature of the L element 15).
The temperature sensor detects the external temperature and the Vdd voltage is changed by feeding back the Vdd voltage generator. Vdd
The voltage is preferably 2% or more and 8% or less, more preferably 3% or more and 6% or less with a change of 10 ° C.

Note that the Vdd voltage in FIG.
It is preferable to lower the off-voltage. Specifically, Vgh (gate off-voltage) is at least Vdd-.
Should be higher than 0.5V. If it is lower than this, off-leakage of TFT occurs, and uneven shot of laser annealing becomes noticeable. If it is too high, on the contrary, the amount of off-leak increases, and therefore it should be lower than Vdd + 4V. Therefore, the gate off voltage Vg
h, that is, the Vdd power supply voltage in FIG.
It should be V or more and +4 V or less, and more preferably 0 V or more and +2 V or less so that the off-voltage of the TFT applied to the gate signal line is sufficiently off. When the TFT is an N channel, Vgl becomes an off voltage, so Vgl
Is preferably −4 V or more and 0.5 V or less, more preferably −2 V or more and 0 V or less with respect to the GND voltage.

Although the pixel configuration of the current program shown in FIG. 6 has been described above, the present invention is not limited to this, and the pixel configuration shown in FIG.
It goes without saying that the present invention can also be applied to the pixel configuration of the voltage program shown in FIG. In addition, V of the voltage program
The t offset cancellation is preferably compensated individually for R, G, and B.

The configuration of FIG. 19 has the scanning lines scanA and s.
a scanning line driving circuit that sequentially selects canB, a data line driving circuit that includes a current source CS that generates a signal current Iw having a current level according to brightness information and sequentially supplies the signal current Iw to the data line data, each scanning line scanA, The plurality of pixels are provided at the intersections of scanB and each data line data, and include a current drive type EL element 15 that emits light when supplied with a drive current.

The pixel configuration shown in FIG. 19 as a characteristic feature is configured such that, when the scanning line scanA is selected, the receiving portion (specifically, the receiving TFT 11c for receiving the signal current Iw from the data line data). ), A conversion unit that temporarily converts the current level of the captured signal current Iw into a voltage level and holds the voltage level, and a drive current having a current level according to the held voltage level.
(Otherwise, they may be abbreviated as EL, OEL, PEL, and PLED).

The conversion section includes a conversion TFT 11a having a gate, a source, a drain and a channel, and a capacitor 19 connected to the gate. T for conversion
FT11a, signal current Iw taken in by the receiving unit
To the channel to generate the converted voltage level at the gate and hold the voltage level generated in the capacitor 19.

Further, the conversion section is composed of the conversion TFT 11a.
It includes a switching TFT 11d inserted between the drain and the gate. Switching TFT 11
d is turned on when converting the current level of the signal current Iw to a voltage level, electrically connecting the drain and gate of the converting TFT 11a to generate a voltage level with the source as a reference at the gate of the converting TFT 11a. Further, the switching TFT 11d is cut off when the voltage level is held in the capacitor 19, so that the gate of the conversion TFT 11a and the capacitor 19 connected thereto are converted into the conversion TFT 11a.
Disconnect from the drain.

Further, the driving unit includes a gate, a drain,
It includes a driving TFT 11b having a source and a channel. The driving TFT 11b receives the voltage level held in the capacitor 19 at its gate, and a driving current having a corresponding current level flows to the EL element 15 via the channel. The gate of the conversion TFT 11a and the driving T
The gate of the FT 11b is directly connected to form a current mirror circuit so that the current level of the signal current Iw and the current level of the drive current have a proportional relationship.

The driving TFT 11b operates in the saturation region,
A drive current according to the difference between the voltage level applied to the gate and the threshold voltage is passed through the EL element 15.

The driving TFT 11b is set so that its threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel. Specifically, the driving TFT
The gate length of 11b is set so as not to be shorter than the gate length of the converting TFT 11a. Alternatively,
The driving TFT 11b may be set so that its gate insulating film is not thinner than the corresponding gate insulating film of the converting TFT 11a in the pixel.

Further, the driving TFT 11b may be set by adjusting the concentration of impurities implanted into its channel so that the threshold voltage does not become lower than the threshold voltage of the corresponding conversion TFT 11a in the pixel. Assuming that the conversion TFT 11a
When the threshold voltages of the drive TFT 11b and the drive TFT 11b are set to be the same, when the cutoff level signal voltage is applied to the gates of both commonly connected thin film transistors, both the conversion TFT 11a and the drive TFT 11b are turned off. Should be. However, in reality, there is a slight variation in the process parameters even within the pixel, and the conversion T
The threshold voltage of the driving TFT 11b may be lower than the threshold voltage of the FT 11a.

At this time, a weak current of the subthreshold level flows through the driving TFT 11b even with a signal voltage below the cutoff level, so that the EL element 15 slightly emits light and the contrast of the screen deteriorates. Therefore, the driving TFT
The gate length of 11b is made longer than the gate length of the conversion TFT 11a. As a result, even if the process parameters of the thin film transistor vary within the pixel, the driving TFT1
The threshold voltage of 1b does not become lower than the threshold voltage of the converting TFT 11a.

In the short channel effect region A having a relatively short gate length L, the threshold value Vth of the TFT increases as the gate length L increases.
Rises. On the other hand, in the suppression region B having a relatively large gate length L, the threshold value Vth of the TFT is substantially constant regardless of the gate length L. Utilizing this characteristic, the driving TFT 11
The gate length of b is longer than that of the conversion TFT 11a. For example, when the conversion TFT 11a has a gate length of 7 μm, the driving TFT 11b has a gate length of 10 μm.
Set to about m.

The gate length of the converting TFT 11a may belong to the short channel effect region A, while the gate length of the driving TFT 11b may belong to the suppressing region B. As a result, it is possible to suppress the short channel effect in the driving TFT 11b, and it is possible to suppress the threshold voltage reduction due to the change of the process parameter. As described above, it is possible to suppress the sub-threshold level leak current flowing in the driving TFT 11b, suppress the slight light emission of the EL element 15, and contribute to the improvement of the contrast.

A method of driving the pixel circuit shown in FIG. 19 will be briefly described. First, at the time of writing, the first scanning line sca
The nA and the second scanning line scanB are brought into the selected state. When both scanning lines are selected, the current source CS is applied to the data line data.
By connecting with, the signal current Iw according to the luminance information flows through the conversion TFT 11a. The current source CS is a variable current source controlled according to the brightness information. At this time, since the gate-drain of the conversion TFT 11a is electrically short-circuited by the switching TFT 11d, the expression (3) is established, and the conversion TFT 11a operates in the saturation region. Therefore, between the gate and the source (Equation 1)
A voltage Vgs given by the formula is generated.

Next, the first scanning line scanA and the second scanning line scanB are brought into a non-selected state. In detail,
First, the second scanning line scanB is set to a low level and the switching TFT 11d is turned off. As a result, the voltage Vgs is held by the capacitor 19.
Next, the first scan line scanA is set to a high level and turned off.
By setting the state, the pixel circuit and the data line data are electrically cut off, and thereafter the data line data is changed.
Writing to another pixel can be performed via. Here, the data output from the current source CS as the current level of the signal current is valid at the time when the second scanning line scanB is deselected, but thereafter, at any level (for example, writing to the next pixel). Data).

The driving TFT 11b is the conversion TFT 11a.
Since the gate and source are commonly connected and both are formed close to each other inside the small pixel, the driving T
If the FT11b is operating in the saturation region, the driving TFT
The current flowing through 11b is given by the equation (2), which is the drive current Idd flowing through the EL element 15. In order to operate the driving TFT 11b in the saturation region, a sufficient power supply potential may be applied to the Vdd voltage so that the formula (3) is still established even if the voltage drop in the EL element 15 is taken into consideration.

As in the case of FIG. 6B, TFTs 11e and 11f may be added as shown in FIG. 20 for the purpose of increasing the impedance, which results in better current driving. Can be realized. Other matters have been described with reference to FIG. 6 and will be omitted.

[0235] Figures 6 and 19 produced in this manner
Applying a DC voltage to the EL display element described in Section 10
/ Cm²Was continuously driven at a constant current density of. EL structure
At 7.0V, 200 cd / cm²Green (from
The emission of the maximum light wavelength λmax = 460 nm can be confirmed.
It was Brightness of 100 cd / cm in blue light emitting part²And color scheme
The target is x = 0.129, y = 0.105, green light emitting part
Has a brightness of 200 cd / cm ²And the color coordinate is x = 0.34
0, y = 0.625, the luminance of the red light emitting portion is 100 cd
/ Cm²And the color coordinates are x = 0.649, y = 0.338.
The emission color of was obtained.

(Embodiment 7) A display device, a display module, an information display device, and a drive circuit and a drive method thereof, which are shown in FIGS. 6, 19, and 20, will be described below.

In a full-color organic EL display panel, improvement of the aperture ratio is an important development issue. This is because if the aperture ratio is increased, the light utilization efficiency is increased, which leads to higher brightness and longer life. In order to increase the aperture ratio, the area of the TFT that blocks the light from the organic EL layer may be reduced. Low-temperature polycrystalline Si-TFT is 10 to 10 times thicker than amorphous silicon.
The size of the TFT can be made extremely small because it has 100 times the performance and high current supply capability. Therefore, in the organic EL display panel, it is preferable to manufacture the pixel transistor and the peripheral drive circuit by the low temperature polysilicon technique. Of course, it may be formed by the amorphous silicon technique, but the pixel aperture ratio becomes considerably small.

By forming a driving circuit such as the gate driver 12 or the source driver 14 on the array substrate 49, it is possible to reduce the resistance which is a particular problem in the current driven organic EL display panel. That is, the connection resistance of the TCP is eliminated, and the lead line from the electrode is shortened by 2 to 3 mm as compared with the case of the TCP connection, and the wiring resistance is reduced. Furthermore, the process for TCP connection is eliminated,
It has the advantage of lower material costs.

(Embodiment 8) Next, an EL display panel or an EL display device of the present invention will be described. Figure 2
1 is an explanatory diagram centering on the circuit of the EL display device. The pixels 16 are arranged or formed in a matrix.
A source driver 14 that outputs a current for performing a current program of each pixel is connected to each pixel 16. At the output stage of the source driver 14, a current mirror circuit corresponding to the number of bits of the video signal is formed. For example, in the case of 64 gradations, 63 current mirror circuits are formed for each source signal line, and a desired current is supplied to the source signal line 18 by selecting the number of these current mirror circuits.
It is configured so that it can be applied to. The minimum output current of one current mirror circuit is 10 nA or more and 50 nA.
The following is particularly preferable to be 15 nA or more and 35 nA or less. This is to ensure the accuracy of the transistors forming the current mirror circuit in the source driver 14.

Further, a precharge or discharge circuit for forcibly discharging or charging the electric charge of the source signal line 18 is incorporated. The voltage (current) output value of this circuit is
Since the thresholds of the EL element 15 are different for RGB, R, G, B
It is preferable to be configured so that they can be set independently.

The pixel configuration, the array configuration, the panel configuration, etc., which have been described above are the same as those described below.
It goes without saying that the method and apparatus are applied.

It is known that the organic EL element has a large temperature dependence characteristic (temperature characteristic). In order to adjust the change in emission brightness due to this temperature characteristic, a non-linear element such as a thermistor or posistor that changes the output current is added to the current mirror circuit, and the change due to the temperature characteristic is adjusted with the thermistor etc. Create an electric current. In this case, since the EL material to be selected is uniquely determined, a software-controlled microcomputer or the like is not required in many cases. That is, the liquid crystal material may be fixed to a certain shift amount. What is important is that the temperature characteristics differ depending on the emission color material, and it is necessary to perform optimum temperature characteristic compensation for each emission color (R, G, B).

Needless to say, it is preferable that the R, G, and B EL elements 15 have no temperature characteristics, but the temperature characteristics of each EL element must be within a certain range. At least the R, G, and B temperature characteristic directions are the same direction or do not change. Further, the change is a change of 10 ° C. for each color, and is preferably 2% or more and 8% or less, and more preferably 3% or more and 6% or less.

Alternatively, the temperature characteristic compensation may be performed by a microcomputer. The temperature of the EL display panel is measured by the temperature sensor, and the temperature is changed by a microcomputer (not shown) or the like. Further, the reference current or the like may be automatically switched at the time of switching by microcomputer control or the like, or may be controlled so that a specific menu can be displayed. Further, the switching may be performed by using a mouse or the like, or the display screen of the EL display device may be a touch panel, and a menu may be displayed to hold down a specific portion to switch the display.

In the present invention, the source driver 14 is formed of a semiconductor silicon chip and has a glass-on-chip (C
It is connected to the terminal of the source signal line 18 of the array substrate 49 by the OG) technique. Wiring for signal lines such as the source signal line 18 is made of metal such as chromium, aluminum, and silver. This is because a wiring having a narrow wiring width and a low resistance can be obtained. Since the process can be simplified when the pixel is of a reflective type, the metal wiring is preferably formed of the same material as the reflective film of the pixel and simultaneously with the reflective film.

The present invention is not limited to the COG technique, and the above-mentioned source driver 14 or the like may be mounted on the chip-on-film (COF) technique and connected to the signal line of the display panel. The source driver 14 may have a three-chip configuration by separately manufacturing the power supply IC 102.

Also, TCF tape may be used. TC
The F tape film can be formed by thermocompression bonding a polyimide film and a copper (Cu) foil without using an adhesive. In addition, for films for TCP tape, Cu
There are a method of stacking melted polyimide on a foil and casting, and a method of plating or vapor-depositing Cu on a metal film formed by sputtering on a polyimide film. Although any of these may be used, the method of using a TCP tape in which Cu is attached to a polyimide film without using an adhesive is most preferable. For lead pitches of 30 μm or less, a Cu-bonded laminated plate that does not use an adhesive is used. In the method of forming a Cu-bonded laminated plate that does not use this adhesive,
Since the method of forming the Cu layer by plating or vapor deposition is suitable for thinning the Cu layer, it is advantageous for miniaturizing the lead pitch.

On the other hand, the gate driver 12 is formed by the same process as the TFT of the pixel by the low temperature polysilicon technique. This is because the internal structure is easier and the operating frequency is lower than that of the source driver 14. Therefore, it can be easily formed even by the low temperature polysilicon technique, and a narrow frame can be realized. Of course, the gate driver 12 may be formed of a silicon chip and mounted on the array substrate 49 using COG technology or the like. Further, switching elements such as pixel TFTs, gate drivers, etc. may be formed by a high temperature polysilicon technique or may be formed by an organic material (organic TFT).

The gate driver 12 has a gate signal line 17a.
And a shift register 22b for the gate signal line 17b. Each shift register 22 has positive and negative phase clock signals (CLKxP, CLK).
xN) and a start pulse (STx). In addition, it is preferable to add an enable (ENABL) signal that controls output and non-output of the gate signal line and an up-down (UPDWM) signal that vertically reverses the shift direction. Besides, it is preferable to provide an output terminal or the like for confirming that the start pulse is shifted to the shift register and is output. The shift timing of the shift register is controlled by a signal from a control IC (not shown). In addition, it has a built-in level shift circuit and a test circuit for level shifting external data.

Since the buffer capacity of the shift register 22 is small, the gate signal line 17 cannot be directly driven. Therefore, at least two inverter circuits 23 are formed between the output of the shift register 22 and the output gate 24 that drives the gate signal line 17.

The same applies to the case where the source driver 14 is directly formed on the array substrate 49 by a polysilicon technique such as low-temperature polysilicon, and the gate of an analog switch such as a transfer gate for driving the source signal line and the shift register of the source driver. A plurality of inverter circuits 23 are formed between 22. The following items (the output of the shift register and the output stage that drives the signal line (the items related to the inverter circuit arranged between the output stages such as the output gate or the transfer gate) are common to the source driver and the gate driver circuit. For example, FIG.
Then, the output of the source driver 14 is directly the source signal line 18
Although the output of the shift register 22 of the source driver is connected to a multi-stage inverter circuit 23, the output of the inverter circuit is actually the gate of an analog switch such as a transfer gate. It is connected.

The inverter circuit 23 is a P-channel MO
It is composed of an S-transistor and an N-channel MOS transistor. As described above, the inverter circuit 23 is connected to the output end of the shift register 22 of the gate driver 12 in multiple stages, and the final output thereof is connected to the output gate 24. The inverter circuit 23 may be composed of only P channels. However, in this case, it may be configured as a simple gate circuit instead of the inverter circuit.

The channel width of the P-channel or N-channel TFT constituting each inverter circuit 23 is W,
The channel length is L (when the width is more than double gate, the width or channel length of the channels to be added is added), the order of the inverter near the shift register is 1, and the order of the inverter near the display side is N (Nth stage). To do.

When the number of connected stages of the inverter circuit 23 is large, the characteristic differences of the connected inverter circuits 23 are multiplexed (stacked), and the shift register 22 outputs the output gate 24.
There is a difference in the transmission time to (difference in delay time). For example, in an extreme case, the output gate 24 in FIG.
Although a is on (after the pulse is output from the shift register and started counting) after 1.0 μsec (the output voltage is switched), the output gate 24b is 1.5 μsec.
After (starting from the pulse output from the shift register)
It turns on (the output voltage is switched).

Therefore, the number of inverter circuits 23 formed between the shift register 22 and the output gate 24 is preferably small, but the gate width W of the channel of the TFT which constitutes the output gate 24 is preferably very large. Further, since the gate driving capability of the output stage of the shift register 22 is small,
It is impossible to directly drive the output gate 24 with a gate circuit (NAND circuit or the like) forming a shift register. Therefore, it is necessary to connect the inverters in multiple stages. For example, W4 / L of the inverter circuit 23d in FIG.
4 (channel width of P channel / channel length of P channel) and W3 / of the inverter circuit 23c
If the size ratio of L3 is large, the delay time becomes long, and the variation in the characteristics of the inverter also becomes large.

FIG. 22 shows the relationship between delay time variation (dotted line) and delay time ratio (solid line). The horizontal axis is (Wn-1 / Ln
-1) / (Wn / Ln). For example, in FIG. 21, if the inverter circuit 23d and the inverter circuit 23c have the same channel length L and 2W3 = W4, (W3 / L3) /
(W4 / L4) = 0.5. In the graph of FIG. 22, the delay time ratio is (Wn-1 / Ln-1) / (Wn / L
When n) = 0.5, 1 is set, and the time variation is set to 1 as well as the delay.

In FIG. 22, (Wn-1 / Ln-1) / (W
It is shown that the larger n / Ln), the larger the number of connection stages of the inverter circuit 23 and the larger the delay time variation. Also, (Wn-1 / Ln-1) / (Wn /
It is shown that the smaller Ln) is, the longer the delay time from the inverter circuit 23 to the next-stage inverter circuit 23 is. From this graph, it can be seen that it is advantageous in design to set the delay time ratio and the delay time variation within 2. Therefore, it suffices if the condition of the following equation is satisfied.

0.25≤ (Wn-1 / Ln-1) / (W
n / Ln) ≦ 0.75 Further, the P channel W / L ratio (Wp / Lp) of each inverter circuit 23 and the N channel W / L ratio (Ws / L)
It is necessary to satisfy the following relationship with s).

0.4 ≦ (Ws / Ls) / (Wp / Lp) ≦ 0.8 Furthermore, the number n of stages of the inverter circuit 23 formed between the output end of the shift register and the output gate (or transfer gate) is as follows. If the formula is satisfied, there is little variation in delay time, which is good.

3 ≦ n ≦ 8 There is also a problem with mobility μ. When the mobility μn of the N-channel transistor is small, the sizes of the TG and the inverter are large, and the power consumption and the like are large. Also,
The driver formation area becomes large and the panel size also becomes large. On the other hand, if the mobility μn is large, the characteristics of the transistor are likely to deteriorate, so the mobility μn is preferably in the following range.

50 ≦ μn ≦ 150 Further, the slew rate of the clock signal in the shift register 22 is set to 500 V / μsec or less. This is because if the slew rate is high, the N-channel transistor is severely deteriorated.

In FIG. 21, the inverter circuit 23 is connected to the output of the shift register in multiple stages.
It may be a D circuit. This is because a NAND circuit can also form an inverter. That is, the inverter circuit 2
The number of connection stages of 3 may be considered as the number of gate connection stages. Also in this case, the relationship such as the W / L ratio explained so far is applied. The matters described above with reference to FIGS. 21 and 22 are also applied to FIGS. 66, 67, 69 and the like.

Further, when the switching transistor of the pixel is the P channel in FIG. 21 and the like, the output from the final stage inverter has the ON voltage Vgl of the gate signal line 1
7 and the off voltage Vgh is applied to the gate signal line 17. On the contrary, the switching transistor of the pixel is N
In case of channel, the output from the last inverter is
The off voltage Vgl is applied to the gate signal line 17, and the on voltage Vgh is applied to the gate signal line 17.

In the above embodiments, the gate driver is made at the same time as the pixel 16 by the high temperature polysilicon or the low temperature polysilicon technique, but the invention is not limited to this. For example, as shown in FIG. 23, the source driver 14 and the gate driver 12 made of semiconductor chips may be separately mounted on the display panel 82.

When the display panel 82 is used for an information display device such as a mobile phone, it is preferable to mount the source driver 14 and the gate driver 12 on one side of the display panel as shown in FIG. As shown in the figure, the driver IC is mounted on one side.
Call. Conventionally, the gate driver 12 is provided on the X side of the display area.
Was mounted, and the source driver 14 was mounted on the Y side). This is because it is easy to design so that the center line of the display screen 21 becomes the center of the display device, and it is easy to mount the driver IC. It should be noted that the gate driver circuit may be formed in a three-side free configuration by using high temperature polysilicon or low temperature polysilicon technology (that is, at least one of the source driver 14 and the gate driver 12 in FIG. 23 is polysilicon). Directly formed on the array substrate 49 by the technique).

The three-side free structure means the array substrate 4
In addition to the structure in which the IC is directly mounted or formed on 9,
It also includes a configuration in which a film (TCP, TAB technology, etc.) to which the source driver 14 and the gate driver 12 are attached is attached to one side (or almost one side) of the array substrate 49. In other words, it means a configuration, an arrangement in which ICs are not mounted or attached on two sides, or all similar thereto.

When the gate driver 12 is arranged beside the source driver 14 as shown in FIG. 23, the gate signal line 17 is formed.
Needs to be formed up to the display screen 21 along the C side (see FIG. 24 etc.).

The pitch of the gate signal lines 17 formed on the C side is 5 μm or more and 12 μm or less. This is because when the thickness is less than 5 μm, noise is added to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the effect of the parasitic capacitance remarkably occurs when the thickness is 7 μm or less, and further, the image noise such as a beat is generated on the display screen when the thickness is less than 5 μm.
In particular, the generation of noise differs depending on the left and right of the screen, and it is difficult to reduce the image noise such as the beat. If the reduction exceeds 12 μm, the frame width D of the display panel becomes too large, which is not practical.

In order to reduce the above-mentioned image noise, in the lower layer or the upper layer where the gate signal line 17 is formed,
This can be reduced by arranging a grant pattern (a conductive pattern in which the voltage is fixed to a constant voltage or is set to a stable potential as a whole). Further, a separately provided shield plate (shield foil (conducting pattern in which voltage is fixed to a constant voltage or set to a stable potential as a whole)) may be arranged on the gate signal line 17.

The gate signal line 17 on the C side in FIG. 24 is made of ITO.
Although it may be formed of an electrode, it is preferably formed by stacking ITO and a metal thin film or formed of a metal film in order to reduce the resistance. In the case of stacking with ITO, a titanium film is formed on ITO, and aluminum or an aluminum-molybdenum alloy thin film is formed thereon. Or I
A chrome film is formed on the TO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above matters also apply to other embodiments of the present invention.

In FIG. 24 and the like, the gate signal line 17 and the like are arranged on one side of the display area, but the invention is not limited to this and may be arranged on both sides. For example, the gate signal line 17a may be arranged (formed) on the right side of the display screen 21, and the gate signal line 17b may be arranged (formed) on the left side of the display screen 21. The above matters are the same in other embodiments.

In FIG. 25, the source driver 14 and the gate driver 12 are integrated into one chip (one-chip driver IC 14
c) Yes. With one chip, only one IC chip needs to be mounted on the display panel 82. Therefore, the mounting cost can be reduced. Further, various voltages used in the one-chip driver IC 14c can be generated at the same time.

The source driver 14, the gate driver 12, and the one-chip driver IC 14c are made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the present invention is not limited to this. It may be directly formed on the display panel 82 by a polysilicon technique.

In FIG. 26, the gate drivers 12a and 12b are mounted (or formed) on both ends of the source driver 14, but the present invention is not limited to this. For example, as shown in FIG. 23, one gate driver 12 may be arranged on one side adjacent to the source driver 14. Note that, in FIG. 26 and the like, a thick solid line portion indicates a portion where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of scanning signal lines are formed in parallel in the portion b (the lower portion of the screen), and one gate signal line 17 is formed in the portion a (the upper portion of the screen).

When two gate drivers 12a and 12b are used as shown in FIG. 26, the number of gate signal lines 17a formed in parallel with the side C of FIG. 26 is 1 / the number of scanning lines.
The number is 2 (because the number of gate signal lines can be arranged in half on the left and right sides of the screen). Therefore, the frame has a feature that it is even on the left and right sides of the screen.

The present invention relates to the scanning direction of the gate signal line 17,
There is also a feature in screen division. For example, in FIG. 26, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. Further, the gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. Gate signal line 17
The scanning direction is also from the top to the bottom of the screen, as indicated by arrow A. The source signal line 18 is common to the upper part of the screen and the lower part of the screen.

In FIG. 27, the gate driver 12a is connected differently from the adjacent gate signal line 17 at the top of the screen. The gate driver 12a is connected to the odd-numbered gate signal lines 17b. In addition, the gate driver 12
b is connected to the even-numbered gate signal lines 17a.
Regarding the scanning direction of the gate signal line, the gate signal line 17b is from the upper part to the lower part of the screen (arrow A). Gate signal line 1
7a is the direction from the bottom to the top of the screen (arrow B). As described above, by connecting the gate signal line 17 to the gate driver 12 and by setting the scanning method of the gate signal line in a predetermined direction, the display screen 21 does not have a luminance inclination and flicker occurs. Can be suppressed. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. However, it goes without saying that the screen may be divided at the top and bottom. The above items also apply to other embodiments.

In FIG. 25, which is a single chip, the gate driver 12a is connected to the gate signal line 17b at the top of the screen. Further, the gate driver 12b is connected to the gate signal line 17a at the bottom of the screen. Gate signal line 17b
The scanning direction is as shown by arrow A from the top to the bottom of the screen. The scanning direction of the gate signal line 17a is arrow B
As shown by the direction from the bottom to the top of the screen. The source signal line 18 is common to the upper part of the screen and the lower part of the screen. In this way, the gate signal line 17 is connected to the gate driver 1
By connecting the gate signal line 2 with the scanning direction of the gate signal line in a predetermined direction, the display screen 21 does not have a luminance gradient and flicker can be suppressed.

The one-chip driver IC 14c is made of a semiconductor wafer such as silicon and mounted on the display panel 82. However, the present invention is not limited to this. The one-chip driver IC 14c can be mounted on the display panel 82 by the low temperature polysilicon technology or the high temperature polysilicon technology. It may be formed directly. Further, the driver IC that drives the upper part of the screen may be arranged on the upper side of the display screen, and the driver IC that drives the lower part of the screen may be arranged on the lower side of the display screen (that is, the mounted IC is two chips). The above items also apply to other embodiments of the present invention.

In FIG. 25 and FIG. 26, the screen is shown divided at the central portion, but the present invention is not limited to this. For example, in the case of FIG. 26, the display screen 21a may be made smaller and the display screen 21b may be made larger. This display screen 21a is used as a partial display area (see FIG. 28), and mainly time display and date display are performed and used in the low power consumption mode. 25 and 26, the display screen 21a is displayed by the gate signal line 17b, and the display screen 21b is displayed by the gate signal line 17a.

Further, in FIG. 28 and the like, as shown in FIG. 29, the display screen 21a has three sides free, and the display screen 21b has the conventional source driver 14 and the gate driver 12 arranged on different sides. May be That is, the gate signal line 17a and the source signal line 18a are output from the one-chip driver IC 14c.

Further, as shown in FIG. 30, the display screen 21 may be divided into two screens 21a and 21b, and the source driver 14 and the gate driver 12 corresponding to each screen may be arranged. In FIG. 30, each source driver 1
Since the writing time of the video signal output from No. 4 is twice as long as that of the other embodiments, the signal can be sufficiently written in the pixel. Further, as shown in FIG. 31, one display screen 21 may be provided, and one source driver 14 may be arranged above and one below the screen. This can be similarly applied to the gate driver 12.

In the above embodiment, the gate signal lines 17 are formed in parallel and are wired up to the pixel region.
Needless to say, the configuration is not limited to this, and the source signal line 18 may be arranged in parallel to one side as shown in FIG.

28, 29, 30, etc., it is possible to reduce the power consumption by changing the frame rate (driving frequency or the number of screen rewritings per unit time (1 second)) between the display screens 21a and 21b. It is an effective means. Further, changing the number of display colors or the display colors on the display screens 21a and 21b is also effective in reducing power consumption.

In the structure shown in FIG. 6, the cathode of the EL element 15 is connected to the Vs1 potential. However, there is a problem in that the driving voltage of the organic EL that constitutes each color is different. For example, 0.01A per square centimeter
When the current is applied, the terminal voltage of the EL element is 5V for blue (B), but is 9V for green (G) and red (R). That is, the terminal voltages of B, G and R are different. Therefore, the source-drain voltage (SD voltage) of the held TFTs 11c and 11d is different between B, G and R, and the off-leakage current between the source-drain voltage (SD voltage) of the transistor is also different for each color. If an off-leakage current is generated and the off-leakage characteristics are different for each color, flicker occurs in a state where the color balance is deviated, and the gamma characteristic shifts in correlation with the emission color, resulting in a complicated display state.

In order to address this problem, the present invention uses FIG.
As shown in FIG. 3, among at least R, G, and B colors,
The potential of one cathode electrode is different from the potential of the cathode electrodes of the other colors. Specifically, FIG.
Then, B is used as the cathode electrode 53a, and G and R are used as the cathode electrode 53b. Note that, although FIG. 33 assumes lower extraction for extracting light from the glass surface, there is also a case of upper extraction. In this case, the cathode and the anode are reversed.

It goes without saying that it is preferable to make the terminal voltages of the R, G, and B EL elements 15 match as much as possible. At least the white peak brightness is displayed and the color temperature is 60
EL of R, G, B in the range from 00K to 9000K
It is necessary to select the material or structure so that the terminal voltage of the device is 10 V or less. Also, of R, G, and B,
The difference between the maximum terminal voltage and the minimum terminal voltage of each EL element needs to be 2.5 V or less, more preferably 1.5 V or less. Although the colors are RGB in the above embodiments, the colors are not limited to these. This will be explained later.

It is also necessary to correct color unevenness. This color unevenness is caused by variations in film thickness and characteristics because EL materials of different colors are applied separately. In order to correct this, white raster display is performed with a brightness of 30% to 70%, and the in-plane distribution of each color in the display screen 21 is measured. The in-plane distribution is measured every 1 point for at least 30 pixels.
The measurement data is stored in a table composed of a memory, and the stored data is used to correct the input image data and display it on the display screen 21.

Note that the pixels are three primary colors of R, G, and B, but the present invention is not limited to this, and cyan, yellow, and
Three colors of magenta are also acceptable. Further, it may be two colors of B and yellow, or of course, may be a single color. Also, R, G, B,
6 colors of cyan, yellow and magenta may be used, or R,
Five colors of G, B, cyan, and magenta may be used. These are natural colors with a wide color reproduction range and good display. In addition, four colors of R, G, B, and white may be used, or eight colors of R, G, B, cyan, yellow, magenta, black, and white may be used. In addition, the pixels that emit white light are displayed on the display screen 21.
It may be formed (fabricated) over the whole, and displayed in three primary colors with a color filter such as RGB, and may be formed by stacking light emitting materials of respective colors on the EL layer. Alternatively, one pixel may be painted separately such as B and yellow. As described above, the EL display device of the present invention is not limited to one that performs color display with the three primary colors of RGB.

Further, as shown in FIG. 34, pixels 16W emitting white light may be formed in addition to the three primary colors. The white light-emitting pixel 16W is manufactured (formed or configured) by stacking R, G, and B light-emitting structures, and one set of pixels is
It is composed of these three primary colors of RGB and a pixel 16W that emits white light. By thus forming the pixels that emit white light, it becomes easier to express the peak luminance of white, and it is possible to realize an image display with a feeling of brightness.

Further, even when the three primary colors of RGB are used as one set of pixels, as shown in FIG. 35, it is preferable that the area of the pixel electrode for each color be different. Of course, the same area may be used as long as the luminous efficiency of each color is well balanced and the color purity is well balanced. However, when the balance of one or more colors is poor, it is preferable to adjust the pixel electrode (light emitting area), and the electrode area for each color may be determined based on the current density. That is, the color temperature is 600
When the white balance is adjusted in the range of 0K (Kelvin) or more and 9000K or less, the difference in current density of each color is ± 30.
%, And more preferably within ± 15%. For example, if the current density is 100 A / square meter, all three primary colors are 70 A / square meter or more and 130 A / square meter or less, more preferably 85 A / square meter or less.
/ Square meter or more and 115 A / square meter or less.

Further, as shown in FIG. 36, it is preferable to arrange the three primary colors differently in the adjacent pixel rows. For example, if the even-numbered rows have the arrangement of R, G, and B from the left, the odd-numbered rows have the arrangement of B, G, and R. By arranging in this way, the resolution in the diagonal direction of the image is improved even with a small number of pixels. Furthermore, the first row is the arrangement of R, G, B, R, G, and B from the left, and the second row is G,
The arrangement of B, R, G, B, and R is set, and the third row is B, R, G, and
The pixel arrangement may be different in three or more pixel rows, such as the arrangement of B, R, and G.

The cathode electrode 53a is formed by using a metal mask technique in which the organic EL of each color is separately applied. The metal mask is used because the organic EL is weak in water and cannot be etched. Using a metal mask (not shown), the cathode electrode 53a is vapor-deposited and, at the same time, connected to the contact hole 52a. The contact hole 52a can be electrically connected to the B cathode wiring 51a.

Similarly, the cathode electrode 53b is also formed by using a metal mask technique in which organic EL of each color is separately applied.
Using a metal mask (not shown), the cathode electrode 53
b is vapor-deposited and, at the same time, connected to the contact hole 52b. RG cathode wiring 5 through the contact hole 52b
An electrical connection can be made with 1b. The cathode electrode may be formed to have an aluminum film thickness of 70 nm or more and 200 nm or less.

With the above structure, different voltages can be applied to the cathode electrodes 53a and 53b. Therefore, even if the Vdd voltage in FIG.
The voltage applied to the EL element of at least one color can be changed. In FIG. 33, the same cathode electrode 53b is used as RG, but the present invention is not limited to this. R and G may be different cathode electrodes 53b.

With the above structure, it is possible to prevent the generation of off-leakage current between the source-drain voltage (SD voltage) of the transistor and the kink phenomenon for each color. Therefore, flicker does not occur, the gamma characteristic does not shift in correlation with the emission color, and good image display can be realized.

Also, let Vs1 in FIG. 6 be the cathode voltage,
Although the cathode voltage is made different for each color, the present invention is not limited to this, and the anode voltage Vdd may be made different for each color. For example, V of R pixel
The dd voltage may be 8V, G may be 6V, and B may be 10V. It is preferable that these anode voltage and cathode voltage are configured to be adjustable within a range of ± 1V.

Even if the panel size is about 2 inches,
A current of about 100 mA is output from the anode connected to the Vdd voltage. Therefore, it is essential to reduce the resistance of the anode wiring (current supply line) 20. In order to cope with this problem, in the present invention, as shown in FIG. 37, the anode wiring 63 is supplied from the upper side and the lower side of the display area (both ends are fed). By supplying power to both ends as described above, the occurrence of a brightness gradient at the top and bottom of the screen is eliminated.

The pixel electrode 48 may be roughened to increase the emission brightness. This structure is shown in FIG. First, fine unevenness is formed in a place where the pixel electrode 48 is formed by using a stamper technique. When the pixel is a reflection type, a pixel electrode 48 is formed by forming a metal thin film of aluminum having a thickness of about 200 nm by a sputtering method. A convex portion is provided at a position where the pixel electrode 48 is in contact with the organic EL element to roughen the surface. In the case of a simple matrix type display panel, the pixel electrode 48 is a stripe electrode. Further, the convex portion is not limited to the convex shape and may be a concave shape. Moreover, you may form a concave and a convex simultaneously.

The size of the protrusions is about 4 μm, the average value of the distance between adjoining portions is 10 μm, 20 μm, 40 μm, and the unit area density of the protrusions is 1000 to 1200 pieces / mm.
² , 100 to 120 pieces / mm ² , 600 to 800 pieces / mm
^When luminance was measured as No. ² , it was found that the emission luminance increased as the unit area density of the protrusions increased.
Therefore, it was found that by changing the unit area density of the protrusions on the pixel electrode 48, the surface state of the pixel electrode can be changed to adjust the emission brightness. According to the examination, good results could be obtained by setting the unit area density of the protrusions to 100 / mm ² or more and 800 / mm ² or less.

The organic EL is a self-luminous element. When the light generated by this light emission enters a TFT as a switching element, a photoconductor phenomenon (photocon) occurs. The photocon refers to a phenomenon in which a leak (off leak) when a switching element such as a TFT is turned off increases due to photoexcitation.

In order to cope with this problem, the present invention is shown in FIG.
As shown in FIG. 8, a light shielding film 91 is formed under the gate driver 12 (source driver 14 in some cases) and under the pixel TFT 11. The light-shielding film 91 is formed of a metal thin film such as chromium and has a film thickness of 50 nm to 150 nm.
Below. This is because if the film thickness is thin, the light-shielding effect is poor, and if it is thick, irregularities occur and patterning of the upper-layer TFT 11 becomes difficult.

A smoothing film 71a made of an inorganic material having a thickness of 20 nm or more and 100 nm or less is formed on the light shielding film 91. Alternatively, by using the layer of the light shielding film 91, the capacitor 1
One electrode of 9 may be formed. In this case, it is preferable to make the smoothing film 71a as thin as possible and increase the capacitance value of the capacitor. Further, the light-shielding film 91 is formed of aluminum, and a silicon oxide film is formed using the anodic oxidation technique.
The silicon oxide film is formed on the surface of
It may be used as the dielectric film. A pixel electrode having a high aperture (HA) structure is formed on the smoothing film 71b.

The gate driver 12 and the like should prevent light from entering not only from the back surface but also from the front surface. This is because the photocon will cause a malfunction. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the gate driver 12 or the like, and this electrode is used as a light shielding film.

However, if the cathode electrode is formed on the gate driver 12, the electric field from the cathode electrode may cause the driver to malfunction or the cathode electrode and the driver circuit to electrically contact with each other. In order to solve this problem, in the present invention, at least one layer, preferably a plurality of layers of organic EL films are formed on the gate driver 12 and the like at the same time when the organic EL films are formed on the pixel electrodes. Since the organic EL film is basically an insulator, by forming the organic EL film on the gate driver, the cathode and the gate driver are separated from each other, and the above-mentioned problem can be solved.

In a pixel, when one or more terminals of the TFT 11 or the TFT 11 and the signal line are short-circuited, EL
In some cases, the element 15 is constantly turned on and becomes a bright spot. Since these bright spots are visually conspicuous, it is necessary to make them black dots (non-lighting). As a countermeasure against this, the corresponding pixel 16 is detected, and the capacitor 19 is irradiated with laser light to short-circuit the terminals of the capacitor. Then, since the capacitor 19 cannot hold the electric charge, the TFT 11 does not flow the current.

At this time, it is desirable to remove the cathode film corresponding to the position where the laser beam is irradiated. This is to prevent the terminal electrode of the capacitor 19 and the cathode film from being short-circuited by the laser light irradiation.

Also, the structure shown in FIG. 39 is exemplified. FIG. 39 shows an example of a lower extraction structure for extracting light from the array substrate 49 side. Also in FIG. 39, the lower layer of the gate driver 12 (source driver 14 in some cases),
A light shielding film is formed below the pixel TFT 11.

However, since it malfunctions due to the influence of the photo controller, the gate driver 12 (or the source driver 1
In 4), etc., not only the back surface but also the light entering from the front surface should be suppressed. Therefore, in the present invention, the cathode electrode 46 is used as a light shielding film.

On the other hand, when the cathode (or anode) electrode is a transparent electrode, that is, when the pixel electrode is a reflection type and the common electrode is a transparent electrode (ITO, IZO, etc.), a structure for light extraction (light from the array substrate 49 side) is used. In the case of taking out the light from the bottom, and taking the light from the EL film deposition surface into the light), the sheet resistance value of the transparent electrode becomes a problem. This is because the transparent electrode has a high resistance, but it is necessary to pass a current with a high current density through the cathode of the organic EL. Therefore, if the cathode electrode is formed of a single layer of the ITO film, it will be in a heated state due to heat generation, or an extreme brightness gradient will occur on the display screen.

In order to address this problem, the low resistance wiring 92 made of a metal thin film is formed on the surface of the cathode electrode. The low resistance wiring 92 has the same structure as the black matrix (BM) of the liquid crystal display panel (film thickness of 50 nm to 200 nm made of chromium or aluminum material), and the same position (between the pixel electrodes, on the gate driver 12, etc.). Is.
However, the organic EL does not need to form a BM, and therefore has a completely different function. The low resistance wiring 92 is the transparent electrode 7.
It is not limited to the front surface of No. 2 and may be formed on the back surface (the surface in contact with the organic EL film). Further, as the metal film formed in the BM shape, Mg.Ag, Mg.Li, Al.Li
For example, aluminum, magnesium, indium, copper, or alloys thereof may be used, such as alloys or laminated structures. In order to prevent corrosion on the BM,
Furthermore, ITO and IZO films are laminated, and SiNx, S
An inorganic thin film such as iO ₂ or an organic thin film such as polyimide is formed.

When light is to be extracted (upper extraction) from the deposition surface of the EL film, Mg-Al is formed on the organic EL layer 47.
It is preferable to form a film and then form an ITO or IZO film thereon. Alternatively, it is preferable that a Mg—Al film is formed on the organic EL layer 47 and a black matrix (black matrix such as a liquid crystal display panel) is formed thereon. This black matrix is chrome, Al,
It is made of Ag, Au, Cu, etc., on which SiO ₂ ,
It is preferable to form the protective film 1761 made of an inorganic insulating film such as SiNx or an organic insulating film such as polyester or acrylic. Further, it is preferable to form an antireflection film (AIR coat) on the protective film 1761.
The minimum film thickness of the protective film 1761 is 1 μm or more.

Further, even in the case of the bottom extraction, it is also effective to increase the transmittance of the reflection film 46 of the cathode electrode. Even in the configuration in which the display image is viewed from the array substrate 49 side, the reflection film 46 has a high transmittance, so that the reflection is reduced and the circularly polarizing plate 74 is unnecessary. Therefore, the light extraction efficiency may be improved as compared with the upper extraction. The transmittance of the reflective film 46 is 60% or more and 90% or more.
In particular, it is preferably 70% or more and 90% or less. This is because when it is 60% or less, the sheet resistance value of the cathode electrode is low, while the reflection is large. On the contrary, when it is 90% or more, the sheet resistance value of the cathode electrode becomes high, and the brightness gradient of the display image becomes large.

In order to increase the transmittance of the reflective film 46, the Al film is thinly formed with a thickness of 20 nm or more and 100 nm or less. It is preferable to form an ITO or IZO film on it. Alternatively, it is preferable to form a black matrix on the Al film.

As shown in FIG. 40, by making the pixel electrode 48 arcuate, the light emitting area of the organic EL layer 47 becomes wider. Therefore, the current density is reduced and the life of the EL element 15 can be extended. Moreover, since the terminal voltage of the EL element 15 is also reduced, the power efficiency is improved.

FIG. 41 is an explanatory diagram of a method of manufacturing the EL display panel described in FIG. As shown in FIG. 41A, the TFT 11, the gate driver 12 and the like are formed on the array substrate 49.

Next, as shown in FIG. 41B, a smoothing film 71 made of an organic material such as acrylic resin is applied on the array substrate 49. The smoothing film 71 is SOG.
It may be an inorganic material such as. The film thickness is preferably 1.5 μm or more and 3 μm or less. Next, a mask 1771 is formed on the smoothing film 71. The mask 1771 is formed of a metal material, and its formation position corresponds to the pixel 16. Next, etching is performed. The etching may be either wet etching or dry etching such as O ₂ plasma. From between the mask 1771, the smoothing film 71
41C, the smoothing film 71 has an arc shape as shown in FIG.

Further, as shown in FIG. 41 (d),
A mask (not shown) is formed on the smoothing film 71 to form a contact hole 1772. Alternatively, FIG.
The contact hole 1772 is also formed at the same time in the etching step (b).

Next, as shown in FIG. 41 (e), I
The pixel electrode 48 is formed of a transparent electrode such as TO or IZO. The pixel electrode 48 and the TFT 11 are connected by the pixel contact portion 1751. This contact hole is ITO
The pixel electrode 48 composed of is electrically connected to the drain terminal.

Next, on the pixel electrode 48, 50 nm or more 15
A thin carbon film with a thickness of 0 nm or less is vapor-deposited, and organic E
The L layer is formed. The organic EL layer 47 is separately coated on the entire surface in the case of a single color and by using a metal mask in the case of RGB (see FIG. 41 (f)).

After forming the organic EL layer 47, an Al film (reflection film) 46 to be a cathode electrode is formed (FIG. 41).
(G)). Further, the protective film 1 is formed on the Al film (reflection film) 46.
761 is formed (FIG. 41 (h)).

The protective film 1761 may be a protective layer using a film. For example, as the protective layer, it is exemplified to use a film of an electrolytic capacitor on which DLC (diamond-like carbon) is vapor-deposited. Since this film has extremely poor moisture permeability (moisture proof), it can be used as the protective layer 1761. Further, the thickness of the protective layer 1761 is n · d (n is the refractive index of a thin film, and when a plurality of thin films are stacked, the total refractive index of the thin films (n · d of each thin film is
To calculate). d is a film thickness of a thin film, and when a plurality of thin films are laminated, their refractive indexes are comprehensively calculated. ) Is preferably the emission main wavelength λ of the EL element 15 or less.

The organic EL layer 47 or the pixel electrode 48.
Is not limited to an arc shape, and may be a triangular pyramid shape, a conical shape, a sine curve shape, or a structure in which these are combined. Further, one pixel may have a fine arc shape, a triangular pyramid shape, a conical shape, a sine curve shape, a combination thereof, or a structure in which random unevenness is formed. In addition, in FIG. 40, the shape is a convex arc shape, but the same applies to a concave arc shape.

FIG. 42 is a structural view (cross-sectional view) formed into a panel. Although the same applies to the other drawings, in the present specification, each drawing is omitted or enlarged or reduced in order to facilitate understanding or drawing. Also in the sectional view of the display panel of FIG. 42, the smoothing film 71 and the like are shown sufficiently thick. However, the plate thickness of the array substrate 49 is shown to be very thin. Further, TFTs and the like are omitted.

In FIG. 42, a spacer 1781 is arranged between the sealing lid 41 and the array substrate 49, and the protective film 17 is formed.
61 or the reflection film 46 or the organic EL layer 47 and the sealing lid 41 are not in direct contact with each other. The desiccant is arranged or filled in the peripheral portion of the display area. A cylindrical or spherical spacer is used. Height is 1
The thickness is preferably 0 μm or more and 100 μm or less. Further, the protective film 1761 can be processed to serve as a spacer. That is, a part or the whole of the protective film 1761 is processed or formed into a projection shape, a column shape, or a stripe shape so that the protection film 1761 has a spacer function. Note that a structure in which the spacer 1781 is used as a drying agent is also preferable.

In the pixel shown in FIG. 19, the driving TFT 11b and the converting TFT 11a have a current mirror relationship,
These characteristics (threshold value Vt, S value, mobility μ, etc.) must match. Also in the pixel of FIG. 6, it is needless to say that it is preferable that the characteristics of the TFTs are the same.

The semiconductor film forming the TFT 11 of the pixel 16 is generally formed by laser annealing in the low temperature polysilicon technique. Variations in the laser annealing conditions cause variations in the characteristics of the TFT 11. However, if the characteristics of the TFTs 11 in one pixel 16 are the same, it is possible to drive the EL element 15 so that a predetermined current flows in the method of performing the current programming as shown in FIGS. This is an advantage over voltage programming.

To solve this problem, in the present invention, as shown in FIG. 43, the laser irradiation spot 230 during annealing is used.
Is irradiated in parallel with the source signal line 18. Further, the laser irradiation spot 230 is moved so as to coincide with one pixel column. Of course, it is not limited to one pixel row,
For example, RGB may be irradiated with the laser in the unit of 1 pixel 16 in FIG. 43 (in this case, it means 3 pixel columns). In particular, the pixel is made up of three RGB pixels and has a square shape. Therefore, R, G,
Each pixel of B has a vertically long pixel shape. Therefore, pixel 1
The TFTs 11 formed in 6 are arranged in the vertical direction as shown in FIG. 34 (conversion TFT 11a, driving TFT 11b). Therefore, by making the laser irradiation spot 230 vertically long and annealing, it is possible to prevent the characteristic variation of the TFT 11 from occurring within one pixel.

Generally, the length of the laser irradiation spot 230 is a fixed value such as 10 inches. Since this laser irradiation spot 230 is moved, 1
It is necessary to arrange the panel so that the two laser irradiation spots 230 can be kept within a movable range (that is, the laser irradiation spots 230 do not overlap in the central portion of the display screen 21 of the panel).

In the structure shown in FIG. 44, three panels are vertically arranged within the range of the length of the laser irradiation spot 230. The annealing device that irradiates the laser irradiation spot 230 recognizes the positioning markers 242a and 242b on the glass substrate 241, and moves the laser irradiation spot 230. The recognition of the positioning marker 242 is performed by the pattern recognition device. An anneal device (not shown) recognizes the positioning marker 242 and determines the position of the pixel row. Then, the laser irradiation spot 230 is irradiated so as to exactly overlap the pixel row position, and annealing is sequentially performed.

The laser annealing method (method of irradiating a linear laser spot in parallel with the source signal line 18) described with reference to FIGS. 43 and 44 is preferably adopted especially in the current programming method of the organic EL panel. This is because the parallel direction of the source signal line and the characteristics of the TFT 11 match (the characteristics of the pixel TFTs adjacent in the vertical direction are similar). Therefore, the change in the voltage level of the source signal line is small during current driving, and insufficient current writing is unlikely to occur (for example, in the case of white raster display, since the currents flowing through the conversion TFTs 11a of adjacent pixels are almost the same, (There is little change in the amplitude of the current output from the driver 14).

Further, a uniform image display can be realized by the method of simultaneously writing a plurality of pixel rows described with reference to FIG. 45, FIG. 46, etc. (because display unevenness due to variations in TFT characteristics hardly occurs). . In FIG. 45, etc., since a plurality of pixel rows are selected at the same time, the TFTs of adjacent pixels
Is uniform, the TFT characteristic unevenness in the vertical direction can be absorbed by the source driver 14.

As shown in FIG. 6, the gate signal line 17a is conductive during the row selection period (here, the TFT 11 of FIG.
Since it is a channel transistor, it becomes conductive at a low level), and the gate signal line 17b becomes conductive during the non-selection period.

When the source signal line is in the gradation 0 display state and a current value for gradation 1 is applied and the row selection period is operated for 75 μsec, as shown by the solid line a in FIG. , If the parasitic capacitance of the source signal line 18 increases, EL
The current value output to the element 15 decreases.

The dotted line b in FIG. 47 shows the case where the current value for gradation 1 is made to flow ten times as much as the solid line a, and the current value output to the EL element 15 is increased as the parasitic capacitance of the source signal line 18 increases. The reduction rate of is small. For a given current value,
Since a variation of about 10% cannot be observed as a difference in brightness for the human eye, if the reduction of about 10% is admitted, the allowable source capacitance is 2 pF or less in the solid line a.
The dotted line b is 25 pF or less.

The time t required for changing the current value of the source signal line 18 is t = C.multidot., Where C is the size of the stray capacitance, V is the voltage of the source signal line, and I is the current flowing through the source signal line.
Since it is V / I, the fact that the current value can be increased ten times means that the time required for changing the current value can be shortened to nearly 1/10, or the current value can be changed to a predetermined current value even if the source capacitance increases ten times. Show. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.

If the input current is multiplied by 10, the output current is also increased by 10.
In order to obtain a predetermined brightness so that the brightness of the EL element becomes 10 times, the conduction period of the switching TFT 11d of FIG. Displayed the brightness. That is,
In order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and program a predetermined current value to the conversion TFT 11a of the pixel 16, it is necessary to output a relatively large current from the source driver 14. . However, when such a large current is supplied to the source signal line 18, this current value is programmed in the pixel, and a large current flows to the EL element 15 with respect to a predetermined current. For example, if programming is performed with a current of 10 times, the current of 10 times is naturally obtained by the EL element 15
Then, the EL element 15 emits light with 10 times the brightness. That is, in order to obtain a predetermined light emission brightness, the time flowing through the EL element 15 may be reduced to 1/10. By driving in this way, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.

It should be noted that a tenfold current value is applied to the pixel conversion TF.
T11a (to be exact, the terminal voltage of the capacitor 19 is set) is written, and the ON time of the EL element 15 is 1/1.
It is set to 0, but this is an example. In some cases,
A ten times larger current value may be written in the pixel conversion TFT 11a to reduce the ON time of the EL element 15 to ⅕. On the contrary, there may be a case where a 10-fold current value is written in the pixel conversion TFT 11a to double the ON time of the EL element 15. The present invention is characterized in that the write current to the pixel is set to a value other than the predetermined value and the current flowing in the EL element 15 is driven in an intermittent state. In this specification, for ease of explanation, it is assumed that an N times larger current value is written in the TFT 11 of the pixel and the ON time of the EL element 15 is made 1 / N times larger. However, the present invention is not limited to this, and N1
Write the doubled current value to the TFT 11 of the pixel, and
It goes without saying that the ON time of 5 may be 1 / N2 times (different from N1 and N2). The intermittent intervals are not limited to equal intervals.

Also, for ease of explanation, 1F (1 field or 1 frame) is used as a reference for 1F.
/ N will be described. However, since one pixel row is selected and a current value is programmed (generally, one horizontal scanning period (1H)) and an error occurs depending on the scanning state, the above description is easy to explain. However, the present invention is not limited to this.

The organic (inorganic) EL display device also has a problem in that the display method is basically different from that of a display that displays an image as a group of line displays with an electron gun, such as a CRT. That is, the EL display device holds the current (voltage) written in the pixel for a period of 1F (one field or one frame). Therefore, when a moving image is displayed, the problem that the outline of the displayed image is blurred occurs.

In the present invention, E only during the period of 1F / N
A current is passed through the L element 15 for another period (1F (N-1) /
N) does not carry current. Consider a case where this driving method is performed and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is, the image data display state becomes a temporally intermittent display (intermittent display) state. When the moving image data display is viewed in this intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT. Although the intermittent display is realized, the main clock of the circuit is the same as the conventional one. Therefore, the power consumption of the circuit does not increase.

In the case of a liquid crystal display panel, the image data (voltage) for light modulation is held in the liquid crystal layer, and it is necessary to rewrite the data applied to the liquid crystal layer when attempting black insertion display. Therefore, the source driver 14
Since it is necessary to increase the operation clock of and to apply the image data to the source signal line 18 alternately with the black display data, in order to realize the black insertion display (intermittent display such as black display), the main circuit of the circuit is required. I need to raise the clock. Also, an image memory for performing the time axis expansion is required.

However, in the pixel structure of the EL display panel of the present invention, FIG. 6, FIG. 159, FIG. 162, FIG. 184, FIG.
1, FIG. 85, FIG. 86, FIG. 72 to FIG. 76, FIG. 83, FIG.
7, FIG. 79, FIG. 80, FIG. 182, etc., the image data is held in the capacitor 19, and a current corresponding to the terminal voltage of this capacitor 19 is passed through the EL element 15. Therefore, the image data is not held in the light modulation layer like the liquid crystal display panel.

The present invention controls the current flowing through the EL element 15 simply by turning on / off the switching TFT 11d, the TFT 11e, or the like. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is retained in the capacitor 19 as it is. Therefore, the switching element or the like is turned on at the next timing, and the EL element 1
When a current is passed through 5, the current that flows is the same as the current value that was flowing before. In the present invention, it is not necessary to raise the main clock of the circuit even when trying to realize black insertion display (intermittent display such as black display). Moreover, since it is not necessary to perform time-axis expansion, an image memory is also unnecessary. In addition, the organic EL element 15 has a short time from applying a current to emitting light and has a high-speed response. Therefore, it is suitable for displaying moving images, and by implementing intermittent display, it is possible to solve the problem of displaying moving images, which is a problem of conventional data-holding type display panels (liquid crystal display panels, EL panels, etc.).

As shown in FIG. 48, the gate signal line 17b
Conventionally, the conduction period is 1F (when the current program time is 0, the normal program time is 1H, and the number of pixel rows of the EL display device is at least 100 rows or more, so even if it is 1F, the error is 1% or less. 47, and if N = 10, according to FIG. 47, even if the source capacitance is about 20 pF from the gradation 0 to the gradation 1 which takes the longest time to change, 75 μ
It can change in seconds. This indicates that an EL display device of about 2 type can be driven at a frame frequency of 60 Hz.

Further, when the source capacitance is large in a large-sized display device, the source current may be increased 10 times or more. Generally, when the source current value is increased N times, the conduction period of the gate signal line 17b (TFT 11d) may be set to 1 F / N. As a result, it can be applied to a display device for a television, a monitor and the like.

A more detailed description will be given below with reference to the drawings. First, the parasitic capacitance 404 in FIG. 6 is generated by the coupling capacitance between the source signal lines, the buffer output capacitance of the source driver 14, the cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance 404 is normally 1
It becomes 0 pF or more. Source driver 1 for voltage drive
Since voltage is applied to the source signal line 18 with a low impedance from No. 4, there is no problem in driving even if the parasitic capacitance 404 is somewhat large.

However, it is necessary to program the capacitor 19 of the pixel with a minute current of 5 nA or less in current driving, particularly in image display of black level. Therefore, when the parasitic capacitance 404 is generated with a magnitude equal to or larger than a predetermined value, the time for programming one pixel row (usually within 1H, but it is not limited to within 1H because two pixel rows may be written simultaneously). It is not possible to charge and discharge the parasitic capacitance inside. If charging / discharging cannot be performed in the 1H period, writing into the pixel becomes insufficient and no resolution is obtained.

In the case of the pixel configuration of FIG. 6, as shown in FIG. 18A, the program current I1 flows through the source signal line 18 during current programming. This current I1 is TF for conversion
V1 of the capacitor 19 is set (programmed) so that the current flowing through T11a and flowing the program current I1 is retained. At this time, the switching TFT 11d is in an open state (off state).

Next, the TFT 11 operates as shown in FIG. 18B during the period in which a current is passed through the EL element 15. That is, the off voltage Vgh is applied to the gate signal line 17a, and the conversion TFT 11a and the capture TFT 11c are turned off. on the other hand,
The on voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on.

Now, assuming that the program current I1 is N times the current (predetermined value) originally flowing, the EL of FIG.
The current flowing through the element 15 also becomes I1. Therefore, the EL element 15 emits light with a brightness N times the predetermined value.

Therefore, if the switching TFT 11d is turned on for a period of 1 / N of the time (about 1F) originally turned on and the other period (N-1) / N is turned off, the average brightness of the entire 1F is predetermined. It becomes the brightness of. This display status is CR
It is similar to T scanning the screen with an electron gun. The difference is that 1 / N of the entire screen (where the entire screen is 1) lights up in the range where the image is displayed (in the CRT, the range where the light is illuminated is 1 pixel row (strictly speaking). Is 1 pixel)).

In the present invention, this 1 / N image display area moves from the top to the bottom of the display screen 21 as shown in FIG. 49 (a1). In the present invention, the EL is used only during the 1F / N period.
A current flows through the element 15 and the other period (1F · (N−1) /
No current flows in N). Therefore, the image is displayed intermittently, but since the image is held by the afterimage to the human eye, the entire screen appears to be displayed uniformly.

In this display state, image data display and black display (non-lighting) are repeatedly displayed for each 1F. That is,
The image data display state becomes a temporally intermittent display (intermittent display) state. In the liquid crystal display panel (EL display panel other than the present invention), data is held in the pixel for the period of 1F, and therefore, in the case of moving image display, even if the image data changes, the change cannot be followed, It was a blurred video (blurred image outline). However, in the present invention, since the image is displayed intermittently, the outline of the image is not blurred and a good display state can be realized. That is, it is possible to realize moving image display close to that of a CRT.

Further, in the EL display device, since black display is completely non-lighted, there is no reduction in contrast as in the case where the liquid crystal display panel is intermittently displayed. Further, as shown in FIG. 18, intermittent display can be realized by simply turning on / off the switching TFT 11d. this is,
This is because the image data is stored in the capacitor 19. That is, the image data is held in each pixel 16 during the period of 1F. Whether or not a current corresponding to the held image data is passed through the EL element 15 is realized by controlling the switching TFT 11d.

Therefore, the number of TFTs 11 forming one pixel does not change between the case where the intermittent display is realized and the case where it is not realized. In other words, the effect of the parasitic capacitance 404 of the source signal line 18 is removed while maintaining the pixel configuration, and a good current program is realized. In addition, a moving image display similar to a CRT is realized.

Since the operating clock of the gate driver 12 is sufficiently slow as compared with the operating clock of the source driver 14, the main clock of the circuit does not become high. Moreover, the value of N can be easily changed.

The image display direction (image writing direction) is shown in FIG.
As shown in FIG. 0, the first field may be from the top of the screen to the bottom (FIG. 50 (a)), and the second field may be from the bottom of the screen to the top (FIG. 50 (b)). . That is, FIG. 50 (a) and FIG. 50 (b) may be alternately repeated.

Further, as shown in FIG. 51, in the first field, the screen is directed from the top to the bottom (see FIG.
(A)), once the entire screen is displayed in black (non-display area) 312 (FIG. 51 (b)), then in the second field, the screen is changed from the bottom to the top (FIG. 51 (c)), Further, the entire screen may be temporarily displayed in black (non-display area) 312 (FIG. 51).
(D)). That is, the states of FIGS. 51 (a) to 51 (d) may be alternately repeated.

50, 51, etc., the method of writing the screen is from top to bottom or bottom to top of the screen, but it is not limited to this. The above matters also apply to other embodiments of the present invention.

In FIG. 49A, the image display area 311 is
N and the non-display area 312 is (N-1) / N (however, this is the case of the ideal state. In reality, the capacitor 19 and the source-gate (S) of the conversion TFT 11a (S).
G) Different because there is a penetration due to capacity). That is,
This is a case where the number of image display areas 311 is one. The image display area 311 moves downward from the top of the screen as shown by the arrow (FIG. 49 (a1) → FIG. 49 (a2) → FIG. 49.
(A3) → FIG. 49 (a1) →). However, the movement of the image display area 311 is not limited to the movement from the top to the bottom of the screen, and the movement from the bottom to the top of the screen may be performed. Also, even if the first frame (first field) is moved (moved) downwards from the top of the screen, the next second frame (second field) is moved upwards from the bottom of the screen. It goes without saying that it is good.
Further, scanning (operation) may be performed from right to left of the screen or from left to right of the screen.

FIG. 48 shows operation timing waveforms. As described above, it is assumed that one screen is displayed in the period of 1F and current programming is performed in the period of 1H. FIG. 48A shows the timing waveform of the gate signal line 17a in FIGS. 6A and 6B. Also, FIG. 48 (b)
Shows a timing waveform of the gate signal line 17b. Basically, when the gate signal line 17b becomes the ON voltage Vgl, the switching TFT 11d becomes conductive (the period is 1F).
/ N), the peak current of the EL element 15 is N of the predetermined current I1.
A double current flows, and the EL element 15 emits light with a brightness (N · B) N times the predetermined brightness B. The switching TFT 11d is turned off during the period of 1F / (N-1) / N. The control of the gate signal line can be easily realized by controlling the two shift registers (22a, 22b) in the gate driver 12 as shown in FIG. Shift register 2
2a holds (scans) the control data of the gate signal line 17a
However, the shift register 22b may hold (scan) the control data of the gate signal line 17b.

FIG. 52 shows the waveform of the gate signal line 17b. FIG. 52A shows the gate signal line 17b of the first pixel row.
52B shows the voltage waveform of the gate signal line 17b of the second pixel row adjacent to the first pixel row. Similarly, FIG. 52C shows the voltage waveform of the gate signal line 17b of the next third pixel row, and FIG. 52D shows the voltage waveform of the gate signal line 17b of the fourth pixel row.

As described above, the gate signal line 1 is provided in each pixel row.
The waveforms of 7b are made the same, and they are applied while being shifted at intervals of 1H. By scanning in this manner, the EL element 1
Since it is possible to shift the pixel rows that are sequentially illuminated while prescribing the time when 5 is illuminated to 1 F / N, it is easy to make the waveform of the gate signal line 17b the same in each pixel row and to shift it. . The shift register 22 of FIG.
This is because it is sufficient to control ST1 and ST2 which are the data applied to a and 22b. For example, if the ON voltage Vgl is output to the gate signal line 17b when the input ST2 is at the L level and the off voltage Vgh is output to the gate signal line 17b when the input ST2 is at the H level, then the gate signal line 1
ST2 applied to 7b is input at the L level only for the period of 1 F / N, and is set to the H level for the other periods. This input S
Only T2 is shifted by the clock CLK2 synchronized with 1H.

Similarly, it is easy to create the waveform of the gate signal line 17a shown in FIG. 48 (a). This is because ST1 which is the input data of the shift register 22a in FIG. 21 may be controlled. For example, when the input ST1 is at L level, the ON voltage Vgl is output to the gate signal line 17a, and the input ST1
When 1 is at H level, the off voltage Vg is applied to the gate signal line 17a.
If h is output, ST1 applied to the gate signal line 17a is input at the L level for a period of 1H, and is set to the H level for the other periods. The input ST1 is simply shifted by the clock CLK1 synchronized with 1H.

In FIG. 49B, the image display area 311 is
(2N), and two image display areas 311a and 311b
Is an example of moving from the top to the bottom of the screen as shown by the arrow (FIG. 49 (b1) → FIG. 49 (b2) → FIG. 49 (b).
3) → FIG. 49 (b1) →). However, the movement of the image display areas 311a and 311b is not limited to the movement from the top to the bottom of the screen, and the movement from the bottom to the top of the screen may be performed. In addition, the first frame (first field) is moved from the top of the screen downward,
It goes without saying that the frame (second field) may be scanned (operated) so as to move from the bottom to the top of the screen. Further, scanning (operation) may be performed from right to left of the screen or from left to right of the screen.

Further, FIG. 49C shows the image display area 31.
1 is set to 1 / (3N), and three image display areas 311a,
This is an example in which 311b and 311c are moved from the top to the bottom of the screen as shown by arrows (FIG. 49 (c1) → FIG. 49).
(C2) → FIG. 49 (c3) → FIG. 49 (c1) →).

As shown in FIGS. 49 (b) and 49 (c), the more the image display area 311 is divided, the more the frame rate of the entire image display (the number of times the screen is written in one second, for example, the frame rate 60). Can reduce the rewriting of the screen 60 times per second). If the frame rate is reduced, the operating clock of the circuit can be reduced accordingly, and the power consumption can be reduced. That is, the light emitting period of the EL element 15 is shortened, the apparent instantaneous luminance is increased, and the image display area 311 and the non-display area 312 are repeated at high speed, so that flicker is reduced. Therefore, the frame rate can be reduced.

By driving as described above, the number of times of lighting in one frame (one field) can be increased and flicker can be reduced. When the EL element is turned on, the frequency component is increased by increasing the number of times it is turned on, which makes it difficult for the human eye to observe. For example, when the lighting period for one time is set to 1/7 and the light is turned on seven times in one frame, display without flicker can be realized even when the frame frequency is 30 Hz.

The brightness of the image can be adjusted (varied) by controlling the on / off of the switching TFT 11d. For example, in the case of FIG. 49A (when there is one image display area 311), the brightness of the display screen 21 changes by changing the area of the non-display area 312 (see FIG. 53A1). 53 (a2) is darker, and FIG. 53 (a3) is darker than FIG. 53 (a2).

Similarly, in the case of FIG. 49 (b) (when there are two image display areas 311), FIG. 53 (b1) to FIG.
53 (b2) is darker than FIG. 53 (b2).
The display brightness of the display screen 21 becomes darker in 3). Also,
The same applies to the case of FIG. 49C (when there are three image display areas 311; that is, three or more) (FIG. 53C2 is darker than FIG. 53C1) and FIG.
(C3) becomes darker).

Note that the image display area 311 scans the display screen 21 in FIG. 49, but the present invention is not limited to this, and as shown in FIGS. 53 (c1) and (c2), one frame ( The entire screen may be set as the non-display area 312 in the first field, and the entire screen may be set as the image display area 311 in the next second frame (2 fields). That is, the entire screen is alternately switched between the image display state and the non-lighting state. However, the image display time and the non-lighting time are not limited to the equal time. For example, the image display time may be 1F / 4 and the non-lighting time may be 3F / 4. in this way,
The display brightness of the image can also be changed (adjusted) by changing the ratio of the image display time and the non-lighting time.

In any case, as shown in FIG. 54, the display brightness B of the image can be linearly changed by changing the value of N. Further, the brightness of the image can be easily changed only by controlling the value of N.

FIG. 55 is a block diagram of a circuit for adjusting (controlling) the display brightness according to the present invention. The frame memory (field memory) 354 stores video data input from the outside. The CPU 353 calculates using the accumulated video data. The calculation is at least one of the maximum brightness, the optimum brightness, the average brightness, and the brightness distribution of the video data.
Use one or more. In addition, the maximum brightness, the optimum brightness, the average brightness, the brightness distribution and the rate of change thereof of each frame of continuous video data are also considered.

The calculation result is stored in the luminance memory 352. The brightness memory 352 is data in which the brightness of the image is corrected. For example, on a bright screen such as a beach, the average brightness of the image is corrected to be bright, and if there is a relatively dark portion in the image data, it is converted to image data that is darker than the actual value. Further, on a screen at night, etc., since the image is entirely dark, a relatively bright part is corrected to be brighter.

The counter circuit 351 is a circuit for counting the N value in FIG. Gate signal line 1
In the waveform of 7b, the N value is changed in real time.
Since the N value is time, it can be easily changed by counting with the counter, and the brightness of the image can be changed.

The switching circuit 355 is the TFT 1 of the pixel 16.
It is a circuit for switching between a voltage Vgl for turning on 1 and a voltage Vgh for turning off (in the case where the pixel TFT 11 is the P channel, and vice versa for the N channel). That is, based on the output of the counter circuit 351, FIG.
The period of 1F / N shown in is changed. Therefore, the brightness of the display screen 21 can be easily changed in real time.

The display brightness is controlled in real time according to the video signal data. By controlling in this way, it is possible to substantially expand the dynamic range of brightness expression to three times or more. In addition, the EL display device is completely in black display (non-lighting) when no current is applied to the EL element, so that black floating in image display does not occur. That is, the contrast is also high. Particularly in the case of current programming, in black display, since the current value programmed in the pixel is as small as 10 nA, the parasitic capacitance 404 cannot be sufficiently charged and discharged, and it is difficult to realize complete black display. Further, the pulse applied to the gate signal line 17 supplies electric power to the source signal line 18 (piercing voltage), and black floating occurs.

The present invention forcibly switches TFT 1
1d is turned off, and the current supply to the EL element 15 is stopped. Therefore, the EL element 15 is completely turned off. Therefore, good contrast can be realized. Further, it is necessary to adjust the output timing of the data applied to the source signal line 18 and the timing of the gate signal lines 17a and 17b. In particular, it is preferable that the output of Vgl (voltage for turning on the TFTs 11b and 11c in FIG. 6) of the gate signal line 17a that selects a pixel row be shorter than 1H. This will be described with reference to FIG.

In FIG. 55, the brightness of the image is changed in real time based on the video data of the video signal, but the invention is not limited to this. For example,
When the user presses the brightness adjustment switch or turns the brightness adjustment volume, this change is detected and the counter value of the counter circuit 351 is changed, and the display screen 21
The brightness (or contrast or dynamic range) of may be changed. Also, the brightness of outside light is detected by a photo sensor, and based on the detected data,
The brightness of the display screen 21 may be changed automatically. In addition, the contents of the image to be displayed and the data can be manually
Alternatively, it may be configured to change automatically.

The brightness is adjusted by the TFT on the EL element 15 side.
This can be achieved by turning on / off the switching TFT 11d in FIG. In this case, the program current (voltage: in the case of the voltage programming method) output from the source driver 14 has a fixed value (the program current is not changed), so that the circuit configuration of the source driver can be simplified. That is, it is not necessary to change the output current (voltage) or the like according to the brightness of the display screen. For example, in the conventional liquid crystal display panel, when displaying 64 gradations,
The 64th gradation of maximum brightness is used. When lowering the brightness by adjusting the brightness than this, for example, up to the 32nd gradation is used. If the circuit is configured in this way, the number of gradations displayed decreases when the screen brightness is dark.

Also, with the method of turning on / off the TFT 11 on the EL element 15 side (intermittingly displaying the current flowing through the EL element 15), the brightness can be freely adjusted by adjusting the off period. At that time, the brightness adjustment according to the present invention can be maintained even in the gamma adjustment and the linearity brightness change. The power supply voltage Vdd also has a fixed value, which is advantageous in terms of configuration.

By controlling the on / off state of the switching TFT 11d from the top to the bottom of the screen, the brightness of the screen can be easily Gaussian distributed. It requires almost no arithmetic function to control. This method will be described later.

The period for turning on / off the EL element 15 must be 0.5 msec or more. When this cycle is short, the image is not completely displayed in black due to the afterimage characteristic of human eyes, and the image becomes blurry and the resolution is lowered. Alternatively, the display state of the data holding type display panel is set. However, the on / off cycle is 100 ms
If it is ec or more, it looks like a blinking state. Therefore, E
ON / OFF cycle of L element is 0.5 msec or more and 100 ms
ec or less, more preferably 2 msec or more and 30 msec or less. More preferably, the on / off cycle is 3 m
It should be no less than sec and no more than 20 msec.

The number of divisions of the black screen (non-display area) 312 is
Although a good moving image display can be realized with only one, it is preferable to divide the black insertion portion into a plurality of pieces because the flicker on the screen is easily visible. However, if the number of divisions is too large, blurring of moving images occurs, so the number of divisions should be 1 or more and 8 or less. Furthermore, it is preferable to set it to 1 or more and 5 or less.

Note that it is preferable that the number of divisions of the black screen can be changed between the still image and the moving image. What is the number of divisions?
When N = 4, 75% is a black screen and 25% is an image display. At this time, the number of divisions 1 is to scan 75% of the black display portion in the vertical direction of the screen with the black band state of 75%. 7
The number of divisions is 3 when scanning is performed with 3 blocks of a 5% black screen and a 25/3% display screen. Increase the number of divisions for still images and decrease the number of divisions for moving images. The switching may be performed automatically (moving image detection or the like) according to the input image, or may be performed manually by the user. In addition, the video of the display device or the like may be switched so as to correspond to the input outlet.

For example, in a mobile phone or the like, the number of divisions is set to 10 or more in the wallpaper display and input screen (extremely, it may be turned on and off every 1H). When displaying an NTSC video, the number of divisions should be 1 or more and 5 or less. It is preferable that the number of divisions can be switched in multiple stages of 3 or more. For example, it is 2, 4, 8 or the like without the number of divisions.

The ratio of the black screen to the entire display screen is 0.2 or more and 0.9 or less (1.2 or more and 9 or less when displayed by N) when the area of the entire screen is 1. In particular, it is preferably 0.25 or more and 0.6 or less (1.25 or more and 6 or less when expressed by N). Because 0.20
This is because the effect of improving the moving image display is low when it is below.
Further, when it is 0.9 or more, the brightness of the display portion increases, and it is easy to visually recognize that the display portion moves up and down.

The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less), more preferably 12 or more and 65 or less (12 Hz or more and 65 Hz or less). This is because if the number of frames is small, the flickering of the screen becomes conspicuous, and if the number of frames is too large, writing from the source driver 14 or the like becomes difficult and the resolution deteriorates.

In any case, as described above with reference to FIGS. 48 and 55, in the present invention, the gate signal line 17 is used.
Control may be performed, or the current (voltage) applied to the source signal line 18 may be changed, or both may be combined.

Needless to say, the above items can be applied to the pixel configuration of the voltage program shown in FIGS. 85 and 87. For example, in FIG. 85, the TFT 11e may be on / off controlled.

As shown in FIG. 56, the time at which the ON voltage Vgl is set to 1F / N of the gate signal line 17b is 1F (not limited to 1F and may be a unit period), as shown in FIG. Any time will do. This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period of the unit period. However,
When the EL element 15 is caused to emit light immediately after the programming period (1H) in FIG. 56A and the gate signal line 17b is set to the on-voltage Vgl, the holding ratio characteristic of the capacitor 19 in FIG. Good. Further, during the 1F / N period, the position may be changed as indicated by the symbols A and B and the arrow in FIG. 56 (b). Figure 21
This change can be easily realized if the timing of data to be applied to ST in (1) (when L level is set in 1F) can be adjusted or varied.

Further, as shown in FIG. 57, the period (1 F / N) in which the gate signal line 17b is kept at the ON voltage Vgl may be divided into a plurality of portions (the number of divisions K). That is, the period of 1F / (K / N) is performed K times during the period of time for turning on the voltage Vgl. By controlling in this way, the image display state is as shown in FIG.
(B) (K = 2) and FIG. 49 (c) (K = 3). In this way, by dividing the image portion (image display area 311) to be turned on into a plurality of portions, the occurrence of flicker can be suppressed,
Image display at a low frame rate can be realized. Further, it is preferable that the number of divisions of this image be variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume to detect this change and change the K value, the contents of the image to be displayed and the data can be manually changed. Alternatively, it may be configured to change automatically.

As described above, if the timing of the data applied to ST in FIG. 21 (when the L level is set at 1F) can be adjusted or varied,
The value of K (the number of divisions of the image display area 311) can be easily changed.

In FIG. 57, the period (1F / N) for setting the gate signal line 17b to the ON voltage Vgl is divided into a plurality of (division number K), and the period for setting the ON voltage Vgl is 1F / N.
Although the (K / N) period is performed K times, it is not limited to this. 1F / (K / N) period is L (L ≠ K)
You may carry out once. That is, according to the present invention, the display screen 21 is displayed by controlling the period (time) of flowing through the EL element 15, so that the period of 1F / (K / N) is L.
Carrying out (L ≠ K) times is included in the technical idea of the present invention. Further, by changing the value of L, the brightness of the display screen 21 can be changed digitally. For example, with L = 2 and L = 3, 50% brightness (contrast)
Make a change. These controls are also shown in FIGS. 21, 55, 66,
This can be easily realized with the circuit configuration shown in FIG.

When the image display area 311 is divided,
The period in which the gate signal line 17b is kept at the on-voltage Vgl is not limited to the same period. For example, as shown in FIG. 58, the period during which the on-voltage Vgl is set may be a plurality of periods such as t1 and t2.

In FIG. 48, the adjacent pixel rows are illustrated as being sequentially turned on (displayed), but the present invention is not limited to this. As shown in FIG. 59, interlaced scanning may be performed. This interlaced scanning means that an image is written in odd pixel rows in the first field (see FIG. 49).
(A) Write pixel row 391), and in the second field, an image is written in an even pixel row (FIG. 48 (b) write pixel row 391). The pixel row that is not written holds the image data of the previous field (held pixel row 392). In this way, flicker can be reduced by performing interlaced scanning with the EL display device.

According to the driving method of FIG. 59, the gate signal lines 17b of all (or a plurality of) even pixel rows can be shared, and the gate signal lines 17b of all (or a plurality of) odd pixel rows can be shared. Can share. Therefore, the number of wirings of the gate signal line 17 can be significantly reduced. In the case where the entire screen is alternately displayed with the image display area 311 and the non-display area 312, all gate signal lines 17b
Can share. These configurations are particularly effective in a configuration with three sides free as shown in FIG.

In the interlaced scanning, the image is written in the odd pixel row in the first field and the image is written in the even pixel row in the next second field, but the invention is not limited to this. For example, in the first field, an image is written every two pixel rows by skipping two pixel rows, and in the next second field, an image is not written in the first field.
An image may be written for each pixel row. Further, it may be three pixel rows or four pixel rows. Further, in the first field, an image may be written every two pixel rows from the second row of the screen (see FIG. 60A), and in the next second field, an image may be written every two pixel rows from the first row (see FIG. 60A). Fig. 60
(See (b)). Further, as shown in FIG. 60, the writing pixel row or the writing pixel row may be controlled to be the non-display area 312. Further, in the first field, the image may be written from the top to the bottom of the screen, and in the second field, the image may be written from the bottom to the top of the screen. These are all included in the concept of interlaced scanning.

Interlaced scanning can also be easily realized by implementing the method described with reference to FIGS. 48 and 52. The pixel row corresponding to the non-display area 312 which is not turned on is shown in FIG.
This is because the switching TFT 11d shown in FIG.

Further, it goes without saying that the non-display area 312 and the interlaced scanning can be combined as shown in FIG. In FIG. 61A, the scanning region 50 including the writing pixel row 391 and the holding pixel row 392.
1 is sequentially shifted. In FIG. 61A, the image is written from the first line. Similarly in FIG. 61B, the scanning region 501 including the writing pixel row 391 and the holding pixel row 392 is sequentially shifted. Note that FIG.
In (b), the image is written from the second line.

The above embodiments have mainly described the configuration of the pixel 16 in FIG. However, the present invention is not limited to this. For example, the pixel 16 of FIG. 19 or 20.
But you can do it.

In the pixel configuration of FIG. 19, the gate signal line 17
By applying the on-voltage Vgl to a, the current value applied to the source signal line 18 in the capacitor 19 is programmed. As shown in FIG. 62, the data corresponding to the video signal is applied to the source signal line 18 from the power source switching means 403 in the source driver 14. As for the programmed current, when the current mirror efficiency is 1, the current flows into the driving TFT 11b, and this current is applied to the EL element 15. This relationship (timing waveform, etc.) is shown in FIG.
The items illustrated in FIG. 2 can be used or similar, and thus need not be described. However, when performing the current program, the acquisition TFT 11c and the switching TFT 11d
It may be necessary to individually control the on or off timing of the. In this case, the capturing TFT 11c
The gate terminal for turning on and off the switching TFT 11d must be another gate signal line 17.

In order to carry out the display method shown in FIG. 49 or the like, it is necessary to cut off the current flowing through the EL element 15. For the purpose of blocking this, as shown in FIG.
1e is added. A current is applied to the EL element 15 by setting the gate terminal of the TFT 11e to the ON voltage Vgl, and a current to the EL element 15 is cut off (non-lighting state) by setting the gate terminal of the TFT 11e to the OFF voltage Vgh.

Therefore, by applying the signal waveforms of the gate signal lines 17a and 17b described in FIG. 48 and the like, the image display described in FIG. 49 and the like can be realized.

As shown in FIG. 63, the image display area 311 and the non-display area 312 may switch between odd pixel rows and even pixel rows for each frame (field). Figure 6
If the odd pixel rows are displayed and the even pixel rows are hidden in 3 (a), the odd pixel rows are hidden and the even pixel rows are hidden in the next frame (field) (see FIG. 63 (b)). indicate.

As described above, if the non-display area and the display area are repeated for each pixel row, the occurrence of flicker can be significantly suppressed.

In FIG. 63, the non-display pixel row and the display pixel row are set for each one pixel row, but the present invention is not limited to this, and the non-display pixel row may be set for every two or more pixel rows. Rows and display pixel rows may be used.

For example, if every 2 rows, in the first field (frame), the 1st pixel row and the 2nd pixel row are the display pixel rows, and the 3rd pixel row and the 4th pixel row are the non-display pixel rows. Then, the 5th pixel row and the 6th pixel row become display pixel rows. In the next second field (frame), if the first pixel row and the second pixel row are non-display pixel rows and the third pixel row and the fourth pixel row are display pixel rows, the fifth pixel row and the sixth pixel row The eyes are non-display pixel rows. Also, the next third field (frame)
Then, similar to the first field, if the first pixel row and the second pixel row are the display pixel rows and the third pixel row and the fourth pixel row are the non-display pixel rows, the fifth pixel row and the sixth pixel row are It becomes a display pixel row.

In this specification, the terms field and frame are used synonymously or separated. Generally, in the interlaced driving of NTSC, one frame is composed of two fields. However, in progressive driving, one frame is one field. As described above, fields and frames are used differently in the world of video signals, but the image displayed on the display panel according to the present invention may be either progressive or interlaced. Therefore, it is said that either one is acceptable. Conceptually, in a field or a frame, it is a unit of time to finish writing a series of screens.

The display method of FIG. 64 is also effective. For ease of explanation, FIG. 64 (a) is the first field (first frame), FIG. 64 (b) is the second field (second frame), and FIG. 64 (c) is the third field (first frame). 3 frame) and FIG. 64 (d) as the fourth field (fourth frame).

In the first field (frame), the first pixel row and the second pixel row are set as non-display pixel rows, and the third pixel row and the fourth pixel row are set.
The pixel row is the display pixel row, and the fifth pixel row and the sixth pixel row are the display pixel rows. In the second field (frame), the odd pixel rows are the display pixel rows and the even pixel rows are the non-display pixel rows. In the third field (frame), the first pixel row and the second pixel row are the display pixel rows, and the third pixel row and the fourth pixel row are the non-display pixel rows. In the fourth field (frame), the odd pixel rows are non-display pixel rows and the even pixel rows are display pixel rows. After that, the first field (first
Repeat from the display state of (frame).

In the driving method of FIG. 64, one loop is made up of 4 fields (frames). In this way, by displaying images in multiple fields (multiple frames),
Occurrence of flicker is often suppressed more than in FIG.

In the embodiment of FIG. 64, in the first field (frame), non-display pixel rows are set every two pixel rows, and in the second field (frame), every one pixel row is set as non-display pixel rows. However, it is not limited to this.
Further, in the first field (frame), non-display pixel rows are arranged in every fourth pixel row, in the second field (frame), each non-display pixel row is arranged in every second pixel row, and one pixel is formed in the third field (frame). Each row is a non-display pixel row,
In the 4th field (frame), the non-display pixel rows are set every 4 pixel rows, in the 5th field (frame), the non-display pixel rows are set every 2 pixel rows, and the 1st pixel row is set in the 6th field (frame). Each may be a non-display pixel row.

The driving method of the present invention can easily realize a display effect (animation effect, etc.). Figure 65
The display area is as shown in FIG. 65 (a) → FIG. 65 (b) → FIG.
It is a display method that appears in sequence from (c) to FIG. 65 (d). An animation effect can be realized by slowly scrolling the non-display area 312. These controls can be easily realized with the circuit configurations shown in FIGS. 21, 66, 67, and the like. This does not write the black display state as an image,
An animation effect is easily realized by controlling the gate signal line 17b and the like.

[0416] A display panel such as a liquid crystal display panel which holds data for one field (one frame) period in a pixel has a problem that a moving image blur occurs. However, since the CRT or the like is only displayed for a moment by the electron gun, the problem of moving image blur does not occur.

Black insertion is an effective means for solving this problem. The present invention can easily realize a black insertion method close to that of a CRT, which is excellent in displaying moving images.

FIG. 68 shows that the letter F moves from the top to the bottom of the screen. As shown in FIG. 68, a non-display state (FIGS. 68 (b), (d), (f)) is inserted between image displays (FIGS. 68 (a), (c), (e)). There is. Therefore, the image is displayed in a scattered manner. Therefore, moving image blurring does not occur and good moving image display can be realized.

As described above, to make the entire screen a non-display area, the circuit configuration shown in FIG. 66 may be adopted. The difference from FIG. 21 is that an ENBL terminal 601 is provided. ENBL
The terminal 601 is the OR circuit 6 in which the gate signal line 17 is formed.
02 is connected to one terminal. By setting the ENBL terminal to the L level, the Vgh level is output to all the gate signal lines 17b, the switching TFT 11d or the TFT 11e for supplying the current to the EL element 15 is turned off, and the entire screen becomes the non-display area 312. Become. Further, when the ENBL terminal is at H level, normal operation is performed.

Note that, in FIGS. 21, 66, 67, and 69, the data input to the ST terminal is sequentially shifted by the clock (serial operation), but the present invention is not limited to this. . For example, a parallel input that determines the on / off state of each gate signal line at a time may be used (a configuration in which the on / off logic of all gate signal lines is output and determined at one time for the number of controllers or gate signal lines 17). Such).

In the embodiment shown in FIG. 68, a moving image is displayed.
It is also easy to implement an animation effect such as flashing for each R, G, B (see FIG. 70). Figure 7
70A is an image of the red display 311R,
70 (c) is an image of green display 311G, FIG. 70 (e).
Is an image of blue display 311B. FIG. 70 (a),
A non-display state (Fig. 70) between each image of (c) and (e).
(B), (d), (f)) are inserted. If this operation is slowly performed from the operation shown in FIGS. 70A to 70F, the R, G, and B images can be displayed as if they are flashing.

Further, as shown in FIG. 71, it is easy to implement an animation effect such as flashing for each different image. In FIG. 71, FIG. 71 (a) shows the first
Image 311a, FIG. 71 (c) is the second image 311b, FIG.
1 (e) is the third image 311c. 71 (a),
The non-display state (FIGS. 71 (b), (d), and (f)) is inserted between the images in (c) and (e). FIG. 71
By slowly performing the operation from (a) to FIG. 71 (f), it is possible to display the first, second, and third images as if they were flashing.

In the above embodiment, conceptually, a current N times the predetermined value of the source signal line 18 is made to flow, and the EL element 15
Is a method (configuration) in which N times the current is passed for a period of 1 / N to obtain a desired brightness. This method (configuration) solved the problem of insufficient writing due to the presence of the parasitic capacitance 404.

Note that the N-fold driving method improves the luminous efficiency as compared with the 1-fold driving method (conventional driving method). This is the influence of the punch-through voltage of the driving TFT 11b (on the side of the capacitor 19) in FIG. 6, and the N-fold increase can reduce the influence of the punch-through voltage. It is suitable that the N multiple is 1.5 times or more and 8 times or less. If it is more than this, the luminous efficiency of the EL element is lowered, and the efficiency as a whole is also lowered. Therefore, the N multiple is preferably 2 times or more and 6 times or less. Here, multiplying by N means
That is, the light emitting period is set to 1 / N. Therefore, if the N multiple is set to 2 times or more and 6 times or less, it means that the light emission period is set to 1/2 or more and 1/6 or less (at normal brightness).

The present invention is based on the switching TFT 11
After turning off d and cutting off the current to the EL element 15, by turning on the switching TFT 11d again, a current can be passed through the EL element 15 in the same manner as before. The present invention successfully applies this principle to pass a current in a period of 1 / N to obtain a predetermined brightness. What can be driven in this way is that the value of the current to be passed is the capacitor 1 for each pixel 16.
This is because it is held at 9. That is, the present invention
It can be said that the pixel configuration peculiar to the EL display panel is successfully applied while holding the current value flowing through the L element 15.

(Ninth Embodiment) The configuration of FIG. 72 has a driving TF having a driving capacity N-1 times that of the driving TFT 11a.
This is a method of solving the problem of insufficient writing due to the presence of the parasitic capacitance 404 by forming T11an.

The difference between FIG. 72 and FIG. 6A is that the driving T
In addition to FT11a, N-1 times as many driving TFT11an-
1 and the switching TFT 11f are added.
The difference between FIG. 6 and FIG. 72 will be mainly described. Driving TFT
The reason for using 11an-1 is that the currents of the driving TFT 11an-1 and the driving TFT 11a are multiplied by N when added. That is, the driving TFT 11
This means that the channel width W2 of an-1 is N-1 times the channel width W1 of the driving TFT 11a. For example, if N = 10 and the channel width W1 of the driving TFT 11a is 1, the driving TFT 11an
The channel width W2 of -1 is 9 times. Therefore, theoretically, if the driving TFT 11a allows a current of 1 to flow, the driving TFT 11an-1 has the ability to flow a current 9 times higher.

In FIG. 72, the driving TFT 11an-1 is used.
The drive current of N-1 is N-1 in the configuration of FIG.
This is because, when a double current is passed through the source signal line 18, a current that is one time that of the driving TFT 11 a that passes a current through the EL element 15 is added. In the configuration of FIG. 73, the current of the driving TFT 11b that causes a current to flow in the EL element 15 does not flow in the source signal line 18, so the driving current of the TFT 11n needs to be N times.

For ease of explanation, the driving TF is
T11a is assumed to flow a current of I1, and the driving TFT 11
If an-1 flows the current of In-1, I1 + In
An expression of −1 = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15) is established.

In the current program period, the gate signal line 17
a is applied to the on-voltage Vgl, the driving TFT 11b,
The switching TFT 11f and the capturing TFT 11c are turned on. Further, the off voltage Vgh is applied to the gate signal line 17b, and the switching TFT 11d is turned off. Therefore, the voltage corresponding to the program current Iw is programmed in the capacitor 19. That is,
I1 + In-1 = Iw (In this case, Iw is the EL element 15
A current that is N times the current I1 flowing through the source signal line 18 flows into the source signal line 18.

Next, in a period in which a current is passed through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the driving TFT 11b, the switching TFT 11f, and the fetch TFT 11c are turned off. Therefore, the source signal line 18 and the pixel 16 are separated. Further, the ON voltage Vgl is applied to the gate signal line 17b, and the switching TFT 11d is turned on. Therefore, the current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.

By driving as described above, the source signal line 18 can be supplied with a current N times as large as the desired value of the current (current flowing through the EL element). Therefore, the influence of the parasitic capacitance 404 is excluded, and the current can be sufficiently programmed in the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.

In FIG. 72, the driving TFT 11an-1 having a current capacity of N-1 is formed in one pixel, but the invention is not limited to this. As shown in FIG. 74, a plurality of TFTs (TFT 11n1 to TFT 11n in FIG.
6) may be produced. The operation is similar to that of FIG.

The configuration of FIG. 72 can also be developed in the current mirror system shown in FIG. As shown in FIG. 73, a TFT having N times the driving capability
11n may be formed. However, the current mirror configuration does not require the switching TFT 11f.

In FIG. 73, the ratio between the channel width W2 of the TFT 11n and the channel width W1 of the driving TFT 11b is N: 1. Here, in order to facilitate the explanation, it is assumed that the driving TFT 11b passes a current I1.
FT11n is supposed to flow an In current, In = Iw
(In this case, Iw is N times the current I1 flowing through the EL element 15).

In the current program period, the gate signal line 17
The on-voltage Vgl is applied to a, and the capturing TFT 11c,
The switching TFT 11d is turned on. Therefore, the voltage corresponding to the program current Iw is programmed in the capacitor 19. That is, In = Iw (in this case, Iw is N times the current I1 flowing through the EL element 15)
Current flows through the source signal line 18. In addition, T for import
It is preferable to control the on / off state of the FT 11c and the switching TFT 11d by slightly shifting the timing. In this case, it is necessary to separate the gate signal line for controlling the take-in TFT 11c and the gate signal line for controlling the switching TFT 11d, and perform independent control.

Next, in the period in which a current flows through the EL element 15, the off voltage Vgh is applied to the gate signal line 17a, and the take-in TFT 11c and the switching TFT 11d are turned off. Therefore, the source signal line 18 and the pixel 16 are separated, and the current I1 corresponding to 1 / N of the program current Iw flows through the EL element 15.

By driving as described above, the source signal line 18 can be supplied with N times as much current as the desired value (current flowing through the EL element). Therefore, the parasitic capacitance 40
The effect of 4 is eliminated, and the current can be sufficiently programmed in the capacitor 19. On the other hand, a desired value of current can be applied to the EL element 15.

It should be noted that the gate signal line 17b and the TFT 11e
As described with reference to FIG. 62, is provided for controlling the non-image display as shown in FIG. 25 or the like so that a current flows through the EL element 15 only for the 1 / N period. Therefore, FIG.
In this configuration, an EL element 1 is supplied with a current N times larger.
By pulse-driving the current flowing in 5 for the 1 / N period, the problem of insufficient writing due to the parasitic capacitance 404 is completely eliminated. Further, black insertion display can be easily realized, and good moving image display can be realized.

The configuration shown in FIG. 73 is very effective.
For example, in order to realize N = 10 with only the configuration of FIG. 6, it is necessary to apply a pulsed current 10 times higher than a desired value to the EL element 15. In this case, the EL element 15
Therefore, the Vdd voltage needs to be designed high, and the EL element 15 may deteriorate.

However, in the configuration of FIG. 73, the TFT 11n
The channel width W2 of 5 times that of the driving TFT 11b,
Since programming is performed with a current twice as high as 5 × 2 = 10, it can be realized by applying a double current to the EL element 15 for only a half period. Therefore, the problem of deterioration of the EL element 15 is eliminated, and it is not necessary to increase the Vdd voltage.

On the contrary, in order to realize N = 10 only by the TFT 11n, in the configuration of FIG. 73, the channel width W2 of the TFT 11n needs to be 10 times as large as that of the driving TFT 11b. When it is multiplied by 10, the formation area of the TFT 11n becomes
It occupies most of the pixel area. Therefore, the pixel aperture ratio becomes extremely small or unrealizable. However, in the configuration of FIG. 73, it is sufficient to set the channel width W2 of the TFT 11n to 5 times that of the driving TFT 11b, so that a sufficient pixel aperture ratio can be realized.

There are many ways to realize N = 10. For example, the channel width W2 of the TFT 11n is set to the driving TFT 1
2 times as much as 1b and 5 times higher current to EL element 15 as 1/5
And the channel width W of the TFT 11n
2 is 4 times that of the driving TFT 11b, and a current 2.5 times higher is applied to the EL element 15 for a period of 1 / 2.5. In other words, the design of the TFT 11n (channel width W
The multiplication should be 10 in consideration of 2), the current flowing through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.

It should be noted that in FIG. 73, TF having the current capacity of N is used.
Although it has been stated that the T11n is formed in one pixel, it is not limited to this. As shown in FIG. 75, a plurality of TFTs
(TFT 11n1 to TFT 11n5 in FIG. 75) may be manufactured. The operation is similar to that of FIG.

The fact that there are many ways to realize N = 10 also applies to the configuration of FIG. Driving TFT 11an-1
The channel width W2 of 4 times that of the driving TFT 11a,
A method of applying a current twice as high as that to the EL element 15 for a half period, or making the channel width W2 of the driving TFT 11an-1 twice as large as that of the driving TFT 11a, and making the EL element 15 one-fifth the current 5 times higher. It is a method of applying for a period of time. That is, the design of the driving TFT 11an-1 (channel width W
The multiplication should be 10 in consideration of 2), the current flowing through the EL element 15 and the period thereof. Thus, the value of N can be designed freely.

The matters explained above are shown in FIG. 72, FIG.
Obviously, the same can be applied to FIGS. 76 to 78. That is, according to the present invention, the driving TF having a large channel width is used.
T is formed in each pixel to increase the current that drives the source signal line 18. Moreover, as described in FIG.
In addition to increasing the current flowing through the element 15, the EL element 15
It is a method or a configuration in which the current flowing through the device is set for a predetermined period.

By controlling the on / off state of the switching TFT 11d or TFT 11e, the switching of FIG.
5, the display described in FIG. 49 and the like can be realized. With this display, the moving image display can be improved and the brightness can be adjusted. Therefore, in the present invention, a current N times or a current proportional to N is applied to the EL element 15, but the present invention is not limited to this. The EL element 15 may be configured to flow a current of a predetermined value or less. Even in this case, it is possible to improve the display of the moving image and to easily adjust the brightness.

Similarly to FIGS. 6 and 72, when the switching TFT 11d is turned on, it is possible to suppress the characteristic variation due to the kink phenomenon of the driving TFT 11a by increasing the resistance value. This has been described with the configuration of FIG. The TFT 11e shown in FIG. 6B is arranged, and the Vbb voltage (Vgl <Vgl <
By applying Vbb <Vgh), a driving TFT
The variation of the current flowing through 11a is reduced.

Therefore, also in the pixel configurations of FIGS. 6 and 72, it is preferable to apply the Vbb voltage to the gate signal line 17b to turn on the switching TFT 11d. That is, the OFF voltage Vgh is applied to the switching TFT 11d in the OFF state, and the Vbb voltage is applied in the ON state.

This control is easy if the circuit configuration is as shown in FIG. The inverter at the output stage of the shift register 22b can apply the off voltage Vgh to the gate signal line 17b in the off state and the Vbb voltage to the gate signal line 17b in the on state if the off voltage Vgh and the Vbb voltage are used as the power source. Is.

The on / off control of the gate signal line 17 is based on the data held by the shift register 22, but the invention is not limited to this.
A method of independently controlling each gate signal line 17 without providing 2 may be adopted. For example, any gate signal line 17 that outputs the ON voltage may be selected by the multiplexer circuit. Further, all gate signal lines may be drawn out in parallel, and an ON voltage or an OFF voltage may be freely applied to each gate signal line. As described above, by arranging such that the arbitrary gate signal line 17 can be selected regardless of the data held in the shift register 22, FIG.
9, FIG. 53, FIG. 45, FIG. 46, FIG. 210, FIG. 213, FIG. 218, FIG. 221, FIG. 223, FIG.

Similar to FIG. 6B, a TFT 11e for applying a Vbb voltage may be separately formed or arranged as shown in FIG. The same applies to the current mirror configuration. For example, as shown in FIGS. 79 and 80, a switching TFT 1 that applies a Vbb voltage
If may be formed or arranged separately. The same applies to the pixel configuration in FIG. 70.

In FIG. 82, the driving TFT 1
By separating 1a into the TFT 11a1 and the TFT 11a2 and connecting the gate terminals in cascade, it is possible to suppress the kink phenomenon and also suppress variations in characteristics. This is because the driving TFT 11a in FIG. 6 and the driving TFT in FIG.
11b, the driving TFT 11a in FIG. 72, the driving TFT 11b in FIG. 73, and the like (driving TFT
It is preferable to adopt it as a configuration of).

In FIGS. 74 and 75, the TFT 11n
Was divided into multiple, but as another configuration,
The TFTs 11n1 and TF divided as shown in FIG.
The potential (Vgh or Vg applied to the gate signal line 17c) as to whether or not the T11n2 is operated to improve the drive current.
It may be controlled by l). When the TFT 11f2 is turned off, the current flowing through the source signal line 18 becomes the TFT 11n.
1, which is half that in the case where the TFT 11n2 is operating. These controls may be determined from the viewpoint of image display data of the display panel and power consumption.

The difference between FIGS. 76 and 77 is that the gate terminal of the switching TFT 11f is connected to the gate signal line 17c. That is, the on / off state of the switching TFT 11f is not affected by the potential state of the gate signal line 17a, and independent control can be realized. When the switching TFT 11f is constantly off, the TFT 11
n is a state of being separated from the pixel, and has the pixel configuration of FIG. Gate signal line 17c and gate signal line 17
If a and a are logically short-circuited and used, the configuration shown in FIG. 76 is obtained.

The problem of FIG. 76 here is that the TFT 11n
When the characteristic deviation such as the threshold Vt of the driving TFT 11a occurs in each pixel, the current flowing through the EL element 15 varies from pixel to pixel. If the currents vary, the displayed image will appear grainy even in a uniform display such as white raster. In that respect, this problem does not occur in the configuration of FIG.

Therefore, when the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the off state. Further, when the screen size of the display panel is large and the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a to realize the pixel configuration of FIG. It is good to drive by doing.

FIG. 69 shows a circuit block for driving the pixel configuration of FIG. A shift register 22c that drives the gate signal line 17c is formed, and the gate signal line 17c is driven. When driving with the pixel configuration of FIG. 6, the data of ST3 is constantly set to L and the gate signal line 17c is constantly set to Vgh.
It is controlled so that the off voltage of is output. When used in the configuration of FIG. 77, the data input states (timing, logic, etc.) of the shift registers 22c and 22a may be the same.

The structure of FIG. 77 can also be realized by the structure of a current mirror. FIG. 78 shows the pixel configuration. Figure 7
As shown in FIG. 8, the divided driving TFTs 11a, T
The potential (Vgh or Vg applied to the gate signal line 17c) as to whether or not the FT 11n is operated to improve the drive current.
It may be controlled by l). When the switching TFT 11f is turned off, only the driving TFT 11a operates due to the current flowing through the source signal line 18.

Therefore, similar to the pixel configuration of FIG. 77,
When the screen size of the display panel is small and the influence of the parasitic capacitance 404 is small, the switching TFT 11f is constantly used in the off state. The screen size of the display panel is large,
When the influence of the parasitic capacitance 404 cannot be eliminated only by the operation of the driving TFT 11a, the gate signal line 17c is short-circuited with the logic of the gate signal line 17a, and the driving current is increased to drive. Thus, the circuit block of FIG. 69 can be applied to the pixel configuration of FIG. 78 as well.

In the structure of FIG. 69, the gate signal line 17
A shift register 22c for controlling c was newly formed and operated. However, the configuration is not limited to this. Vgl is applied to the gate terminal of the switching TFT 11f.
Alternatively, since only the Vgh voltage is applied, the control logic of the gate signal line 17c is easy. TFT 11n
When not operating, the off voltage Vgh may be applied to the gate terminals of all the switching TFTs 11f in the display screen 21. When operating the TFT 11n, the potential of the gate signal line 17a may be applied to the gate signal line 17c. Therefore, as shown in FIG. 69, the shift register 2 is separately provided.
It is not necessary to use 2c. That is, the shift register 2
The data of 2a is output to the gate signal line 17c as it is, or the potential of all the gate signal lines 17c is the off voltage Vg.
This is because it is only necessary to add a gate circuit so that it becomes h.

(Embodiment 10) A driving method of the present invention will be described below. By multiplying the current flowing through the source signal line 18 by N times, the influence of the parasitic capacitance 404 is eliminated, and good image display with high resolution can be realized. Figure 45
FIG. 9 is an explanatory diagram of another embodiment for increasing the current flowing through the source signal line. The driving method of the present invention in FIG. 45 is
Basically, this is a method in which a plurality of pixel rows are selected at the same time, and the parasitic capacitance of the source signal line is charged / discharged by a current combined with the plurality of pixel rows, thereby significantly reducing the insufficient current writing. According to this driving method, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced and the current flowing through the EL element 15 can also be reduced. Here, in order to facilitate the description, N = 10 will be described as an example (the current flowing through the source signal line is multiplied by 10).

In the present invention described with reference to FIG. 45 and the like, K pixel rows are simultaneously selected as pixel rows. Source driver IC
Then, N times the predetermined current is applied to the source signal line 18. A current that is N / K times the current flowing through the EL element is programmed in each pixel. In order to make the EL element have a predetermined emission brightness, the time flowing through the EL element is set to K / N time for one frame. By driving in this way, the source signal line 1
The parasitic capacitance of No. 8 can be sufficiently charged and discharged, and good resolution and a predetermined light emission brightness can be obtained.

That is, the current is passed through the EL element only during the K / N period of one frame, and the other period (1F (N-1)).
K / N) means that no current flows. In this display state, image data display and black display (non-lighting) every 1F
Is repeatedly displayed, and the image data display is in a temporally intermittent display (intermittent display) state. Therefore, the outline of the image is not blurred and a good moving image can be displayed. Also,
Since the source signal line 18 is driven by a current of N times, it is not affected by parasitic capacitance and can be applied to a high-definition display panel.

First, in order to facilitate understanding, a method of selecting one pixel row and programming an N-fold current as described above will be described with reference to drive waveforms and the like. FIG. 84 is an explanatory diagram thereof. Although the screen is illustrated as being horizontally long in FIG. 84, it is not limited to this and may be vertically long or may have another shape such as a circle.

FIG. 84 (a) shows the state of writing on the display screen 21. In FIG. 84 (a), 871 is a writing pixel row. Note that in FIG. 84A, the number of pixel rows written in the 1H period is one. Further, in the following embodiments, the pixel configuration of FIG. 6 will be described as an example, but the present invention is not limited to this, and a pixel configuration of a current mirror such as FIG. 19 may be used. Also, FIG. 85, FIG. 86, and FIG.
It goes without saying that the present invention can also be applied to the pixel configuration of the voltage program system such as.

In FIG. 84 (a), the gate signal line 17
When a is selected, the current flowing through the source signal line 18 is programmed in the conversion TFT 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows in the EL element 15. This is because when the switching TFT 11d on the EL element 15 side is in the ON state, the source signal line 1
This is because the capacitance component of the EL element 15 is visible from 8 and the capacitance 19 is affected by this capacitance, making it impossible to perform sufficiently accurate current programming in the capacitor 19. Therefore, as shown in FIG. 84B, the pixel row in which the current is written becomes the non-display area 312. Switching TFT1 for other pixel rows
Since 1d is in the ON state, the image display area 311
Becomes Note that in the pixel configuration of the current mirror shown in FIG. 19 and the like, even if a current flows through the conversion TFT 11a that performs current programming, the E signal is emitted from the source signal line 18.
The L element 15 cannot be seen. Therefore, it is not necessary to set the non-lighting state as in FIG. 84 (b). That is, FIG.
It is not an essential condition of the invention to set the writing pixel row to the non-display area 312 as in (b).

FIG. 88 shows a voltage waveform applied to the gate signal line 17. The voltage waveform shows the off voltage as Vgh (H level)
And the on-voltage is Vgl (L level). Figure 8
The lower row of 8 shows the number of the selected pixel row. Further, (1) and (2) in the figure represent the pixel row numbers selected.

In FIG. 88, the gate signal line 17a
When (1) is selected (Vgl voltage), a program current flows from the conversion TFT 11a of the selected pixel row to the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N
= 10 will be described. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Therefore, the capacitor 19 is programmed so that a 10 times larger current flows through the conversion TFT 11a. When the pixel row (1) is selected, the gate signal line 17b in the pixel configuration of FIG.
The off voltage Vgh is applied to (1), and no current flows through the EL element 15.

After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and the conversion T of the selected pixel row is performed.
A program current flows from the FT 11a to the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N = 10 will be described). Therefore, the capacitor 19 is programmed so that a 10 times larger current flows through the conversion TFT 11a. When the pixel row (2) is selected,
In the pixel configuration of FIG. 6, the off voltage Vgh is applied to the gate signal line 17b (2), and no current flows in the EL element 15. However, the gate signal line 17a of the previous pixel row (1)
The off voltage Vgh is applied to (1), and the gate signal line 1
Since the on-voltage Vgl is applied to 7b (1), it is in a lighting state.

After the next 1H, the gate signal line 17a
(3) is selected (Vgl voltage) and the gate signal line 17b
The off voltage Vgh is applied to (3), and no current flows through the EL element 15 of the pixel row (3). However, the off voltage Vgh is applied to the gate signal lines 17a (1) and (2) of the previous pixel rows (1) and (2), and the gate signal line 17b is applied.
Since the ON voltage Vgl is applied to (1) and (2),
It is lit.

An image is displayed in synchronism with the above operation in synchronization with the 1H synchronization signal. However, in the driving method of FIG. 88, E
A 10 times larger current flows through the L element 15. Therefore, the display screen 21 is displayed with a brightness of about 10 times. of course,
It is needless to say that the program current may be set to 1/10 in order to display a predetermined brightness in this state. However, if the current is 1/10, insufficient writing will occur due to parasitic capacitance and the like. Therefore, the basic purpose of the present invention is to program with a high current and obtain a predetermined brightness by inserting the non-display area 312. .

However, the method of FIG. 84 is also within the scope of the present invention. That is, it is a concept that a current higher than a predetermined current is allowed to flow in the EL element 15 to sufficiently charge and discharge the parasitic capacitance of the source signal line 18. According to this, the EL element 15 does not need to flow N times as much current. For example, E
A current path is formed in parallel with the L element 15 (a dummy EL element is formed, and this EL element is formed with a light-shielding film so as not to emit light, etc.), and the current is diverted to the dummy EL element and the EL element 15. Is also good. That is, when the signal current is 0.2 μA, the program current is set to 2.2 μA, and the conversion TFT is used.
2.2 μA is applied to 11a. Of this current, a signal current of 0.2 μA is passed through the EL element 15 and 2 μA is passed through the dummy EL element.

With the above configuration, the current flowing through the source signal line 18 is increased N times,
The conversion TFT 11a can be programmed so that N times the current flows, and the current EL element 15 has N
This means that it is possible to pass a current sufficiently smaller than twice. According to the above method, as shown in FIG. 89 and the like, the entire display screen 21 can be set as the image display area 311 almost or completely as shown in FIG. 84 without providing the non-display area 312.

However, theoretically, all programmed currents flow through the EL element 15 unless the dummy EL element or the like is formed. Therefore,
In FIG. 84, the display screen emits light with N times the brightness. In order to emit light with a predetermined brightness, a non-display area 312 may be provided as shown in FIG. 89. FIG. 89 is an explanatory diagram of the method.

FIG. 89 (a) shows the state of writing on the display screen 21. In FIG. 89 (a), 871a
Is a write pixel row. A program current is supplied from the source driver 14 to each source signal line 18. In addition,
In FIG. 89 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all, and 0.
The period may be 5H or 2H. Further, although the programming current is written in the source signal line 18, the present invention is not limited to the current programming method, and a voltage programming method of writing a voltage in the source signal line 18 may be used.

In FIG. 89 (a), similar to FIG. 84,
When the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed in the converting TFT 11a.
At this time, an off voltage is applied to the gate signal line 17b, and E
No current flows through the L element 15. This is the EL element 15
When the switching TFT 11d on the side is on,
The capacitance component of the EL element 15 can be seen from the source signal line 18,
This is because the capacitor 19 is affected by this capacitance and a sufficiently accurate current program cannot be performed in the capacitor 19. Therefore,
Taking the configuration of FIG. 6 as an example, the pixel row in which the current is written becomes the non-display area 312 as shown in FIG. 89 (b).

Now, N times (here, as described above, N times
= 10), the brightness of the screen will be 10 times higher, so 90% of the display screen 21 may be set as the non-display area 312. Therefore, 220 horizontal scanning lines in the image display area with QCIF (S = 22
If 0), 22 are set as the image display area 311 and 22
0-22 = 198 may be set as the non-display area 312.
Generally speaking, if the horizontal scanning line (the number of pixel rows) is S, the S / N area is the image display area 311, and this image display area 311 is made to emit light at N times the luminance, and the vertical direction of the screen is displayed. Then, the area of S (N−1) / N becomes the non-display area 312. This non-display area is a black display (non-light emission). Further, this non-display area 312 is a switching T
It is realized by turning off the FT 11d. Note that N
Although it is assumed that the light is turned on with double the brightness, naturally, the value of N times must be adjusted by brightness adjustment and gamma adjustment.

Also, in the above embodiment, if programming is performed with a current of 10 times, the screen brightness becomes 10 times, and the display screen 2
The range of 90% of 1 should be the non-display area 312. However, this is not limited to common use of the RGB pixels as the non-display area 312. For example,
The R pixel has 1/8 as the non-display area 312, the G pixel has 1/6 as the non-display area 312, and the B pixel has 1 /
10 may be changed to each non-display area 312 depending on each color. Further, the non-display area 312 (or the image display area 311) may be individually adjusted with RGB colors, but in order to realize these,
Separate gate signal lines 17b are required for R, G, and B.
However, by enabling the individual RGB adjustments described above, it becomes possible to adjust the white balance, which facilitates color balance adjustment for each gradation.

As shown in FIG. 89B, the pixel row including the write pixel row 871a is set as the non-display area 312,
The S / N range of the screen above the write pixel row 871a is set as the image display area 311 (when the write scan is from the top to the bottom of the screen, and when the screen is scanned from the bottom to the top, the opposite is true). Become). The image display state is the image display area 3
11 becomes a strip and moves from the top to the bottom of the screen.

FIG. 90 shows a voltage waveform applied to the gate signal line 17. The voltage waveform shows the off voltage as Vgh (H level)
And the on-voltage is Vgl (L level). Figure 9
In the lower part of 0, the number of the selected pixel row is described. Further, (1), (2), (3), and (4) in the figure represent the selected pixel row numbers.

In FIG. 90, the gate signal line 17a
When (1) is selected (Vgl voltage), a program current flows from the conversion TFT 11a of the selected pixel row to the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N
= 10 will be described. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Therefore, the capacitor 19 is programmed so that a 10 times larger current flows through the conversion TFT 11a. When the pixel row (1) is selected, the gate signal line 17b in the pixel configuration of FIG.
The off voltage Vgh is applied to (1), and no current flows through the EL element 15.

1H (for ease of explanation, 1
After that, the gate signal line 1 is not limited to H.
7a (2) is selected (Vgl voltage), and a program current flows from the conversion TFT 11a of the selected pixel row to the source driver 14 in the source signal line 18. This program current is N times the predetermined value (for ease of explanation, N = 10 will be described). Therefore, the capacitor 19 is programmed so that a 10 times larger current flows through the conversion TFT 11a. At this time, the ON voltage Vgl is applied to the gate signal line 17b (1). According to the embodiment of FIG. 89, the period in which the ON voltage is applied is the S / N period. After that, the gate signal line 17b
The off voltage Vgh is applied to (1), and the pixel row (1)
No current flows through the EL element 15 of.

When the pixel row (2) is selected, as shown in FIG.
In the pixel configuration, the off voltage Vgh is applied to the gate signal line 17b (2), and no current flows in the EL element 15. However, the gate signal line 17a of the previous pixel row (1)
The off voltage Vgh is applied to (1), and the gate signal line 1
Since the on-voltage Vgl is applied to 7b (1), it is in a lighting state. The period during which this ON voltage is applied is
According to the embodiment of FIG. 89, this is the S / N period. After that, the off voltage Vgh is applied to the gate signal line 17b (2), and no current flows in the EL element 15 of the pixel row (2).

After the next 1H, the gate signal line 17a
(3) is selected, the off voltage Vgh is applied to the gate signal line 17b (3), and no current flows in the EL element 15 of the pixel row (3). However, the off voltage Vgh is applied to the gate signal lines 17a (1) and (2) of the previous pixel rows (1) and (2).
Is applied and the ON voltage Vgl is applied to the gate signal lines 17b (1), 17 (2), and thus the lighting state is achieved. The above operation is repeated to realize the display state of FIG. 89.

In the display of FIG. 89, one image display area 3
11 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the image display area 311 moves. In particular, it becomes easy to be recognized when the eyelids are closed or when the face is moved up and down.

To address this problem, the image display area 311 may be divided into a plurality of areas, as shown in FIG. In FIG. 91B, the non-display area 312 is divided into five. If the area obtained by adding these five areas has an area of S (N-1) / N, the brightness becomes equivalent to that in FIG. Conversely, when viewed from the image display area 311, the image display area (lighting area) 31
1 is divided into six, but if it is configured (driven) such that the portion including the regions divided into six is approximately equal to the S / N, the display luminance is equivalent to that in FIG. 89.

Incidentally, as also shown in FIG. 91 (b),
It is not necessary to make the divided image display areas 311 equal. Further, it is not necessary to make the divided non-display areas 312 equal.

As described above, by dividing the image display area 311 into a plurality of areas, the flicker of the screen is reduced, flicker does not occur, and good image display can be realized. Note that the division may be made finer, but the more the division is performed, the lower the moving image display performance becomes.

FIG. 92 shows a voltage waveform applied to the gate signal line 17. The difference between FIG. 92 and FIG. 90 is that the gate signal line 1
7b, and the gate signal line 17b is turned on / off by the number corresponding to the number of divided screens (Vg
l and Vgh) work. Since other points are the same as those in FIG. 90, description thereof will be omitted.

In the above embodiments, the pixel row selected simultaneously is one pixel row. FIG. 46 shows a method of simultaneously selecting a plurality of pixel rows. In FIG. 46, for ease of explanation,
The description will be made assuming that selection is performed simultaneously with five pixel rows, but the present invention is not limited to this, and it is sufficient if there are two or more pixel rows. However, if the number of pixel rows selected at the same time increases, the conversion TF
The variation absorption effect of T11a is reduced.

In the following embodiments, the pixel configuration of the current program shown in FIG. 6 will be described as an example, but the present invention is not limited to this. It goes without saying that the current mirror shown in FIG. 19 is also effective. As the number of pixel rows selected at the same time increases, the parasitic capacitance 40 of the source signal line is increased.
This is because charging and discharging such as 4 becomes easy. Also, FIG.
6, the pixel configuration of voltage programming such as FIG. 87 is also effective. By increasing the number of pixel rows selected at the same time,
This is because adjacent pixel rows can be precharged and can be applied to a high-definition display panel.

Here, for ease of explanation,
The current flowing from the source driver 14 to the source signal line 18 (or the current drawn by the source driver 14 from the source signal line 18, the conversion TFT 11a is the source signal line 1).
It is assumed that the current flowing into 8 is 10 times the predetermined value (N = 10). Therefore, 5 pixel rows are selected at the same time.
If there are pixel rows (K = 5), five conversion TFTs 11a
Works. That is, a current of 10/5 = 2 times per pixel flows through the conversion TFT 11a. If the pixel rows selected at the same time are two pixel rows, the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times per pixel flows through the conversion TFT 11a.

If the pixel rows selected at the same time are five pixel rows (K = 5), the program currents of the five conversion TFTs 11a are added. For example, in the write pixel row 871a, originally, the write current is Id, and N = 1.
If it is set to 0, a current of Id × 10 will flow through the source signal line 18. The write pixel row 871b adjacent to the write pixel row 871a (871b is the source signal line 18)
This is a pixel row that is used supplementarily to increase the amount of current to the pixel. Therefore, the number of pixels (rows) in which the image is written is 871.
a, and a pixel (row) 871b is used as an auxiliary for writing to 871a).

Ideally, the conversion TFT 11a of 5 pixels
However, a current of Id × 2 is supplied to the source signal line 18, and the capacitor 19 of each pixel 16 is programmed with a double current. However, in reality, the characteristics of the TFTs 11 of the five pixels are deviated, so that the current programmed in the capacitor 19 of each pixel varies. For example, in the writing pixel row 871a, 1.8 times,
Each of the four write pixel rows 871b is 2.2 times,
2.0, 1.6, and 2.4 times the current is programmed. In this example, the write pixel row 871a is programmed with 1.8 times the current, which is (2.0-1.8) /
There is an error of 2.0 = 10%. However, the current obtained by adding these is kept at the specified value of 10 times.

That is, the current programmed from the source driver 14 flows through the source signal line 18 according to the regulation, whereas the current according to the characteristic variation flows through the selected pixel. Therefore, the larger the characteristic variation of the conversion TFT 11a of each pixel, the more the target program current deviates from the set value. However, since the characteristics of the adjacent conversion TFTs 11a are substantially the same, uniform display can be realized even if the pixel rows selected at the same time are increased as shown in FIG.

The embodiments shown in FIGS. 45 and 46 are more effective for the display panel having the TFT 11 formed by the amorphous silicon technique than the display panel having the TFT 11 formed by the low temperature polysilicon technique. This is because the characteristics of the adjacent TFTs of the amorphous silicon TFT 11 are substantially the same. Therefore, even if the TFTs are driven by the added current, the drive current of each TFT is almost the target value.

In FIG. 46, the write pixel row 871a
If K rows (K = 5) are simultaneously written with the image data of
The row ranges (871a, 871b) are displayed in the same manner. When the same display is performed in this way, the resolution is naturally lowered. In order to deal with this, as shown in FIG. 46B, the portion of the write pixel row 871 is formed in the non-display area 3.
It is set to 12. Then, the resolution does not decrease.

After the next 1H, the same operation is performed with the position shifted by one pixel row as the write pixel row 871a, and when the non-display area 312 is also shifted by one pixel (row), the current programmed pixel (row ) Is displayed.

When driven as described above, the write pixel row 8 to which the current data different from the original display data has been written
71b is not displayed, and a complete image display can be realized by shifting the above operation line by line. In addition, the parasitic capacitance 4 is caused by the effect of the write pixel row 871b that is used as an auxiliary.
Charging / discharging of 04 can also be realized within 1H period.

FIG. 93 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. Similar to FIG. 88, the voltage waveform has an off voltage of Vgh (H level) and an on voltage of Vgh.
Gl (L level). The number of the selected pixel row is described in the lower part of FIG. Also,
(1), (2), (3), ... (6) indicate the selected pixel row numbers. The number of lines is 220 in the case of the QCIF display panel and 480 in the case of the VGA panel.

In FIG. 93, the gate signal line 17a
When (1) is selected (Vgl voltage), a program current flows from the conversion TFT 11a of the selected pixel row to the source driver 14 in the source signal line 18. Here, for ease of explanation, first, the write pixel row 871a
Is the pixel row (1) -th row.

The program current flowing through the source signal line 18 is N times the predetermined value (N = 1 for ease of explanation).
It will be described as 0. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Also, description will be made assuming that 5 pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that a double current flows through the conversion TFT 11a.

When the writing pixel row is the (1) th pixel row, as shown in FIG. 93, (1), (2), (3), (4) and (5) are applied to the gate signal line 17a. Is selected. That is, pixel rows (1), (2), (3),
(4) and (5) driving TFT 11b and loading TFT 1
1c is on. Further, since the gate signal line 17b has the opposite phase to the gate signal line 17a, the switching TFT 11d of the pixel rows (1), (2), (3), (4), and (5) is in the off state. , No current flows in the EL element 15 of the corresponding pixel row, and the non-display area 31
It becomes 2.

Ideally, the conversion TFT 11a of 5 pixels
Respectively, a current of Id × 2 flows through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with a double current. Here, in order to facilitate understanding, the description will be given assuming that the characteristics (Vt, S value) of the conversion TFTs 11a match.

The pixel rows selected at the same time are 5 pixel rows (K =
Since it is 5), the five conversion TFTs 11a operate. That is, a current of 10/5 = 2 times per pixel flows through the conversion TFT 11a. The source signal line 18 has 5
A current that is the sum of the program currents of the two conversion TFTs 11a flows. For example, in the writing pixel row 871a, originally,
The write current is Id, and the source signal line 18 has Id
Apply a current of × 10. The write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the write pixel row 871b later, there is no problem.

Therefore, the write pixel row 871b is
Since the same display as the writing pixel row 871a is performed during the 1H period, at least the writing pixel row 871a and the writing pixel row 871b selected for increasing the current are used as the non-display area 312. However, in the pixel configuration of the current mirror as shown in FIG. 19 and the pixel configuration of the voltage programming method as shown in FIG. 86, the display state may be set in some cases.

[0508] After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17a (6) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (6) toward the source driver 14 to the source signal line 18. By operating in this way, the pixel row (1)
Holds regular image data.

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17a (7) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (7) toward the source driver 14 to the source signal line 18. By operating in this way, the pixel row (2)
Holds regular image data. One screen is rewritten by the above operation and scanning while shifting by one pixel row at a time.

Although it is similar to FIG. 84, in the driving method of FIG. 93, each pixel is programmed with a double current (voltage). Therefore, the emission brightness of the EL element 15 of each pixel is ideally 2 Doubled. Therefore, the brightness of the display screen is twice the predetermined value.

[0511] In order to set this to a predetermined brightness, FIG.
As shown in FIG. 7, the non-display area 312 may include a half of the display screen 21 including the write pixel row 871. Since this has been described with reference to FIG. 90 and the like, description thereof will be omitted.

[0512] As the area of the black display area (non-display area) 312 occupying the display screen 21 is increased, the moving image display performance is improved. Therefore, as shown in FIG. 94, the image display area 311 may be reduced and the non-display area 312 may be increased in area.

As shown in FIG. 45, the current to be programmed in each pixel is doubled, and the area of the image display area 311 is displayed on the display screen 21.
If it is 1/2 of that, a predetermined display brightness can be obtained. However, when the image display area 311 is smaller than 1/2 of the display screen 21 as shown in FIG. 94, the screen becomes dark.
Therefore, in order to obtain a predetermined brightness, the current programmed in each pixel may be increased. For example, if the image display area (lighting area) 311 is ⅕ of the area of the display screen 21 and five pixel rows (K = 5) are selected at the same time,
The current (voltage) to be programmed in one pixel row may be 5 times the predetermined value. The current flowing through the source signal line 18 is 5 × 5
Pixel rows = 25 times.

In any case, in the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) supplied to the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14. Whether two pixel rows are simultaneously turned on, five pixel rows are simultaneously turned on, or only one pixel row is selected depends on whether the ST * terminal applied to the shift register 22 of the gate driver 12 shown in FIG. Can be set by data. Therefore, the specifications of the source driver 14 are
It does not depend on the number of pixels selected. Also, since the screen brightness can be adjusted by turning on / off the gate signal line 17b, the source driver 1 can be adjusted by adjusting the brightness of the display screen 21.
It does not change the output current from 4. Therefore, the gamma characteristic of the EL element 15 may be determined for one current. Therefore, the configuration of the source driver 14 is extremely easy and highly versatile. The above items can be applied to other embodiments of the present invention.

Although the above-described embodiment has a configuration in which one selected pixel row is arranged (formed) for each pixel row, the present invention is not limited to this and one pixel row may be used. Book select gate signal lines may be arranged (formed).

FIG. 95 shows an example thereof. Note that, for ease of explanation, the pixel configuration will be described mainly taking the case of FIG. 6 as an example. In FIG. 95, the selection gate signal line 17 of the pixel row is
a selects three pixels (16R, 16G, 16B) at the same time, and puts each pixel in a data write state. It should be noted that the R symbol relates to red pixels, the G symbol relates to green pixels, and the B symbol
The symbol of means the blue pixel relation.

The pixel 16R writes data from the source signal line 18R to the capacitor 19R, the pixel 16G writes data from the source signal line 18G to the capacitor 19G, and the pixel 16B writes data from the source signal line 18B to the capacitor 19B.

The TFT 11d of the pixel 16R is connected to the gate signal line 17bR, the TFT 11d of the pixel 16G is connected to the gate signal line 17bG, and the TFT 11 of the pixel 16B.
d is connected to the gate signal line 17bB. Therefore, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be individually on / off controlled. That is, the EL elements 15R, E
By controlling the gate signal lines 17bR, 17bG, and 17bB of the L element 15G and the EL element 15B, the lighting time and the lighting cycle can be individually controlled.

To realize this operation, in the configuration of FIG. 21, a shift register 22 for scanning the gate signal line 17a, a shift register 22 for scanning the gate signal line 17bR, and a shift for scanning the gate signal line 17bG. It is appropriate to form (arrange) four registers 22 and a shift register 22 that scans the gate signal line 17bB.

FIG. 96 shows the arrangement of the pixels 16.
In FIG. 96, the pixels are formed in a horizontal stripe shape (note that the conventional configuration is generally a vertical stripe shape). By arranging pixels in a horizontal stripe pattern,
The connection between the gate signal line 17 and the switching element becomes easy, and the pixel layout becomes easy. In addition, an EL element made of a polymer material can be easily manufactured by inkjet.

Although the pixels are formed in the horizontal stripe shape in FIGS. 95 and 96, they may be formed in the vertical stripe shape as in the conventional case. In addition, the reverse bias voltage application method, the block drive method, the control method using the Vbb voltage, and the configuration in which the respective voltages of RGB are separated, which are described in this specification,
A method using the punch-through voltage of the TFT 11b, FIG.
It is needless to say that it is appropriate to combine the method of (1), the configuration of adding a dummy pixel row, and the like with other embodiments in this specification.

FIG. 97 shows operation waveforms of the pixel configuration of FIG. Note that, for ease of explanation, description will be made assuming that one pixel row (of course, if counting with RGB, this means three pixel rows) is selected. However, it goes without saying that a driving method of simultaneously selecting a plurality of pixel rows can be realized as described with reference to FIGS. 45, 46, 116, and the like. Further, as described with reference to FIG. 110, it is necessary to control the timing of the gate signal lines even within the range of the 1H period. However, in order to simplify the description, here, the gate signal lines 17a are used to control the timing of the pixel rows. The selection is described as being in the 1H period. The above items also apply to other driving methods and panel configurations described in this specification.

In FIG. 97, the writing pixel row is (1)
In the case of the pixel row, the gate signal line 17a has 16 pixel blocks (it is easier to understand if this is regarded as one pixel row)
Is selected (see also FIG. 95). That is, the pixel 16R, the pixel 16G, and the pixel 16B are selected,
Switching TFTs 11b, TF of 16R of pixel row (1), 16G of pixel row (1) and 16B of pixel row (1)
T11c is turned on.

The pixel 16R of the pixel row (1) writes the image data from the source signal line 18R to the capacitor 19R, and the pixel 16G of the pixel row (1) writes the image data from the source signal line 18G to the capacitor 19G. The pixel 16B in row (1) writes the image data from the source signal line 18B in the capacitor 19B.

Note that, in order to facilitate the description, in FIG. 97, it is assumed that an N times (N = 2) current flows through the EL element 15 in each pixel in the period of 1 / N of one frame (one field). Described as programmed. Note that, as described in the present specification, it can be applied to other embodiments. Further, by increasing the N value, the influence of the parasitic capacitance 404 of the source signal line 18 can be ignored, and the pixel 1
It goes without saying that the image data can be easily written in No. 6. That is, N is not limited to 2. Also, N is not limited to an integer, and can be realized with a value such as 2.5. Further, the selection time of the gate signal line 17a is not limited to 1H and may be 2H or more.

The gate signal line 17bR, the gate signal line 17bG and the gate signal line 17bB in the pixel row (1) are in the opposite phase to the gate signal line 17a. Therefore,
At least the switching TFT 11d of the pixel 16R, the pixel 16G, and the pixel 16B of the pixel row (1) is in the off state, and the EL elements (15R, 15G, 1
No current flows in 5B), which becomes the non-display area 312.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b. At the same time, the gate signal line 1
7a (2) is selected (Vgl voltage), and source signal lines 18 (18R, 18G, and 18B, respectively) from the TFTs 11a of the pixels 16R, 16G, and 16B of the selected pixel row (2) toward the source driver 14. ), The program current flows. By operating in this way, the image data is held in the pixels 16R, 16G, and 16B of the pixel row (1).

After the next 1H, the gate signal line 17
The a (2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the TFT 11a of the selected pixel row (3) changes from the source driver 1 to the source driver 1.
A programming current flows through the source signal line 18 toward the signal line 4. By operating in this way, the image data is held in the pixel row (2). One screen is rewritten by scanning the above operation while shifting it by one pixel row at a time.

Next, the operation of the gate signal line 17b of FIG. 97 will be mainly described. The pixel 16R has a gate signal line 17b
R is connected. The gate signal line 17 is provided in the pixel 16G.
bG is connected. A gate signal line 17bB is connected to the pixel 16B. Therefore, pixel 16
R can control on / off of the current flowing through the EL element 15R by the gate signal line 17bR. Similarly, pixel 16
G can control ON / OFF of the current flowing through the EL element 15G with the gate signal line 17bG, and pixel 16B can control ON / OFF of the current flowing through the EL element 15B with the gate signal line 17bB.

In FIG. 97, the gate signal line 17bR, the gate signal line 17bG and the gate signal line 17bB have the same waveform in each pixel row. Therefore, the EL elements 15R, 15G and 15B are simultaneously turned on / off (lighted and non-lighted). In FIG. 97, the EL element 15 is turned on and off every 4H, but the invention is not limited to this. It may be every 1H or more. In principle, the EL element 15 may be turned on / off at a cycle of 1H or less.

[0531] However, if the on / off cycle is too fast, moving image blur occurs in the moving image display. Therefore, EL
It is necessary that the interval between turning on, turning off the light, and turning on the device 15 be 0.5 msec or more. When this cycle is short, the image is not completely displayed in black due to the afterimage characteristic of human eyes, and the image becomes blurry and the resolution is lowered. Further, the display state of the data holding type display panel is set. However, the on / off cycle is 100 msec.
In the above case, since it looks like a blinking state, the on / off period of the EL element should be 0.5 μsec or more and 100 msec or less, and further 2 msec or more and 30 msec or less. More preferably, it should be 3 msec or more and 20 msec or less.

From the above relationship, the number of insertion of the non-display area 312 for turning on / off the screen is determined from the time required for one frame (one field) and the cycle or number of signals (Vgh, Vgl) applied to the gate signal line 17b. To be done.
Although a good moving image display can be realized by using only one non-display area 312, it is preferable to divide the non-display area 312 insertion portion into a plurality of parts because the flicker of the screen is easily visible.
However, if the number of divisions is too large, blurring of moving images occurs, so the number of divisions is preferably 1 or more and 8 or less, and more preferably 1 or more and 5 or less.

According to the present invention, even if the current flowing through the EL element 15 is cut off by turning off the TFT 11d, when the TFT 11d is turned on again, the same current as the current that has been flowing before flows through the EL element 15. be able to. This is because the current value to be passed is stored in the capacitor 19 of the pixel (analog memory). This matter is a great feature of the present invention. That is, it means that the control for turning on / off the current flowing through the EL element 15 can be freely performed.

In FIG. 97, the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB have the same waveform in each pixel row, and the selection of the pixel row is performed by sequentially shifting the selected pixel row every 1H. , The EL elements 15R, 15G, and 15B are arranged at the display screen 2
Moving from top to bottom at high speed. The on / off control, the insertion ratio of the non-display area 312, and the number of non-display areas 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Needless to say, the Vgh data applied to the gate signal line 17b may be controlled in parallel.

Although the signal applied to the gate signal line 17 is a periodic signal, it is not limited to this and may be an aperiodic signal. However, if the total time of turning on or off the EL element 15 is different, the brightness of the screen is changed or the color balance is deviated. Therefore, the EL element 15 is not changed in one frame (one field) period.
It is necessary to set the total sum of the times for turning on and off to a constant value. As a special case, there is a case where the total sum of the times when the EL element 15 is turned on or off in a period of two frames (two fields) or more may be set to a constant value. One frame (field) is very fast, and FSC
This is the case of (frame sequential control) driving.

In FIG. 98, the waveform applied to the gate signal line 17bR is changed in a 2H cycle, and the gate signal line 17bG is changed.
The waveform applied to the gate signal line 1
The waveform applied to 7bB is changed in 4H cycles. Other matters are the same as those in FIG. 97, and thus the description thereof will be omitted.

The synchronization change pattern in FIG. 98 is for facilitating drawing and is not limited to 2H, 3H and the like. A signal applied to at least one of the gate signal lines 16bR connected to the pixel 16R, the gate signal line 16bG connected to the pixel 16G, and the gate signal line 16bB connected to the pixel 16B. The waveform is different from that of the other gate signal lines 17b.

When driven as shown in FIG. 98, the EL element 15
The light emitting positions of R, 15G, and 15B move from top to bottom of the display screen 21 at high speed. At this time, the EL element 1
5R ON / OFF (lighting, non-lighting) cycle and EL element 15
ON / OFF (lighting / non-lighting) cycle of G and EL element 15B
The on / off (lighting / non-lighting) cycle is different. In this way, by changing the lighting cycle of the EL element 15,
The occurrence of flicker is less noticeable.

[0539] Further, the on / off control and the non-display area 31
The insertion ratio of 2 and the number of non-display areas 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, it goes without saying that the control of the signal (Vgh, Vgl) data applied to the gate signal line 17b may be controlled in parallel.

In FIG. 99, the Vgl period applied to the gate signal line 17bR is set shorter than that of the other gate signal lines 17b. Therefore, the lighting time of the EL element 15R connected to the gate signal line 17bR becomes long (the TFT 11d of the pixel 16R is turned on for a long time). Therefore, the R emission brightness of the display screen 21 becomes strong.

As described above, the signals applied to the gate signal line 17bR, the gate signal line 17bG, and the gate signal line 17bB are individually controlled, that is, the time, timing, and cycle for turning on the EL element 15 are controlled. As a result, the color balance of the display screen 21 and the occurrence of flicker can be suppressed.

In FIG. 99, the gate signal line 17bG
The waveform applied to the gate signal line 1
The waveform applied to 7bB was changed in 4H cycles, but this is for easy drawing.
It is not limited to At least pixel 16
A signal waveform applied to one or more gate signal lines 17b among the gate signal line 16bR connected to R, the gate signal line 16bG connected to the pixel 16G, and the gate signal line 16bB connected to the pixel 16B. Of which, TFT11d
The gate signal line 17b has a different application time of a signal for turning on (or turning off).

When driven as shown in FIG. 99, the EL element 15
The light emitting positions of R, 15G, and 15B move from top to bottom of the display screen 21 at high speed. At this time, the EL element 1
Since the ON (lighting) time of the 5R, the ON (lighting) time of the EL element 15G, and the ON (lighting) time of the EL element 15B can be made different, the color balance of the screen can be adjusted, and the flicker Occurrence becomes less noticeable. Such color balance adjustment is preferably configured so that the user can adjust it while looking at the display screen 21. Since it is sufficient to increase or decrease the number of ON ST data input to the shift register 22 shown in FIG.
This adjustment is easy. Further, the on / off control, the insertion ratio of the non-display area 312, and the insertion number of the fertilizer area 312 can be easily realized by controlling the ST data to the shift register 22 described with reference to FIG. Of course, the signal applied to the gate signal line 17b (Vgh,
It goes without saying that the control of Vgl) data may be controlled in parallel.

Note that FIGS. 95 to 99 have been described by exemplifying the case where the pixel configuration is FIG. However, the above example
It goes without saying that the present invention can be applied to other pixel configurations. For example, FIG. 19, FIG. 20, FIG. 86, FIG. That is, the technical idea described in FIGS. 95 to 99 can be applied to other configurations.

The driving method described with reference to FIGS. 46, 45, 93, etc. was a method of simultaneously selecting a plurality of pixel rows.
The following points must be noted in this driving method. From the conclusion, it is preferable to provide (form) pixels (rows) (dummy pixels (rows)) that do not contribute to display. The reason for this will be described below.

FIG. 100 is an explanatory diagram of a driving method for simultaneously selecting two pixel rows. In FIG. 100, the pixel 16
The state where a and 16b are selected is illustrated. The TFT 11a of the pixel 16a and the TFT 11a of the pixel 16b respectively supply the current Idd to the source signal line 18.

For ease of explanation, the T of each pixel is
It is assumed that there is no variation in the current passed by the FT 11a, and 2 × Id
Let d = Iw. That is, the source driver 14 absorbs the current Iw from the source signal line 18, and the current Iw is 2
The equally divided current is programmed into the capacitor 19 of each pixel. For example, if Idd = 15 nA, Iw = 30
nA.

As shown in FIG. 1A, two write pixel rows 871 (871a, 871b) are selected,
The display screen 21 is sequentially selected from the upper side to the lower side. However, as shown in FIG. 1B, although the write pixel row 871a exists at the bottom of the screen, the write pixel row 871b disappears. That is, only one pixel row is selected. Therefore, all the current Iw applied to the source signal line 18 is written in the write pixel row 871a. Therefore, Iw = Idd, and twice as much current is programmed in the pixel as compared with the write pixel row 871a in FIG.

To solve this problem, the present invention is shown in FIG.
As shown in FIG.
Since 471 is formed (arranged), when the selected pixel row is selected up to the lower side of the display screen 21, the final pixel row and the dummy pixel row 2471 of the display screen 21 are selected. Therefore, the write pixel row in FIG.
A current of dd = Iw / 2 is written.

FIG. 101 shows the state of FIG. 1 (b). As is apparent from FIG. 101, when the selected pixel row is selected up to the pixel 16b row on the lower side of the display screen 21, the final pixel row and the dummy pixel row 2471 of the display screen 21 are selected. Further, as shown in FIG. 102, the dummy pixel row 2471 is formed (arranged) outside the display screen 21. That is, the dummy pixel row 2471 is not illuminated, is not illuminated, or is invisible even when illuminated.

Even when the dummy pixel row 2471 is formed (arranged) as shown in FIGS. 101 and 102, the gate signal line 17b and the like are shared by the lighting control line 1791 as described with reference to FIG. 187. Block lighting drive can be implemented. It can also be combined with reverse bias driving (see FIG. 103).

Although the dummy pixel row 2471 is provided on the lower side of the display screen 21 in FIG. 1, the invention is not limited to this. For example, as shown in FIG. 104 (a),
When scanning from the bottom side to the top side of the screen (upside-down reverse scanning), as shown in FIG.
A dummy pixel row 2471 should be formed also on the upper side.
That is, dummy pixel rows 2471 are formed (arranged) on each of the upper side and the lower side of the screen 21 (see FIG. 105). With the above configuration, it is possible to support upside down scanning of the screen.

The above-mentioned embodiment is a case where two pixel rows are simultaneously selected. The present invention is not limited to this, and for example, a method of simultaneously selecting 5 pixel rows may be used.

FIG. 106 is an explanatory diagram of a driving method for simultaneously selecting 5 pixel rows. As shown in FIG. 106, four dummy pixel rows 2471 are formed on the upper and lower sides of the screen.

FIG. 107 is an explanatory diagram of a driving method of the display panel of FIG. Iw = 5 from the source driver 14
It is assumed that the current of × Idd is output (or absorbed). The current Idd is a current written in each pixel (programmed current), and it goes without saying that it varies depending on the display image.

In the driving method of simultaneously selecting 5 pixel rows,
The source driver 14 outputs a current that is 5 times the current Idd written in the pixel. In FIG. 107A, the display screen 21
Only the uppermost pixel is selected. However, since Iw = 5 × Idd in this state, a current which is five times the predetermined value is written in the write pixel row 871.

To solve this problem, according to the present invention, FIG.
As shown in (a), four dummy pixel rows 24
71a are selected at the same time. That is, the four dummy pixel rows 2471a and the write pixel row 871 in one display area are simultaneously selected. Therefore, since Iw = 5 × Idd, the write pixel row 871 selected in FIG.
A predetermined current Idd is programmed into the memory.

In FIG. 107 (b), two write pixel rows 871 on the display screen 21 are selected and the dummy pixel row 24 is selected.
One of 71a is not selected, but three are selected. Therefore, the total number of selected pixel rows is five. Therefore, I
Since w = 5 × Idd, a predetermined current Idd is programmed in the two write pixel rows 871 selected in FIG. 107 (b).

Similarly, in FIG. 107 (c), the display screen 2
Three write pixel rows 871 of 1 are selected, two dummy pixel rows 2471a are not selected, and two dummy pixel rows 2471a are selected. Therefore, the total number of selected pixel rows is five. Therefore, since Iw = 5 × Idd, FIG. 107 (c)
A predetermined current Idd is programmed in the two write pixel rows 871 selected in step 1.

Similarly, in FIG. 107 (d), four write pixel rows 871 on the display screen 21 are selected, three dummy pixel rows 2471a are not selected, and one dummy pixel row 2471a is selected. In addition, in FIG. 107E, five write pixel rows 871 on the display screen 21 are selected, and dummy pixel rows 24 are selected.
71a is not selected. Hereinafter, five pixel rows are sequentially selected (FIGS. 107 (f), (g), (h)). When the lower side of the display screen 21 is reached, the dummy pixel row 2471b
The number of selected items increases every 1H.

By driving in this way, even if the number of pixel rows to be simultaneously selected increases, when selecting the upper side or the lower side of the display screen 21, the pixel rows including the dummy pixel row 2471 can be set to a constant value. it can. Therefore, the current value output by the source driver 14 can be fixed to the number of pixel rows simultaneously selected for the image data.
The configuration is simplified, and a target predetermined current (voltage) is written in each pixel.

As described above, in the driving method of selecting 5 pixel rows at the same time, 5-1 = 4 dummy pixel rows may be formed on one side of the screen. That is, it is only necessary to form or arrange dummy pixel rows of (pixel row number-1) or more that are simultaneously selected.

Further, although the above-described embodiments are the ones in which two pixel rows are simultaneously selected and the five pixel rows are simultaneously selected, the present invention is not limited to this and three pixels are selected. Rows or more pixel rows may be selected simultaneously.
Moreover, although it has been described that the adjacent pixel rows are simultaneously selected, the present invention is not limited to this. For example, it may be selected every other pixel row or may be selected randomly.

In the above embodiments, when selecting a plurality of pixel rows, the dummy pixel row 2471 is selected at the beginning or the end of the scanning of the display screen 21 and the current Iw flowing through the source driver 14 is set to a constant value. However, the present invention forms or arranges dummy pixel rows, and is not limited to making the current flowing through the source driver 14 a constant value.

FIG. 108 shows a driving method in which the dummy pixel row 2471a is turned on while the write pixel row 871a is not selected. Also, the writing pixel row 871a
Is one pixel row, but is not limited to this, and needless to say, it may be a plurality of pixel rows as shown in FIG. An example of such driving is the case where the gate driver 12 is directly formed on the array substrate 49 (gate driver built-in configuration).

In the structure with a built-in gate driver, it is difficult to form a complicated circuit from the viewpoint of yield or formation area. Therefore, although the gate driver 12 is formed with a circuit configuration that is as simple as possible, there are cases where the operation is restricted.

For example, even if the data (ST) is input to the shift register 22 of the gate driver 12, the gate signal line 1 is not returned until after 2 to 3 clocks (the clock is set to 1H).
It is exemplified that the ON signal Vgl is not output to 7a.
However, after the ON data is output to the gate signal line 17a (1), the ON data position is sequentially shifted in synchronization with the 1H clock.

As described above, if the gate signal line 17a (1) is not selected after a few clocks, no pixel row is selected for a few clocks. During this period, the output of the source driver 14 is preferably in the 0 state (no current input / output). However, since the output stage of the source driver 14 is composed of a constant current circuit, it is difficult to make the flowing current completely zero. When a current flows through the source signal line 18 (the source driver 14 absorbs the electric charge of the source signal line 18), the potential of the source signal line 18 is lowered.
When the potential of the source signal line 18 decreases, the potential of the capacitor 19 of each pixel 16 may also decrease. When the potential of the capacitor 19 decreases, the potential of the gate terminal of the TFT 11a decreases, so that the TFT 11a flows more current. This state appears remarkably,
This is the case where the screen is displayed in black. TFT11a of each pixel
This is because the black floating occurs when the current flows through the.

To address this problem, when none of the gate signal lines 17 on the display screen 21 is selected (state), the dummy pixel row 2471 is selected and driven so that current flows to the source signal line. That is, dummy pixel row 2
The switching TFT 11 of 471 is turned on, and the impedance of the driving TFT 11a is lowered. Therefore, the current flowing into the source driver 14 is configured to be supplied from the TFT 11a of the dummy pixel row 2471.

It is important to note that when no pixel row on the display screen 21 is selected, the source driver 14
The output stage circuit of is to keep the current off as much as possible.

In FIG. 108 (a1), the gate driver 1
2 It is assumed that the start signal is applied to the built-in shift register 22. FIG. 108 (a2) is the same as FIG.
This is 1H later than (a1). Similarly, FIG.
(A3) is after 1H, and FIG. 108 (a4) is after 1H. That is, FIG. 108 (a1), (a
In 2), none of the gate signal lines of the display screen 21 is selected in the first 2H period, and after 3H, the state shown in FIG.
The pixel row (1) is selected for the first time in FIG.
4) shows that the pixel row (2) is selected by shifting by one pixel row.

As described above, FIGS. 108 (a1) and (a2)
Then, no pixel row is selected. As a countermeasure, the dummy pixel row 2471a is selected and the dummy pixel row 247 is selected so as not to change the potential of the source signal line 18.
The current from the TFT 11a is supplied to 1a.

As described above, by supplying a current to the dummy pixel row 2471a, it is possible to realize a good image display without blackening. Also, the white balance of the screen does not change.

In FIG. 108 (a), the dummy pixel row 2471a closer to the source driver 14 is selected, but the present invention is not limited to this. For example, in FIG.
8B, the dummy pixel row 2471b far from the source driver 14 may be selected. Further, both the dummy pixel rows 2417a and 2471b may be selected.

The driving method of FIG. 108 (b) is the same as that of FIG.
The operation is similar to 08 (a). In FIG. 108 (b1),
A start signal is applied to the shift register 22 with the gate driver 12 incorporated therein, and FIG.
This is 1H later than 1). Similarly, FIG.
3) is after 1H, and FIG. 108 (b4) is after 1H.

In FIG. 108 (b), as in the case of FIG. 108 (a), no gate signal line of the display screen 21 is selected in the first 2H period, and the first pixel row in FIG. 108 (b3) after 3H. FIG. 108 (b4) shows that the pixel row (2) is selected by shifting the pixel row by 1 pixel row after (1) is selected. As shown in FIG. 108B, it is easier to stabilize the potential of the source signal line 18 by selecting the dummy pixel row 2471b farther from the source driver 14. This state is shown in FIG.

In the embodiment of FIG. 108, the number of pixel rows selected is one, but the number of pixel rows is not limited to this. For example, it can be applied to a driving method for selecting a plurality of pixel rows as shown in FIG. In the driving method of selecting a plurality of pixel rows, if it is intended to solve the problem of black floating or image quality change that occurs when no pixel row of the display screen 21 is selected,
It is not necessary to form a plurality of dummy pixel rows 2471 as in FIG. As shown in FIG. 108, there may be one dummy pixel row 2471. This is because the potential of the source signal line 18 and the like can be stabilized with this one dummy pixel row.

Also, dummy pixel rows 2471a and 2471
b is the scanning direction of the display screen 21 (for example, in FIG. 1 and FIG.
04), the selected dummy pixel row 2471 may be changed.

In FIG. 108, during the period of one frame (or one field), the dummy pixel row 24 is displayed in a state where no pixel row of the display screen 21 is selected.
It was to select 71. However, in the actual driving state, the pixel row may not be selected in one horizontal scanning period.

FIG. 110 is an operation waveform diagram for explaining this state. In the display device of the present invention, a pixel row is selected with a clock of 1H (1 horizontal scanning period), and the selected pixel row is sequentially shifted. However, even in the 1H period, the pixel row is selected in the predetermined period.

Basically, the off voltage Vgh is applied to the gate signal line 17b of the selected pixel row for the entire period of 1H. In FIG. 110, when the pixel row number is 1, the off voltage Vgh is applied to the gate signal line 17b of the pixel row (1). When the pixel row number is 2, the off voltage Vgh is applied to the gate signal line 17b of the pixel row (2).

On the other hand, the ON voltage Vgl is applied to the gate signal line 17a for a period shorter than 1H. Therefore, when the pixel row number is 1, the pixel row (1) in the period a and the period b is not selected. The reason why the non-selected period is generated as described above is that the punch-through voltage is likely to occur when the timing of changing the gate signal line 17b and the timing of changing the gate signal line 17a coincide with each other. This is because when the punch-through voltage occurs, the desired voltage (current) is not retained in the capacitor 19 and the emission brightness of the EL element 15 varies.

At least the period a shown in FIG. 110 is preferably secured. The period of b may be 0 in some cases. This may be determined in consideration of the timing of ON / OFF control of the EL element 15. Basically, from the timing when the gate signal line 17b changes from the on voltage Vgl to the off voltage Vgh (that is, the non-selected state), at least 1/64 time of 1H or more and 1/8 time of 1H or less elapses. Then, after more than 1/32 time of 1H or more and 1/8 time of 1H or less, the gate signal line 1
It is preferable to select 7a. Alternatively, from the timing when the gate signal line 17b changes from the on-voltage Vgl to the off-voltage Vgh (that is, the non-selected state), at least 0.5 μsec or more and 20 μsec or less elapses, and further 1 μsec or more and 10 μsec or less elapses. Therefore, it is preferable to select the gate signal line 17a. Further, it is more preferable to apply the precharge (discharge) voltage described in FIG. 163 or the like during the period a or the period b.

During the period in which the gate signal line 17a is selected, the switching signal CSW shown in FIG. 110 becomes the off voltage Vgh. ON voltage Vg of the switching signal CSW
With l, the output stage of the source driver 14 is controlled to be in the off state. In addition, the dummy pixel row 247 described with reference to FIG.
It is controlled so that 1 is selected. By configuring or operating as described above, good image display can be realized without blackening. Further, it is possible to prevent a change in the white balance of the screen from occurring.

In FIG. 109, dummy pixel row 2
Although 471 is illustrated as forming the EL element 15 and the TFT 11d, basically the dummy pixel row 2471 supplies a current to the source signal line 18 (in some pixel configurations, the current is absorbed from the source signal line 18). Therefore, the EL element 15 is not necessary. On the contrary, the EL element 15
When the above is formed, the EL element 15 lights up, which causes a problem.

According to the present invention, the dummy pixel row 2471 is shown in FIG.
1, the EL element 15 and the like are not formed. The capacitor 19b for generating the punch-through voltage may or may not be added. However, in the case where the pixel 19 of the display screen 21 is provided with the capacitor 19b for generating the punch-through voltage, it is preferable that the dummy pixel row 2471 is also formed. This is the TFT 11a of the dummy pixel row 2471.
This is for making the current flowing by the same as the current flowing by the TFT 11a of the pixel 16 of the display screen 21.

FIG. 111 shows the case of the pixel configuration of FIG.
In the pixel configuration of the current mirror of FIG. 19, as shown in FIG. 112, in the dummy pixel row 2471, the driving TF is used.
T11b and EL element 15 are deleted. In the case of the voltage-programmed pixel configuration shown in FIGS. 85 and 87, the switching TFT 11b and the capacitor 19a are used as shown in FIG. This is because the voltage programming method does not supply a current from the pixel driving TFT to the source signal line 18.

Since the dummy pixel row 2471 shown in FIGS. 111 and 112 does not need to emit light, the dummy pixel row 2471 shown in FIG.
Pixel electrodes 4 of the dummy pixel row 2471 as shown in FIG.
No EL film is formed on No. 8. As shown in FIG. 114, an insulating film 2561 is formed on the pixel electrode 48 to bring it into an insulating state. Alternatively, as shown in FIG. 115, the pixel electrodes 48 of the dummy pixel row 2471 and the reflective film 46 of the cathode are electrically short-circuited. With this configuration, the potential of the pixel electrode 48 is stable.

Similar to FIG. 89, when one image display area 311 moves from the top to the bottom of the screen as shown in FIG. 94,
When the frame rate is low, it is visually recognized that the image display area 311 moves. Especially when you close your eyelids
Alternatively, it becomes easier to be recognized when the face is moved up and down.

To solve this problem, the image display area 311 may be divided into a plurality as shown in FIG.
In FIG. 116 (b), the non-display area 312 is divided into three. If the area obtained by adding the three becomes the area of S (N-1) / N, the brightness becomes equivalent to that of FIG.

FIG. 117 shows a voltage waveform applied to the gate signal line 17. The difference between FIG. 93 and FIG. 117 is basically the operation of the gate signal line 17b. Gate signal line 17b
Corresponds to the number of divided screens, and turns on and off (Vgl and Vgh) by the number. The other points are almost the same as or can be inferred from FIG.

As shown in FIG. 116 (b) as well, the scanning direction of the non-display area 312 is not limited to only from the top to the bottom of the screen. Good. Further, the scanning direction from the upper side to the lower side and the scanning direction from the lower side to the upper side may be alternately or randomly scanned. It goes without saying that the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.

As described above, by dividing the image display area 311 into a plurality of areas, the flicker of the screen is reduced, flicker does not occur, and good image display can be realized. Note that the division may be made finer, and the more the division is performed, the more the flicker is reduced. In particular, since the EL element 15 has a high responsiveness, the display luminance does not decrease even if the EL element 15 is turned on / off in a time shorter than 5 μsec.

In the driving method of the present invention, the EL element 15
Since ON / OFF can be controlled by ON / OFF of the signal applied to the gate signal line 17b, the clock frequency can be controlled at a low frequency of KHz order. Further, when the black screen insertion (non-display area 312 insertion) is realized, an image memory or the like is not required. Therefore, the drive circuit or method of the present invention can be realized at low cost.

FIG. 118 shows a case where the pixel rows selected at the same time are two pixel rows. According to the examination result, in the display panel formed by the low temperature polysilicon technology, the display uniformity was practical in the method of simultaneously selecting two pixel rows. this is,
It is presumed that the characteristics of the conversion TFTs 11a of the adjacent pixels are extremely matched. Further, when performing laser annealing, good results were obtained by irradiating the stripe-shaped laser in the irradiation direction parallel to the source signal line 18.

In FIG. 118, when the write pixel row is the (1) th pixel row, (1) and (2) are selected for the gate signal line 17a (see FIG. 119). At this time, the driving TFT 1 of the pixel rows (1) and (2)
1b, the taking-in TFT 11c is in the ON state. Further, since the gate signal line 17b has a phase opposite to that of the gate signal line 17a, at least the switching TFT 11d of the pixel rows (1) and (2) is in the OFF state, and the EL element 15 of the corresponding pixel row has No current is flowing. That is, it becomes the non-display area 312. In FIG. 118, the image display area 311 is divided into five in order to reduce the occurrence of flicker.

[0597] Ideally, a conversion TFT of two pixels (rows)
11a causes a current of Id × 5 (when N = 10) to flow in the source signal line 18, and the capacitor 1 of each pixel 16
9 will be programmed with 5 times the current.

[0598] Two pixel rows (K =
Since it is 2), the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times per pixel flows through the conversion TFT 11a, and a current obtained by adding the program currents of the two conversion TFTs 11a flows through the source signal line 18.

For example, originally, the current to be written in the write pixel row 871a is Id, and the source signal line 18 is
A current of Id × 10 is passed. There is no problem since the regular image data is written in the writing pixel row 871b later. The write pixel row 871b displays the same as the write pixel row 871a during the 1H period.
1a and the write pixel row 871b selected to increase the current are at least the non-display area 312.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (3) to the source driver 14 in the source signal line 18. By operating in this way, the pixel row (1)
Holds regular image data.

After the next 1H, the gate signal line 17a
(2) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (2). At the same time, the gate signal line 17a (4) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (4) to the source driver 14 in the source signal line 18. By operating in this way, the pixel row (2)
Holds regular image data. One screen is rewritten by the above operation and scanning while shifting by one pixel row at a time.

Although it is similar to FIG. 62, in the driving method of FIG. 120, each pixel is programmed with 5 times the current (voltage), so that the emission brightness of the EL element 15 of each pixel is ideally 5 Doubled. Therefore, the brightness of the image display area 311 is five times higher than the predetermined value. In order to set this to a predetermined brightness, as shown in FIG.
The non-display area 312 may include 1 and a range of 1/5 of the display screen 21. Since this has been described with reference to FIG. 90 and the like, description thereof will be omitted.

In the driving method in which a plurality of pixel rows are selected at the same time, it becomes more difficult to absorb the characteristic variation of the conversion TFT 11a as the number of pixel rows selected simultaneously increases. However, if the number of selected pixels decreases, the current programmed for one pixel increases, and a large current flows through the EL element 15. If the current flowing through the EL element 15 is large, E
The L element 15 is likely to deteriorate.

FIG. 121 solves this problem. The basic concept of FIG. 121 is that, in 1 / 2H (1/2 of the horizontal scanning period), a plurality of pixel rows are simultaneously selected as described in FIG.
In 2), as described in FIG. 84, the method of selecting one pixel row is combined. By combining in this way, it is possible to absorb the characteristic variation of the converting TFT 11a and to improve the in-plane uniformity at a higher speed.

In FIG. 121, for ease of explanation, it is assumed that 5 pixel rows are simultaneously selected in the first period and 1 pixel row is selected in the second period.

First, in the first period, as shown in FIG. 121 (a1).
As shown in FIG. 5, 5 pixel rows are simultaneously selected. This operation has been described with reference to FIG. The current passed through the source signal line is 25 times the predetermined value. Therefore, the conversion TFT 11a of each pixel 16 is programmed with a 5 times larger current.
Since the current is 25 times, the parasitic capacitance 404 is charged / discharged in an extremely short time. Therefore, the potential of the source signal line becomes a target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is also programmed so that a five times larger current flows. The application time of this 25 times current is 1 / 2H
(1/2 of one horizontal scanning period).

As a matter of course, the write pixel row 871
Since the same image data is written in the 5 pixel rows, the TFT 11 is turned off in order not to display.
Therefore, the display state is shown in FIG. 121 (a2).

During the next 1 / 2H period, one pixel row is selected,
Perform current (voltage) programming. This state is shown in FIG.
It is illustrated in (b1). The write pixel row 871a is current (voltage) programmed so as to flow 5 times as much current as before. Here, FIG. 121 (a1) and FIG. 121 (b)
The reason why the currents passed through the pixels are the same in 1) is to reduce the programmed change in the terminal voltage of the capacitor 19 so that the target current can flow faster.

That is, in FIG. 121 (a1), a current is caused to flow through a plurality of pixels, and the values are brought close to a value at which an approximate current flows at high speed. In the first stage, since the programming is performed by the plurality of conversion TFTs 11a, an error occurs due to the variation of the TFT with respect to the target value. However, in the second stage,
Select only the pixel rows to write and hold data,
A complete program is performed from a rough target value to a predetermined target value.

Note that scanning the non-display area 312 from the top of the screen to the bottom and scanning the write pixel row 871a from the top to the bottom of the screen are shown in FIGS. 45, 46, and 84.
The description is omitted because it is similar to the embodiment described above.

FIG. 122 shows drive waveforms for realizing the drive method shown in FIG. As shown in FIG. 121, 1H
The (one horizontal scanning period) is composed of two phases and is switched by the ISEL signal. The ISEL signal is shown in FIG.

First, the ISEL signal will be described. In FIG. 123, the current output circuit 1222 includes 122
2a and 1222b. Each current output circuit 1222 outputs 8-bit gradation data to D
It is composed of a DA circuit 1226 for A conversion, an operational amplifier 1224 and the like. The circuit operation of the current output circuit 1222 has been described above, and will be omitted. In the embodiment of FIG. 121, the current output circuit 1222a is configured to output 25 times the current. On the other hand, the current output circuit 122
2b is configured to output 5 times the current. The outputs of the current output circuits 1222a and 1222b are applied to the source signal line 18 with the switch circuit 1223 controlled by the ISEL signal.

When the ISEL signal is at the L level, the current output circuit 1222a that outputs 25 times the current is selected and the source driver 14 absorbs the current from the source signal line 18. Current output circuit 1 that outputs 5 times the current at H level
222b is selected and the source driver 14 absorbs the current from the source signal line 18. Thus, the resistance 122
Since it is only necessary to change the value of 8, it is easy to change the magnitude of the current such as 25 times or 5 times. Also, the resistor 1228
Can be easily changed by setting it as a volume, or by connecting it to a plurality of resistors and an analog switch and selecting it.

As shown in FIG. 122, when the write pixel row is the (1) th pixel row (see the column of pixel row number 1 in FIG. 122), the gate signal line 17a is (1), (2),
(3), (4), and (5) are selected. That is, the driving TFT 11b and the capturing TFT 11c of the pixel rows (1), (2), (3), (4), and (5) are in the ON state.
Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. The off voltage Vgh is applied to the gate signal line 17b. Therefore, the switching TFTs 11d of the pixel rows (1), (2), (3), (4), and (5) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. It becomes the non-display area 312.

[0615] Ideally, the conversion TFT 11a of 5 pixels
Respectively, a current of Id × 2 flows through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of the conversion TFTs 11a match.

There are 5 pixel rows (K =
Since it is 5), the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the conversion TFT 11a. The source signal line 18 has 5
A current that is the sum of the program currents of the two conversion TFTs 11a flows. For example, in the writing pixel row 871a, originally,
The write current is Id, and the source signal line 18 has Id
Apply a current of × 25. The write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18. However, since normal image data is written in the write pixel row 871b later, there is no problem.

Therefore, the write pixel row 871b is
During the 1H period, the same display as the writing pixel row 871a is performed. Therefore, the write pixel row 871a and the write pixel row 871b selected for increasing the current are at least the non-display area 312.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the writing pixel row 871a, that is, only the (1) th pixel row is selected. As is apparent from FIG. 122, the ON voltage Vgl is applied only to the gate signal line 17a (1), and the gate signal lines 17a (2), (3), (4),
The off voltage Vgh is applied to (5). Therefore, the conversion TFT 11a in the pixel row (1) is in an operating state (a state in which current is supplied to the source signal line 18),
Driving TFTs for pixel rows (2), (3), (4), (5)
11b and the take-in TFT 11c are in the off state, that is, in the non-selected state. Also, because ISEL is at H level,
The current output circuit 1222b that outputs a quintuple current is selected, and the current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b is the same as the previous 1 / 2H state, and the off voltage Vgh is applied. Therefore, pixel rows (1), (2),
Switching TFT 11d of (3), (4), and (5)
Is in the off state, no current flows through the EL element 15 of the corresponding pixel row, and the EL element 15 becomes the non-display area 312.

From the above, the conversion T of the pixel row (1) is
The FT 11a sends a current of Id × 5 to the source signal line 18, and the capacitor 19 of each pixel row (1) receives 5
Double current is programmed.

In the next horizontal scanning period, one pixel row and the writing pixel row are shifted. That is, this time is the time when the write pixel row is (2). In the first 1 / 2H period, FIG.
As shown in 2, when the writing pixel row is the (2) th pixel row, the gate signal lines 17a are (2), (3), (4),
(5) and (6) are selected. That is, the driving TFs of the pixel rows (2), (3), (4), (5), and (6)
The T11b and the taking-in TFT 11c are in the ON state. Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. Also, the gate signal line 17b
The off voltage Vgh is applied to (2), (3), (4), (5), and (6). Therefore, the switching TFTs 11d of the pixel rows (2), (3), (4), (5), and (6) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. Non-display area 31
It becomes 2. On the other hand, the gate signal line 17b of the pixel row (1)
Since the Vgl voltage is applied to (1), the switching TFT 11d is in the ON state, and E of the pixel row (1) is
The L element 15 lights up.

[0621] 5 pixel rows (K =
Since it is 5), the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the conversion TFT 11a. The source signal line 18 has 5
A current that is the sum of the program currents of the two conversion TFTs 11a flows.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(2) Only the pixel row is selected. As is apparent from FIG. 122, only the gate signal line 17a (2) has the on-voltage Vg
1 is applied to the gate signal lines 17a (3), (4),
The off voltage Vgh is applied to (5) and (6).
Therefore, the conversion TFTs 11 of the pixel rows (1) and (2)
Although a is an operating state (current is flowing to the EL element 15 in the pixel row (1) and current is supplied to the source signal line 18 in the pixel row (2)), pixel rows (3), (4 ), (5),
The driving TFT 11b and the capturing TFT 11c in (6) are in the OFF state, that is, in the non-selected state. Further, since ISEL is at the H level, the current output circuit 1222b that outputs a quintuple current is selected, and this current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b is the same as the previous 1 / 2H state,
The off voltage Vgh is applied. Therefore, the switching TFTs 11d of the pixel rows (2), (3), (4), (5), and (6) are in the off state, and no current flows in the EL element 15 of the corresponding pixel row. Non-display area 31
It becomes 2.

From the above, the conversion T of the pixel row (2) is
The FT 11a causes a current of Id × 5 to flow in the source signal line 18. Then, the capacitors 19 of each pixel row (2)
Is programmed with 5 times the current. One screen can be displayed by sequentially performing the above operations.

In the driving method described in FIG. 121, G pixel rows (G is 2 or more) are selected in the first period, and N pixel rows are selected.
Program to flow double the current. In the second period after the first period, a B pixel row (B is smaller than G and is 1 or more) is selected, and programming is performed so that N times the current flows through the pixel.

However, there are other measures. G in the first period
Pixel rows (G is 2 or more) are selected and programmed so that the total current of each pixel row is N times the current. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more) are selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times. For example, in FIG.
In 1 (a1), when 5 pixel rows are simultaneously selected and a double current is supplied to the conversion TFT 11a of each pixel, a 5 × 2 = 10 times current flows through the source signal line 18. In the next second period, in FIG. 121 (b1), one pixel row is selected, and a 10-fold current is passed through the conversion TFT 11a of this one pixel.

With this method, a plurality of current output circuits 1222 are not required as shown in FIG. 123, and the source driver 14 has one current output circuit 12 for each source signal line.
22 can be configured. In other words, in this method, the output current of the source driver 14 that allows the current of the source signal line 18 to flow is a constant value (naturally, this constant value changes depending on the image data. In this case, the number of selected pixels is changed to 1H period. No matter what,
It means constant). Therefore, the configuration of the source driver 14 becomes easy.

In FIG. 121, the period for simultaneously selecting a plurality of pixel rows is 1 / 2H and the period for selecting one pixel row is 1 / 2H, but the invention is not limited to this. For example, the period for simultaneously selecting a plurality of pixel rows is 1 /
4H, and the period for selecting one pixel row may be 3 / 4H. In addition, a period for simultaneously selecting a plurality of pixel rows and 1
The period including the period for selecting the pixel row is set to 1H, but is not limited to this. For example, in the 2H period,
The period may be 1.5H.

Also, in FIG. 121, the period for simultaneously selecting five pixel rows is set to 1 / 2H, and 2H is set for the next second period.
The pixel rows may be selected at the same time. Even in this case, it is possible to realize image display without any trouble in practical use.

In FIG. 121, the first period for simultaneously selecting 5 pixel rows is set to 1 / 2H and the second period for selecting 1 pixel row is set to 1 / 2H. However, the present invention is not limited to this. It is not something that will be done. For example, in the first stage, 5 pixel rows are simultaneously selected, in the second period, 2 pixel rows are selected from the 5 pixel rows, and finally, 1 pixel row is selected.
It may be one stage. That is, the image data may be written in the pixel rows in a plurality of stages.

In FIG. 123, each source signal line 18 is provided with two current output circuits 1222.
This is to output the current of 25 times in the first period, which is the first embodiment of No. 21, and to output the current of 5 times in the second period. To realize this with one current output circuit 1222, the circuit configuration in FIG. 120 may be adopted. DA
The circuit 1226 performs digital-analog conversion with the magnitude of the reference voltage (Iref) as the maximum value. For example, if the Iref voltage is 5V, 5V divided into 256 is output as an analog value as the minimum value. That is, the maximum value of the analog output is a 5V-1 bit analog value, the minimum value is 0V, and the minimum resolution is 5V / 256 (when the input is the 8-bit specification). If the Iref voltage is 2.
If it is 5V, a value obtained by dividing 2.5V into 256 is analog-outputted as the minimum value. That is, the maximum value of the analog output is a 2.5V-1 bit analog value, the minimum value is 0V, and the minimum resolution is 2.5V / 256 (when the input is an 8-bit specification).

That is, the output current value can be changed by one current output circuit 1222 by dynamically switching the Iref voltage. FIG. 120 shows a realizing circuit.

In FIG. 120, a resistor RI that divides the Vi voltage into four is provided. The divided voltage is input to the switch circuit 1223, and one voltage is selected and becomes the Iref voltage. This Iref voltage is the operational amplifier 1
224 is input. Therefore, the first half of 1 / 2H
Iref voltage in the period of and the Ir in the latter half period of 1 / 2H
By switching the ef voltage and the current output circuit 1222 connected to all the source signal lines 18, the magnification of the output current can be changed. Of course, as shown in FIG.
It may be generated by selecting 24.

Also in the case of FIG. 123, the number of image display areas 311 may be one as shown in FIG. Also, FIG.
As shown in FIG. 26, it may be divided into a plurality of image display areas 311.

As shown in FIG. 127, when the write pixel row is the (1) pixel row, the gate signal lines 17a are (1), (2), (3), (4) and (5). It is selected. That is, pixel rows (1), (2), (3),
(4) and (5) driving TFT 11b and loading TFT 1
1c is on. Since ISEL is at L level, the current output circuit 1222a that outputs 25 times the current
Is selected and connected to the source signal line 18. In addition, the gate signal lines 17b (1), (2), (3),
The off voltage Vgh is applied to (4) and (5). Therefore, pixel rows (1), (2), (3),
The switching TFT 11d in (4) and (5) is in the OFF state, and no current flows in the EL element 15 of the corresponding pixel row, and the area becomes the non-display area 312.

[0635] The pixel rows selected simultaneously are 5 pixel rows (K =
Since it is 5), the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the conversion TFT 11a. The source signal line 18 has 5
A current that is the sum of the program currents of the two conversion TFTs 11a flows. For example, in the writing pixel row 871a, originally,
The write current is Id, and the source signal line 18 has Id
Apply a current of × 25. The write pixel row 871b for writing image data after the write pixel row (1) is an auxiliary pixel row used to increase the amount of current to the source signal line 18, but the write pixel row 871b is used later for a regular image. There is no problem because the data is written.

Accordingly, the write pixel row 871b is
During the 1H period, the same display as the writing pixel row 871a is performed. Therefore, the write pixel row 871a and the write pixel row 871b selected for increasing the current are at least the non-display area 312.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(1) Only the pixel row is selected. Gate signal line 17a
The on voltage Vgl is applied only to (1), and the off voltage Vgh is applied to the gate signal lines 17a (2), (3), (4), and (5). Therefore, although the conversion TFT 11a of the pixel row (1) is in the operating state (the state in which the current is supplied to the source signal line 18), the pixel row (2),
The driving TFT 11b and the loading TFT 11c in (3), (4), and (5) are in the off state, that is, in the non-selected state.
Further, since ISEL is at the H level, the current output circuit 1222b that outputs a quintuple current is selected, and this current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b is the same as the previous 1 / 2H state, and the off voltage Vgh is applied.
Therefore, pixel rows (1), (2), (3), (4),
The switching TFT 11d of (5) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row, which becomes the non-display area 312.

From the above, the conversion T of the pixel row (1) is
The FT 11a sends a current of Id × 5 to the source signal line 18, and the capacitor 19 of each pixel row (1) receives 5
Double current is programmed.

In the next horizontal scanning period, one pixel row and the writing pixel row are shifted. That is, this time is the time when the write pixel row is (2). In the first 1 / 2H period, the gate signal line 17a is (2), (3), (4), (5),
(6) is selected. That is, pixel row (2),
Driving TFT 11 of (3), (4), (5), and (6)
b, the take-in TFT 11c is on. Also, IS
Since EL is at L level, the current output circuit 1222a that outputs 25 times the current is selected and connected to the source signal line 18. In addition, the gate signal line 17b (2),
The off voltage Vgh is applied to (3), (4), (5), and (6).
Is being applied. Therefore, pixel row (2),
Switching TFs of (3), (4), (5), and (6)
Since T11d is in the OFF state, no current flows in the EL element 15 of the corresponding pixel row, and the EL element 15 becomes the non-display area 312. On the other hand, since the Vgl voltage is applied to the gate signal line 17b (1) of the pixel row (1), the switching T
The FT 11d is in the ON state, and the EL element 15 of the pixel row (1) is lit.

There are five pixel rows (K =
Since it is 5), the five conversion TFTs 11a operate. That is, a current of 25/5 = 5 times per pixel flows through the conversion TFT 11a, and a current obtained by adding the program currents of the five conversion TFTs 11a flows through the source signal line 18.

In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 871a is selected. That is,
(2) Only the pixel row is selected. Gate signal line 17a
The on voltage Vgl is applied only to (2), and the off voltage Vgh is applied to the gate signal lines 17a (3), (4), (5), and (6). Therefore, pixel row (1),
The conversion TFT 11a of (2) is in an operating state (pixel row (1)
Is a state in which a current is supplied to the EL element 15 and a pixel row (2) is supplying a current to the source signal line 18), but the pixel rows (3), (4), (5) and (6) Driving TFT 11
b, the take-in TFT 11c is in the off state, that is, in the non-selected state. Further, since ISEL is at the H level, the current output circuit 1222b that outputs a quintuple current is selected, and this current output circuit 1222b and the source signal line 18 are connected. The state of the gate signal line 17b is 1
There is no change from the state of / 2H, and the off voltage Vgh is applied. Therefore, pixel rows (2), (3), (4),
The switching TFT 11d of (5) and (6) is in the off state, and no current flows in the EL element 15 of the corresponding pixel row, and the area becomes the non-display area 312.

From the above, the conversion T of the pixel row (2) is
The FT 11a sends a current of Id × 5 to the source signal line 18, and the capacitor 19 of each pixel row (2) receives 5
Double current is programmed. One screen can be displayed by sequentially performing the above operations.

As is apparent from the above description, the above operation is the same as in FIG. The difference is the gate signal line 1
The gate signal line 17b is turned on / off (Vgl and Vgh) by the number corresponding to the number of divided screens.

As shown in FIG. 126, the scanning direction of the non-display area 312 is not limited to the top to bottom direction of the screen. Scanning may be performed from the bottom of the screen upward. Further, the scanning direction from the upper side to the lower side and the scanning direction from the lower side to the upper side may be alternately or randomly scanned. It goes without saying that the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.

As described above, the flicker on the screen is reduced by dividing the image display area 311 into a plurality of areas. Therefore, flicker does not occur and good image display can be realized. The division may be made finer, and the more the division is performed, the more the flicker is reduced. In particular, the EL element 15
Since the response is fast, the display brightness does not decrease even if it is turned on / off in a time shorter than 5 μsec.

Also in the embodiment shown in FIG. 127, G pixel rows (G is 2 or more) are selected in the first period, and programming is performed so that N times the current flows in each pixel row, and after the first period. In the second period, B pixel rows (B is smaller than G and is 1 or more) are selected,
The pixel is programmed so as to flow N times the current. However, similar to FIG. 122, there are other measures. That is, in the first period, G pixel rows (G is 2 or more) are selected,
It is programmed so that the total current of each pixel row is N times the current. In the second period after the first period, B pixel rows (B is smaller than G and is 1 or more) are selected, and the total current of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times.

The above embodiments are methods of displaying an image by progressive scanning. That is, in terms of television signals, non-interlaced drive (progressive drive) is used. The present invention is also effective for interlaced driving. FIG. 128 is an explanatory diagram of interlaced driving.

The interlaced drive is normally 2 fields and 1 frame. Fig. 128 is also 1 in 2 fields
It has been described as a frame (one screen). But this is N
In the case of a TSC television signal, it is not always necessary to follow the principle of 2 fields = 1 frame in the image display of a mobile phone or the like.

For example, four fields may be one frame. The first field writes 4Y-3 (Y is an integer of 0 or more) pixel rows, and the second field writes 4Y-2 (Y
Is an integer of 0 or more). The third field writes 4Y-1 (Y is an integer of 0 or more) pixel rows,
The fourth field is a method of writing 4Y (Y is an integer of 0 or more) pixel rows. That is, the interlaced drive is a method of forming one frame (one screen) with a plurality of fields.

FIG. 128 (a) shows the first field,
Write even pixel rows. FIG. 128B shows the second field in which odd pixel rows are written. FIG. 129 shows FIG.
3 is a drive waveform for realizing the drive method of FIG. The odd field and the even field are for convenience.
In FIG. 128, first, it is assumed that an image is written from odd-numbered pixel rows.

Referring to FIG. 128, gate signal line 17a
When (1) is selected (Vgl voltage), a program current flows from the conversion TFT 11a of the selected pixel row to the source driver 14 in the source signal line 18. Here, for ease of explanation, first, the write pixel row 871a
Is the pixel row (1) -th row.

Also, the program current flowing through the source signal line 18 is N times the predetermined value (for the sake of simplicity, the description will be made assuming that N = 10 as in the above embodiments. N =
It is not limited to 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ).

In FIG. 129, when the writing pixel row is the (1) th pixel row, the Vgl voltage is applied to the gate signal line 17a (1), and the driving TFT 11b and the capturing TFT 11c are turned on. Also, the gate signal line 1
The Vgh voltage is applied to 7b (1). Therefore, the switching TFT 11d of the pixel row (1) is in the off state, no current flows in the EL element 15 of the corresponding pixel row, and the area becomes the non-display area 312.

In the next 1H, the writing pixel row is the (3) th pixel row. The Vgl voltage is applied to the gate signal line 17a (3), and the driving TFT 11b and the capturing TFT 11 are
c is turned on. Also, the gate signal line 17b (3)
Is applied with a Vgh voltage. Therefore, the switching TFT 11d of the pixel row (3) is in the OFF state, and no current flows in the EL element 15 of the corresponding pixel row, and the EL element 15 becomes the non-display area 312. Also, the gate signal line 1
The Vgl voltage is applied to 7b (1), and the switching TFT 11d is in the ON state. Therefore, the switching TFT 11d of the pixel row (1) is also in the ON state, and the EL element 15 of the corresponding pixel row emits light.

At the next 1H, the writing pixel row is the (5) th pixel row. The Vgl voltage is applied to the gate signal line 17a (5), and the driving TFT 11b and the capturing TFT 11 are
c is in the on state. Also, the gate signal line 17b (5)
Is applied with the Vgh voltage, the switching TFT 11d of the pixel row (5) is turned off, no current is flowing through the EL element 15 of the corresponding pixel row, and the non-display area 3
Twelve. In addition, Vg is applied to the gate signal line 17b (3).
The l voltage is applied, and the switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (3) is also in the ON state, and E of the corresponding pixel row is
The L element 15 emits light.

As described above, in the first field, the odd pixel rows are sequentially selected and the image data is written.

In the second field, image data is sequentially written from (2) pixel row. Gate signal line 17
The Vgl voltage is applied to a (2), and the driving TFT 11
b, the taking-in TFT 11c is turned on. In addition, the Vgh voltage is applied to the gate signal line 17b (2), the switching TFT 11d of the pixel row (2) is turned off, and no current flows in the EL element 15 of the corresponding pixel row. It becomes the display area 312.

In the next 1H, the writing pixel row is the (4) th pixel row. The Vgl voltage is applied to the gate signal line 17a (4), and the driving TFT 11b and the capturing TFT 11 are
c is turned on. Also, the gate signal line 17b (4)
Is applied with the Vgh voltage, the switching TFT 11d of the pixel row (4) is turned off, no current is flowing through the EL element 15 of the corresponding pixel row, and the non-display area 3
Twelve. In addition, Vg is applied to the gate signal line 17b (3).
The l voltage is applied, and the switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (3) is also in the ON state, and E of the corresponding pixel row is
The L element 15 emits light.

In the next 1H, the writing pixel row is the (6) th pixel row. The Vgl voltage is applied to the gate signal line 17a (6), and the driving TFT 11b and the capturing TFT 11 are
c is turned on. In addition, the gate signal line 17b (6)
Is applied with the Vgh voltage, the switching TFT 11d of the pixel row (6) is turned off, no current flows through the EL element 15 of the corresponding pixel row, and the non-display area 3
Twelve. In addition, Vg is applied to the gate signal line 17b (4).
The l voltage is applied, and the switching TFT 11d is in the on state. Therefore, the switching TFT 11d of the pixel row (4) is also in the ON state, and the E of the corresponding pixel row is
The L element 15 emits light.

As described above, in the second field, the even pixel rows are sequentially selected and the image data is written. One image display is completed in the first field and the second field. In the second field, when writing even pixel rows, all odd pixel rows are in the non-display area 31.
2 In the first field, when writing the odd pixel rows, all the even pixel rows are the non-display area 312.

However, with the driving method of FIG. 128, a 10 times larger current (N = 10) is made to flow through the source signal line 18, and the conversion T
When the FT 11a is current-programmed, the display brightness becomes 10/2 = 5 times the predetermined brightness even if the processing of alternately displaying the odd pixel rows or the even pixel rows is performed. Therefore, it is necessary to drive with N = 2 in order to increase the display brightness by one. However, when driven with N = 2, the current value written in the source signal line 18 is small and the parasitic capacitance 404
Cannot be sufficiently charged and discharged, so that insufficient writing occurs in the capacitor 19 and the resolution deteriorates.

To solve this, as shown in FIG. 130, not only the odd pixel rows or the even pixel rows but
A part of the display screen 21 may be the non-display area 312a. In FIG. 130, scanning is performed in the order of FIG. 130 (a) → FIG. 130 (b) → FIG. 130 (c) → FIG. 130 (a). FIG.
As can be seen from (b), a display area is formed in a predetermined range on the upper side (when scanning is performed from the top to the bottom of the screen) of the write pixel row 871a. However, since the display area is an odd-numbered pixel row or an even-numbered pixel row, it is set for each one pixel row. The non-display area 312a is a continuous non-display area.

However, if the display area is partially fixed on the display screen and scanned as in the driving method shown in FIG. 130, flicker is likely to occur. However, the frame rate is 80H
In the case of z or more, the display state of FIG. 130 (image display area 3
It should be noted that flicker does not occur even when 11 is set to one). In other words, the frame rate is 80
If it is set to Hz or higher, it is not necessary to divide the image display area 311.

If the frame rate is low, it may be divided as shown in FIG. Since this has been described above, FIG. 131 will not need any explanation. However, in FIG. 131, a pair of the non-display area 312b and the image display area 311 is used as a divided area in order to facilitate drawing, but the drawing is not limited to this, and a plurality of hidden areas may be displayed in the divided area. There is no problem even if the area 312b and the plurality of image display areas 311 exist.

A variety of configurations can be considered for the drive system. In FIG. 132, when the writing pixel row is the (1) th pixel row, (1) and (G) are selected as the gate signal line 17a. That is, the driving TFTs 11b and the capturing TFTs 11c of the pixel rows (1) and (G) are in the ON state.
Further, the Vgh voltage is applied to the gate signal line 17b. Therefore, at least the switching TFTs 11d of the pixel rows (1) and (G) are in the OFF state, no current flows in the EL element 15 of the corresponding pixel row, and the EL element 15 becomes the non-display area 312.

[0666] Two pixel rows (K =
Since it is 2), the two conversion TFTs 11a operate. That is, a current of 10/2 = 5 times per pixel flows through the conversion TFT 11a. The source signal line 18 has 2
A current that is the sum of the program currents of the two conversion TFTs 11a flows.

After the next 1H, the gate signal line 17a
(G) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (G). At the same time, the gate signal line 17a (2) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (2) toward the source driver 14 to the source signal line 18. By operating in this way, the pixel row (G)
Holds regular image data.

After the next 1H, the gate signal line 17a
(1) is not selected, and the ON voltage Vgl is applied to the gate signal line 17b (1). At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and the program current flows from the conversion TFT 11a of the selected pixel row (3) to the source driver 14 in the source signal line 18. By operating in this way, the pixel row (1)
Holds regular image data. One screen is rewritten by the above operation and scanning while shifting by one pixel row at a time.

If flicker is apt to occur, the operation shown in FIG.
The non-display area 312 or the image display area 311 may be divided into a plurality of areas as shown in FIG. Since this has been described above, FIG. 133 will not need any explanation.

FIG. 134 and FIG. 135 show the pseudo interlace drive. In the pseudo interlace drive, in the first F (first field), two pixel rows (a plurality of pixel rows), an odd pixel row and an even pixel row, are simultaneously selected, and image data is written without overlapping the selected pixel rows. The next 2F is a method of simultaneously selecting two pixel rows (a plurality of pixel rows) of an even pixel row and an odd pixel row except the first pixel row, and writing image data without overlapping the selected pixel rows.

135 (a1), (a2) and (a3) are the first field, and FIG. 135 (b1), (b2),
(B3) is the second field. The first field is as shown in FIG. 135 (a1) → FIG. 135 (a2) → FIG. 135 (a3).
→ is sequentially written and the video data is written in a pair of two pixel row 871. Therefore, two pixel rows display the same image, and this display state is held for one field period. In the first field, the image data of the odd pixel row is displayed on the odd pixel row and the next even pixel row. That is, the image data of the first row is displayed on the first pixel row and the second pixel row, the image data of the third row is displayed on the third pixel row and the fourth pixel row, and the image of the fifth row is displayed. The data is the fifth pixel row and the sixth
The image data is displayed on the pixel row, and the image data on the seventh row is displayed on the seventh pixel row and the eighth pixel row.

The second field is shown in FIG. 135 (b1) → FIG.
35 (b2) → FIG. 135 (b3) → in sequence, video data is written in a pair of writing pixel rows 871 in two pixel row pairs. Therefore, two pixel rows display the same image, and this display state is held for one field period. In the second field, the image data of even pixel rows is displayed on the corresponding even pixel row and the next odd pixel row. That is, the image data of the second row is displayed on the second pixel row and the third pixel row, the image data of the fourth row is displayed on the fourth pixel row and the fifth pixel row, and the image of the sixth row is displayed. The data is displayed on the sixth pixel row and the seventh pixel row, and the image data on the eighth row is displayed on the eighth pixel row and the ninth pixel row.

Note that the first pixel row in FIG. 135 (a1) holds the state of the first field. Further, although the odd-numbered image data is written in the first field and the even-numbered image data is written in the second field, the present invention is not limited to this and may be reversed.

When the image display is performed as described above, it is assumed that the display images of two fields are added together by an afterimage by the human eye, and when one frame (two fields) is completed, the first pixel row is , A display image of the first field. The second pixel row is the first field of the first field.
The image data of the pixel row and the image data of the second pixel row of the second field are added. The third pixel row is a combination of the image data of the third pixel row of the first field and the image data of the second pixel row of the second field. Further, the fourth pixel row is a combination of the image data of the third pixel row of the first field and the image data of the fourth pixel row of the second field. The fifth pixel row is a combination of the image data of the fifth pixel row of the first field and the image data of the fourth pixel row of the second field.

As described above, since each pixel row is formed by superimposing the images of two fields, the contour of the display image is smooth. In particular, although a small amount of moving image blur occurs when displaying a moving image, good resolution can be obtained (recognized as) for almost a still image.

FIG. 136 shows drive waveforms for realizing the display method of FIG. 135. The upper position of the drawing is the drive waveform of the first field (1F), and the lower position of the drawing is the drive waveform of the second field (2F).

In the first field (1F), first,
Gate signal lines 17a (1) of the first pixel row and the second pixel row,
(2) is selected. The source signal line 18 has 10 times (N
= 10) drive current flows, so pixel row (1),
The conversion TFT 11a of (2) is programmed with a current of 5 times each. At this time, the off voltage Vgh is applied to the gate signal lines 17b (1) and (2) of the first pixel row and the second pixel row.
Is applied, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 of the first pixel row and the second pixel row do not light up.

After 2H (2H (because image data is written for each even-numbered pixel row or odd-numbered pixel row, it becomes 2H), the gate signal lines 17a (3), (4) of the third and fourth pixel rows are selected, A drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the conversion TFTs 11a of the pixel rows (3) and (4) are programmed with 5 times the current. At this time, the off voltage Vgh is applied to the gate signal lines 17b (3) and (4) of the third pixel row and the fourth pixel row, and the switching TFT 11d is in the off state. Therefore, the EL elements 15 of the third pixel row and the fourth pixel row do not light up.

On the other hand, the gate signal lines 17b (1), (2)
Since the on-voltage Vgl is applied to the switching TFT, the switching TFT 11d of the first pixel row and the second pixel row is turned on, and
The L element 15 lights up.

After 2H, the gate signal lines 17a (5) and (6) of the fifth pixel row and the sixth pixel row are selected. Since a 10 times (N = 10) driving current flows through the source signal line 18, the conversion TFTs 11a of the pixel rows (5) and (6).
Are programmed at 5 times the current. At this time,
Gate signal lines 17b (5) of the fifth pixel row and the sixth pixel row,
The off voltage Vgh is applied to (6), and the switching TFT 11d is in the off state. Therefore, the EL elements 15 of the fifth pixel row and the sixth pixel row do not light up.

On the other hand, the gate signal line 17b (1),
Since the ON voltage Vgl is applied to (2), (3), and (4), the switching TFTs 11d of the first pixel row, the second pixel row, the third pixel row, and the fourth pixel row are turned on, E
The L element 15 lights up. The above operation is performed up to the last odd pixel line of the screen to display one screen.

In the second field (2F), the first
The pixel row is not selected and the state of the first field is retained. Next, the gate signal lines 17 of the second pixel row and the third pixel row
a (2) and (3) are selected. A drive current 10 times (N = 10) flows through the source signal line 18. Therefore,
The conversion TFTs 11a of the pixel rows (2) and (3) are programmed with a current of 5 times each. At this time, the OFF voltage Vgh is applied to the gate signal lines 17b (2) and (3) of the second pixel row and the third pixel row, and the switching TFT 11
d is an off state. Therefore, the EL elements 15 of the second pixel row and the third pixel row do not light up.

After 2H, the gate signal lines 17a (4) and (5) of the fourth pixel row and the fifth pixel row are selected, and the drive current 10 times (N = 10) flows through the source signal line 18. Therefore, the conversion TFTs 11a of the pixel rows (4) and (5) are programmed with a current of 5 times each. At this time, the gate signal lines 17b (4) of the fourth pixel row and the fifth pixel row,
The off voltage Vgh is applied to (5), and the switching TFT 11d is in the off state. Therefore, the EL elements 15 of the fourth pixel row and the fifth pixel row do not light up.

On the other hand, gate signal lines 17b (2), (3)
Since the on-voltage Vgl is applied to the first pixel row,
Switching TFT 11d for the second pixel row and the third pixel row
Is turned on, and the EL element 15 is turned on.

Further, after 2H, the gate signal lines 17a (6) and (7) of the sixth pixel row and the seventh pixel row are selected, and the source signal line 18 receives a 10 times (N = 10) drive current. Flowing. Therefore, the conversion TFTs of the pixel rows (6) and (7)
Each of 11a is programmed with 5 times the current. At this time, the gate signal lines 17b of the sixth pixel row and the seventh pixel row
The off voltage Vgh is applied to (6) and (7), and the switching TFT 11d is in the off state. Therefore,
The EL elements 15 of the sixth pixel row and the seventh pixel row do not light up.

On the other hand, the gate signal line 17b (1),
ON voltage Vgl is applied to (2), (3), (4), and (5).
Is applied, the TF for switching the first pixel row, the second pixel row, the third pixel row, the fourth pixel row, and the fifth pixel row.
T11d is turned on and the EL element 15 is turned on. The above operation is performed up to the last even pixel row of the screen, and one screen is displayed.

In the above embodiment, one screen is displayed with two fields. FIG. 137 displays one screen with two or more fields. 137 (a) is the first field, FIG. 137 (b) is the second field, and FIG.
(C) is the third field.

In the first field, 4Y-3 (Y is an integer of 1 or more) pixel rows and 4Y-2 pixel rows are write pixel rows 871. Image data is written every two pixel rows. In the second field, the 4Y-1 pixel row and the 4Y pixel row are the write pixel row 871. The previous field is also 2
Image data is written pixel by pixel. In the third field, 4Y-2 pixel rows and 4Y-1 pixel rows are write pixel rows 871. Image data is written every two pixel rows.
By writing in 3F as described above, each pixel data is complemented with image data of a plurality of fields.

Although FIG. 137 shows the embodiment in which one screen is composed of three fields, the image display may be realized by using more fields. For example, in the case of 4 fields, in the first field, 4Y-3 (Y is an integer of 1 or more) pixel rows and 4Y-2 pixel rows are the write pixel rows 871. Image data is written every two pixel rows. In the second field,
The 4Y-1 pixel row and the 4Y pixel row are write pixel rows 871.
Is. In the third field, 4Y-2 pixel rows and 4Y-
One pixel row is the write pixel row 871. Similarly to the above, the image data is written every two pixel rows. In the fourth field, 4Y-3 pixel rows and 4Y pixel rows are write pixel rows 8
71. Similarly, the image data is written every two pixel rows in the previous field. By writing in 4 fields as described above, each pixel data is complemented with image data of a plurality of fields.

The above embodiments have been described mainly by exemplifying the pixel configuration of FIG. 6, but the driving method of the present invention is as shown in FIG.
It is also effective for other current programmed pixel configurations such as FIG. 79.

FIG. 138 is an explanatory diagram of a driving method of the pixel configuration of FIG. 79. Note that, here too, for ease of explanation, the current flowing from the source driver 14 to the source signal line 18 (or
The description will be made assuming that the current drawn in from the driver TFT 11a and the current drawn by the driving TFT 11a into the source signal line 18 are 10 times the predetermined value (N = 10). In addition, the driving TFT 11a and the TFT 1
It is assumed that the current magnification of 1b is 1: 1 (current magnification of 1).

Therefore, if the pixel rows selected at the same time are five pixel rows (K = 5), the five driving TFTs 11a operate. Since the current magnification is 1, the driving TFT
The same current as that of the TFT 11a also flows through 11b. In other words, 10/5 = twice the current per pixel is the driving TF.
It flows to T11a. Since the current programmed in the driving TFT 11a of the pixel 16 is twice the predetermined value, the current flowing through the EL element is also twice. Therefore, the EL element 15 is less deteriorated as compared with the case where a 10 times larger current is passed as shown in FIG. On the other hand, since the current flowing through the source signal line 18 is 10 times, the parasitic capacitance 404 similar to that in FIG.
Can be charged and discharged. This also applies to FIG. 46.

If the current magnification is 2, the driving TFT
The current supplied to the EL element 15 by 11b is 1 time. Therefore, a predetermined current is applied to the EL element 1 so as to obtain a predetermined brightness.
Can be flushed to 5. That is, in the pixel configurations of FIGS. 19 and 79, the current magnification (TFT 11a and TFT 11b
By designing (adjusting) the current ratio of (1) and the current flowing in the source signal line 18 (programming current), it is possible to design a display panel with high versatility.

The number of pixel rows selected at the same time is 5 pixel rows (K =
In the case of 5), the program currents of the five driving TFTs 11a are added. For example, the writing pixel row 87
If the current originally written in 1a is Id and N = 10, a current of Id × 10 is passed through the source signal line 18. The writing pixel row 871b adjacent to the writing pixel row 871a (871b is an auxiliary pixel row used to increase the amount of current to the source signal line 18. Therefore, the pixel (row) in which the image is written is 871a, 87
A writing pixel (row) 871b is used as an auxiliary element for writing to 1a).

In FIG. 138, the write pixel row 871
K lines (K = 5) are simultaneously written with the image data of a. Therefore, the ranges of K rows (871a, 871b) are displayed in the same manner. In this way, when the same display is performed, the resolution is naturally lowered. To deal with this, FIG.
As shown in (b), the portion of the write pixel row 871b is set as the non-display area 312. Therefore, the resolution is not reduced.

The write pixel row 871a shown in FIG. 138 (a) is in the display state, but since this pixel is being programmed, it changes in the state of current writing to the pixel. Therefore, it may be the non-display area 312.

After the next 1H, the same operation is performed with the pixel row shifted by one pixel row as the writing pixel row 871a. The non-display area 312 is also shifted by one pixel (row). As described above, the write pixel row 871b in which the current data different from the original display data is written is not displayed, and a complete image display can be realized by shifting the above operation row by row. In addition, the write pixel row 871b used as an auxiliary
By the effect, the charging and discharging of the parasitic capacitance 404 can be realized sufficiently within 1H period.

FIG. 139 is an explanatory diagram of drive waveforms for realizing the drive method of FIG. 138. In the voltage waveform, the off voltage is Vgh (H level) and the on voltage is Vgl (L level). Further, the number of the selected pixel row is described in the lower part of FIG. 139. In addition, (1) in the figure,
(2), (3) ... (11) indicate the selected pixel row number. The number of pixel rows is 480 in the VGA panel and 768 in the XGA panel.

In FIG. 139, the gate signal line 17a
(1) and the gate signal line 17b (1) are selected (Vgl
Voltage), a program current flows from the driving TFT 11a of the selected pixel row toward the source driver 14 to the source signal line 18. In addition, the program current flowing through the source signal line 18 is N times the predetermined value (for ease of explanation,
The description will be given assuming that N = 10. Of course, since the predetermined value is a data current for displaying an image, it is not a fixed value unless it is a white raster display or the like. ). Also, description will be made assuming that 5 pixel rows are simultaneously selected (K = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that a double current flows through the driving TFT 11a.

Basically, the gate signal lines 17a and 17b
Since and have the same phase, they can be shared. Strictly speaking, however, when selecting or deselecting a pixel row, it is preferable that the switching TFT 11d is first turned off and then the capturing TFT 11c is turned off. Gate signal line 17
It is better to separate it from b.

When the write pixel row is the (1) th pixel row, as shown in FIG. 139, the gate signal line 17a,
An on-voltage Vgl is applied to 17b. Therefore, the pixel rows (1), (2), (3), (4), and (5) are selected. That is, pixel rows (1), (2),
The taking-in TFT 11c and the switching TFT 11d in (3), (4), and (5) are in the ON state. Further, the gate signal line 17b has a phase opposite to that of the gate signal line 17b. Therefore, pixel rows (1), (2), (3),
The switching TFT 11d in (4) and (5) is in the OFF state, and no current flows in the EL element 15 of the corresponding pixel row, and the area becomes the non-display area 312.

Ideally, the driving TFT 11a of 5 pixels
However, a current of Id × 2 is supplied to the source signal line 18, and the capacitor 19 of each pixel 16 is programmed with a double current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of the driving TFTs 11a match.

There are five pixel rows (K =
Since it is 5), the five driving TFTs 11a operate. That is, a current of 10/5 = 2 times per pixel flows through the driving TFT 11a. The source signal line 18 has 5
A current that is the sum of the program currents of the two driving TFTs 11a flows. For example, in the writing pixel row 871a, originally,
The write current is Id, and the source signal line 18 has Id
Apply a current of × 10.

The four write pixel rows 871b for writing image data after the write pixel row (1) are auxiliary pixel rows used to increase the amount of current to the source signal line 18. However, since normal image data is written in the write pixel row 871b later, there is no problem. Therefore, the write pixel row 871b displays the same as the write pixel row 871a during the 1H period. for that reason,
Write pixel row 871 selected to increase current
b is at least the non-display area 312.

After the next 1H (position of pixel row number 6),
The gate signal lines 17a (1) and 17b (1) are not selected, and the data to be written in the pixel is fixed. At the same time,
The gate signal line 17a (6) is selected (position of pixel number 2), and the program current flows from the driving TFT 11a of the selected pixel row (6) to the source driver 14 in the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

After the next 1H, the gate signal line 17a
(2) and 17b (2) are not selected. Further, the gate signal line 17a (7) is selected (Vgl voltage), and the program current flows from the driving TFT 11a of the selected pixel row (7) toward the source driver 14 to the source signal line 18. By operating in this way, the pixel row (2)
Holds regular image data. One screen is rewritten by the above operation and scanning while shifting by one pixel row at a time.

Although it is similar to FIG. 84, in the driving method of FIG. 93, each pixel is programmed with a double current (voltage). Therefore, the emission brightness of the EL element 15 of each pixel is ideally 2 Doubled. Therefore, the brightness of the display screen is twice the predetermined value.

To set this to a predetermined brightness, FIG.
As shown in FIG. 7, the non-display area 312 may include a half of the display screen 21 including the write pixel row 871. Since this has been described with reference to FIG. 90 and the like, description thereof will be omitted. Note that the driving method of FIG. 121 is the same as that of FIGS.
It goes without saying that it is also applicable to 9, FIG. 81, FIG. 86, FIG. Since the description has been given earlier, it will be omitted.

As the area of the black display area (non-display area) 312 occupying the display screen 21 is increased, the moving image display performance is improved. Therefore, as shown in FIG. 94, the image display area 311 may be reduced and the non-display area 312 may be increased in area.

In the embodiment of the present invention, the program current (voltage) can be adjusted by changing the current (voltage) supplied to the source signal line 18. That is, the current flowing through the source signal line 18 can be adjusted only by adjusting the reference current (voltage) of the source driver 14.
21. Whether two pixel rows are turned on at the same time, five pixel rows are turned on at the same time, or only one pixel row is selected is shown in FIG.
The shift register 2 of the gate driver 12 shown in FIG.
It can be set by the data to the ST * terminal applied to 2. Therefore, the specifications of the source driver 14 do not depend on the number of pixels to be selected. Further, since the brightness of the screen can be adjusted by turning on / off the gate signal line 17c, the brightness of the display screen 21 does not change the output current from the source driver 14. Therefore, the EL element 15
The gamma characteristic of 1 may be determined for one current. Therefore, the configuration of the source driver 14 is extremely easy and highly versatile. The above items can be applied to other embodiments of the present invention.

Similar to FIG. 89, when one image display area 311 moves downward from the top of the screen as shown in FIG. 94,
When the frame rate is low, it is visually recognized that the image display area 311 moves. Especially when you close your eyelids
Alternatively, it becomes easier to be recognized when the face is moved up and down. For this problem, as shown in FIG. 116, the image display area 311 may be divided into a plurality of areas.

As shown in FIG. 116 (b), the scanning direction of the non-display area 312 is not limited to the upper direction of the screen and the lower direction of the screen. Good. Further, the scanning direction from the upper side to the lower side and the scanning direction from the lower side to the upper side may be alternately or randomly scanned. It goes without saying that the number of divisions may be changed for each frame or at a predetermined position on the display screen 21.

As described above, by dividing the image display area 311 into a plurality of areas, the flicker of the screen is reduced, flicker does not occur, and good image display can be realized. Note that the division may be made finer, and the more the division is performed, the more the flicker is reduced. In particular, since the EL element 15 has a high responsiveness, the display luminance does not decrease even if the EL element 15 is turned on / off in a time shorter than 5 μsec.

45 and 46 have been described by exemplifying the pixel configuration of the current programming method as shown in FIGS. 6, 79 and 19, but the invention is not limited to this. For example, in FIG.
It is also effective in the pixel configurations of the voltage programming method such as 1, FIG. 86, and FIG. 87. By applying a voltage to a plurality of pixel rows at the same time, the pixels can be precharged, so that a high-definition display panel of SXGA or higher can be supported. In addition, the electric drive circuit and the signal processing circuit are simplified, and good black display can be realized.

As an application example of the voltage program, the pixel configuration of FIG. 81 will be exemplified and described. Note that FIG. 140 and FIG.
1 is the drive waveform. In FIG. 140 and FIG. 141, the description will be given assuming that the non-display area 312 includes five pixel rows, but the present invention is not limited to this, and is merely for facilitating the description. For example, two pixel rows may be simultaneously selected or ten pixel rows may be selected. Further, one pixel row may be the non-display area 312. This is shown in FIG. 85, FIG. 86, and FIG.
The same applies to 7 and the like.

Further, with respect to the pixel configuration of the voltage program shown in FIGS. 81, 85, 86, 87, etc., FIG.
18, FIG. 121, FIG. 125, FIG. 126, FIG. 128, FIG.
The driving method described in 37 or the like can be applied.
It goes without saying that a driving method in which the non-display area 312 is formed by driving the EL element 15 so that N times the current flows can be applied. However,
40 and FIG. 141, the description is complicated and will not be described.

As shown in FIG. 141, when the writing pixel row is the (1) th pixel row (the position of the pixel row number 5), (1), (2), (3), and (4),
(5) is selected. That is, pixel row (1),
(2), (3), (4), (5) driving TFT 11b
Is on, and the off voltage Vgh is applied to the gate signal line 17b. Therefore, pixel row (1),
(2), (3), (4), (5) switching TF
Since T11d is in the OFF state, no current flows in the EL element 15 of the corresponding pixel row, and the EL element 15 becomes the non-display area 312. Therefore, the pixel row (1) is precharged with the voltage for a period of 5H.

The precharged pixel row has the same display as the other 4 pixel rows during the 5H period. Therefore, at least the pixel row in which writing is performed is the non-display area 312. Especially, in the video signal, since the video data is similar in the adjacent pixels, the pre-charging facilitates the writing of the regular image data.

Therefore, the present invention is a method of writing the image data in a plurality of pixel rows and setting the non-display area 312 until the regular image data is written. However, 1
Even if a pixel row is selected, the display is unstable when the image data of this pixel row is being written, so that it is also a concept of the present invention to make it non-display. In addition, the current flowing through the EL element 15 is made larger than a predetermined value, and the non-display area 312 is
To form a predetermined brightness. It is also an effect of the present invention to realize a good moving image by this display method.

At the next 1H, (2) the image data of the pixel row is fixed. As is clear from FIG. 141, an off voltage (Vgl: since the TFT 11b is the N channel) is applied to the gate signal line 17a (1) and the gate signal line 17b (1) (pixel row number 6). Gate signal line 17a (6)
And the gate signal line 17b (6), the on-voltage (Vgh: T
(Because FT11b is the N channel) is applied. Therefore, the image data to the conversion TFT 11a of the pixel row (2) is held.

As described above, 1 is synchronized with the horizontal scanning period.
By shifting the pixel rows and the writing pixel rows and sequentially performing the above operation, one screen can be displayed.

FIG. 140 shows a method in which the timing of the gate signal line 17b is shifted by 1H in the pixel configuration of FIG. As is clear from FIG. 140, the pixel to be set is brought into the display state.

For example, in the pixel row (1), image data is written for a period of 5H (period of pixel row numbers 1 to 5). That is, the gate signal line 17a of the pixel row (1) is in the selected state (the ON voltage Vgh is applied because the TFT 11b is the N channel). At 5H, the gate signal line 17b (1) has an on-voltage (Vgl: TFT1).
Since 1d is applied to the P channel), E
A current is flowing through the L element 15. Therefore, the EL element 15 is in a lighting state. This point is different from FIG. Although the non-display area 312 is shown in FIG. 141, the other points are the same as those in FIG.

In the embodiment of the present invention in which a plurality of pixel rows are simultaneously turned on to write image data, the uppermost side or the lowermost side of the display screen 21 or both pixel rows are adjacent to each other for being turned on at the same time. There is no pixel row. To solve this problem, dummy pixel rows may be formed or arranged on the uppermost side or the lowermost side of the display screen 21, or both.

For example, in the driving method of simultaneously selecting 5 pixel rows described in FIG. 92, 4 pixel rows are formed on the lower side of the screen. Of course, when the upside-down driving is performed, four dummy pixel rows are also provided on the upper side of the screen. Since the EL element 15 is not formed in this dummy pixel row, it does not emit light. Of course, even if the EL element 15 is formed, it does not emit light or is shielded from light so that it is not displayed. In addition, in FIG. 6, other than the switching TFT 11d for one pixel may be formed. It should be noted that one or more dummy pixel rows are formed.

Although it has been stated that adjacent pixel rows are turned on at the same time, the present invention is not limited to this. For example, the timing of turning on a plurality of pixel rows may be different. Further, the effect is exhibited even if the first row is separated from the third row to the second pixel row. In the extreme, when selecting two pixel rows, one pixel row is fixed (for example, the bottom pixel row or a dummy pixel row on the screen) and turned on, and another one pixel row is scanned and sequentially turned on. You may let me.

FIG. 6, FIG. 19, FIG. 62, FIG. 72, FIG.
This is a common matter in the current programming method shown in FIG. 73 and the like, but there is a problem that black display in the current programming method is difficult (of course, the present invention shown in FIGS. 45 and 46 can be greatly improved. Further, it is also effective to combine with the following embodiments. Of course, the following embodiments may be carried out independently without combining with the embodiments of FIGS. For example, even if the white peak current flowing through the EL element 15 is 2 μA, the first gradation in 64 gradation display is 2 μA / 64≈30 nA. It is difficult to charge and discharge the parasitic capacitance 404 such as the source signal line 18 with this minute current in the 1H period. Although the pixels 16 are formed or arranged in a matrix, only one pixel is shown in the drawings for ease of explanation.

To address this problem, in the present invention, the voltage source 401 for writing the black level voltage (current) to the source signal line 18 is formed or arranged. Specifically, the voltage source 401 is configured so that a predetermined voltage is generated by a DC / DC converter, and this voltage can be applied by the power source switching means 403 including an analog switch or the like.

A specific example of the signal waveform applied to the source signal line 18 is shown in FIG. During the first t2 period of the 1H period in which the current program is performed, the source signal line 18 of the driving TFT 11b (converting TFT 11a in FIG. 6 and the like) is applied with the voltage Vb for turning off or displaying almost black. This voltage is generated by the voltage source 401 and is applied to the source signal line 18 by the power source switching means 403. During the program period, the take-in TFT 11c and the switching TFT 11d are in the ON state, so the voltage Vb applied to the source signal line 18
Is the terminal voltage of the capacitor 19, that is, the driving TFT 1
The gate terminal voltage is 1b. Therefore, the first pixel in the 1H period is in black display (non-lighting state).

Originally, when the displayed image is black,
The terminal voltage of the capacitor 19 is maintained as it is. When the image actually displayed is white display, the voltage Vw for white display (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. It is held at 19 and the 1H period ends. Here, for ease of explanation, it is assumed that the voltage Vw (current Iw) for white display is applied because the image actually displayed is white display. But, of course,
In the case of a natural image, the voltage held in the capacitor 19 is V
It is a voltage (current) between b and Vw.

As shown in FIG. 142, by applying a signal to the source signal line 18 and driving the gate signal lines 17a and 17b, good black display can be realized, and the image display of FIG. 49 and the like can be realized. Can be implemented.

Even with the pixel configuration of FIG. 6, good black display can be realized by applying the signal waveform of FIG. 142. During the first t2 period of the 1H period in which the current program is performed, the conversion T
A voltage Vb for turning off or displaying almost black is applied to the source signal line 18 of the FT 11a. This voltage is generated by the voltage source 401, and the source signal line 1 is generated by the power source switching means 403.
8 is applied.

[0733] In the program period, the driving TFT 11b,
Since the capturing TFT 11c is in the ON state, the voltage Vb applied to the source signal line 18 becomes the terminal voltage of the capacitor 19, that is, the gate terminal voltage of the converting TFT 11a. Therefore, the first pixel in the 1H period is in black display (non-lighting state).

As described above, when the displayed image is black, the terminal voltage of the capacitor 19 is maintained as it is. When the image actually displayed is white display, the voltage Vw for white display (which should be expressed as Iw in the case of current programming) is applied after the Vb voltage is applied, and this voltage (current) is applied to the capacitor. Held in 19 1
The H period ends.

The voltage source 401 (precharge circuit) shown in FIG. 62 or the like may be directly formed on the array substrate 49 by a low temperature polysilicon technique or the like. The EL element 15
Since R, G, and B have different element configurations and materials, the voltage (current) at which light is generated is often different (rising voltage (current)). In order to correspond to this characteristic, R, G,
It is preferable that the B precharge voltage can be set individually, and at least one of the three primary colors can be changed.

Note that the precharge time t2 for applying the Vb voltage needs to be 1 μsec or more. Further, the precharge time t2 for applying the Vb voltage is 1% or more of 1H 1
It is preferably 0% or less, more preferably 2% or more and 8% or less.

Further, it is preferable that the voltage to be precharged can be changed depending on the content (brightness, definition, etc.) of the display screen 21. For example, when the user presses the adjustment switch or turns the adjustment volume, this change is detected and the value of the precharge voltage (current) is changed. You may comprise so that it may change automatically according to the content and data of the image to display. For example, the intensity of external light from the outside is detected by a photo sensor, and the precharge (discharge) voltage (current) is adjusted by the detected value. In addition, the precharge (discharge) voltage (current) is adjusted according to the type of image (computer image, daytime screen, starry sky, etc.). The adjustment is determined in consideration of the average brightness of the image, the maximum brightness, the minimum brightness, the moving image, the still image, and the brightness distribution.

In FIG. 62 and the like, the precharge circuit and the like are briefly described. Further, a more detailed description will be given with reference to FIG. Since the discharge and the precharge are simply directions in which a potential is applied, hereinafter, the discharge and the precharge are synonymous and will be described using the precharge.

FIG. 143 shows a circuit configuration in which current driving and voltage driving are combined. The switch circuit 1223 is connected to the source signal line 18 having a display area and is composed of an analog switch. A voltage is applied to the terminal a of the switch circuit 1223 (precharge voltage), and a program current for programming the pixel is applied to the terminal b.

The current output circuit 1222 has 8 bits (25
(6 gradations) IDATA is input, and this IDATA is D
DA conversion is performed by the A circuit 1226 to obtain an analog voltage.
This analog voltage is output transistor (or FE
T) 1227 applied to the base terminal of the operational amplifier 12
It is converted into a current output by the action of 24b and the resistor 1228. The output transistor 1227 and the operational amplifier 12
A voltage-current conversion circuit such as 24 is a general one,
It is well known to those skilled in the art and will not require further explanation.

On the other hand, the voltage output circuit 1221 comprises a buffer circuit including an adjusting volume (VR) 1225 and an operational amplifier 1224a. The adjustment volume 1225 is common to all the source signal lines. This adjustment volume 12
By adjusting 25, the precharge voltage Vb is determined.

When the first precharge voltage Vb in one horizontal scanning period (1H) is applied, the switch circuits 1223 connected to all the source signal lines are connected to the terminal a. Therefore, all the source signal lines 18 are set to the precharge voltage Vb. After that, switch circuit 1
223 is switched to the terminal b, and current data (256 gradations) corresponding to the image is applied to the source signal line 18.
This current data is written in each pixel 16 and E of each pixel is written.
A current flows through the L element 15 to emit light.

In FIG. 143, the precharge voltage Vb is a fixed value, but in FIG.
FIG. 6 is a circuit configuration diagram that allows 56 values (8 bits). In FIG. 144, the voltage output circuit 1221 receives 8-bit VDATA and is converted into an analog voltage by the DA circuit 1226a. The converted analog voltage is input to one terminal of the operational amplifier 1224c and is configured to be adjusted to a predetermined voltage with respect to the reference voltage of the adjustment volume (VR) 1225.

The output of the operational amplifier 1224c is sent to the switch circuit 1223 via the operational amplifier 1224a of the buffer.
It is applied to the a terminal of a. On the other hand, the switch circuit 1223
A current output is applied to the b terminal of a.

VDATA is a voltage corresponding to IDATA. First 1 to 10 μse in one horizontal scanning period (1H)
The precharge voltage Vb corresponding to VDATA is applied during the period c (preferably 1/100 to 1/5 of 1H). At this time, the switch circuits 1223 connected to all the source signal lines are connected to the terminal a. Therefore, each source signal line 18 is connected to VDAT.
The precharge voltage Vb corresponding to A is set. Figure 1
The difference from 43 is that the precharge voltage V is applied to each source signal line.
That is, b can be set. That is, each source signal line 1
A DA circuit for converting IDATA to D / A, and V
It has a DA circuit for converting DATA to DA. However, each source signal line 18 is not limited to having a DA circuit for converting IDATA to DA and a DA circuit for converting VDATA to DA. For example, D
This is because even one A circuit can be realized by sampling and holding the output of each source signal line.

The voltage converted from VDATA is applied in the first period of 1H. This voltage value is the ID applied later.
It becomes almost equal to the source signal line potential due to the current value corresponding to ATA. Therefore, by applying the voltage of VDATA, the potential of the source signal line becomes almost the target value, and I
Only the target value is corrected with DATA. With the above configuration, insufficient current writing to the source signal line 18 is eliminated.

In FIG. 144 (a), the switch circuit 1223a switches between the a terminal and the b terminal, but the invention is not limited to this. For example, FIG.
As in (b), the output of the voltage output circuit 1221 may be applied to the a terminal so that the output of the current output circuit 1222 is constantly connected to the source signal line 18.

By providing the DA circuit 1226 that can change the output in accordance with the reference voltage, the flexibility of the circuit configuration is further improved. The output change according to the reference voltage means, for example, when the reference voltage is 2.54V, the output can be changed at intervals of 0.01V (when a DA circuit of 8 bits and 256 gradations is adopted). ). When the reference voltage is 5.08V, the output can be changed at intervals of 0.02V. That is, by changing the reference voltage, the output of the DA circuit can be instantaneously changed in proportion to the reference voltage. FIG. 145 is a circuit block diagram when such a DA circuit is adopted.

In FIG. 145, the Vref voltage is applied to the DA circuit 1226a. Vref voltage is Vv
RV * resistor and switch circuit 1223b that divides the voltage into four
Is output from the circuit consisting of. Therefore, the Vref voltage can be switched in four steps by the CVS signal, and the output of the DA circuit 1226a can be instantaneously switched in four steps.

On the other hand, the Iref voltage is applied to the DA circuit 1226b. The Iref voltage is output from a circuit including an RV * resistor that divides the Vi voltage into four and a switch circuit 1223c. Therefore, the Iref voltage can be switched in four steps by the CIS signal, and the output of the DA circuit 1226b can be instantaneously switched in four steps.

By configuring as shown in FIG. 145, the current (voltage) output to the source signal line 18 can be changed in four steps in the period of 1H. As a method of using this, for example, a high voltage (current) is first applied for a moment, the target value is reached at high speed by this application, then the voltage (current) is changed to a steady value, and the target value is set. The voltage (current) written in the pixel can be changed at high speed.

However, in the configuration of FIG. 145, the circuit scale becomes considerably large. Generally, the configuration shown in FIG. 146 is sufficient. The configuration of FIG. 145 is configured such that the voltage output circuit 1221 can output two voltage values. One of the two voltages is a voltage that makes the image display black. The other one is a voltage for whitening the image display. Specifically, if the Vdd voltage in FIG. 6 is 6V, the black voltage is 3V to 4V and the white voltage is 1V to 2V.
The white voltage and the black voltage are adjusted by the adjusting volume (VR) 1225, and this voltage is the operational amplifier 1224 of the buffer.
It is applied to the switch circuit 1223b via a and 1224c. The output of the switch circuit 1223b is VSL.
Switchable by voltage.

The precharge voltage Vb (white voltage or black voltage) is applied at the beginning of one horizontal scanning period (1H). Since each source signal line is connected to the terminal c of the switch circuit 1223a, each source signal line 18 is first precharged to the white voltage or the black voltage. After that, the switch circuit 1223 is switched to the terminal b, and current data (256 gradations) corresponding to the image is applied to the source signal line 18. This current data is written in each pixel 16, and a current flows through the EL element 15 of each pixel to emit light.

In the above embodiments, each source signal line 18 is set to be precharged to the white voltage or the black voltage first, but the present invention is not limited to this. It is realistic to configure the display data (VDATA, IDATA) to be precharged when the display data is equal to or more than a predetermined value or less than the predetermined value.

[0755] Fig. 147 illustrates the case of 64-gradation display for ease of explanation. In FIG. 147 (a), 5
The range (KW) from the 7th gradation to the 63rd gradation is precharged with the white voltage. That is, the voltage output circuit 122 of FIG.
The white voltage is output from 1. Further, the range (KB) from the 0th gradation to the 7th gradation is precharged with the black voltage. That is,
The black voltage is output from the voltage output circuit 1221 of FIG. 146. Then, from the eighth gradation to the 56th gradation, the output of the voltage output circuit 1221 is in a high impedance state (the switch circuit 1223a does not select the terminal a).

[0756] As described above, the white voltage is applied to the gradation to be displayed in white, and the black voltage is applied to the gradation to be displayed in black.
Further, by not precharging at the halftone portion (KM), it is possible to realize high-speed gradation display satisfactorily.

In the case of the current program method, in black display,
Program current (current written in pixel) is 5 nA or more 2
Since it is as small as 0 nA or less, insufficient writing occurs. Therefore, the original black display can be realized by precharging the black voltage. However, insufficient writing may occur even with a dark gray display. in this case,
It is effective to perform the second black precharge in addition to the white and black precharge.

FIG. 147 (b) shows this embodiment. KB
By precharging the black voltage within the range of 1, the original black display can be realized. Then, by precharging the range of KB2 with the second black (gray),
It is possible to realize sufficient gradation display for the gray portion close to black.

More specifically, in the pixel configuration of FIG. 6, if the Vdd voltage is 6V, the black voltage for precharging in the range of KB1 is 3V to 3.5V, and K
Black voltage for pre-charging B2 gray is 3.5V ~
It is 4.0V. The white voltage in the KW range is 1V to 2V. In the range of KM, precharge by voltage is not performed.

In FIG. 147 (b), for ease of explanation,
The case of 64-gradation display is illustrated. In FIG. 147 (b), the range (KW) of the 57th gradation to the 63rd gradation is precharged with the white voltage. Range from 0th gradation to 7th gradation (K
B1) is precharged with a black voltage. 15th from the 8th gradation
The gradation range (KB2) is precharged with the second black voltage. Voltage output circuit 1 from the 16th gradation to the 56th gradation
The output of 221 is brought to a high impedance state (switch circuit 1223a does not select terminal a).

As described above, more appropriate gradation display can be realized by dividing the black range into a plurality of ranges and precharging them with different voltages. Note that FIG.
7 (b) has two black areas, but is not limited to this and may have three or more areas. Further, the precharge may be collectively performed on all the source signal lines. These circuit configurations are shown in FIG.
This is easy because three or more 24 are arranged and three or more switch circuits 1223b can be selected.

Note that in FIG. 147, the current passed through the EL element 15 at gradation 0 (black display) is not 0A. The EL element 15 does not emit light unless a predetermined current or more is passed. The current in the range that does not emit light is called dark current. The dark current is about 10 nA or more and 50 nA or less when the pixel size is 10,000 square μm. Within this dark current range, the pixel is in black display, and current flows even at gradation 0. The source driver 14 needs to be driven by a current to which a dark current is added.

Hereinafter, the circuit configuration shown in FIGS. 143 to 146 will be referred to as an output stage circuit 1271. Output stage circuit 1271
Is arranged (formed) on each source signal line 18 as shown in FIG. Note that FIG.
In FIG. 48, the output stage circuit 1271 is illustrated as being formed in the source driver 14 formed of a silicon chip, but the present invention is not limited to this, and may be formed directly on the glass substrate 241 at the same time as the pixel TFT 11 and the like. Good. In other words, high temperature polysilicon technology, low temperature polysilicon technology,
CGS (Conti) developed by Sharp Corporation
glass by transferring a semiconductor circuit formed on a quartz substrate developed by Seiko Epson Co., Ltd. The output stage circuit 1271 may be formed by a technique of forming it on a substrate or the like. It goes without saying that the output stage circuit 1271 can be directly formed when the glass substrate 241 is a metal substrate or a semiconductor substrate.

Also, the source driver 14 has a signal terminal electrode portion of the source driver of several μm to 100 μm by using a plating technique or a nail head bonding technique.
A protruding electrode (not shown) made of gold (Au) having a height of 1 is formed. The protruding electrode and each signal line are electrically connected to each other via a conductive bonding layer (not shown). The adhesive of the conductive bonding layer is mainly composed of epoxy type, phenol type, etc., and mixed with flakes of silver (Ag), gold (Au), nickel (Ni), carbon (C), tin oxide (SnO ₂ ), etc. Or a UV curable resin. This conductive bonding layer is formed on the protruding electrode by a technique such as transfer.

Although the source driver 14 (or the gate driver 12) is shown or described as being loaded on the substrate, the present invention is not limited to this. In addition, the source driver 14 (or the gate driver 12) is not mounted on the substrate, and the driver I
You may connect with a signal line using the polyimide film etc. which loaded C.

In FIG. 148, the output stage circuit 1271 is arranged only at one end of the display screen 21, but the present invention is not limited to this. For example, as shown in FIG. 149, the source drivers 14a and 14b may be arranged. In FIG. 149, two gate drivers 12 are also formed. That is, the display screen is composed of 21a and 21b. With this structure, the display screens 21a and 21b are
Separate images can be displayed at 1b.

Since the display screen 21 is divided into two in the configuration of FIG. 149, the video signal output from the output stage circuit 1271 may have a half operating frequency as compared with the case where there is one display screen 21. In addition, the parasitic capacitance generated in the source signal line 18 and the like is also halved. Therefore, the load on the output stage circuit 1271 is 1/2 × 1/2 = 1/4. Therefore, even if the current output from the output stage circuit 1271 is minute, the parasitic capacitance of the source signal line 17 can be sufficiently charged and discharged,
Write shortage does not occur.

In the configuration of FIG. 149, the display screen 21 is changed to the screen 2
Since the central portion is divided into 1a and the screen 21b, a boundary may be visible at the division position. FIG. 150 addresses this problem. The source driver 14a has a display screen 2
The odd-numbered pixel row of 1 is driven, and the source driver 14b drives the even-numbered pixel row of the display screen 21. Therefore, the boundary of the display screen 21 does not occur.

Further, in order to improve the shortage of the write current to the pixel, as shown in FIG. 151, the output stage circuit 1271 corresponding to each source signal line 18 in the source drivers 14a and 14b is made to have two outputs. Good. That is, the output stage circuit 1271a includes two output stages (output stage A and output stage B), the output stage A is connected to the odd pixel rows of the display screen 21a, and the output stage B is connected to the display screen 2
It is connected to the even pixel rows of 1a. The output stage circuit 1271b also includes two output stages (output stage A and output stage B), the output stage A is connected to an odd pixel row of the display screen 21b, and the output stage B is an even pixel of the display screen 21b. Connected to a row. With such a configuration, a sufficient current can flow in the source signal line even with a minute current, and a good image display can be realized.

It should be noted that in FIG. 151, the output stage circuit 12
In the reference numeral 71, one source signal line 18 is connected to each pixel, but the present invention is not limited to this. The pixel is configured to be differential and two source signal lines (one source signal line for bias current is used for each pixel). , The other source signal line may be driven by a bias current + a signal current.

FIG. 152 is a more specific module configuration diagram. In FIG. 152, 14b is a source driver, and 14c is a chip (one-chip driver IC) in which a gate driver and a source driver are integrated. 1
The chip driver IC 14c drives the gate signal line of the display screen 21. The one-chip driver IC 14c drives the source signal line 18a of the display screen 21a. The source driver 14b drives the source signal line 18b and drives the display area screen 21b.

Note that FIG. 152 is an example, and the source driver 14b also has a gate driver function, and the display screen 2
The gate signal line 17b of 1b may be driven. In addition, the power supply IC 102 and the control IC 101
Is shown as being stacked on the printed circuit board 103, but the present invention is not limited to this, and may be directly formed on the display panel 82 using the polysilicon technique described above. This also applies to FIGS. 227 and 228. Other configurations are the same as those in FIG. 227, FIG. 228, FIG. 26, FIG.

The control IC 101 drives both the one-chip driver IC 14c and the source driver 14b. Control IC 101 to 1 chip driver IC
Signals (power supply wiring, data wiring, etc.) supplied to 14c are supplied via the flexible substrate 104c. But,
The source drivers 14b are far apart, so
First, the flexible substrate 104a is connected to the back surface of the display panel 82.

[0774] FIG. 153 is a view of the display panel 82 observed from the back side. Signal wirings (including power supply wirings) 1321 are formed on the back surface of the display panel 82. Signal wiring 13
21 is formed of a metal material such as copper, aluminum (Al), silver, silver-palladium, palladium, gold, and Al-Mo. The signal wiring 1321 transmits a signal from one end of the display panel 82 to the other. The flexible substrate 104b is connected to one end of the display panel 82, and signals and the like are supplied from the flexible substrate 104b to the source driver 14b. Note that FIG. 154 is a diagram when viewed from A in FIG. 153.

62, 142, 143 to 147.
6 has been described by exemplifying the pixel configuration of the current programming method as shown in FIGS. 6 and 19, but it is not limited to this. For example, FIGS. 85, 86, 87, 155, and 1
It is also effective in the pixel configuration of the voltage programming system such as 56. In that case, b of the switch circuit 1223 of FIG.
The signal applied to the terminals must be a voltage. This change is easy, and a person of ordinary skill in the art can easily cope with it. In voltage driving, there is no shortage of charge due to the parasitic capacitance of the source signal line 18, but by adopting a method of simultaneously applying a voltage to a plurality of pixel rows, the driving circuit and the signal processing circuit are simplified, and
This is because excellent black display can be realized. Further, this is because the hidden display of the image can be realized, and the effect of absorbing the variation of the TFT 11 is exerted.

Therefore, it goes without saying that the matters described with reference to FIGS. 143 to 147 can be applied to all the display panels, display devices, information display devices, etc. of the present invention.

As described above, the present invention can be applied to various pixel configurations. FIG. 157 shows the TFT1 of FIG.
In this embodiment, one P channel is changed to N channel.
Also in FIG. 157, it is needless to say that the switching TFT 11d can be turned on / off by controlling the gate signal line 17 and the image display of FIG. 48 and 55.
Since the driving waveforms such as are the same or similar, the description will be omitted. Further, it is also effective to use only the driving TFT 11b and the taking-in TFT 11c as N-channel TFTs in FIG. This is because the punch-through voltage to the capacitor 19 is reduced and the holding characteristic of the capacitor is also improved.

Note that FIG. 157 shows a configuration including only the current source 402. That is, the voltage source 401 for performing the precharge is not provided. However, when the parasitic capacitance 404 is relatively small or the 1H period is sufficiently long, the voltage source 4
Even without 01, black display can be sufficiently realized. Also, FIG.
As described in 9, etc., when implementing the complete non-display area 312, in most cases, the voltage source 401 is not necessary. If necessary, it may be configured as shown in FIG. 158.

Also, FIG. 159 shows P of the TFT 11 of FIG.
This is an embodiment in which the channels are N channels. Figure 15
Also in 9, the TFT 11e and the like can be turned on and off by controlling the gate signal line 17, and it is needless to say that the image display of FIG. The drive waveforms shown in FIGS. 48 and 55 are the same or similar, and thus the description thereof will be omitted.

As described above, the voltage source 401 supplies Vb
Good black display can be realized by applying a voltage (Ib current).

When N = 10 or more and a high current pulse is applied to the EL element 15, the EL terminal voltage also increases. The EL element 15 has different rising voltages and gamma curves for R, G, and B. In particular, since B has a gentle gamma curve, the terminal voltage of the EL element 15 tends to increase. If the terminal voltage is adjusted to the EL element 15 of a color (R, G, B colors) having a high rising voltage and a gentle gamma curve, power consumption increases.

One method of solving this is a method of separating the cathode by R, G and B shown in FIG. In addition,
It is not necessary for R, G, and B to have different cathode potentials. In particular, only one color cathode, whose gamma curve is distant from the other colors, may be separated. As another method, a configuration in which the Vdd power supply voltage is separated as shown in FIG. 160 is also effective. That is, the R color Vdd power supply is changed to VddR.
And the G color Vdd power supply is VddG, and the B color Vdd is
In this configuration, the power source is VddB. By separating in this way, RGB can be adjusted by different power supplies, and even if the terminal voltages of the RGB EL elements 15 are different, the increase in power consumption is small.

Note that there is no need to set different Vdd potentials for R, G, and B. In particular, only one color Vdd whose gamma curve is distant from the other colors may be separated. Further, as shown in FIG. 161, it may be combined with the configuration of FIG. In other words, the cathode potentials (R pixel is V
The sR and G pixels are VsG, and the B pixel is VsB). In particular, only the cathode potential of only one color whose gamma curve is separated from the other colors may be separated. Further, the Vdd power supply voltage is separated. Rdd Vdd power supply is VddR, G
The color Vdd power supply is VddG, and the B color Vdd power supply is Vdd
This is a configuration with dB. Also in this case, it is not necessary to set different Vdd potentials for R, G, and B. In particular, only one color Vdd whose gamma curve is distant from the other colors may be separated.

Note that although the pixel 16 has the configuration of FIG. 6 in FIGS. 160 and 161, it is not limited to this.
19, FIG. 20, FIG. 159, FIG. 162, FIG. 157, FIG.
58, FIG. 81, FIG. 85, FIG. 86, FIG. 72 to FIG. 76, FIG.
It goes without saying that the configurations shown in FIG. 3, FIG. 67, FIG. 79, FIG. 80, FIG.

The problem to be solved by the present invention is that the current applied to the EL element 15 is instantaneous, but there is a problem that it is N times larger than the conventional one. If the current is large, the life of the EL element may be shortened. In order to solve this problem, it is effective to apply the reverse bias voltage Vm to the EL element 15.

A method of applying the reverse bias voltage Vm will be described below. In order to apply the reverse bias voltage Vm, it is necessary to individually control the gate terminals of the driving TFT 11b and the capturing TFT 11c in the configuration of FIG. That is, the driving TFT 11b and the loading TFT 11c
Need to be turned on and off individually. This control method will be described with reference to FIG.

First, as shown in FIG. 163 (a), the taking-in TFT 11c is turned on and the switching TFT 11d is turned on.
Is turned on (see also FIG. 6). And
The reverse bias voltage Vm and the a terminal of the EL element 15 are applied. The reverse bias voltage Vm is a voltage lower than the cathode voltage Vs and within a range of 5V to 15V.

When the EL element 15 is turned on, a high voltage of 5 V or more and 15 V or less with respect to the cathode voltage Vs is applied to the a terminal. That is, the reverse bias voltage Vm
Means that a voltage whose absolute value is ideally equal and whose polarity is opposite to the voltage applied when the EL element 15 is lit is applied. In reality, it is difficult to apply voltages having the same absolute value and opposite polarities, so a voltage of 2-3 times the opposite polarity is applied. As described above, by applying the reverse bias voltage Vm, the EL element 15 hardly deteriorates.

Then, as shown in FIG. 163 (b), the switching TFT 11d is turned off and the driving TFT 11b is turned on.
Turn on. Then, the black display voltage Vb is applied to the capacitor 1
Write to 9. This operation is described in FIG. 142. Next, as shown in FIG. 163 (c), the on / off state of the TFT 11 is the same as that of FIG.
The image display voltage (current) from is written in the capacitor 19. This operation is also described in FIG. 142. Finally, Figure 1
As shown at 63 (d), the driving TFT 11b and the taking-in TFT 11c are turned off, the switching TFT 11d is turned on, and a current is passed through the EL element 15 to light it.

The above operation is shown in FIG. The reverse bias voltage Vm is applied to the source signal line 18 during the t1 time of the 1H period, the black display voltage Vb is applied during the next t2 period, and the image data Vw (Iw) is applied during the t3 period. Other operations will be described with reference to FIG. 163, and FIG.
Since it has been described with reference to FIG.

FIG. 165, FIG. 155, FIG. 156, FIG. 163
In this configuration, when the current of the source signal line 18 is taken into the pixel 16, a reverse current flows through the EL element 15. Therefore, when the EL element 15 is an organic electroluminescent element, it becomes possible to delay the electrochemical deterioration due to the redox reaction of the organic molecule as in the case where a reverse voltage is applied.

FIG. 166 shows an energy diagram of a three-layer type organic light emitting device consisting of anode / hole transport layer / light emitting layer / electron transport layer / cathode. The behavior of the positive and negative carriers during light emission is shown in FIG. The electron is the cathode
More holes are injected into the electron transport layer, and at the same time holes are also injected into the hole transport layer from the anode. Injected electrons,
The holes move to the counter electrode due to the applied electric field. At that time, they are trapped in the organic layer or carriers are accumulated due to the difference in energy level at the interface of the light emitting layer.

When space charges are accumulated in the organic layer, the molecules are oxidized or reduced, and the radical anion molecules or radical cation molecules produced are unstable, resulting in deterioration of film quality and reduction of brightness and constant current driving. It is known that this causes an increase in driving voltage. To prevent this
As an example, the device structure is changed and a reverse voltage is applied.

In FIG. 166 (b), since the reverse current is applied, the injected electrons and holes are extracted to the cathode and the anode, respectively. This eliminates the formation of space charges in the organic layer and suppresses the electrochemical deterioration of the molecules, which makes it possible to prolong the life.

Note that although the three-layer element is described in FIG. 166, even in the multi-layer element of four layers or more and the element of two layers or less, the organic film is formed by the electrons and holes injected from the electrodes. It is the same that the electrochemical degradation of Therefore, it becomes possible to prolong the life according to this embodiment regardless of the number of layers. It is also effective in a device in which a plurality of materials are mixed in one layer because electrochemical deterioration of molecules similarly occurs.

As described above, the feature of the present invention is to provide the function of preventing the deterioration of the organic molecules and the function of supplying the bias current for preventing the waveform distortion due to the stray capacitance parasitic on the source signal line. That is, display is possible without increasing the number of transistors required for a pixel. That is, it is not necessary to increase the number of transistors for flowing the reverse current, which leads to the advantage that the aperture ratio of each pixel of the display device does not have to be reduced.

The effect of applying the reverse bias voltage Vm will be described with reference to FIG. 167. FIG. 167 shows the emission luminance of the EL element 15 and the terminal voltage of the EL element when driven with a predetermined current. In FIG. 167, the dotted line b indicates the terminal voltage of the EL element 15 when the reverse bias voltage Vm is applied to the EL element 15. The alternate long and short dash line c indicates the terminal voltage of the EL element 15 when the reverse bias voltage Vm is not applied to the EL element 15. The solid line a indicates the EL element 1 when the reverse bias voltage Vm is applied to the EL element 15 (solid line a).
5 shows the emission luminance ratio of 5 (ratio when the initial luminance is 1).

In FIG. 167, specifically, the case where the EL element emits R light and is current-driven at a current density of 100 A / square meter. Sample B continuously applies a current having a current density of 100 A / square meter for time t. Although the terminal voltage increased at the lighting time of 1500 hours, the brightness rapidly decreased, and after 2500 hours, only about 15% of the initial brightness was obtained.

Sample A was pulse-driven at 30 Hz, a current density of 200 A / square meter was applied at half time t2, and a reverse bias voltage of -14 V was applied at half time t1 (that is, unit time). The average light emission luminance is the same in Samples A and B). Sample A
As shown by the dotted line b, there was almost no change in the terminal voltage of the EL element 15, and the lighting time when the brightness was 50% was 4000 hours.

As described above, even if the reverse bias voltage Vm is applied, the terminal voltage of the EL element 15 does not increase, and the reduction rate of the emission luminance is small. Therefore, long-life driving of the EL element 15 can be realized.

FIG. 168 shows changes in the reverse bias voltage Vm and the terminal voltage of the EL element 15. The terminal voltage is when the rated current is applied to the EL element 15. Figure 1
No. 68 is the case where the current passed through the EL element 15 has a current density of 100 A / square meter, but the tendency of FIG. 168 is almost the same as the case of the current density of 50 to 100 A / square meter. Therefore, it is estimated that it can be applied in a wide range of current density.

The vertical axis represents the ratio of the initial terminal voltage of the EL element 15 to the terminal voltage after 2500 hours. For example,
When the elapsed time is 0 hours, the terminal voltage when a current density of 100 A / square meter is applied is 8 V, and when the elapsed time is 2500 hours, the terminal voltage is 10 V when a current density of 100 A / square meter is applied. If
The terminal voltage ratio is 10/8 = 1.25.

The horizontal axis represents the ratio of the rated terminal voltage V0 to the product of the reverse bias voltage Vm and the time t1 when the reverse bias voltage is applied in one cycle. For example, at 60 Hz, if the time when the reverse bias voltage Vm is applied is 1/2, t1 = 0.
It is 5. In addition, when the elapsed time is 0 hours, the current density is 1
The terminal voltage (rated terminal voltage) when a current of 00 A / square meter is applied is 8 V, and the reverse bias voltage Vm is 8
If V, | reverse bias voltage × t1 | / (rated terminal voltage × t2) = | −8V × 0.5 | / (8V × 0.5) =
It becomes 1.0.

According to FIG. 168, | reverse bias voltage × t
When 1 | / (rated terminal voltage × t2) is 1.0 or more, the terminal voltage ratio does not change (it does not change from the initial rated terminal voltage), and the effect of applying the reverse bias voltage Vm is well exhibited. However, since | reverse bias voltage × t1 | / (rated terminal voltage × t2) is 1.75 or more, the terminal voltage ratio tends to increase, so 1.0 or more, preferably 1.75.
The magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or the ratio of t1 and t2) may be determined as follows.

However, when the bias drive is performed, it is necessary to alternately apply the reverse bias voltage Vm and the rated current. As shown in FIG. 167, when it is attempted to equalize the average brightness per unit time of the samples A and B, when the reverse bias voltage Vm is applied, it is necessary to instantaneously flow a high current as compared with the case where the reverse bias voltage Vm is not applied. is there. Therefore, when the reverse bias voltage Vm is applied (Sample A in FIG. 167), the terminal voltage of the EL element 15 must also be increased.

However, in FIG. 168, the rated terminal voltage V0 is the terminal voltage satisfying the average brightness (that is, the terminal voltage for lighting the EL element 15) even in the driving method in which the reverse bias voltage is applied (in this specification). According to a specific example, it is a terminal voltage when a current having a current density of 200 A / square meter is applied.However, since the duty is 1/2, the average luminance of one cycle is the luminance at a current density of 200 A / square meter. Become).

The above items assume that the EL element 15 is a white raster display (when a maximum current is applied to the EL elements on the entire screen). When performing, it is a natural image and gradation display is performed. Therefore, the white peak current of the EL element 15 (current flowing at maximum white display; in the specific example of the present specification, average current density of 100 A / square meter of current) does not always flow.

Generally, when displaying an image, the current (current flowing) applied to each EL element 15 is a white peak current (current flowing at the rated terminal voltage. According to the specific example of this specification, the current Since the density is about 0.2 times the current of 100 A / square meter), in the embodiment of FIG. 168, the value on the horizontal axis needs to be 0.2 times when displaying an image. Therefore, the magnitude of the reverse bias voltage Vm and the application time ratio t1 (or t2, or t2, so that | reverse bias voltage × t1 | / (rated terminal voltage × t2)) is 0.2 or more.
Alternatively, the ratio between t1 and t2, etc.) may be determined.
Further, preferably, | reverse bias voltage × t1 | / (rated terminal voltage × t2) is such that the magnitude of reverse bias voltage Vm and application time ratio t1 are such that 1.75 × 0.2 = 0.35 or less. Should be decided.

That is, 1.0 on the horizontal axis (| reverse bias voltage × t1 | / (rated terminal voltage × t2)) of FIG. 168.
Since it is necessary to set the value of to 0.2, when displaying an image on the display panel (this usage condition is normal. The white raster will not always be displayed), | The reverse bias voltage Vm is set to a predetermined time t so that xt1 | / (rated terminal voltage xt2) becomes larger than 0.2.
1 is applied. Also, | reverse bias voltage × t
Even if the value of 1 | / (rated terminal voltage x t2) becomes large,
As shown in FIG. 168, the terminal voltage ratio does not increase so much. Therefore, in consideration of performing white raster display, the upper limit may be set so that the value of | reverse bias voltage × t1 | / (rated terminal voltage × t2) satisfies 1.75 or less.

(Eleventh Embodiment) The reverse bias system of the present invention will be described below with reference to the drawings. The present invention is basically applied with the reverse bias voltage Vm (current) during the period when no current is flowing through the EL element 15, but the present invention is not limited to this. For example, the reverse bias voltage Vm may be forcibly applied while a current is flowing through the EL element 15. In this case, as a result, no current will flow through the EL element 15, and the EL element 15 will be in a non-lighting state (black display state). Further, although the present invention is mainly described by applying the reverse bias voltage Vm in the pixel configuration of the current program, the present invention is not limited to this. For example, in FIG. 87, the TFT 11e is turned off,
If the reverse bias voltage Vm is applied to the anode of the EL element 15 as in the case of FIG. 169, the application of the reverse bias voltage Vm described below can be easily realized even in the pixel configuration of the voltage programming method. Therefore, FIG.
The effects described with reference to 68 and the like can be exerted.

FIG. 169 is an explanatory diagram of the driving method of the reverse bias voltage applying method of the present invention. FIG. 169 shows FIG.
The switching TFT 11g for applying the reverse bias voltage Vm is arranged or formed in the pixel configuration. The gate terminal of the switching TFT 11g is connected to the control gate signal line 17d. Switching TFT1
By turning on 1g, the reverse bias voltage Vm becomes EL.
It is applied to the anode of the element 15.

First, as shown in FIG. 170 (a1), when the on-voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b and the taking-in TFT 11c are turned on. Then, as shown in FIG. 170 (a2), the program current Iw flows from the source driver 14 to the intake TFT 11c and the like, and the capacitor 19 is current-programmed. Although not limited to N times, here, for ease of explanation, it is assumed that N times the current is programmed and the current Id is supplied to the EL element 15 for a period of 1 F / N.

Next, as shown in FIG. 170 (b1), the off voltage Vgh is applied to the gate signal line 17b,
The driving TFT 11b and the taking-in TFT 11c are turned off.
When the ON voltage Vgl is applied to the gate signal line 17b at the same time (not limited to the same time), the switching TFT 11d is turned on. Then, FIG. 170 (c2)
As shown by, the power source Vdd passes through the conversion TFT 11a, and the current-programmed current Id flows to the EL element 15, and the EL element 15 emits light as shown in FIG. 170 (c1). This emission brightness has a program conversion efficiency of 1
If it is 00%, light is emitted with a brightness of about N times.

[0814] The light emitting period is 1 F / N. Remaining 1F
During the period of (1-1 / N), the switching TFT 11d is in the off state, and the EL element 15 is not illuminated (black display). Since no current flows through the EL element 15 when it is not lit, perfect black display can be realized. Further, since the white peak current is large during light emission, the light emission brightness is also high. Therefore, the driving method of the present invention can realize a very high contrast display.

[0815] During the entire period of 1F, the current of 1 times is EL
In order to realize black display when the current is passed through the element 15 (conventional driving method), it is necessary to program the black display current in the capacitor 19. However, in the current driving method, since the current value at the time of black display is small, there is a problem that the effect of the parasitic capacitance is large and sufficient resolution cannot be obtained and black floating occurs. In addition, the penetration voltage from the gate signal line 17 is also affected. Due to these problems, the EL element 15 is slightly turned on even in the black display portion, and the contrast is extremely deteriorated.

According to the driving method of the present invention, 1F (1-1 /
During the period N), no current completely flows through the EL element 15, so that perfect black display can be realized. That is, the black floating does not occur. Therefore, high-contrast display can be realized without performing the precharge for black display described in FIG.

Of course, it goes without saying that the method described in FIG. 169 and the like may be added to the method in FIG. 163 and the like. Further, the realization of high contrast display is similarly effective in the pixel configuration of the voltage program such as FIG. That is, by performing the 1F / N pulse driving, the EL element 1 is operated for a period of 1F (1-1 / N).
Therefore, no current flows through 5, and high contrast display can be realized. Of course, by intermittently displaying images, good moving image display can be realized.

Depending on the pixel configuration, when the punch-through voltage acts in the direction of increasing the current flowing through the EL element 15, the white peak current increases and the contrast feeling of the image display increases, so that a good image display is obtained. Will be realized.

As shown in FIG. 170 (d1), an ON voltage is applied to the gate signal line 17d, and the switching T
Turn on FT11g. At this time, TF for switching
T11d is turned off. Switching TFT 11
By turning on g, the anode of the EL element 15 (the reverse bias voltage Vm is set to E
It may be applied to the cathode of the L element 15. The reverse bias voltage Vm can also be expressed as a reverse bias voltage Vm (reverse bias current Im) flowing in the positive bias voltage in some cases. This is because the application of the voltage Vm causes an alternating current to flow, and the accumulated charges are discharged). The application time t1 is configured to satisfy the state of FIG. 168 (FIG. 17).
0 (d2)).

It is preferable that the period in which the reverse bias voltage Vm is applied is a period in which the current Id does not flow in the EL element 15. This is not impossible, but if the current Id is flowing, it will be short-circuited with the reverse bias voltage Vm.

In FIG. 170 (d1), the period for applying the reverse bias voltage Vm is set to one of 1F, but the period is not limited to this, and it is not limited to this.
In the period of F, the reverse bias voltage Vm may be applied to the EL element 15 twice or more or three times or more).

[0821] The gate signal line 17b is applied at an arbitrary timing during the period in which the off voltage is applied to the gate signal line 17b.
This control can be easily performed by applying an on-off voltage to d. The total sum of these on times is shown in FIG.
The time may be set to t1 time described in 8.

[0823] The period 1F (1-1 / N) in which no current flows through the EL element 15 may be divided into a plurality of periods. The division into a plurality of sections suppresses the occurrence of flicker. When the period 1F (1-1 / N) is divided into a plurality of periods, the reverse bias voltage Vm may be applied during that period.
However, it is not necessary to apply the reverse bias voltage Vm to all of the divided periods 1F (1-1 / N).

Note that, as shown in FIG. 167, the driving method in which the reverse bias voltage is not applied and the current does not flow in the EL element 15 is corrected (or supplemented) below based on the contents described in FIG. 168. To do. The time t1 described in FIG. 168 is the time when the reverse bias voltage Vm is applied. The time t2 is the time when the current is applied to the EL element 15.

The reverse bias voltage Vm does not have to be a DC fixed value (Vm = -8V). That is, the reverse bias voltage Vm may be a sawtooth waveform signal or a pulse waveform signal. Alternatively, a sine wave signal waveform may be used. The reverse bias voltage in this case is an integrated value of the waveform or an effective value. Further, although the application time t1 is also unclear, a value obtained by integrating the reverse bias voltage Vm, an effective value is a rectangular waveform, and a time when the rectangular waveform is applied may be set to t1.

For example, the waveform of the reverse bias voltage is shown in FIG.
In the voltage waveform (triangular wave) shown in FIG. 1 (a), the maximum amplitude value is 16 V and the application time is t1 = 100 μsec. In this case, as shown in FIG. 171 (b),
This is equivalent to a voltage waveform in which the maximum amplitude value is 8 V and the application time is t1 = 100 μsec. Also, as shown in FIG. 171 (c), the maximum amplitude value is 16 V and the application time is t1 = 50.
The processing may be performed by regarding it as equivalent to the voltage waveform of μsec. The above items also apply to the positive voltage applied to the EL element 15.

The same applies to the current Id flowing through the EL element 15. In other words, the current (voltage) flowing through the EL element 15 may not be direct current, but may be a sine current waveform or the like. In this case as well, if converted to a direct current effective value and converted to the rectangular wave application period t2. Good.

As shown in FIG. 172 (a), the period for applying the reverse bias voltage Vm is set as all periods except the period for applying the on-voltage to the gate signal line 17a (normally, 1H period: program period). Good.

Further, since the reverse bias voltage Vm may be applied to the EL element 15 while the current Id is not applied, as shown in FIG. 172 (b), the gate signal line 1
The reverse bias voltage Vm may be applied during a period including a period (program period) in which the ON voltage is applied to 7a (see FIG. 172 (b), a period in which the current Id is applied to the EL element 15 ( The reverse bias voltage Vm is applied except during the period when the ON voltage is applied to the gate signal line 17b).

The matters concerning the application time, the application method, the application timing, etc. of the reverse bias voltage Vm described with reference to FIGS. 172 and 170 are also applicable to the other embodiments.

As described above, in the present invention, the non-lighting period (non-display area) 312 is provided in the 1F period. By providing the non-lighting period, the moving image display performance is improved, and the EL in the non-lighting period is set. The reverse bias voltage Vm can be applied to the element 15. Therefore, the EL element 15 does not deteriorate,
Since the terminal voltage does not increase, the power supply voltage Vdd can be set low.

In FIG. 172, the reverse bias voltage Vm is applied immediately before the EL element 15, but
As another configuration, as illustrated in FIG. 173, a configuration in which a reverse bias voltage Vm (current −Im) is applied to the EL element 15 via the switching TFT 11d is also illustrated.

By applying an on-voltage to the gate signal line 17d, the switching TFT 11g is turned on and the reverse bias voltage Vm is applied. At the same time, by turning on the switching TFT 11d as well, the reverse bias voltage Vm can be applied to the EL element 15. FIG. 173
With this configuration, since the application of the reverse bias voltage Vm can be controlled by both the switching TFTs 11g and 11d, the control becomes easy and the flexibility is improved.

An ON voltage is applied to the gate signal line 17 when the corresponding pixel is selected. The off voltage is applied during the non-selected period. Therefore, since the off-voltage is applied to the gate signal line during most of the period of 1F, the off-voltage can be used as the reverse bias voltage.

The off voltage is normally lower than the cathode voltage because it turns off the TFT completely (of course, the opposite is true when the TFT is a P channel). In particular,
When the TFT is amorphous silicon, the off voltage is usually set to be quite low.

In the configuration of FIG. 174, the gate signal line 17a
Drive TFT 11b and capture TFT 11c connected to
Is an N-channel TFT. Therefore, the driving TFT 11b and the taking-in TFT 11c are turned on by the on-voltage Vgh, and are turned off by the off-voltage Vgl. The off voltage Vgl is applied to the gate signal line 17b during most of 1F. The off voltage Vgl is set as the reverse bias voltage Vm (Vgl = Vm).

The switching TFT 11g is also controlled by the voltage applied to the gate signal line 17d, as in the previous embodiment. It should be noted that the voltage to be applied to the gate signal line 17d controls ON / OFF of the switching TFT 11g, but the voltage to be applied is not limited to Vgh and Vgl, but may be any other voltage. Can be used.

When the switching TFT 11g is turned on, the off voltage Vg applied to the gate signal line 17a.
l is applied to the EL element 15. Therefore, the reverse bias voltage Vm can be applied to the EL element 15. In the configuration of FIG. 174, the reverse bias voltage V as shown in FIG.
Since a signal line for supplying m is unnecessary, the pixel aperture ratio can be improved. In FIG. 174, the gate signal line 17
The voltage applied to b may be configured to be applied to the EL element 15 (the switching TFT 11d needs to have an N-channel configuration).

FIG. 174 shows a configuration in which the voltage of the gate signal line 17 is set to the reverse bias voltage, whereas FIG. 175 shows a configuration in which the voltage applied to the source signal line 18 is set as the reverse bias voltage of the EL element 15. When the reverse bias voltage Vm is applied to the source signal line 18 at the timing when the switching TFT 11g turns on, the EL signal passes through the source signal line 18.
The reverse bias voltage Vm can also be applied to the element 15. The timing and the like have been described with reference to FIG.

The time for applying the reverse bias voltage Vm is E
When it is longer than the period in which the current is applied to the L element 15, the voltage charged in the EL element 15 is discharged as shown in FIG. 176, so that the anode terminal and the cathode terminal of the EL element 15 are discharged. It is also effective in short-circuiting. By short-circuiting in this way, the holes accumulated in the hole transport layer of the EL element 15 are extracted, and the electrons accumulated in the electron transport layer are also extracted, so that deterioration of the EL element can be suppressed. . The application time of the reverse bias voltage Vm described in FIGS. 172 and 170,
For matters relating to the application method, application timing, etc., see FIG.
It goes without saying that the present invention is also applied to the embodiments of the above.

In FIG. 176, each TFT is composed of P channels, but in FIG. 177, the structure of FIG. 176 is changed to N channels. In FIG. 177, when the switching TFT 11g is turned on, the EL element 15
The anode terminal and the cathode terminal are short-circuited, and the Vdd voltage is applied to both terminals. EL element 1 during this period
The holes accumulated in the hole transport layer of No. 5 are extracted, and
The electrons accumulated in the electron transport layer are also extracted, and the deterioration of the EL element can be suppressed. Needless to say, as with FIG. 176, the matters concerning the application time, the application method, the application timing, etc. of the reverse bias voltage Vm described in FIGS. 172 and 170 are also applicable to the embodiment of FIG.

The reverse bias voltage Vm can also be applied to the EL element 15 by changing the control direction in which the current flows. FIG. 178 is a block diagram thereof.
Reference numeral 402 in FIG. 178 is a constant current source.

In FIG. 178, the switching TFT
When 11g is on, switching TFT 11
A current in the same direction as the constant current source 402 flows through g, and a forward voltage is applied to the EL element 15. On the other hand, when the switching TFT 11g is off, the EL element 15 and the constant current source 402 form a loop, so the direction of the current flowing through the EL element 15 is reversed. That is, the constant current source 402
TF for switching by arranging or forming
By controlling T11g, the reverse bias voltage Vm can be easily applied to the EL element 15. FIG. 179 shows the timing of the gate signal line 17 at this time. The ON voltage is applied to the gate signal line 17d during a period other than the period in which the gate signal line 17a is selected. Thus, E
The holes accumulated in the hole transport layer of the L element 15 are extracted, and the electrons accumulated in the electron transport layer are also extracted,
The deterioration of the hole transport material due to oxidation and the reduction of the electron transport material can be suppressed.

In FIG. 180, the switching TFT 11g is an N channel, the switching TFT 11g is in an off state when the switching TFT 11d is on, and the switching TFT 11g is in an on state when the switching TFT 11d is off. It is a composition. When the switching TFT 11d is turned on, the EL element 15 lights up, and the switching TFT 11g
When is on, the reverse bias voltage Vm is applied to the EL element 15.

It is effective to set the reverse bias voltage Vm to a voltage lower than the cathode voltage Vk. However, in order to separately generate the reverse bias voltage Vm, a generation circuit is required. To solve this problem, a flying capacitor is formed in FIG. Flying capacitor 1
001 may be arranged (formed) for each pixel, or one circuit may be arranged (formed) on the panel.

The flying capacitor 1001 is operated by controlling the gate signal lines 17e and 17f.
Then, the gate signal line 17e and the gate signal line 17f are operated in opposite phases.

First, an ON voltage is applied to the gate signal line 17e to turn on the TFTs 11i and 11j, and the capacitor 1
The Vdd voltage is applied to 9b. At this time, the gate signal line 1
An off voltage is applied to 7f to charge the capacitor 19b, and then the TFTs 11h and 11k are turned off.

Next, an off voltage is applied to the gate signal line 17e to turn off the TFTs 11i and 11j, an on voltage is applied to the gate signal line 17f, and the TFTs 11h and 11k are turned on. Then, V charged in the capacitor 19b
The dd voltage has an opposite phase, and the -Vdd voltage is applied to the EL element 15.

With the above-mentioned structure, the Vm voltage (Vm = -Vdd) having the opposite phase can be generated. Therefore, the Vm voltage supply wiring is not required.

The above embodiments have been described mainly by exemplifying the pixel configuration of the current programming method described in FIG. 6, but the present invention is not limited to this, and as shown in FIG. 182, the pixel configuration of the current mirror. However, the reverse bias voltage V
It goes without saying that it can be configured so that m can be applied. Note that the operation will not be described because the configuration described in FIG. 169 can be applied as it is. Also, as shown in FIG. 183, it goes without saying that the reverse bias voltage can be applied even in the pixel configuration of voltage programming. The same applies to FIG. 87 and the like. Therefore, even in the pixel configuration of the voltage program, the configuration or method of applying the reverse bias voltage to the EL element 15 at the time of non-lighting can be applied.

In the above embodiment, the present invention is
It has been described that the configuration or method is such that the reverse bias voltage Vm is applied to the EL element 15 when the EL element 15 is not lit. This is not limited to displaying the display screen 21 and applying the reverse bias voltage Vm to the EL element 15 when the EL element 15 is not lit. In the active matrix type EL display panel, the configuration in which the reverse bias voltage Vm is constantly applied when the LED is not illuminated is also within the scope of the present invention.

For example, the reverse bias voltage Vm may be applied to the EL elements 15 of the entire display screen 21 for a predetermined period after the use of the EL display panel is finished. Further, the EL elements 15 of the entire display screen 21 may be sequentially scanned and the reverse bias voltage Vm may be applied for a predetermined period after the use of the EL display panel is finished. Also, when using the EL display panel (for example, power ON
Hour), and the EL element 15 of the entire display screen 21 for a predetermined time.
May be sequentially scanned to apply the reverse bias voltage Vm. Further, when the EL display panel is not used, the reverse bias voltage Vm may be applied at predetermined time intervals (for example, every 10 hours for every 1 hour). Conversely, when the EL display panel is used, the reverse bias voltage Vm may be applied at predetermined time intervals (for example, every 10 hours for every 1 hour).

In FIG. 159, the TFT which constitutes a pixel
11 is five. However, in FIG. 6A, the number is four. Therefore, the configuration of FIG. 6A has the advantages that the number of TFTs 11 constituting the pixel 16 is one less, the aperture ratio can be increased, and the occurrence rate of pixel defects is less.

FIG. 162 also shows a pixel configuration of the current program system. Current programming can be performed by applying an on-voltage to the gate signal line 17a. In addition, by applying an off voltage to the gate signal line 17b,
By applying an on-voltage to 7b, a programmed current can flow in the EL element 15.

Also in the configuration of FIG. 162, gate signal line 1
By applying on-voltage or off-voltage to 7c,
It is possible to control the current flowing through the EL element 15, and FIG.
The driving method or display state illustrated in FIG.

Although the TFT 11e is added in FIG. 162, this TFT 11e is deleted and the gate signal line 17b is added.
It is needless to say that the image display shown in FIG. 49 and the like can also be realized by operating the switch to control the on / off state of the switching TFT 11d.

FIG. 184 also shows a pixel structure of a current programming method. Current programming can be performed by applying an on-voltage to the gate signal line 17a. In addition, by applying an off voltage to the gate signal line 17b,
By applying an on-voltage to 7b, a programmed current can flow in the EL element 15.

Also in the configuration of FIG. 184, gate signal line 1
By applying on-voltage or off-voltage to 7c,
Since the switching TFT 11d can be turned on and off, the current flowing through the EL element 15 can be controlled.
Therefore, the driving method or display state shown in FIG. 49 or the like can be realized.

Note that FIG. 81 shows an example of a pixel configuration for voltage programming. The present invention controls the application time of the current flowing through the EL element 15 for a predetermined time of one field or one frame (1F, of course, 2F or more may be considered as one segment), and thereby a predetermined light emission brightness is obtained. Is the way to get. That is, the method is to obtain a predetermined brightness by making the current flowing through the EL element higher than the predetermined brightness and shortening the ON time for the brightness higher than the predetermined brightness.

FIG. 87 also shows a pixel configuration by voltage programming. In FIG. 87, 19a is a threshold detecting capacitance (capacitor), and 19b is an input signal voltage holding capacitance (capacitor).

In step 1 (section 1), the TFT1
Since the TFTs 11e are all turned on from 1a to turn on the driving transistor once, the deviation of the current value occurs due to the variation of the threshold value.

In step 2 (section 2), the TFT1
1b, the TFT 11d remains ON, the TFT 11c,
By turning off the TFT 11e, the driving T
Since the current value of the FT11a becomes 0, the driving TFT
The threshold value 11a is detected by the threshold value detecting capacitor 19a.

[0863] In step 3 (section 3), the TFT1
1b, the TFT 11d is turned off, the TFT 11c,
By turning on the TFT 11e, the input signal voltage of the data signal line is held in the input signal voltage holding capacitor 19b, and at the same time, a signal voltage obtained by adding a threshold to the input signal voltage is applied to the gate of the driving TFT 11a. EL
The element 15 is current-driven to emit light. This driving TFT
Since 11a operates in the saturation region, a current proportional to the square of the voltage value obtained by subtracting the threshold value from the gate voltage flows,
Since the threshold has already been applied to the gate voltage by the threshold detecting capacitor 19a, the threshold is canceled as a result. Therefore, even if the threshold value of the driving TFT 11a varies, a constant current value always flows in the EL element 15 as shown in the simulation result.

In step 4 (section 4), when the pixel 16 enters the non-selection period, the TFT 11b and the TFT 11d are turned off, the TFT 11e is turned on, and the TFT 11c is turned on.
Even in the FF, the input signal voltage held in the input signal voltage holding capacitor 19b and the threshold voltage held in the threshold detecting capacitor 19a are applied to the gate of the driving TFT 11a. Current flows and continues to emit light.

As described above, in order to detect the threshold value of the driving transistor more accurately, the period of the first step is set to 2 μsec or more and 10 μsec or less, and the period of the second step is set to 2 μsec or more and 10 μsec or less. It is necessary to. This is to secure sufficient writing or operation time. However, if it is too long, the original voltage programming time becomes short and the stability is lost.

Therefore, the voltage programming method of FIG. 81 is also effective for implementing the driving method or display device of the present invention. In FIG. 81, the gate signal line 17
By controlling b, the switching TFT 11d
Can be turned on and off. Therefore, the current flowing through the EL element 15 can be made intermittent. Also in FIG. 87, by controlling the gate signal line 17c, T
The FT 11e can be on / off controlled. Therefore, the display states shown in FIGS. 49 and 53 can be realized.

[0868] Further, a driving method in which the current flowing through the EL element 15 is multiplied by N and the ON / OFF state of the TFT 11e is controlled to turn on the light for 1 / N (note that N
It is clear that the present invention can be realized (not limited to double or 1 / N). That is, the present invention is not limited to the pixel configuration of the current program shown in FIG. 6, and the driving method of the present invention can be realized with the pixel configuration of the voltage program shown in FIG. Therefore, the matters described in this specification can be applied to the pixel configuration or device described or illustrated in this specification.

Similarly, FIGS. 85 and 86 also have a pixel configuration for voltage programming. 85 and 86, the TFT 11e can be turned on / off by controlling the gate signal line 17b. Therefore, the current flowing through the EL element 15 can be made intermittent. Therefore, FIG.
The display states of FIG. 9, FIG. 53, etc. can be realized. Therefore,
You can easily achieve animation effects. Also, various image displays can be realized. Further, since other matters and operations are similar or similar to those in FIG. 87, description thereof will be omitted. Needless to say, the above items can be applied to the reverse bias voltage Vm application method described with reference to FIGS. 163 and 169.

For example, the reverse bias voltage Vm is R, G, B
The voltage value may be different for each pixel. In that case, the number of gate signal lines of the TFT for controlling the reverse bias voltage Vm increases. This is because the R, G, and B EL elements 15 have different terminal voltages and applied currents. For example,
In this system, −15V is applied to the EL element of the R pixel and −12V is applied to the EL elements of the G and B pixels.

Also, the application time of the reverse bias voltage (current) applied to each R, G, B EL element 15 may be different. This is because the terminal voltage and applied current are different for each RGB pixel. For example, the reverse bias voltage Vm is applied to the EL element of the R pixel for 1/2 time of 1F, and the reverse bias voltage Vm is applied to the EL element of the G and B pixels for 1/3 time of 1F. Is the method.

Further, the application time or the applied voltage of the reverse bias voltage (current) may be different for each part of the display screen 21. This is because, for example, when a Gaussian distribution method that brightens the central portion of the display screen is adopted, the EL element in the central portion has a larger current value than the peripheral portion.

As a problem of the method of applying the pulse voltage of N times, there is a problem that the current flowing through the EL element 15 becomes large and the EL element 15 is easily deteriorated. Also, N =
When it is 10 or more, there is also a problem that the terminal voltage of the EL element 15 required when a current flows becomes high and the power efficiency becomes poor. However, this task is E
This is a problem that occurs when the current flowing through the L element is large.
Taking the pixel configuration of FIG. 6 as an example,
This will be described with reference to FIG. 185 (a).

As shown in FIG. 185 (a), when the current Idd to the EL element 15 is flowing, the Vdd voltage (power supply voltage) is the source-drain voltage Vsd of the driving TFT 11a and the terminal of the EL element 15. The voltage is divided by the voltage Vd.
At this time, if the Idd current is large, the Vd voltage also becomes high.

If the Vdd voltage is sufficiently high, the driving TFT1
A current Idd equal to the current Iw programmed in 1a flows through the EL element 15. Therefore, as shown by the solid line in FIG. 186, the currents Iw and Idd have the same or substantially linear relationship (proportional relationship). A linear relationship means that the capacitor 19 is penetrated by a signal applied to the gate signal line 17 or the like, and Idd = I
It means that it cannot be w.

In the present invention, the Vdd voltage is used at such a low voltage that Idd and Iw cannot maintain a linear (proportional) relationship. That is, the relationship of required Vsd + Vd> Vdd is established. Furthermore, it is preferable that Vd> Vdd.

For example, assume that N = 10 and the Iw current required for maximum white display is 2 μA. In this state,
If the Idd current is 2 μA, Vd will be
= 14V, the Vdd voltage at this time is set to 14V or less. Or, if Vsd = 7V at this time, V
Let d + Vsd = 14V + 7V = 21V <Vdd = 21V.

When driven in this state, the currents Idd and Iw
186 becomes the relationship shown by the dotted line in FIG. 186, and the relationship between Iw and Idd is no longer linear in the maximum white display (non-linear relationship, range A in FIG. 186). However, in the black display or the gray display (area where the display brightness is relatively low), the linear relationship (range B in FIG. 154) is maintained.

In the area A, the current flowing through the EL element 15 is limited, and a large current that deteriorates the EL element 15 does not flow. In addition, when the Iw current is increased in the area A, the Idd current is increased although the change rate is small, so that gradation display can be realized. However, gamma conversion is necessary because it is non-linear in the area A. For example, when the image display is 64 gradation display, the input image data 64 gradation data is converted into a table, converted into 128 gradations or 256 gradations, and applied to the source driver 14.

[0879] In the area A, Vsd of the driving TFT 11a is
The voltage and the Vd voltage of the EL element 15 are divided to determine the terminal voltage Va of the EL element 15. At this time, a noteworthy point is that the EL element 15 is formed uniformly by vapor deposition (or formed by coating by an ink jet technique or the like), and thus is formed uniformly. Therefore, the EL terminal voltage Va has a uniform value within the surface of the display screen 21. Therefore, the characteristics of the driving TFT 11a vary and are corrected by the terminal voltage Va of the EL element 15. As a result, by lowering the Vdd voltage as in the present invention, the driving TFT 1
The characteristic variation of 1a can be absorbed, and the power consumption can be reduced by reducing the Vdd voltage. Moreover, even when N is large, a high voltage is not applied to the EL element 15.

The EL element 15 can be formed not only by the vapor deposition technique and the ink jet technique but also by the stamp technique in which the stamp with the ink is applied to the paper for printing.

First, a portion to be a stamp is formed. S
A stamp is formed by forming a groove pattern having the same shape as the light emitting region of the organic EL element on the i substrate by a semiconductor process and filling the groove with a material for doping the organic EL material. On the other hand, an organic EL material to be an electrode or a light emitting layer is formed on the glass substrate on which the organic EL element is formed.

Next, the stamp and the glass substrate on which the material to be the organic EL element is attached are exactly overlapped. While maintaining this state, heat treatment is performed at + 100 ° C to + 200 ° C for about 10 minutes. By doing so, the doping material embedded in the groove of the stamp is evaporated and diffused into the light emitting layer of the organic EL element. After that, apply stamps embedded with a doping material according to color to the organic EL element in order,
Paint RGB separately. With this stamp technology, 1
E of 0 μm rectangular pattern and pattern with 10 μm line width
The L element 15 can be easily formed.

[0883] Note that the EL element 1 is
The method is to obtain a predetermined brightness by applying a current to No. 5, making the applied current higher than a predetermined brightness, and shortening the ON time for the brightness higher than the predetermined brightness. However, the present invention is a method in which the average luminance within a certain period is set to a predetermined value.
Therefore, 1F (1 field or 1 frame)
It is not limited to. For example, the display state of FIG. 53 (c1) continues for 2F, the display state of FIG. 53 (c2) continues for 3F, and the display state of FIG. 53 (c1) and FIG.
The state of 2) may be alternately repeated. Finally 5
The driving may be performed so that the average luminance is desired at F.

Therefore, the technical idea of the present invention is to generate the ON state and the OFF state of the EL element 15 within a fixed period, and alternately repeat the ON state and the OFF state.
By repeating this, a predetermined display brightness is obtained. The control is realized by controlling the on / off voltage of the gate signal line 17.

Note that the source signal line 18 is supplied with a current N times the predetermined current and the EL element 15 is supplied with a current N times the predetermined current for a 1 / N period, but this cannot be realized in practice. This is because the signal pulse applied to the gate signal line 17 actually penetrates into the capacitor 19 and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set in the capacitor 19. For example, even if driving is performed so as to set a current value of 10 times, only a current of about 5 times is set in the capacitor 19. Even when N = 10, the current actually flowing through the EL element 15 is the same as when N = 5. Therefore, the present invention is a method in which a current value of N times is set and a current proportional to or corresponding to N times is driven to flow through the EL element 15 (however, the driving method described in FIG. 186 is also performed. Limited is difficult). Alternatively, it is a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.

Further, a current (voltage) which is higher than a desired value (a current which becomes higher than the desired brightness when the current is continuously applied to the EL element 15 as it is) is applied to the driving TFT 11a (in the case of exemplifying FIG. 6). By programming and intermittently flowing the current flowing through the EL element 15, a desired light emission brightness of the EL element is obtained.

Further, if FIG. 6 is shown as an example (FIGS. 142 and 8)
5, FIG. 86, FIG. 183, FIG. 87, etc. are also effective), the driving TFT 11a and the signal (current, voltage) path for programming the driving TFT are set (configuration, arrangement, connection). ), The current from the first switching TFT 11c and the driving TFT 11a is E
In a pixel configuration including a second switching TFT 11d for setting (configuring, arranging, connecting) a flow path to the L element 15, the first switching TFT 11c is provided.
Is turned on (path is set), and the second switching TFT
In a first state in which 11d is turned off (path is cut), a first state in which a current (voltage) is programmed in the driving TFT, and the first switching TFT 11c is turned off (path is cut), and a second state is set. A second state in which the switching TFT 11d is turned on (a path is set), a third state in which the first switching TFT 11c is turned off (a path is cut), and the second switching TFT 11d is turned off (a path is cut). And the state of.

Also, in the active matrix type display panel, the current path flowing from the driving TFT 11a to the EL element 15 is cut or reduced for a predetermined period of one frame (one field) period (the current waveform flowing to the EL element 15 is The present invention is not limited to a rectangle or DC, but may be a sine waveform, etc. Further, the DC amplitude value may be changed) to reduce the light emission luminance of the EL element 15 in at least one frame (one field). is there.

[0888] Also, an operation of programming the driving TFT 11a so that the EL element 15 emits light with a brightness higher than a desired value, and the programmed signal (current) is passed through the EL element 15, and at least one frame (1 The operation is performed so as not to flow into the EL element 15 in a predetermined period during the field period.

Alternatively, the current flowing through the EL element 15 is limited so that the brightness becomes equal to or lower than the brightness corresponding to the current programmed in the driving TFT 11a.

[0891] Also, the EL element 1 has a brightness higher than the desired value.
5 is programmed so that light is emitted, and the average brightness (desired brightness) of one frame (one field) is equal to or less than the desired brightness or at least the desired brightness (programmed brightness (current)). The operation is performed so that the program current does not flow into the EL element 15. Further, it is not limited to completely turning on / off the current flowing through the EL element 15.

[0892] For example, referring to FIG.
By setting T11d to the high resistance ON state (that is,
A current smaller than a predetermined value is flowing in the EL element 15), and the EL element 15 can be turned off or low-luminance light emission can be performed. When the EL element 15 emits light with low luminance, it is necessary to understand that the non-display area 312 of the display screen 21 is replaced with dark (luminance close to gray or black display) instead of full black display. That is, the non-display area 312 may be a display with lower brightness than the normal display. The low-brightness display includes a display state in which an image can be recognized.

In the above embodiment, the reverse bias voltage is applied during the non-lighting time of the EL element 15 (FIG. 170, FIG. 1).
68, etc.) is effective. Further, it goes without saying that it is also effective for the voltage programmed pixel configuration shown in FIG.

Note that in FIG. 49, etc., the non-display area 3
12 need not be completely unlit. There is no problem in practice even if there is faint light emission or faint image display. That is, it should be interpreted as an area having lower display brightness than the image display area 311. In addition, the non-display area 31
The term 2 also includes the case where only one or two colors of the R, G, and B image displays are in the non-display state.

In each pixel configuration (see, for example, FIG.
1, FIG. 158, FIG. 184 (a)), TF for switching
Even if the gate terminal of T11d is directly applied to the on / off voltage, the current flowing through the EL element 15 can be operated intermittently. Also, in FIG.
T11e, the conversion TFT 11a in FIG. 19, and FIG.
0, directly to the gate terminal of the driving TFT 11b,
Even if the on / off voltage can be applied, the current flowing through the EL element 15 can be operated intermittently. That is, the display state shown in FIG. 49 or the like can be implemented by controlling the gate terminal of the TFT that applies a current to the EL element 15.

As described above, according to the present invention, the EL element 15 is intermittently displayed by turning on and off the current applied to the EL element 15. To display intermittently,
In the example of FIG. 6, it is necessary to control the switching TFT 11d to be turned on and off. Therefore, the switching TFT
A gate signal line for turning on / off 11d is required. That is, in order to display the EL element 15 intermittently,
The capacitor requires a first switching element that forms a path for programming a current flowing through the EL element 15, and a first gate signal line for on / off controlling the first switching element. In addition, a second switching element that forms a current path flowing through the EL element 15,
The second for turning on and off the second switching element
Gate signal line is required. That is, two gate signal lines are required for each pixel.

However, if two or more gate signal lines are required for one pixel, the problem will arise in the three side free pixel configuration described in FIG. This is because even if the gate driver 12 is formed by a low temperature polysilicon technique or the like, the number of shift registers becomes large and the circuit configuration becomes complicated. In particular,
The challenge becomes even greater if an amorphous silicon technology is used to realize a three-side free configuration. This is because the gate driver 12 (or the source driver 14) cannot be directly formed on the display panel 82 by the amorphous silicon technology.

Therefore, it is necessary to arrange the source driver 14 and the gate driver 12 on one side of the display screen 21 in order to form the display panel by the amorphous silicon technology. Then, the gate signal line 17a and the gate signal line 17
It is necessary to wire all of b in the left and right of the display screen. If the number of gate signal lines 17 is small, it may still be possible, but since the number of vertical pixels is 220 dots even in QCIF, the gate signal line 17 has 220 ×
2 = 440. In addition, even when the gate driver 12 is built in by the low temperature polysilicon technology, if the number of wirings of the gate signal line 17 is large, the frame cannot be narrowed.
Therefore, the product power is lost.

The present invention described below solves the above problems. Briefly, a plurality of gate signal lines 17b for turning on / off the EL element 15 are commonly used. The current flowing through the EL element 15 is turned on / off for each common block.

Also in the embodiment of FIGS. 45 and 116, E
It is not necessary to control ON / OFF of the L element 15 for each pixel row. This is because the non-display area 312 can be formed and the image display area 311 can be formed even if each block is turned on / off. The method of performing on / off control in blocks as described above is called block drive. However, since there is an example in which adjacent pixel rows are used as blocks, the concept is broader than the concept of ordinary blocks. However, in the pixel configuration of FIG. 6, the pixel row for which current programming is performed needs to be in a non-lighting state. Therefore, the block including the pixel row selected for the current programming needs to be the non-display area 312. However, even in the case of FIG. 6, it is not necessary to set the non-display area 312 even in the pixel row for which the current programming is performed, if some blurring is allowed in the image. Further, in the pixel configuration of the current mirror of FIG. 19, even in the pixel row for which current programming is performed, the non-display area 31
It does not have to be 2.

The present invention will be described mainly by exemplifying the pixel configuration of the current program shown in FIG. 6, but the present invention is not limited to this, and other current program configurations (current The pixel configuration of the mirror) is also applicable. Further, the technical concept of turning on and off in blocks can be applied to the pixel configuration of voltage programming such as in FIGS. 86 and 87. Further, since the present invention is a method of intermittently making the current flowing through the EL element 15, FIG.
It can also be combined with the method of applying the reverse bias voltage described in 3 and the like. As described above, the present invention can be implemented in combination with other embodiments.

FIG. 187 shows an example of block driving.
First, for ease of explanation, it is assumed that the gate driver 12 is directly formed on the array substrate 49 or the silicon chip gate driver 12 is mounted on the array substrate 49. The source driver 14 and the source signal line 18 are omitted because the drawing is complicated.

In FIG. 187, the gate signal line 17a is connected to the gate driver 12. On the other hand, the gate signal line 17b of each pixel is connected to the lighting control line 1791. In FIG. 187, four gate signal lines 17b are connected to one lighting control line 1791. Blocking with the four gate signal lines 17b is not limited to this, and more blocks may be used. In general, the display screen 21 is preferably divided into at least 5 or more, and more preferably 10 or more. Furthermore, it is preferable to divide into 20 or more. Because when the number of divisions is small,
This is because if flicker is easily visible and if the number of divisions is too large, the number of lighting control lines 1791 increases, and the layout of the lighting control lines 1791 becomes difficult.

Therefore, in the case of the QCIF display panel, since the number of vertical scanning lines is 220, at least 220/5 = 44 or more, preferably 220/1.
Blocking is required when 0 = 11 or more. However, when two blocks are divided into an odd row and an even row, flicker is relatively small even at a low frame rate.
Sometimes two blocks are sufficient.

In the embodiment of FIG. 187, the lighting control line 179
1a, 1791b, 1791c, 1791d are sequentially applied with the on-voltage Vgl or the off-voltage Vgh to turn on / off the current flowing through the EL element 15 for each block.

In the embodiment of FIG. 187, the gate signal line 17b and the lighting control line 1791 do not cross each other. Therefore, the gate signal line 17b and the lighting control line 17
The short defect with 91 does not occur. Further, since the gate signal line 17b and the lighting control line 1791 are not capacitively coupled to each other, the lighting control line 1791 to the gate signal line 17b are not connected.
The capacity addition when viewed from the side is extremely small. Therefore, it is easy to drive the lighting control line 1791.

FIG. 188 shows the connection state of FIG. 187 in more detail. A gate signal line 17a is connected to the gate driver 12. By applying the on-voltage Vgl to the gate signal line 17a, a pixel row is selected, the TFTs 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is applied to each pixel. Program capacitor 19. On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11d of each pixel. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791, the driving TFT 11a and the EL
A current path is formed with the element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is opened.

Note that the control timing of the on / off voltage applied to the lighting control line 1791 and the timing of the pixel row selection voltage Vgl output to the gate signal line 17a by the gate driver 12 are synchronized with one horizontal scanning clock (1H). It is preferable. However, it is not limited to this. The signal applied to the lighting control line 1791 simply turns on / off the current to the EL element 15. Further, it does not need to be synchronized with the image data output by the source driver 14. This is because the signal applied to the lighting control line 1791 controls the current programmed in the capacitor 19 of each pixel 16. Therefore,
It does not necessarily have to be synchronized with the selection signal of the pixel row. Further, the clock is not limited to the 1H signal even in the case of synchronization, and even if it is 1 / 2H, it is 1 / 4H.
May be

FIG. 189 shows a case where the pixel configuration is the current mirror pixel configuration shown in FIG. However,
As described in the previous embodiment, in order to control the current flowing through the EL element 15, the TFT 11e is formed and the gate signal line 17b for controlling the TFT 11e is formed.
Is added.

Note that in FIG. 189, the taking-in TFT 1
Control 1c and switching TFT 11d (on / off)
The common gate signal line (gate signal line 17a) is used, but the gate signal line is not limited to this and may be a separate gate signal line 17. In this case, the capturing TFT 11c
The first gate signal line 17 that controls the gate driver 12 and the second gate signal line 17 that controls the switching TFT 11d are connected to the gate driver 12.

In FIG. 189, the gate signal line 17a is connected to the gate driver 12. A pixel row is selected by applying an ON voltage to the gate signal line 17a. Note that the same applies to FIG. 188 and the like, but the selected pixel row is not limited to one pixel row. For example, in FIGS. 94, 118, and 121, a plurality of pixel rows are selected. As described above, the present invention is not limited to the number of pixel rows selected.

In FIG. 189, when the ON voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b and the switching TFT 11d of each selected pixel are turned on, and the current (voltage applied to the source signal line 18 ) Is programmed into the capacitor 19 of each pixel. That is, the source driver 14 outputs (absorbs) the current (voltage) written in the pixel 16. On the other hand, the gate signal line 17b is connected to the gate terminal of the TFT 11e of each pixel. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791, a current path between the driving TFT 11b and the EL element 15 is formed, and conversely, when the OFF voltage Vgh is applied, the EL
The anode terminal of the element 15 is opened.

FIG. 190 shows a pixel configuration for voltage programming. However, as described in the previous embodiment, the EL
Controls the current flowing through the element 15 (to enable intermittent operation)
In order to do so, the switching TFT 11d is formed, and the gate signal line 17b for controlling the switching TFT 11d is added. This gate signal line 17
b is connected to the lighting control line 1791 for each plurality of pixel rows.

In FIG. 190, the gate signal line 17a is connected to the gate driver 12. By applying an ON voltage to the gate signal line 17a, the driving TFT
11b is turned on, and a predetermined pixel row is selected.

In FIG. 190, when the ON voltage Vgl is applied to the gate signal line 17a, the driving TFT 11b of each selected pixel is turned on and the current (voltage) applied to the source signal line 18 is applied to each pixel. Program capacitor 19 of That is, the source driver 14 outputs (absorbs) the current (voltage) written in the pixel 16. On the other hand, the gate signal line 17b is connected to the gate terminal of the switching TFT 11d of each pixel. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791, the driving T
A current path is formed between the FT 11a and the EL element 15, and conversely, when the off voltage Vgh is applied, the anode terminal of the EL element 15 is opened.

In FIG. 191, the intermittent operation of the current flowing through the EL element 15, which is the pixel configuration of another voltage program, is performed using the switching TFT 11d. The gate signal line 17d for controlling the switching TFT 11d is connected to the lighting control line 1791 for each plurality of pixel rows.

In the pixel configuration of FIG. 191, two gate signal lines 17a and 17c are required to measure the offset voltage and hold the voltage written in one frame period in the capacitor 19. Therefore, the two gate signal lines 17a and 17c are connected to the gate driver 12. This configuration is shown in FIG. The gate driver 12 includes a gate signal line 17a and a gate signal line 1
By applying on-off voltage to 7c,
The T11c and the driving TFT 11b are controlled to be turned on and off, and the voltage output from the source driver 14 is programmed in the pixel. On the other hand, the gate signal line 17d is connected to the gate terminal of the switching TFT 11d of each pixel. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791, a current path between the driving TFT 11a and the EL element 15 is formed, and conversely, when the OFF voltage Vgh is applied,
The anode terminal of the EL element 15 is opened.

As described above, the present invention can be applied regardless of whether the pixel structure is the current program system or the voltage program system. Although the above embodiment has been described by exemplifying the active matrix type display panel, the present invention is not limited to this and can be applied to a simple matrix type display panel. because,
This is because the EL element 15 can be turned on or off for each block even in the simple matrix type display panel.

FIG. 193 shows another embodiment. In the following embodiments, differences from the above-described embodiments will be mainly described. Therefore, the pixel configuration and the like can be applied to any of the configurations described with reference to FIGS.

In FIG. 193, the gate signal line 17b is shared by every two pixel rows, and the lighting control line 17 is provided every four blocks.
The configuration is common to 91. The gate signal line 17b for the first and second pixel rows and the gate signal line 17b for the ninth and tenth pixel rows are connected to the lighting control line 1791a.
Have in common. Therefore, the lighting control line 1791a
When the on-voltage Vgl is applied to the
The 2nd, 9th and 10th pixel rows are illuminated.

[0921] Further, the gate signal line 17b for the third and fourth pixel rows and the gate signal line 17b for the eleventh and twelfth pixel rows are commonly used by the lighting control line 1791b. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791b, at least the third, fourth, eleventh and twelfth pixel rows are lit.

Similarly, the gate signal line 17b for the fifth and sixth pixel rows and the gate signal line 17b for the thirteenth and fourteenth pixel rows are shared by the lighting control line 1791c. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791c, at least the fifth, sixth, thirteenth and fourteenth pixel rows are lit.
In addition, the gate signal lines 17 of the seventh and eighth pixel rows
b and the gate signal line 17b of the 15th and 16th pixel rows are shared by the lighting control line 1791d. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791d, at least the 7th, 8th, 15th and 16th pixel rows are lit.

When the gate signal line 17b is connected to the lighting control line 1791 as shown in FIG. 193, small lighting blocks are displayed in a dispersed manner. Therefore, flicker is less likely to occur even at a low rate.

FIG. 194 shows a configuration in which the gate signal line 17b is commonly connected to the lighting control line 1791 by skipping four pixels. The gate signal lines 17b of the first, fifth, ninth, and thirteenth pixel rows are commonly used by the lighting control line 1791a. Therefore, the lighting control line 1791a
When the on-voltage Vgl is applied to the
The fifth, ninth and thirteenth pixel rows are illuminated.

Also, the second, sixth, tenth,
The gate signal line 17b of the 14th pixel row is shared by the lighting control line 1791b. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791b, at least the second, sixth, tenth, and fourteenth pixel rows are lit.

Similarly, the gate signal line 17b of the third, seventh, eleventh, and fifteenth pixel rows is commonly used as the lighting control line 1791c. Therefore, when the ON voltage Vgl is applied to the lighting control line 1791c, at least the third, seventh, eleventh and fifteenth pixel rows are lit. Also, the 4th, 8th, 1st
The gate signal line 17b of the second and 16th pixel rows is commonly used by the lighting control line 1791d. Therefore, when the on-voltage Vgl is applied to the lighting control line 1791d, at least the fourth, eighth, twelfth, and sixteenth voltages are applied.
The th pixel row lights up.

When the gate signal line 17b is connected to the lighting control line 1791 as shown in FIG. 194, the pixel rows to be lit are dispersed more than in FIG. 193. Therefore, flicker is less likely to occur even at a low rate.

FIG. 195 shows the gate signal line 1 of the odd-numbered pixel row.
7b is connected to the lighting control line 1791a, and the gate signal lines 17b of even-numbered pixel rows are connected to the lighting control line 1791b.

In FIG. 195, the EL element 15 is provided for each pixel row.
Since the lighting can be controlled, flicker is reduced even at a low rate. In addition, the number of lighting control lines 1791 is two, which is small.

In FIG. 196, the gate signal line 17b is switched to the lighting control line 1791a or the lighting control line 179 every four pixel rows.
1b is connected. In FIG. 196, it is easy to synchronize with the timing of the current (voltage) program to the pixel.

[0931] In the above embodiments, the ON / OFF control is performed for each pixel row by the voltage applied to the lighting control line 1791, and the present invention aims to intermittently operate the EL element 15. Therefore, the lighting control line 1791
It is not limited to the presence or absence of.

For example, in FIG. 197, the lighting control driver circuit 1891 is formed (arranged) on one side of the display screen.
That is, the gate driver 12 is formed (arranged) on one side of the display screen, and the lighting control driver circuit 18 is provided on the opposite side of this side.
91 are arranged (formed). Lighting control driver circuit 1
891 may be directly formed on the array substrate 49 by using a low temperature polysilicon or a high temperature polysilicon technique, or may be composed of a silicon chip and COG is formed on the array substrate 49.
You may load using technology etc. However, as shown in FIG. 197, the circuit configuration becomes extremely simple by sharing (blocking) the plurality of gate signal lines 17b. Therefore, even if it is formed directly on the array substrate 49, or if it is composed of silicon chips and mounted on the array substrate 49, it occupies almost no area. Therefore, a narrow frame of the display panel can be realized. The lighting control driver circuit 1891 may be arranged on the same side as the source driver 14 to realize a three-side free configuration.

In the embodiments up to FIG. 197, the gate driver 12 is directly formed on the array substrate 49 using low temperature polysilicon or high temperature polysilicon technology, or is constituted by a silicon chip, and COG technology or the like is applied to the array substrate 49. However, the present invention is not limited to this. For example, as shown in FIG. 198, the gate signal line 17a may be wired from the side where the source driver 14 is arranged. That is, the lighting control line 1
Both 791 and the gate signal line 17a are formed at the edge of the display screen 21. The other structure is similar to that of FIG.

Also, as shown in FIG. 199, the source driver 14 and the gate driver 1 are provided on two sides of the display screen.
Alternatively, the two may be arranged (formed) and connected to the gate driver 12 and the source driver 14 at the center of the display screen 21. With this configuration, the routing of the gate signal line 17a is reduced (1 /
2), and a narrower frame can be realized.

FIG. 200 is an explanatory diagram in which the source driver 14 and the gate driver 12 are arranged on the panel. Figure 2
In 00, the source driver 14 is made of a silicon chip and arranged on one side of the array substrate 49. The gate driver 12 is directly formed on the array substrate 49 by using low temperature polysilicon, CGS technology or high temperature polysilicon technology. The on / off voltage to the lighting control line 1791 is output from the source driver 14.

FIG. 201 shows a lighting control driver circuit 1891.
Is an example in which low temperature polysilicon, CGS technology or high temperature polysilicon technology is directly formed on the array substrate 49. Of course, the lighting control driver circuit 1891 may be made of a silicon chip and mounted on the array substrate 49 using COG technology or the like.

FIG. 202 shows an example in which the on / off signal to the lighting control line 1791 is output from the control IC 101 or the like. In this way, the source driver 1 is configured by outputting the ON / OFF data of the lighting control line 1791 from the control IC 101 such as a microcomputer.
4 is simplified, and even if the driving method is changed, the source driver 14 need not be changed.

FIG. 203 shows a configuration using a gate driver 12a and a source driver 14a for driving the display screen 21a, and a gate driver 12b and a source driver 14b for driving the display screen 21b. The other structure is similar to that of the previous embodiment, and the description thereof is omitted.

In FIG. 204, an ON / OFF signal to the lighting control line 1791 is output from the control IC 101 or the like, and the gate driver 12 and the source driver 14 are arranged on the array substrate 49 by using low temperature polysilicon, CGS technology or high temperature polysilicon technology. This is an example of direct formation.
Of course, the source driver 14, the lighting control driver circuit 1891, and the like are manufactured using a silicon chip, and the array substrate 4
9 may be loaded using COG technology or the like.

FIG. 205 shows a configuration in which an ON / OFF signal to the lighting control line 1791 is output from the control IC 101 or the like, and a control signal to the gate signal line 17a and image data to the source signal line 18 are realized by the source driver 14a. The source driver 14a is made of low temperature polysilicon, C
It may be directly formed on the array substrate 49 by using the GS technique or the high temperature polysilicon technique. In addition, the source driver 14a and the like are manufactured from a silicon chip, and the array substrate 4
9 may be loaded using COG technology or the like.

In FIG. 173 to FIG. 182, etc., the method of applying the reverse bias voltage Vm has been described. The reverse bias voltage Vm was basically applied to the EL element 15 when no current was applied. On the other hand, FIG.
In the block driving method described in 88, etc., the non-display area 312 and the image display area 311 are formed for each block. Based on these, the reverse bias voltage Vm can be applied to the EL element 15 in the non-display area 312 by block driving. That is, the reverse bias voltage (current) is applied to each block. However, the reverse bias voltage Vm is not limited to being applied to all blocks in the non-display area 312. For example, an arbitrary block may be divided into a plurality of blocks, and the reverse bias voltage Vm may be applied to each of the divided blocks. Of course, the non-display area 312 may be controlled for each block, and the application of the reverse bias voltage Vm may be controlled for each pixel row.

As described above, by applying the reverse bias voltage Vm to each block, the configuration shown in FIG.
The pixel configuration described in 3 and the like is simplified, and the control is easy. In particular, the reverse bias voltage Vm is applied to the non-display area 312.
, So that the logic is simple.

FIG. 206 shows an embodiment of the present invention in the case where the block drive and the reverse bias voltage drive are combined, which is the same as the pixel configuration of FIG. 173. This pixel configuration is shown in FIG.
It is combined with the block drive described in 88. It goes without saying that the block drive can be applied to any of the configurations described in FIGS. 188 to 205.

In FIG. 206, by applying the off voltage Vgh to the lighting control line 1791, the corresponding block becomes the non-display area 312. At the same time (they are not limited at the same time. The off voltage Vgh is applied to the corresponding lighting control line 1791.
Is applied for any period), the on-voltage Vgl is applied to the reverse bias control line 2111. Then, the reverse bias voltage Vm is applied to the EL element 15 of the block. In other words, in terms of logic,
The signal of the opposite phase of the lighting control line 1791 may be used as the reverse bias control line 2111.

Similarly, FIG. 207 shows a configuration in which a reverse bias drive system is added to the configuration of FIG. 189. Also, FIG.
8 is a configuration in which a reverse bias drive system is added to the configuration of FIG. 190, and FIG. 209 is a configuration in which a reverse bias drive system is added to the configuration of FIG. The operation is easy and will not need any explanation.

As described above, it is not necessary to completely synchronize the application of the reverse bias voltage Vm and the block drive. Further, it is not necessary to completely match the scanning cycle.

The block driving of the present invention will be described below. FIG. 210 is an explanatory diagram of the block driving method of the present invention. Also in the following explanatory diagrams, the pixel configuration will be described as the pixel configuration illustrated in FIG. 6 for ease of description. However, the present invention is not limited to this, and FIG.
It goes without saying that other pixel configurations such as those shown in FIGS. 86 and 87 are also possible.

In the case of the pixel configuration of FIG. 6, it is necessary to turn off the switching TFT 11d of the pixel row for which current programming is being performed. That is, the EL element 15 is driven so as not to be seen from the source signal line 18 in the selected pixel row (the EL element 15 is not connected to the source signal line 18). This is to prevent the program current from the source signal line 18 from flowing into the EL element 15. E
This is because if a programming current flows in the L element 15, a regular current cannot be programmed in the capacitor 19.

Therefore, when the block driving is performed, the block including the selected pixel row needs to be the non-display area 312. In other words, when the pixel row in the block is selected, this block is constantly in the non-display area 3
12 On the contrary, the other blocks are the image display area 311.
However, any of the non-display areas 312 may be used. Flicker is suppressed by performing on / off control of blocks other than the selected pixel row.

FIG. 210 (a) is a block 1981b-1.
The writing pixel row 871a of the book is selected. Therefore, the block 1981b is controlled to be in a non-lighting state. If the block 1981 includes 6 pixel rows, the selected block 1981 has a period of 6H,
It is controlled to a non-lighting display.

FIG. 210 (b) shows 1H from FIG. 210 (a).
It is a display state later. Selected write pixel row 871
a is shifted by one pixel row. In FIG. 210A, blocks in the non-display area 312 are 1981b and 19b.
81d, 1981f, 1981h, and 1981j.
In FIG. 210B, the blocks in the non-display area 312 are
1981a, 1981b, 1981e, 1981g, 1
It is 981i. That is, in FIGS. 210A and 210B, the non-display area 312 and the image display area 311 are inverted except for the block 1981b including the selected write pixel row 871a.

Note that the selected pixel row is not limited to one pixel row, and a plurality of selected pixel rows may be used. For example, FIGS.
6, the method of selecting a plurality of pixel rows and the block driving of FIG. 210 or the method of FIG.
6 can be combined with the reverse bias voltage drive of 6 or the like.

Further, in FIG. 210, the switching TFT 11d of the selected pixel row is turned off and the EL element 15 is not turned on. However, in the case of the current mirror configuration as shown in FIG. 19, the source signal line 18 and the EL element are not turned on. 15 is not connected. Therefore, the selected pixel row may be in the display state. However, it is preferable to control the selected pixel row to a non-illuminated state because the image in that period is under programming during programming.

In FIG. 210, the inversion of the non-display area 312 and the image display area 311 is performed in the cycle of 1H, but it is not limited to this and may be 2H or more. Good. The lighting control may be performed relatively randomly. Further, as a matter of course, the reverse bias voltage Vm may be applied to the non-lighted blocks.

[0955] The non-display area 312 and the image display area 3
The control with 11 does not have to be performed simultaneously for the RGB pixels, and the lighting control may be different for R, G, and B. This includes the case of FSC (frame sequential control).

Further, in FIG. 210, ON / OFF control is performed for each block, but the present invention is not limited to this. For example, as shown in FIG. 211, two blocks (for example, blocks 1981b and 1981 in FIG. 211 (a)).
c and the non-display area 312. Also, block 1
981d and 1981e are used as the image display area 311). Also, after 1H, as shown in FIG.
The lighting control may be performed as in (b). Figure 211
In (a) and (b), lighting control is performed by shifting one block at a time. Note that in FIGS. 210, 211, etc., the number of blocks 1981 is very small for ease of illustration. The above matters also apply to the other embodiments.

FIG. 212 shows a method of forming a brightness distribution on the display screen 21 by controlling the lighting of blocks. For ease of explanation, FIG. 212 (a) is set to the state of the 1Hth,
212 (b) will be described assuming that it is 1H after the next of FIG. 212 (a). Of course, FIGS. 212 (a) and 212 (b) may be in a state of being separated by a predetermined period.

A Gaussian distribution is exemplified as the brightness distribution. In other words, it is a method of brightening the central portion of the display screen and darkening the peripheral portion thereof, thereby visually brightening them and reducing power consumption. In the present invention, in the horizontal direction of the screen, the data itself is changed by the modulation of the video signal to form the brightness distribution. For example, a line memory for one pixel row is mounted, and this memory holds coefficients required for calculation. For example, if the edge of the screen is 50% of the center, the coefficient corresponding to 50% is held. Less than,
Coefficients are held in the line memory so that the central portion becomes 100% and the Gaussian distribution is satisfied. The applied image data is calculated with the coefficient of this line memory, and the calculated result is applied to each source signal line.

[0959] Note that the non-display area 312 is also displayed in the vertical direction of the screen.
If you configure the pixel so that it can be turned on and off, the data itself is changed in the horizontal direction of the screen by the modulation of the video signal,
Therefore, it is not necessary to form the brightness distribution. For example, the signal line may be formed so that the switching TFT 11d of one pixel column can be on / off controlled. That is, the switching TFTs 11d may be controlled in a matrix on the display screen.

The Gaussian distribution is an example. In other words, a luminance distribution state that brightens the vicinity of the central portion of the display screen 21 is generated. Therefore, the brightness distribution is not limited to the Gaussian distribution, and may be a sine curve-shaped brightness distribution or a conical brightness distribution. Further, since the present invention controls the switching TFT 11d and the like to generate the brightness distribution, it is not limited to brightening the central portion of the display screen 21. For example, the central part of the display screen may be in the darkest state, or the upper part of the display screen may be in the brightest state. These brightness distribution states are also for switching T
This can be easily realized by controlling the FT 11d and the like. This is because it can be realized simply by adjusting (changing) the control timing and ON time of the gate signal line 17b.

Also, the brightness distribution state can be freely or automatically changed by the user according to the type of image. For example, in the partial display, the partial display position can be displayed particularly bright. In addition, it is possible to easily change the color of an arbitrary display portion or to display only a required portion outdoors so as to be bright.

The brightness is not limited to the three primary colors of R, G, and B being generated at the same time and changed to the same position (white color moves). For example, the maximum brightness position of only R can be moved. As described above, the color pattern on the display screen 21 can be generated by changing the maximum brightness (minimum brightness) position of each color.

The formation of the brightness distribution in the vertical direction of the display screen 21 is realized by the on / off control of block 1981. That is, the block 198 in the central portion of the display screen.
The number of OFF times of 1 is reduced, and the number of OFF times is increased above or below the display screen. The display turns darker as the number of off times increases, and becomes brighter as the number of off times decreases. By controlling this on / off, a Gaussian distribution can be formed in the vertical direction of the display screen. Therefore, the brightness of the left and right sides of the display screen is adjusted (controlled) by calculating the image data (or the amplitude value may be modulated by analog modulation).
The brightness of the display screen is adjusted (controlled) by the on / off control of the block 1981 in the vertical direction of the display screen.

Note that in FIG. 212 and the like, block 1
Although the brightness distribution is formed by the on / off control of 981, the invention is not limited to this. Block 198
It is needless to say that the brightness distribution can be formed by performing on / off control for each pixel row, not limited to 1. It can also be realized by performing on / off control for each of a plurality of pixel rows. That is, the on / off control in block 1981 is merely the on / off control as a group of a plurality of pixel rows. Therefore, FIG. 212 and the like are one example in which the technical scope of the present invention is limited.

The non-display area 312 in FIG. 212 (a) is a block 1981b, 1981d, 1981h, 1981.
j. The non-display area 312 in FIG. 212 (b) is a block 1981a, 1981c, 1981i, 1981k.
Is. Therefore, the central blocks 1981e, 1
In FIGS. 212 (a) and 212 (b), 981f and 1981g are lit. Therefore, the central part becomes bright.

On the other hand, in FIG. 212 (a), block 19
81a, 1981c, 1981i, and 1981k are image display areas 311, but in FIG. 212 (b), they are non-display areas 312. Therefore, the upper and lower parts of the displayed image are dark.

From the above, the brightness distribution can be formed in the display image by performing the ON / OFF control for each block 1981. Note that, in FIG. 212, blocks 1981e, 1981f, and 1981g in the central portion are shown in FIG.
Although both (a) and (b) are turned on, the brightness can be freely controlled and the occurrence of flicker can be suppressed by performing control such as turning off in the next 1H.

In FIG. 212, the blocks 1981 were all the same width. However, visually, the display screen 21
The central part of may be made finer and the peripheral part may be roughened, for example,
It implements like FIG. This is because the human visual resolution is high in the central part of the screen.

In FIG. 213, the on / off control is as shown in FIG.
13 (a) and 13 (b) are performed alternately. In the blocks 1981f to 1981n at the center of the display screen 21, on / off control is performed in small block units (one unit), the top and bottom of the center are controlled in two block units, and the top and bottom of the display screen are in three block units. ON / OFF control is performed with. Note that the OFF control of the write pixel row 871a is performed by using FIG.
The non-display area 312 is formed by the method described in 77.

In FIG. 213, the width of the lighting block 1981 is changed to perform on / off control in the central portion of the display screen to realize a visually matched display. In FIG. 214, a plurality of unit cycles are used. The Gaussian distribution on the display screen is realized by controlling the number of times of turning on and off. FIG. 214 shows 6 cycles (FIG. 214 (a) → (b))
→ (c) → (d) → (e) → (f) → (a) → (b) →
(C)->(d)->(e)->(f)-> (a)) forms the brightness distribution of the display screen. Of course, it is not limited to 6 cycles, and may be 2 cycles or 8 cycles or more. The unit of the cycle may be 1H, 1F, or may be synchronized with another clock. Note that FIG.
Also in the above, the Gaussian distribution in the horizontal direction of the display screen is performed by a video signal or the like. This has been described with reference to FIG. The above items also apply to other inventions.

As shown in FIG.
In (b) and (e), the image display area 31 is displayed at the center of the display screen.
214, a large number of image display areas are generated near the center of the display screen in FIGS. 214C and 214F. By controlling in this way, the central part of the display screen becomes bright. Therefore, a good Gaussian distribution can be generated.

FIG. 215 does not generate the Gaussian distribution, but suppresses the occurrence of flicker by changing the position of the lighting block 1981 in a plurality of periods. In FIG. 215 (a), the non-display area 312 is generated every two blocks, and the next block in FIG. 215 (b) is generated.
In, the non-display area 312 is generated every three blocks. In the next block, FIG. 215 (c), the non-display area 312 is generated every four blocks. As described above, the non-display area 312 or the image display area 31
The occurrence of flicker can be suppressed by changing the position 1 at a plurality of cycles. A Gaussian distribution can also be generated by combining the methods described in FIGS. 213 and 214.

In the above embodiment, as shown in FIG. 216, the lighting position is changed in block 1981 units. However, the present invention is not limited to this. For example, as shown in FIG.
The lighting position may be changed block by block. That is, in the above-described embodiment, the ON / OFF control is mainly performed in block units, but the present invention is not limited to this. Generation of Gaussian distribution and suppression of flicker are described in block 1981.
This is because it can be realized without using a unit. As described above, the non-lighting control may be performed on a pixel row basis.
Of course, the non-lighting control or the lighting control may be performed in units of a plurality of pixel rows.

Also, it is not limited to the pixel row,
The on / off processing may be performed on the pixel columns, or the on / off processing may be performed on both the pixel rows and the pixel columns. Further, the pixel rows that are turned on and off are not limited to sequential processing, and random processing may be performed. By randomly controlling the pixel rows (pixel columns) to be turned on and off, it is possible to make the display screen 21 difficult to see and to cause flicker. Further, the specific pixel row (pixel column) can be always set as the non-display area 312. Further, the whole screen or a part thereof is displayed on / off at a low frame rate (a non-display area 312 and an image display area 311).
It is also possible to make the screen flush by repeating the above. These can be applied as image scramble processing or special effect processing.

[0975] However, the above display state is in the block 19
It goes without saying that the control by 81 units facilitates the circuit configuration and the panel configuration and the pixel configuration.

As shown in FIG. 218, the image is displayed by scanning the image display area 311 from the top to the bottom of the display screen 21 ((a) → (b) → (c) → (d) →
(E) → (a) → (b) → (c) →). At this time, the brightness distribution (Gaussian distribution or the like) can be realized in the vertical direction of the display screen by controlling the scanning clock.

In FIG. 218, in the display state of (c), when the image display area 311 is scanned, the image display area 311
Slow down the scanning speed of. When the image display area 311 is scanned in the portions (a) and (e), the image display area 311 is scanned.
Increase the scanning speed of. When the image display area 311 is scanned in the portions (b) and (d), the image display area 31
The scanning speed of 1 is an intermediate speed between (a) and (c). The scanning speed can be realized by controlling CLK * applied to the shift register 22 of the gate driver 12 described with reference to FIG. Further, it can be realized by controlling the lighting control line 1791 described with reference to FIG.

As described above, by controlling the image display area 311, the central part of the display screen 21 has the highest brightness and the upper and lower parts of the screen are the darkest. Therefore, a Gaussian distribution or the like can be formed in the vertical direction of the display screen 21.
Of course, a Gaussian distribution or the like may be formed in the horizontal direction of the screen by controlling in the pixel column direction. It can also be realized by arithmetic processing of video signals.

Note that in FIG. 218, the image display area 311 is displayed.
Although it is described that the scanning speed of 1 is changed at the screen position to form a luminance distribution such as a Gaussian distribution on the display screen, this technical idea is not limited to the EL display device. For example, it is obvious that an LED display device can also be applied. Further, the invention is not limited to the self-luminous display panel (display device). For example, a liquid crystal display device can also be applied.

In the liquid crystal display device, the backlight is improved and realized. As the backlight, one having a plurality of stripe-shaped light emitting regions arranged along the pixel row direction is used. For example, at least 10 or more stripe-shaped white EL elements are formed along the pixel row direction. It suffices to light the striped light emitting elements in order from the top. That is, when the striped EL elements are turned on, the striped E corresponding to the central portion of the display screen 21 is displayed.
If the lighting time of the L element 15 is lengthened, the light emission state of the backlight can be changed to the state shown in FIG. 218.

Therefore, in the liquid crystal display device, the lighting display state itself cannot be set as shown in FIG. 218, but the image display described in FIG. 218 is realized by setting the lighting region of the backlight in the scanning state. it can.
The above matters are shown in FIGS. 221, 222, 223, and 210.
It goes without saying that it can be applied to such cases.

FIG. 219 shows the drive waveform of the gate signal line 17a. In addition, in order to facilitate the explanation, the MCL
The period of K is 1H (1 horizontal scanning period). However, it is not limited to this. Flexible control can be realized by using a clock faster than 1H.

The portion indicated by'a 'in FIG. 219 is shown in FIG.
It corresponds to the display state of (a). Similarly, the portion indicated by “b” in FIG. 219 corresponds to the display state of FIG. 218 (b), and the portion indicated by “c” of FIG. 219 corresponds to the display state of FIG. 218 (c). The portion indicated by'd 'in FIG. 219 corresponds to the display state of FIG. 218 (d), and the portion indicated by'e' of FIG. 219 corresponds to the display state of FIG. 218 (e).

The pixel configuration will be described by exemplifying the configuration of FIG. Therefore, when the ON voltage Vgl is applied to the gate signal line 17a, the corresponding pixel row is selected. However, the embodiment of the present invention is not limited to the pixel configuration shown in FIG. 6, and the current mirror configuration shown in FIG.
6, can be applied to the pixel configuration of the voltage program such as FIG.

As shown in FIG. 219, 'a',
In the portion of "e", the pixel row is shifted by the clock of 1H width. Pixel rows are shifted by the clock of 2H width in the parts of "b" and "d". Further, in the portion of'c ', the pixel row is shifted by the clock of 3H width. Therefore, the'c 'part is three times slower than the'a' part, and the pixel row shift operation is slow. That is, the'c 'part becomes three times brighter than the'a' part. Therefore, the central part of the display screen becomes brightest and the upper and lower parts can be darkest.

In FIG. 219, the data transfer of the shift register 22 is set to 3 clocks in the central portion of the display screen. Further, in the upper and lower parts of the display screen, the data transfer of the shift register 22 is one clock. In addition, the data transfer of the shift register 22 is set to 2 clocks in the upper and lower parts and the central part of the display screen. However, as shown in FIG. 219, when the clocks are switched in three stages, the boundaries of the switching are displayed clearly with a difference in brightness. Therefore, it is preferable to reduce the difference between the data transfer clocks and to change the number of changing clocks so that the boundary cannot be seen. That is, FIG. 219 is a diagram for explanation.

For example, in the central part of the display screen, the data transfer of the shift register 22 is 5 clocks, in the upper and lower parts of the display screen, the data transfer of the shift register 22 is 3 clocks, and in the upper and lower parts and the central part of the display screen. The data transfer of the shift register 22 is 4 clocks.

Also, the display screen is divided into nine or more areas,
From the top of the display screen, the first area, the second area, the third area, ...
If the ninth area is the fifth area, the data transfer of the shift register 22 is 15 clocks in the central area, and the first area and the ninth area are one data transfer of the shift register 22.
1 clock. The data transfer of the shift register 22 in the second area and the eighth area is 12 clocks. Data transfer of the shift register 22 to the third area and the seventh area is 1
3 clocks. The data transfer of the shift register 22 in the fourth area and the sixth area is 14 clocks. As described above, if the display screen is divided and the on / off control is optimally performed for each, the boundary of brightness is not noticeable.

The method shown in FIG. 220 is also effective for making the boundary of the brightness of the display screen invisible. FIG. 22
0, the gate signal line 17 in the central area of the display screen 21
The signal waveform of a is shown in figure.

As can be seen from FIG. 220, the shift start timing of 3 clocks with respect to the display position is changed in each field (frame) (F). In FIG. 220, the start position is shifted by one clock from 1F to 4F for ease of explanation. In reality, 1 for each F
Rather than shifting by clock, processing is performed such that one F shifts by one clock, but another F does not shift. Further, the number of times of shifting the three clocks is changed for each F.

For example, in the 1st floor, 3 in the center of the display screen is displayed.
Assume that the start position of the clock starts from the pixel row (90) (90th pixel row), and the range in which the shift register is transferred in 3 clocks is 20 pixel rows. On the 2nd floor, the start position of 3 clocks at the center of the display screen is the pixel row (9
Starting from 2), the range in which the shift register is transferred in 3 clocks is 16 pixel rows. Further, in the 3rd floor, the start position of 3 clocks in the central portion of the display screen starts from the pixel row (94), and the range to which the shift register is transferred in 3 clocks is 12 pixel rows. further,
On the 4th floor, the start position of 3 clocks in the center of the display screen starts from the pixel row (96), and the range to which the shift register is transferred at 3 clocks is 8 pixel rows. By performing the processing as described above, it is possible to make the boundary between the display brightness at the upper part of the display screen and the display brightness at the center part inconspicuous at the brightest part.

Note that the shift start position is processed in a loop. For example, in FIG. 220, 1F → 2F → 3F → 4F
→ 1F → 2F ... Further, in FIG. 220, the pixel row is shifted in the central portion of the display screen in 3 clock cycles, but the present invention is not limited to this. As described in FIG. 219, the number of clocks is changed so that the luminance distribution changes smoothly. Needless to say, the display area is adjusted.

It is needless to say that by combining FIG. 219 and FIG. 220, the brightness distribution processing of the screen display is inconspicuous and good display can be realized.

The driving method described with reference to FIGS. 219 and 220 is to intentionally form the luminance distribution on the display screen 21, but this technical concept can be applied to other image displays.

FIG. 221 shows the display screen 21 in which two luminance portions are formed (displayed). In FIG. 221, the image display area 311a is displayed brighter than the image display area 311b. In FIG. 221 (a), the image display area 311a of the memo 1 is replaced with another image display area 31.
Make it brighter than 1b. It is not possible to display the image display area 311a brighter than the image display area 311b.
It can be easily configured by the method described in the above. Further, since it is sufficient to control the number of times the display area of each unit is selected, it can be easily realized by another method.

In FIG. 221, the area selected by the user is displayed brightly (or darkly) to improve the usability of the display device. Of course, it is also preferable to change the color of the selected image display area 311. It is preferable to apply the display method of FIG. 221 to a menu selection screen or the like. This is because the screen display can be switched by the user's operation and the operability is improved.
Further, the screen display state of FIG. 221 may be automatically set by the control of a microcomputer or the like. Also, since the outside light is strong outdoors and the displayed image cannot be seen, it is necessary to strongly light only the particularly necessary portion (the image display area 31
1a) Control may be performed. For example, when the brightness of external light is detected and the detected external light intensity is equal to or higher than a certain value, the user presses the power switch to display the display screen 21.

Further, as shown in FIG. 222 (a),
The image display area 311a that strongly lights may be provided at a plurality of positions on the display screen 21 or may be blinked. Blinking means turning on / off the image display region 311a in 0.5 second cycles or alternately displaying low luminance and high luminance in FIG. 222 (a).

Further, as shown in FIG. 222 (b),
High brightness image display area 311a, low brightness image display area 31
Image display may be performed by combining 1b and the non-display area 312.

FIG. 223 shows a scroll effect of the display screen 21. In FIG. 190 (a), the high-brightness image display area 311a extends to the center of the display screen 21, and FIG. 190 (b) extends to the vicinity of the lower end of the display screen 21.
The high-luminance image display area 311a is used.

Needless to say, it is possible to display the entire display screen 21 at a low brightness at the same time. In the present invention, the brightness of the display screen 21 is adjusted (controlled) by controlling the lighting control line 1791 or the gate signal line 17b to turn on / off the current flowing through the EL element 15. Therefore, since the image data output from the source driver 14 does not change, the contrast of the display image and the gamma curve are maintained at constant values regardless of the brightness of the display image. Therefore, even if the entire display screen 21 is displayed at low brightness at the same time, the gradation characteristic is maintained as it is (for example,
When displaying 64 gradations, the brightness of the display screen is 1 /
Even if it becomes 2, 64 gradations are maintained).

As shown in FIG. 223, first, the entire display screen 21 is set as a low-brightness image display area 311b (set as a low-brightness display), and the display screen 21 is displayed in order to exert the effect of rewriting the display screen. From the top to the bottom, a high-luminance image display area 311a is formed (high-luminance display is performed). Therefore, one display screen 21 is rewritten by performing high-luminance display in the arrow direction of FIG. 223. Then, if the high-brightness display is continued for a certain period of time, the display screen 21 is displayed from the viewpoint of low power consumption.
The whole is displayed in low brightness.

[1002] Note that the organic EL display panel requires large power for white raster display. If the power supply circuit for this white raster display is provided, the power supply circuit becomes very large. On the other hand, the normal character display consumes only 1/5 to 1/3 the power of the white raster display. Therefore, it is not preferable from the economical or system size point of view to retain the output current of the power supply so that white raster display can be supported.

[1003] To solve this problem, the present invention is configured to reduce the brightness of an image when displaying an image (for example, white raster display) that consumes a certain power or more. is doing. For example, 1 for white raster
When the current of 00 mA flows, the image data is processed so that the current becomes 50 mA, which is 1/2. That is, the total sum of the data of the input image is obtained, and when the total sum exceeds a certain value, the arithmetic processing is performed on the image data to reduce the value of the image data so that the power can be displayed by the power supply.

[1004] Of course, the present invention is not limited to reducing the value of the image data, and the non-lighting control described in FIGS. 187, 218, 222 and the like is performed to reduce the brightness of the entire display screen 21. be able to. It goes without saying that it is also possible to reduce the brightness of only the image display unit and control the icon parts such as the antenna display and the clock display so as to maintain the conventional brightness (the brightness as it is).

[1005] Note that, in the above embodiment, the image display area 31
It has been described that the image display is performed or the different brightness display areas are formed (displayed) by scanning the 1 or non-display area 312 in the vertical direction of the display screen. However, the present invention is not limited to this. For example, in FIG.
In 1 or the like, the brightness distribution can be formed by controlling the number of times each part of the display screen 21 is selected. That is, FIG.
1, when the frame rate for displaying the display screen 21 is 60 Hz, the image display area 311b is selected 25 times,
If the image display area 311a is controlled so as to be selected 50 times, the image display area 311a becomes 2 times larger than the image display area 311b.
It can be displayed with double the brightness. Similarly, in FIG. 223 (b), the frame rate for displaying the display screen 21 is 60 Hz.
At this time, if the image display area 311b is selected 25 times, the image display area 311a is selected 50 times, and the non-display area 312 is not selected at all, the image display area 311a is twice as large as the image display area 311b. Brightness can be displayed 312
The non-display area of can be displayed in black.

[1006] Needless to say, the matters described above can be applied to the block driving described in FIG. 205 or the like or the reverse bias voltage driving described in FIG. 206. Further, in block driving, it is preferable that the number of pixel rows forming each block is the number representing one character string. For example, if one character is composed of 16 × 16 dots, 16 pixel rows are set as one block. Further, if one character is composed of 24 × 24 dots, 24 pixel rows are regarded as one block. In this way, by matching the number of dots in the vertical direction forming a character with the number of blocks, the image display area 311 and the non-display area 312 can be controlled for each line in which the character is displayed.

(Twelfth Embodiment) As in the display method of FIG. 63, a display method for switching between odd-numbered pixel rows and even-numbered pixel rows (or every plurality of pixel rows) for each predetermined field (frame) is a stereoscopic image display device or Can be applied to the method. Hereinafter, the stereoscopic display device of the present invention will be described with reference to FIG.
24 and FIG. 225 will be described.

First, the display method of the present invention basically forms the image display area 311 and the non-display area 312 in units of pixel rows (direction of pixel rows). Therefore, in the case of displaying as shown in FIG. 63, it is necessary to convert the vertical and horizontal directions, but this conversion is easy. This is because the rows and columns of the image data stored in the memory may be exchanged. If the vertical and horizontal directions are converted, the display state shown in FIG. 224 (a1) is obtained. That is, the scanning direction of the display panel is the arrow direction indicated by A, but the image is on the screen as shown in FIG. 224 (a1).
The bottom of the page is the bottom of the screen. Therefore, the user of the display panel looks as if scanning from the top of the screen to the bottom.

[1009] The display screen 21 of the display panel displays the right-eye image in the odd pixel columns (rows) from the left and the left-eye image in the even pixel columns (rows). The image display is synchronized with the observation glasses 852 that are synchronized with the display panel. The observation glasses 852 include two liquid crystal panels that function as shutters 851.

[1010] In the first field (first frame), as shown in FIG.
24 (a1), the odd-numbered pixel columns from the left (actually odd-numbered pixel rows) become the image display region 311, and the even-numbered pixel columns from the left (actually even-numbered pixel rows) become the non-display region. It becomes 312. In synchronization with the display state of FIG. 224 (a1), the left-eye shutter 851L of the observation glasses 852 is closed and the right-eye shutter 851R of the observation glasses 852 is opened. Therefore, the observer has only the right eye,
You will see the image in FIG. 224 (a1).

In the second field (second frame) next to the first field (first frame), as shown in FIG. 224 (a2), even-numbered pixel columns (actually even-numbered pixel rows) from the left are images. The display area 311 is formed, and the odd-numbered pixel columns (actually, odd-numbered pixel rows) from the left are the non-display area 3
Twelve. In synchronization with the display state of FIG. 224 (a2),
The shutter 851R for the right eye of the observation glasses 852 is closed,
The shutter 851L for the left eye of the observation glasses 852 opens.
Therefore, the observer sees the image of FIG. 224 (a2) only with the left eye.

[1012] By alternately repeating the above operation,
Stereoscopic image display can be realized by allowing the viewer to see alternately the glasses-type shutter 851 used by the viewer and the image display state in synchronism with each other.

[1013] In order to realize a stereoscopic image display without using the shutter 851, a prism 861 may be arranged on the light emitting side of the display panel as shown in FIG. 225. The portion A of the prism 861 is arranged so as to correspond to the image display area 311 at a certain display timing, and the prism 861
The portion B of the non-display area 31 at the display timing described above.
Arrange so as to correspond to 2. In this way, the prism 8
By arranging 61, the image of the odd-numbered pixel rows can be made incident on the right eye of the observer, and the image of the even-numbered pixel rows can be made incident on the left eye of the observer. In addition,
An optical coupling material 862 such as ethylene glycol is arranged between the prism 861 and the display panel to perform optical coupling.

[1014] In FIG. 224, the switching means 85
The number 2 is spectacles, but is not limited to this. Any one may be used as long as it can control the light incident on the right eye and the light incident on the left eye of the observer. For example, a goggle type is exemplified. Also, the switching means 85
An example is one in which 2 and a display panel are integrated (head mounted display). Further, the shutter 851 is not limited to the liquid crystal display panel, and may be a mechanical one such as a camera shutter or a rotary filter. In addition, one that incorporates a polygon mirror, PLZT
Examples of the shutter include a shutter that uses, and a shutter that applies electroluminescence.

As described above, stereoscopic display can be realized by using the display method of FIG. 63 for the display image of one display panel. It should be noted that the apparatus or method shown in FIGS. 224 and 225 can be applied to every plural pixel rows (columns) or odd pixel rows (columns).
Is to display different images for each even-numbered pixel row (column), and its application is not limited to stereoscopic display. For example, it may be used for the purpose of simply displaying two images in an overlapping manner. Needless to say, it is particularly effective to carry out the driving method of the present invention using the EL display device of the present invention.

[1016] The element that drives each pixel is the TFT 11
However, it is not limited to this. For example, the pixel 16 can be configured by combining a thin film diode (TFD), and the current flowing through the EL element 15 can be intermittently operated by operating the voltage level at one terminal of the diode. In this configuration, the cathode electrode is processed (formed) in a horizontal stripe shape as needed. The same applies to switching elements such as varistors and thyristors.

[1017] For example, when the driving TFT in the conversion TFT 11a in Fig. 6 is taken as an example, it may be an N-channel or P-channel bipolar transistor as shown in Fig. 226 (a). Also, as shown in FIG. 226 (b), N-channel or P-channel MOS
It may be a transistor. Further, as shown in FIG. 226 (c), it may be a phototransistor or photodiode, and as shown in FIG. 226 (d), it may be a thyristor element or the like. This means that it can be applied to a switching element that constitutes another pixel.

[1018] Further, the TFT element can be used in either P channel or N channel. Also, EL
The position of the element 15 is not limited to the position shown in FIG. 6 or FIG. For example, FIG. 185 (a) shows the connection state between the conversion TFT 11a and the EL element 15 of FIG. 6 extracted. As this modification, the configuration of FIG. 185 (b) is also illustrated. Further, the configuration of FIGS. 185 (c) and (d) in which the driving TFT is an N channel is also illustrated. These matters apply not only to the conversion TFT 11a but also to switching elements (for example, TFTs 11b, 11c, 11d in FIG. 6) that form other pixels. In addition, the gate driver 12 and the source driver 14
It is similarly applied to the elements constituting the.

[1019] Further, it is desirable that the switching elements such as TFTs are formed of low temperature polycrystalline Si-TFTs.
It may be an amorphous silicon TFT. In particular, when the current flowing through the EL element 15 is 1 μA or less, it is sufficient in terms of characteristics to form the amorphous silicon technique. Also, the gate driver circuit, the source driver circuit, and the like may be formed by elements using amorphous silicon technology.

Also, the configuration of the gate driver 12 shown in FIGS. 21, 66, 67, 69, etc. is not limited to this (in FIG. 21, etc., the shift operation is performed by sequentially synchronizing the ST signal with the clock ( (Serial processing)), for example, a parallel input for determining the on / off state of each gate signal line at a time (the on / off logic of all gate signal lines corresponds to the number of controllers or gate signal lines 17). , Configuration that is output and determined at once).

[1021] FIG. 227 is a block diagram of an organic EL module. The control IC 101 is mounted on the printed circuit board 103.
And a power supply IC 102 are mounted. Printed circuit board 10
3 and the array substrate 49 are electrically connected by the flexible substrate 104. Power supply voltage, current, control signals, and video data are transferred to the array substrate 4 via the flexible substrate 104.
9 source driver 14 and gate driver 12.

[1022] In this case, the problem is the gate driver 1
2 control signal. It is necessary to apply a control signal having an amplitude of at least 5 V or more to the gate driver 12. However, since the power supply voltage of the control IC 101 is 2.5 V or 3.3 V, the control signal cannot be directly applied from the control IC 101 to the gate driver 12.

To address this problem, the present invention applies a control signal for the gate driver 12 from the power supply IC 102 driven at a high voltage. The power supply IC 102 is the gate driver 12
Since the operating voltage is also generated, it is naturally possible to generate a control signal having an optimum amplitude in the gate driver 12.

In FIG. 228, the control signal of the gate driver 12 is generated by the control IC 101, level-shifted once by the source driver 14, and then applied to the gate driver 12. Since the drive voltage of the source driver 14 is 5 to 8 V, the gate driver 12 outputs the control signal of 3.3 V amplitude output from the control IC 101.
Can be converted to a 5V amplitude that can be received.

[1025] FIG. 229 and FIG. 164 are explanatory views of the display module device of the present invention. 229 shows the source driver 1
4 has a built-in display memory 151. The built-in display memory has a capacity of 8-color display (1 bit for each color), 256-color display (3 bits for RG, 2 bits for B), and 4096 colors (4 bits for RGB). These 8 colors, 2
When displaying a 56-color image or a 4096-color image and a still image, the driver controller arranged in the source driver 14 reads the image data of the built-in display memory 151, so that ultra-low power consumption can be realized. Of course, the built-in display memory 151 may be a multi-color display memory of 260,000 colors or more. Further, the image data of the built-in display memory 151 may be used also for a moving image.

[1026] As the image data of the built-in display memory 151, the data after the error diffusion processing or the dither processing may be stored. By performing error diffusion processing, dither processing, or the like, the 260,000-color display data can be converted into 4096 colors, and the capacity of the built-in display memory 151 can be reduced. The error diffusion processing can be performed by the error diffusion controller 141. Further, the error diffusion process may be further performed after the dither process is performed.
The above items also apply to the inverse error diffusion processing.

[1027] In FIG. 229, etc., 14 is described as a source driver, but not only a simple driver,
Inputs from the power supply IC 102, the buffer circuit 154 (including a circuit such as a shift register), the data conversion circuit, the latch circuit, the command decoder, the shift circuit, the address conversion circuit, and the built-in display memory 151 are processed to apply a voltage or a voltage to the source signal line. Various functions or circuits for outputting current are configured. These matters also apply to other embodiments of the present invention.

It is needless to say that the configuration described with reference to FIG. 229 and the like can be applied to the three-side free configuration described in FIGS. 23 to 27, FIG. 29, FIG. 32, and FIG. Yes.

[1029] Fig. 230 shows a configuration example in which the protective cover for protecting the EL element 15 from humidity is the sealing lid 41, and may also be used as a protective cover for a mobile phone or the like. The protective cover is a transparent plate arranged to protect the front surface of the display panel. Alternatively, in a reflective liquid crystal display panel, the front light serves as a protective cover. A circular polarization plate 74 is attached to the sealing lid 41. The circularly polarizing plate 74 may be formed by applying a resin to the thin film or the sealing lid 41 and stretching the resin.

[1030] Then, the casing 193 such as a mobile phone is provided with an EL.
The element array substrate 49 is attached (EL display panel is attached). The gate driver 12 (or the source driver 14) is arranged in the sealing lid 41. The gate driver 12 (or the source driver 14) is also protected by the sealing lid 41. By forming (configuring) as described above, the protective cover can be omitted, and the overall thickness of the display panel module can be reduced.

[1031] As described in FIG. 2, the organic EL
The panel needs to form a reflective film 46 as a cathode electrode (or an anode electrode). This electrode is made of aluminum or the like. Therefore, the reflectance is as good as 85% or more.

[1032] FIG. 231 shows a mobile phone configured such that the reflection film 46 can be used as a mirror. In normal use, it is used as shown in FIG. 232 (or see FIG. 233). When the display panel 2046 is used as a mirror, the display panel 2046 is turned upside down around a right or left fulcrum (not shown), and the rear surface mirror 2045 is used.

However, in the above embodiments, the reflective film formed on the back surface of the EL display panel is used as a mirror. Therefore, the target to be used as a mirror is not limited to a mobile phone, but a TV, a monitor,
It may be a PDA. In addition, a mirror is formed on the back surface of the display panel. Therefore, the structure is not limited to the cathode, and a structure in which a mirror is separately formed on the back surface of the display panel may be used. For example, in a reflective liquid crystal display panel, since the back surface is not used, aluminum or silver may be vapor-deposited on this back surface to form a mirror. in this case,
In order to prevent corrosion of aluminum or silver, it is preferable to form an inorganic thin film such as SiO _{2 on} the surface.
It may also be protected by UV resin or the like.

[1034] Note that in FIG. 231, reference numeral 2041 denotes a speaker that allows the received voice to be heard.
Reference numeral 44 is a microphone for inputting the voice of the user.
Further, as described in FIG. 55, it is preferable to arrange the display mode changeover switch 465. Further, it is preferable to form (dispose) a changeover switch that realizes the function of changing the screen brightness described in FIG. 54 and the like.

[1035] The frame rate is related to the power consumption of the panel module. That is, if the frame rate is increased, the power consumption increases almost in proportion. It is necessary to reduce the power consumption of mobile phones and the like from the standpoint of increasing the standby time. On the other hand, in order to increase the display colors (increase the number of gradations), the drive frequency of the source driver 14 and the like must be increased. However, it is difficult to increase the power consumption due to the power consumption problem.

[1036] Generally, in an information display device such as a mobile phone, low power consumption is prioritized over the number of display colors. The power consumption increases because the operating frequency of the circuit that increases the number of display colors increases or the voltage (current) waveform applied to the EL element changes more often. Therefore, the number of display colors cannot be increased so much. To solve this problem, the present invention displays the image by performing error diffusion processing or dither processing on the image data.

Although not shown in the mobile phone of the present invention described with reference to FIG. 232, a CCD camera is provided on the back side of the housing. The image and data taken by the CCD camera can be immediately displayed on the display screen 21 of the display panel. The image data of the CCD camera can be switched between 24-bit (16.7 million colors), 18-bit (260,000 colors), 16-bit (650,000 colors), 12-bit (4096 colors) and 8-bit (256 colors) by key input. be able to.

[1038] When the display data is 12 bits or more, the error diffusion processing is performed to display. That is, when the image data from the CCD camera exceeds the capacity of the built-in display memory 151, error diffusion processing or the like is performed, and the image processing is performed so that the number of display colors becomes equal to or less than the capacity of the built-in display memory 151.

[1039] Now, the source driver 14 has a built-in display memory 151 for one screen with 4096 colors (4 bits for each RGB).
Will be described as having. When the image data sent from outside the module has 4096 colors, it is directly stored in the built-in display memory 151 of the source driver 14, the image data is read from the built-in display memory 151, and the image is displayed on the display screen 21.

[1040] Image data has 260,000 colors (G: 6 bits,
R and B: 5 bits each, 16 bits in total)
As shown in FIG. 9 and FIG. 164, the data is temporarily stored in the arithmetic memory 152 of the error diffusion controller 141, and at the same time, the arithmetic circuit 153 performs error diffusion or dither processing. The 16-bit image data is converted into 12 bits, which is the number of bits of the built-in display memory 151, by the error diffusion processing or the like, and transferred to the source driver 14. The source driver 14 outputs RGB 4-bit (4096 colors) image data and displays the image on the display screen 21.

Also, in the configuration of FIG. 164 and the like, even if the vertical diffusion signal VD is used (the processing method is changed by the vertical synchronization signal VD), the error diffusion processing or the dither processing method is changed for each field or frame. Good.
For example, in the dither processing, the Bayer type is used in the first frame, and the halftone type is used in the next second frame. As described above, by changing and switching the dither processing for each frame, it is possible to achieve the effect that the dot unevenness due to the error diffusion processing or the like becomes inconspicuous.

[1042] Further, the processing coefficient such as the error diffusion processing may be changed between the first frame and the second frame. In addition, various processes may be combined such that the error diffusion process is performed in the first frame, the dither process is performed in the second frame, and the error diffusion process is performed in the third frame. In addition, a processing method that includes a random number generation circuit and performs processing for each frame with a random number value may be selected.

[1043] If the information such as the frame rate is described in the transmitted format, the frame rate and the like can be automatically changed by decoding or detecting the described data. It is preferable to describe whether the image to be transmitted is a moving image or a still image, especially in the case of a moving image, the number of frames per second of the moving image. Further, it is preferable to describe the model number of the mobile phone in the transmission packet. It should be noted that although it is described as a transmission packet in the present specification, it need not be a packet, and may be any data as long as the information (display color number, frame rate, etc.) described in FIG. Either is fine.

[1044] FIG. 235 shows a transmission format sent to the mobile phone or the like of the present invention. Transmission includes both received data and transmitted data. That is, the mobile phone may transmit voice from the handset or an image captured by the CCD camera attached to the mobile phone to another mobile phone or the like. Therefore, the matters related to the transmission format described in FIG. 234 and the like are applied to both transmission and reception.

[1045] In the mobile phone or the like of the present invention, data is digitized and transmitted in a packet format. FIG. 235
In the frame, the flag part (F), the address part (A), the control part (C), the information part (I), and the frame check sequence (FC
S). As shown in FIG. 236, the control unit (C) has three formats: information transfer (I frame), monitoring (S frame), and unnumbered system (U frame).

[1046] First, the information transfer format is a format of a control field used when transferring information (data). Except for a part of the non-numbering format, the information transfer format is the only format having a data field. . A frame in this format is called an information frame (I frame).

[1047] The monitoring format is a format used for the data link monitoring control function, that is, for confirming the reception of the information frame and for requesting the retransmission of the information frame. A frame in this format is a monitoring frame (S frame)
Say.

[1048] Next, the unnumbered format is a format of a control field used to perform other data ring control functions, and a frame in this format is called an unnumbered frame (U frame).

[1049] The terminal and the network transmit and receive the information frame with the transmission sequence number N (S) and the reception sequence number N.
Manage with (R). Both N (S) and N (R) are made up of 3 bits, and 8 from 0 to 7 are used as a circulation number.
The next is a modulus configuration that becomes 0. Therefore, the modulus in this case is 8, and the number of frames that can be continuously transmitted without receiving the response frame is 7.

[1050] In the data area, 8-bit data indicating the color number data and 8-bit data indicating the frame rate are described. Examples of these are shown in FIGS. 234 (a) and 234 (b). Further, it is preferable to describe the distinction between a still image and a moving image in the number of display colors. In addition, it is desirable to describe the model name of the mobile phone, the content of the image data to be transmitted / received (natural image of a person, a menu screen), etc. in the packet of FIG. 235. The model that receives the data decodes the data, and when it recognizes it as its own (corresponding model number) data, it automatically changes the display color, frame rate, etc. according to the contents described. Further, the described contents may be displayed on the display screen 21 of the display device. The user may look at the description content (display color, recommended frame rate) on the display screen 21 and operate a key or the like to manually change to an optimum display state.

[1051] As an example, in FIG. 234 (b), the numerical value 3 is described as an example that the frame rate is 80 Hz, but the present invention is not limited to this, and 40 to 60H
It may indicate a certain range such as z. Also, the model of the mobile phone may be described in the data area. This is because the performance etc. varies depending on the model and it is necessary to change the frame rate. It is also preferable to describe information such as whether the image is a cartoon or an advertisement (CM). Further, information such as the viewing fee and the packet length may be described in the packet. This is because the user can check the viewing fee and determine whether or not to receive the information. It is also preferable to describe data indicating whether the image data has been subjected to error diffusion processing.

[1052] Also, an image processing method (type of error diffusion processing, dither processing, etc., type of weighting function and its data,
Information such as the gamma coefficient) and model number may be described in the transmitted format. In addition, if information such as image data captured by CCD, JPEG data, its resolution, MPEG data, or BITMAP data is described, the data is decoded or detected based on this information. It will be possible to change the automatically received mobile phone etc. to the optimum state.

[1053] Of course, it is preferable to describe whether the image to be transmitted is a moving image or a still image, particularly in the case of a moving image, the number of frames per second of the moving image. It is also preferable to describe information such as the number of playback frames / second recommended by the receiving terminal.

[1054] The above items are the same when the transmission packet is a transmission. Further, although it is described as a transmission packet in this specification, it need not be a packet. That is,
Any data may be used as long as the information described with reference to FIG.

[1055] It is preferable to add a function to the error diffusion processing controller 141, which performs the inverse error diffusion processing on the data that has been subjected to the error processing and is sent back to the original data, and then performs the error diffusion processing again. . Whether or not the error diffusion process is performed is included in the packet data of FIG. 235. In addition, the data necessary for the inverse error diffusion process such as the error diffusion (including dither etc.) processing method and format are also listed.

The inverse error diffusion process is executed because the gamma curve can be corrected in the process of the error diffusion process. In some cases, the gamma curve of the EL display device or the like that receives the data does not match the sent gamma curve, or the sent data may be image data that has already undergone processing such as error diffusion. In order to deal with this situation, the inverse error diffusion process is performed and converted into the original data so that the influence of the gamma curve correction does not occur. Then, the received EL display device or the like performs error diffusion processing to obtain an optimum gamma curve for the reception display panel, and the error diffusion processing or the like is performed so that the optimum error diffusion processing is performed.

[1057] If it is desired to switch the frame rate according to the display color, a user button may be arranged on a device such as a mobile phone and the display color or the like may be switched using the button or the like.

[1058] FIG. 232 is a plan view of a mobile phone as an example of the information terminal device. The antenna 191 in the housing 193,
A numeric keypad 192 and the like are attached. Reference numeral 194 is a display color switching key or a power on / off and frame rate switching key.

[1059] FIG. 23 shows an internal circuit block of a mobile phone or the like.
7 shows. The circuit is mainly a block of the up converter 205 and the down converter 204, and the duplexer 201.
Block, the LO buffer 203, and other blocks.

[1060] When the key 194 is pressed once, the display color becomes the 8-color mode, when the same key 194 is subsequently pressed, the display color becomes the 256-color mode, and when the same key 194 is further pressed, the display color becomes the 4096-color mode. You may make a sequence. The key is a toggle switch whose display color mode changes each time it is pressed. A change key for the display color may be separately provided. In this case, there are three (or more) keys 194.

[1061] The key 194 may be a push switch, a mechanical switch such as a slide switch, or may be switched by voice recognition. For example, voice inputting 4096 colors into the handset,
For example, the color displayed on the display screen 21 of the display panel is changed by voice input to the receiver, such as "high quality display", "256 color mode" or "low display color mode". This can be easily realized by adopting the existing voice recognition technology.

[1062] The display color may be switched by an electrically switching switch, or a touch panel for selecting by touching a menu displayed on the display screen 21 of the display panel. Alternatively, the switch may be switched depending on the number of times the switch is pressed, or may be switched according to rotation or direction like a click ball.

[1063] Although 194 is the display color switching key, it may be a key for switching the frame rate or the like. Further, it may be a key for switching between a moving image and a still image. Also, a plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be gradually (continuously) changed when the button is held down. In this case, it can be realized by changing the resistance R of the capacitor C and the resistance R constituting the oscillator to a variable resistance or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, it may be realized by forming a plurality of capacitors on a semiconductor chip, selecting one or more capacitors, and connecting them in parallel in a circuit.

[1064] Note that the technical idea of switching the frame rate according to the display color is not limited to the mobile phone, and is widely applied to devices having a display screen such as a palmtop computer, a laptop computer, a desktop computer, and a mobile watch. can do. Further, the present invention is not limited to the liquid crystal display device, but can be applied to a liquid crystal display panel, an organic EL display panel, a TFT panel, a PLZT panel, and a CRT.

[1065] In FIG. 231, 2043 is a function switch (FSW). The FSW 2043 is arranged at a position where it can be held by the little finger and the ring finger. Also,
The FSWs 2043a and 2043b are arranged on the left and right. This is because it is configured to be held by the little finger and ring finger of the right hand, and held by the little finger and ring finger of the left hand. The FSW may be arranged on the back surface of the housing 193.

[1067] Whether to enable the FSW 2043 for the right hand,
Whether to enable the FSW 2043 on the left hand can be switched by the user by command setting. That is,
When the user sets to enable the right side on the menu screen, the FSW 2043 for the right hand is enabled and the FSW for the left hand is enabled.
SW2043 becomes invalid. On the other hand, if the user sets the left screen to be enabled on the menu screen, the left hand FS
W2043 becomes valid and FSW2043 on the right becomes invalid.

As shown in FIG. 238 (a), the FSW
When 2043 is not pressed, the numeric keypad 192 becomes a numeral input key. As shown in FIG. 238 (b), the FSW204
When 3a is pressed, the hiragana input mode is entered. At this time, the uppermost characters of "a, ka, sa, ta, na ..." are designated. In this state, first select "A". Next, FS
When W2043b is also pressed, five characters including the previously pressed character string are entered. When a specific key is pressed in this state, characters are input. Therefore, FSW
By combining 2043 and the numeric keypad 192, Japanese input can be easily realized. Also, FIG.
As illustrated in (d), when only the FSW 2043b is pressed, the English character input mode is set.

[1068] As described above, in addition to the numeric keypad 192, the F key
By arranging SW2043, a wide variety of characters can be easily input.

[Embodiment 13] Furthermore, the EL of the present invention
An embodiment employing a display panel or an EL display device or a driving method will be described with reference to the drawings.

[1070] FIG. 239 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for ease of explanation. Also, there are some areas that are partially enlarged or reduced, and some areas are omitted. For example, the eyepiece cover is omitted in FIG. 239. The above also applies to other drawings.

[1071] The back surface of the body 451 is dark or black. This is for preventing the stray light emitted from the display panel 82 from being diffusely reflected on the inner surface of the body 451 and lowering the display contrast. Further, a λ / 4 plate 50 (phase plate or the like), a polarizing plate 54 and the like are arranged on the light emitting side of the display panel. This is also explained in FIG.

[1072] A magnifying lens 453 is attached to the eyepiece ring 452. The observer changes the insertion position of the eyepiece ring 452 in the body 451 and adjusts the eyepiece ring 452 so that the image displayed on the display panel is in focus. Further, by disposing a positive lens 454 on the light emission side of the display panel as necessary, the chief ray incident on the magnifying lens 453 can be converged. Therefore, the lens diameter of the magnifying lens 453 can be reduced, and the viewfinder can be downsized.

[1073] FIG. 240 is a perspective view of a video camera.
The video camera has a taking lens 461 and a video camera body 4
62, and the taking lens 461 and the viewfinder 466 are back-to-back. An eyepiece cover 464 is attached to the viewfinder 466 (see also FIG. 239). An observer (user) observes the image on the display panel through the eyepiece cover 464.

On the other hand, the EL display panel of the present invention is also used as the display screen 21. Display screen 21 is fulcrum 46
The angle can be freely adjusted with 8. When the display screen 21 is not used, it is stored in the storage unit 463.

[1075] In FIG. 240, reference numeral 465 is a display mode changeover switch. Display mode switch 4
When 65 is pressed, the circuit of FIG. 55 operates and the items described with reference to FIG. 55 are carried out.

[1076] The EL display device of this embodiment can be applied not only to a video camera but also to an electronic camera as shown in FIG. The display panel 82 is used as a monitor attached to the digital camera body 472. A display mode changeover switch 465 is attached to the digital camera body 472 in addition to the shutter 471.

[1077] This display mode switch 465
Is preferably attached to a mobile phone or the like. It is also preferable to add the function of switching the display brightness of the display mode changeover switch described above to a mobile phone or the like. Hereinafter, a method of digitally changing the display brightness will be described.

[1078] As described with reference to FIG. 91 and the like, one of the driving methods of the present invention is to pass an N-fold current through the EL element 15 and
There is a method of turning on only for the period of / M. The brightness can be digitally changed by switching only the M value of 1 / M to be turned on. For example, with N = 4, a four times larger current is passed through the EL element 15. Lighting period is 1
By setting / M and switching M = 1, 2, 3, 4, it is possible to switch the brightness from 1 to 4 times. Note that M =
It may be configured so that it can be changed to 1, 1.5, 2, 3, 4, 5, 6, and the like.

[1079] The above switching operation displays the display screen 21 very brightly when the power of the mobile phone is turned on,
It is used in a configuration in which the display brightness is lowered in order to save power after a certain time has elapsed. It can also be used as a function of setting the brightness desired by the user. For example, when outdoors, the surroundings are bright and the screen cannot be seen at all, so the screen is made very bright. But,
If the EL element 15 is continuously displayed with high brightness, the EL element 15 deteriorates rapidly. Therefore, when it is made extremely bright, it is configured to restore the normal brightness in a short time. Furthermore, when displaying with high brightness, the user can press the button to increase the display brightness.

[1080] Therefore, it is preferable to have a configuration in which the user can switch with a button, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. In addition, it is preferable that the display brightness can be set to 50%, 60%, and 80% by the user or the like.

[1081] Further, it is preferable that the display screen is a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness of the central part is bright and the peripheral part is relatively dark. Visually, if the central part is bright, it is perceived as bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part maintains a luminance of 70% as compared with the central part, it is visually comparable. There is almost no problem even if the luminance is further reduced to 50%. In the self-emission type display panel of the present invention, the N-time pulse drive described above (N-time current is passed through the EL element 15 and 1F of 1F).
Gaussian distribution is generated from the top to the bottom of the screen by using the method of turning on only for the period of / M).

[1082] Specifically, the value of M is increased in the upper and lower parts of the screen, and the value of M is decreased in the central part. This can be realized by modulating the operating speed of the shift register of the gate driver 12. The brightness modulation on the left and right of the screen is generated by multiplying the table data and the video data. By the above operation, when the peripheral brightness (angle of view 0.9) is set to 50%, it is possible to reduce the power consumption by about 20% as compared with the case of 100% brightness. Further, when the peripheral brightness (angle of view 0.9) is 70%, it is possible to reduce the power consumption by about 15% as compared with the case of 100% brightness.

[1085] It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when a Gaussian display is made outdoors, the peripheral portion of the screen becomes completely invisible. Therefore, it is preferable to have a configuration in which the user can switch with a button, can be automatically changed in a setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the peripheral brightness can be set to 50%, 60%, 80% by the user or the like.

[1084] Since the liquid crystal display panel generates a fixed Gaussian distribution by the backlight, it cannot be turned on or off. The fact that the Gaussian distribution can be turned on and off is an effect peculiar to self-luminous display devices.

[1085] Also, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of a fluorescent lamp in the room. That is, when the EL element 15 is operating at a frame rate of 60 Hz when the fluorescent lamp is lit with an alternating current of 60 Hz, a slight interference may occur and the screen may seem to blink slowly. is there. To avoid this, change the frame rate. The present invention adds a frame rate changing function. In addition, N times pulse driving (N times the current is passed through the EL element 15 to
In the method of turning on the light only during the period of M), the value of N or M is changeable.

[1086] The above items are not limited to mobile phones, but can be applied to televisions, monitors and the like. In addition, it is preferable to display icons on the display screen so that the user can immediately recognize the display state. The above items also apply to the following items.

[1087] Further, it is preferable to incorporate an "automatic screen adjustment" function for automatically adjusting the clock phase and the screen position (horizontal / vertical) and an "auto gain control function" for automatically adjusting the black level / contrast.
By adjusting the black level contrast to an appropriate value, it is possible to realize optimum gradation display for each of the RGB colors.
Further, it is preferable to have a function of suppressing bleeding or the like that occurs when the VGA mode or the like is reduced or enlarged and displayed. Also, it is preferable to install a "power save mode" in which the backlight automatically turns off when not used for a certain period of time.

[1088] Also, N times pulse driving (N times current is EL
It is also possible to make the value of M considerably large and reduce the display brightness to such an extent that an image can be recognized faintly by using a method of flowing the light into the element 15 and lighting it for 1 / M of 1F. The above matters also apply to the other inventions.

[1089] The above is the case where the display area of the display panel 82 is relatively small, but the display screen 21 is easily bent when the display area is large such as 30 inches or more. As a countermeasure, in the present invention, as shown in FIG. 242, the display panel 82 has an outer frame 481.
Fixing member 4 so that the outer frame 481 can be suspended.
82 is attached. As shown in FIG. 243 using this fixing member 482, the fixing member 482 such as a screw is used to attach to the wall 491 or the like.

[1090] However, as the screen size of the display panel 82 increases, the weight also increases. Therefore, the display panel 8
The leg mounting portion 484 is arranged on the lower side of
3 allows the weight of the display panel 82 to be held.

[1091] As shown in FIG. 242, the leg 483 is movable left and right as shown in A, and the leg 483 is contractable as shown in B. Therefore, the display device can be easily installed even in a narrow place.

[1092] Note that a plastic film-metal plate composite material (hereinafter referred to as a composite material) is used for the legs 483 or the housing (also in the present invention). The composite material is obtained by strongly adhering a metal and a plastic film via a special surface treatment layer (adhesive layer). The metal plate is preferably 0.2 mm or more and 0.8 mm or less, and the plastic film attached to the metal plate through the special surface treatment layer has a thickness of 15 μm.
It is preferable that the thickness is not less than m and not more than 100 μm. The special adhesion method provides a strong adhesion between the plastic and the metal plate. By using this composite material, it is possible to color, dye, and print the plastic layer.
It is possible to eliminate the secondary processing steps (hand-attaching the film, plating coating) on the pressed parts. It is also suitable for deep drawing and DI molding, which has been impossible in the past.

[1093] In the television shown in FIG. 242, the surface of the screen is covered with a protective film (or a protective plate) 493. This is one purpose to prevent the display screen 21 of the display panel 82 from being damaged by being hit by an object. An AIR coat is formed on the surface of the protective film 493, and the surface is embossed to prevent external conditions (external light) from being reflected on the liquid crystal display screen 21.

[1094] By spraying beads or the like between the protective film 493 and the display panel 82, a certain space is arranged. Further, a fine convex portion is formed on the back surface of the protective film 493, and the convex portion holds a space between the display panel 82 and the protective film 493. in this way,
By holding the space, it is possible to prevent the impact from the protective film 493 from being transmitted to the display panel 82.

[1095] Further, the protective film 493 and the display panel 8
It is also effective to dispose or inject an optical binder such as alcohol or ethylene glycol in a liquid or gel acrylic resin or a solid resin such as epoxy between the two. This is because interface reflection can be prevented and the optical coupling agent functions as a buffer material.

Examples of the protective film 493 include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), a PVA film (plate) and the like. In addition, an engineering resin film (ABS etc.) can also be used. It may also be made of an inorganic material such as tempered glass. Instead of disposing the protective film 493, coating the surface of the display panel 82 with an epoxy resin, a phenol resin, or an acrylic resin to a thickness of 0.5 mm or more and 2.0 mm or less has the same effect.
It is also effective to emboss the surface of these resins.

[1097] It is also effective to coat the surface of the protective film 493 or the coating material with fluorine. This is because stains on the surface can be easily wiped off with a detergent or the like. In addition, the protective film may be formed thick to serve also as the front light.

[1098] The screen is not limited to 4: 3,
A wide display may be used. Resolution is 1280x
It is preferably 768 dots or more. The wide type allows full-screen enjoyment of horizontally-oriented titles and programs such as DVD movies and TV broadcasts. The brightness of the display panel 82 is preferably 300 cd / m ² (candela / square meter), and more preferably 500 cd / m ² (candela / square meter). Also,
A changeover switch is installed so that the image can be displayed at a brightness (200 cd / m ² ) suitable for the internet and ordinary PC work.

[1099] As described above, the user can set the optimum screen brightness according to the display content or the usage method. Furthermore, only the window displaying the video is 500
in the cd / m ^2, other portions are also possible setting that 200 cd / m ^2. It can be used flexibly for checking TV programs by displaying TV programs in the corner of the display. The speaker has a tower shape and is designed to spread the sound not only in the front direction but also in the entire space.

[1100] TV program playback and recording functions are also easier to use. For example, recording reservation from i-mode can be easily performed. Conventionally, it was necessary to make a reservation after checking the time and channel on a TV program guide such as a newspaper, but it is possible to make a reservation by checking the electronic program guide in i-mode. This way, you don't have to worry about not knowing the broadcast time. In addition, shortened playback of recorded programs is also possible. While judging the importance of the presence or absence of telops and voices in news programs and the like, you can skip the parts that you have decided to be unnecessary and see the outline of the program in a short time (1 to 10 minutes for a 30-minute program).

[1101] Further, a hard disk having a disk capacity of 40 GB or more is loaded so that television recording can be performed.
In addition to the main body, this consists of an expansion box that combines the power supply and video input / output terminals. In addition to a personal computer and a television, two types of video equipment can be connected to the expansion box used to connect AV equipment such as video. Video input is equipped with S terminal input in addition to D1 terminal for BS digital tuner,
You can select according to the connected device. Further, the terminals for AV are arranged on the front surface for the convenience of connecting a game machine or the like.

[1102] In addition, the display screen is bent forward 30 degrees or more, backward 1
By setting it to 20 degrees or more and rotating 90 degrees / 180 degrees / 270 degrees, it is possible to freely set up according to the operating environment. For example, the browser screen can be displayed in portrait orientation by rotating 90 degrees. Also, 14
By bending back 5 times, the screen can be displayed to the person sitting face-to-face.

[1103] The above protective film 493, casing, configuration,
It goes without saying that matters relating to characteristics and functions are applied to other display devices or information display devices of the present invention.

[1104] In FIG. 72 and the like, one terminal of the capacitor 19 is connected to the Vdd power supply, but the invention is not limited to this. For example, as shown in FIG.
One terminal may be connected to the gate signal line 17a in the preceding stage (the pixel row immediately before). The gate signal line 17a in the previous stage is 1
The potential is changed before being selected before H, and thereafter, the potential is fixed until the next 1F is selected (until the next selection). That is, since the gate signal line 17a1 in the previous stage is fixed to the off potential Vgh, the capacitor 19
Can be used as one of the electrodes. The configuration in which the gate signal line in the preceding stage is used as the electrode of the capacitor in this way is called the preceding stage configuration.

Although the gate signal line 17a is used as an electrode in FIG. 165, the present invention is not limited to this, and another gate signal line may be used. Further, the technical idea of the former stage configuration is a method of using a fixed potential of a pixel which is not selected. Therefore, in some cases, the gate potential of the latter stage can be used (for example, the gate signal line 17b, the reverse bias voltage Vm, etc.). It goes without saying that the above items can be applied to other pixel configurations.

[1106] Similar matters can be applied to the pixel configuration of the voltage program of FIG. As the first stage configuration,
The configuration of FIG. 155 is illustrated, and one potential of the capacitor 19 is set to the potential of the gate signal line 17a1. Also,
The pre-stage configuration of FIG. 87 is shown in FIG. 156. As described above, by adopting the former-stage configuration, it is possible to reduce the number of power supply wirings formed in the pixel, and it is also possible to realize a high aperture ratio.

[1107] As described above, the TFT 11 of FIG.
d, TFT 11e of FIG. 73, TFT 11d of FIG. 74, TFT 11b of FIG. 75, TFT 11d of FIG. 76, TFT 11d of FIG. 77, TFT 11e of FIG. 78, TFT of FIG. 79.
11e, TFT 11d in FIG. 80, TFT 11 in FIG.
d, the TFT 11d of FIG. 83, the TFT 11e of FIG. 85, the TFT 11e of FIG. 86, and the like, by controlling the on / off states, and FIGS. 49, 53, 59, 61, 63 to 65, 68, 70, It goes without saying that the driving method or display method or device described with reference to FIGS. 71 and 224 can be implemented.

[1108] Further, it is preferable that the driving TFT 11b, the taking-in TFT 11c and the like shown in FIG. 6 are formed by N channels. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the condenser 19 is also reduced, it can be applied to a low frame rate of 10 Hz or less.

On the contrary, it is also effective to make the driving TFT 11b and the taking-in TFT 11c of FIG. 6 P-channel to cause punch-through to improve the black display. When the driving TFT 11b in the P channel is turned off, the off voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side, and the conversion TF is used.
The gate terminal voltage of T11a rises, resulting in more black display. Further, since the current value for the first gray scale display can be increased (a constant base current can be flown up to the gray scale 1), shortage of the write current can be reduced by the current programming method.

[1110] In addition, the gate signal line 17a and the conversion TF
A configuration in which a capacitor is positively formed between the gate terminals of T11a to increase the penetration voltage is also effective (FIG. 2).
44). The capacity of this capacitor is capacitor 19
1/50 to 1/10 of the capacity of
It is preferably not less than 1/15. Alternatively, the source-gate (SG) or gate-drain (GD) capacitance of the driving TFT 11b is preferably 1 to 10 times, more preferably 2 to 6 times the SG (or GD) capacitance. The capacitor may be formed or arranged between one terminal of the capacitor 19 (the gate terminal of the conversion TFT 11a) and the source terminal of the switching TFT 11d (see FIG. 245). Also in this case, the capacity and the like are the same as the values described above.

The capacity of the capacitor 19b for generating the punch-through voltage (capacitance is Cb (pF)) is the capacity of the capacitor 19a for charge retention (capacitance is Ca (pF)).
Then, the gate terminal voltage Vw of the TFT 11a at the time of the white peak current (at the time of the white raster of the display maximum brightness in the image display) is made to flow the current in the black display (the current is basically 0. That is,
Gate terminal voltage V when the image display is black)
b is relevant. These relationships are as follows: Ca / (200Cb) ≦ | Vw−Vb | ≦ Ca / (8C
b) Furthermore, Ca / (100Cb) ≦ | Vw−Vb | ≦ Ca / (10
It is preferable that the condition Cb) is satisfied. Note that | Vw-Vb |
Is the absolute value of the difference between the terminal voltage of the driving TFT when displaying white and the terminal voltage when displaying black (that is, the varying voltage width).

[1112] The driving TFT 11b is a P channel,
The P channel should be at least double gate or more, preferably triple gate or more. More preferably,
Use 4 gates or more. Then, the source-gate (SG) or the gate-drain (G) of the driving TFT 11b.
D) It is preferable to form or dispose capacitors in parallel, which are 1 to 10 times the capacitance (capacity when the TFT is on).

The above items are effective not only in the pixel configuration of FIG. 6 but also in other pixel configurations. For example, in FIG.
9, in the pixel configuration of the current mirror of FIG. 20, a capacitor that causes penetration is arranged or formed between the gate signal line 17a or 17b and the gate terminal of the conversion TFT 11a (see FIGS. 246 and 247). Capture T
The N channel of FT11c has more than double gate.
Alternatively, the capturing TFT 11c and the switching TFT 1
1d is the P channel and more than triple gate.
In the configuration of the voltage program of FIG. 86, the capacitor 19c for generating the punch-through voltage is formed or arranged between the gate signal line 17c and the gate terminal of the driving TFT 11a (see FIG. 248). Further, the intake TFT 11c has a triple gate or more.

[1114] Also, the capacitor 1 for generating the punch-through voltage
9c is a drain terminal of the TFT 11c (capacitor 19b
Side) and the gate signal line 17a or 17c. Further, the capacitor 19c for generating the punch-through voltage
May be arranged between the gate terminal of the TFT 11a and the gate signal line 17a.

[1115] Also, the capacitance of the charge holding capacitor (capacitor 19 in FIGS. 6 and 19) is Ca, and the source-gate capacitance of the switching TFT (11b in FIG. 6, 11c or 11d in FIG. 19) is Cc. (If there is a capacitor for punch-through, the value obtained by adding the capacitance of the capacitor), the high voltage signal applied to the gate signal line is Vgh, and the low voltage signal applied to the gate signal line is Vgl, By configuring to meet the following conditions,
Good black display can be realized.

[1131] 0.05V ≦ (Vgh-Vgl) × (Cc
/Ca)≦0.8 V More preferably, the following condition is satisfied.

[1176] 0.1V ≦ (Vgh-Vgl) × (Cc /
Ca) ≦ 0.5 V The above items are also effective for the pixel configurations shown in FIGS. 142 and 87. For example, in the pixel configuration of the voltage program of FIG. 142, the gate terminal of the TFT 11a and the gate signal line 17a
A capacitor 19b for generating punch-through voltage is formed or arranged in between.

The capacitor 19b for generating the punch-through voltage is formed by the source wiring and the gate wiring of the TFT. However, since this is a configuration in which the source width of the TFT 11 is widened and is formed so as to overlap the gate signal line 17, there may be a case where it cannot be clearly separated from the TFT in practical use. Further, a method of apparently forming the capacitor 19b for punch-through voltage by forming the driving TFT 11b and the taking-in TFT 11c (in the case of the configuration of FIG. 6) larger than necessary is also within the scope of the present invention. The driving TFT 11b and the taking-in TFT 11c have a channel width W / channel length L = 6 /
It is often formed with a thickness of 6 μm. By increasing the channel width W of these, the capacitor for punch-through voltage 1
9b can be configured. For example, the ratio of W: L is 2: 1 or more and 20: 1 or less, preferably 3: 1 or more and 10 :.
A configuration in which the number is 1 or less is exemplified.

[1119] Also, the capacitor 19b for punch-through voltage
It is preferable to change the size (capacitance) of R, G, and B modulated by the pixel (see FIG. 249). R,
The driving currents of the G and B EL elements 15 are different,
Since the cutoff voltage of the element 15 is different,
This is because the voltage (current) programmed in the gate terminal of the conversion TFT 11a of the element 15 is also different. For example, when the capacitor 19bR of the R pixel is 0.02 pF, the capacitors 19bG and 19bB of other colors (pixels of G and B) are used.
Is 0.025 pF. Also, the R pixel capacitor 1
When 9bR is 0.02pF, the G pixel capacitor 19bG is 0.03pF and the B pixel capacitor 19b
bB is 0.025 pF. in this way,
By changing the capacitance of the capacitor 19b for each of the R, G, and B pixels, the offset drive current can be adjusted for each RGB. Therefore, the black display level of each RGB can be set to the optimum value.

[1120] As described above, the capacitor 1 for generating the penetration voltage
Although the capacitance of 9b is changed, the penetration voltage in the configuration of FIG.
It is the relative capacitance of a and the capacitor 19b for generating the punch-through voltage. Therefore, the punch-through voltage generating capacitor 19b is not limited to being changed for the R, G, and B pixels. That is, the capacity of the charge holding capacitor 19a may be changed.
For example, when the R pixel capacitor 19aR is 1.0 pF, the G pixel capacitor 19aG is 1.2 pF, and the B pixel capacitor 19aB is 0.9 pF. At this time, the punch-through voltage generating capacitor 19
The capacitance of b is a common value for R, G, and B. Therefore, according to the present invention, the capacitance ratio between the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b is set to R,
At least one of the G and B pixels is different from the others. The capacitances of both the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b may be changed for the R, G, and B pixels.

[1121] Also, the capacitance of the capacitor 19b for punch-through voltage may be changed between the left and right of the display screen 21 (Fig. 2).
50). The pixel 16a is a gate driver 1
It is close to 2. That is, the pixel 16a is arranged on the signal supply side, and the rise of the gate signal is fast (since the slew rate is high. See the gate waveform 2341a), so that the punch-through voltage becomes large. Pixel 1
Since 6b is arranged (formed) at the end of the gate signal line 17, the signal waveform is dull (because the gate signal line 17 has a capacity. See the gate waveform 2341b). Therefore, the rising of the gate signal is slow (the slew rate is slow), and the punch-through voltage becomes small. Therefore, the pixel 16a close to the connection side with the gate driver 12
The capacitor 19b for generating the punch-through voltage is reduced and the capacitor 19b on the end side of the gate signal line 17 is enlarged.
For example, the capacitance of the capacitor is changed by about 10% between the left and right sides of the screen.

As described with reference to FIG. 249, the punch-through voltage that is generated is determined by the capacitance ratio between the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b. Therefore, in FIG. 250, the size of the penetration voltage generating capacitor 19b is changed between the left and right sides of the screen.
It is not limited to this. The punch-through voltage generating capacitor 19b may be constant on the left and right sides of the screen, and the capacitance of the charge holding capacitor 19a may be changed on the left and right sides of the screen. Further, the capacitor 19b for generating the punch-through voltage
It goes without saying that both the capacitances of the charge holding capacitor 19a may be changed between the left and right sides of the screen.

In FIG. 250, the capacitance of the charge holding capacitor 19a or the punch-through voltage generating 19b is changed on the left and right of the display screen 21, but the gate driver 12 and the like are arranged on the left and right of the display screen 21. In this case (for example, power supply from both sides), the capacitors 19a and 19b on the left and right of the display screen 21 may have the same capacitance. However, when the signal waveform at the center of the screen is dull compared to the signal waveforms on the left and right of the screen, the capacitor 19b for generating the punch-through voltage is made constant on the left and right of the screen, and the capacitor 19a for holding charge is penetrated. The capacities of the voltage generating capacitors 19b are the same on the left and right of the display screen 21, and at least one of the capacities of the charge holding capacitor 19a and the punch-through voltage generating capacitor 19b is at the end and the center of the display screen 21. Change.

In FIG. 250, the punch-through voltage or the like may be different even if the gate driver 12 is formed at the same position as the pixel 16a and the pixel 16c. For example, from the relationship of the power supply position or voltage drop of the gate driver 12 and the signal supply position of the source driver 14. Therefore, the pixel 16c of FIG.
Makes at least one of the capacitance of the capacitor 19b for generating the punch-through voltage and the capacitance of the capacitor 19a for holding the charge different for the pixel 16a. The same applies to the pixel 16d.

As described above, according to the present invention, at least one of the capacitance of the capacitor 19b for generating the punch-through voltage and the capacitance of the charge holding capacitor 19a is displayed on the display screen 21.
It is changed in accordance with other conditions.

As shown in FIGS. 211 and 212, the structure for forming (arranging) the capacitor 19b of the present invention is as follows. That is, the switching TFT turns on and then turns off. At this time, the conversion TFT 11 of the EL element 15 (TFT in FIG. 6) acts on the capacitor 19a and the like.
By changing the gate terminal of 11a), the TFT
The configuration is such that the current of 11 does not flow. Although the P channel is used in FIGS. 211 and 212, the present invention can be applied to the N channel as shown in FIG. 215. In the case of N channel, the TFT is turned on by the Vgh voltage and the TFT is turned on by the Vgl voltage.
Turns off. Therefore, in case of N channel, TFT
When 11b (11c) is turned on (a pixel row is selected) and turned off (the next pixel row is selected), the conversion T
It may be configured so that the FT 11a acts in a direction in which no current flows. Therefore, the present invention is configured such that when the selected TFT is turned off, the EL element 15 is operated in a direction in which no current flows.

[1127] It will be easier to understand if explained with reference to FIG. 252. First, the current Iw as image data is drawn into the source driver 14 from the source signal line 18. Note that, here, for ease of explanation, it is assumed that the source driver 14 operates in a direction in which the program current Iw is absorbed and is programmed in each pixel 16. The operation will be described below with reference to FIGS. 252 and 253. Note that the explanation is for pixel row (1)
Will be explained.

As shown in FIG. 252 (a), the on voltage Vgl is applied to the gate signal line 17a (1) to select the pixel. At this time, the off voltage Vgh is applied to the gate signal line 17b (1). Therefore, the switching TFTs 11b and 11c are turned on and the TFT 11d is turned off.

[1129] The program current Iw is applied to the source signal line 18.
Flows and is supplied by the TFT 11a (current Idd
= Iw). When the program current Idd flows, the potential of the source signal line 18 becomes a predetermined voltage, and the TFT
The gate terminal voltage Vg of 11a is current programmed.
Here, the current programmed current is the Iw current, and the gate terminal voltage Vg of the TFT 11a is set so that the program current Iw flows. In other words, it can be said that the potential of the source signal line is programmed in the pixel. In other words, it can be said that the operating state of the pixel is that the voltage is programmed.

After 1H (1 horizontal scanning period), the off voltage Vgh is applied to the gate signal line 17a (1), and the TFT 1
1b, the TFT 11c is turned off, and the voltage required to flow the program current Iw in the capacitor 19a is held. Further, the ON voltage Vgl is applied to the gate signal line 17b (1), and the TFT 11d is turned on. Therefore, Ie (=
Iw) current flows through the EL element 15, and the EL element 15 is lit by the programmed current Ie (see FIG. 252 (b)).

[1131] The above is the operation of the current program method described above. However, the present invention differs from the above operation. This is because the current Ie flowing through the EL element 15 is smaller than the program current Iw. The reason for this is
This can be seen by looking at the change in Vg (gate terminal voltage of the TFT 11a) in FIG.

[1132] To facilitate understanding, the operation of the P channel of the TFT will be described. P-channel TFT
A larger on-current flows toward the negative side of the gate terminal voltage Vg, and is completely turned off at 0V. The on-current differs depending on the W / L of TFT, mobility, and S value. When the W / L of the TFT is 6/12, the channel current Idd is very small up to about -3V. -4V ~
A current of 1 to 5 μA flows at −4.5V.

[1133] FIG. 253 shows the time for programming the current for making the TFT 11a of the pixel (1) display almost black. First, the gate terminal voltage Vg of the pixel (1) is Vw
It is assumed that the voltage (white display etc.) is maintained. When the pixel (1) is selected, the gate signal line 17a (1) changes from the off voltage Vgh to the on voltage Vgl, so that the potential of the gate signal line 17a penetrates by the capacitor 19b. Due to this penetration, the gate terminal voltage Vg becomes V
It becomes 0.

Next, the TFT 11a is connected to the source driver 14
A current equal to the program current Iw absorbed by is passed. However, in the case of black display, the value of the current passed through the TFT 11a is small. As an example, it is 30 nA or less. Such a current cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period, so that the potential of the source signal line 18 cannot be set to a predetermined voltage within the 1H period. That is, the gate terminal voltage Vg is also low, and the originally required Vb voltage cannot be obtained, but becomes the Vc voltage.

[1135] Since the Vc voltage is lower than the Vb voltage, T
Since the FT 11a passes a larger current than the black display to the EL element 15, the EL element 15 emits light brighter than a desired value. Therefore, in the EL display panel, black floating occurs and high contrast display cannot be realized.

However, the operation of the present invention is different from the above operation. Since the gate signal line 17a (1) changes from the on-voltage Vgl to the off-voltage Vgh, the capacitor 19b is again provided.
This is because a punch-through voltage is generated. This punch-through voltage shifts the Vg voltage from the Vc voltage to the originally required Vb voltage. Therefore, the TFT 11a is programmed so that no current flows or a black current having a desired value is supplied. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention is free from blackening, and high contrast display can be realized. This Vb voltage is held in one field (one frame), that is, until the pixel is next selected and rewritten.

As described above, the present invention makes good use of the punch-through voltage to realize good black display. When the corresponding pixel row is selected and the ON voltage is applied to the gate signal line 17a, the V0 voltage penetrates and the Vg voltage shifts toward whiter display as shown in FIG. 253. However, the voltage that penetrates the source signal line 18
It is charged in a short time by the voltage from. In particular, TFT1
Since the gate terminal voltage Vg of 1a tends to decrease,
The TFT 11a is in a direction in which a current flows more and is charged in a short time. Therefore, the penetration of the V0 voltage does not pose any problem.

[1138] As the gate terminal voltage Vg of the TFT 11a approaches the target value Vb voltage, the TFT 11a is in the direction in which no current flows. Therefore, the target Vb voltage is hardly reached. In particular, the influence becomes more remarkable as the programmed current approaches the black display current. Figure 2
In 53, the voltage is not the Vb voltage but the Vc voltage even at the end of the selection period of 1H.

[1139] After the period of 1H, when the corresponding pixel row is unselected and the off voltage Vgh is applied to the gate signal line 17a, the off voltage Vgh is applied to the gate signal line 17a as shown in FIG. 229. And a penetration voltage is generated. Due to this punch-through voltage, the gate terminal voltage Vg of the TFT 11a reaches the target Vb voltage.

As described above, according to the present invention, the gate signal line 17
The voltage fluctuation of a is transmitted to the TFT 11a via the capacitor 19b.
The current supplied to the EL element 15 is controlled.
This control is particularly effective for realizing black display.

[1141] In the above description, the driving TFT 11 is driven by the punch-through voltage of the gate signal line 17a of the selected pixel row.
It controlled a. However, the present invention is not limited to this. For example, as shown in FIG. 254, it is possible to use the punch-through of the gate signal line 17a of the adjacent pixel row.

As shown in FIG. 93, FIG. 255 shows the voltage waveform of the applied gate signal line 17 in the method of selecting a plurality of pixel rows at the same time and shifting the selected pixel rows one pixel row at a time. .

[1143] FIG. 254 shows the gate signal line 1 of the next pixel row.
7a shows one terminal of the capacitor 19b in FIG.
Connected as described in. Further, as shown in FIG. 187, the gate signal line 17b is shared by a plurality of pixel rows (short-circuited at the lighting control line 1791). Also, FIG. 152 and FIG.
As described in 05, a three-side free configuration in which the gate driver 12 is arranged on one side of the display screen 21 is adopted.

[1144] The TFT 11a of FIG. 6 and the TFT 11 of FIG.
In order to reduce the influence of the kink variation of b, the TFT
It is preferable to fix the potential of the substrate on which 11 is formed.
For example, the TFT may be formed on a metal substrate such as a silicon substrate. Even when the TFT is formed on the glass substrate, a thin potential stabilizing layer is formed on the substrate by using a metal or the like, and the TFT 11 and the like are formed thereon. Further, one terminal of an element such as a TFT may be grounded on this potential stabilizing layer. As described above, by fixing the potential of the substrate, the kink variation can be greatly reduced. In particular, in the case of a structure in which light is taken out upward, it is not necessary to make the substrate transparent, so that the above structure can be easily adopted.

As can be understood from FIG. 255, the gate signal line 17a of the adjacent pixel row becomes the off voltage Vgh with a delay of 1H from the gate signal line 17a of the pixel row of interest. Therefore, the punch-through voltage is applied with a delay of 1H. Other operations are the same as the operations described with reference to FIGS. 252 and 253, and thus the description thereof will be omitted.

[1146] FIGS. 252 and 253 show the driving TFT 11a.
Was for the P channel. When the driving TFT 11a has N channels, the driving waveform is as shown in FIG. N
In the case of a channel, the switching TFT 11b and the like are turned on by applying the Vgh voltage, and turned off by applying the Vgl voltage. Therefore, as can be seen from the Vg waveform in FIG. 256, the punch-through voltage occurs when the voltage applied to the gate signal line 17a changes from Vgl to Vgh and from Vgh to Vgl. When the next pixel row is selected or not selected, Vg
The voltage is lower. Therefore, the driving TFT1
If the channel 1a is formed by N-channel,
As described in 53, good black display can be realized.

[1147] Note that since FIG. 215 is the TFT of FIG. 6 changed to the P channel and N channel, the operation is similar to that of FIG. 6, FIG.
Further, since the change between the P channel and the N channel is the same in FIG. 8 and the like, the concept of the capacitor 19b for the punch-through voltage of the present invention can be applied to other pixel configurations as it is.

[1148] Also, the driving TFT 11 (in FIG. 6, the TFT
11a, the TFT 11b in FIG. 19) has better control by punch-through voltage in N channel than in P channel in many cases. The reason for this will be described below.

FIG. 257 (a) shows the current output when the drain voltage (D) is made sufficiently lower than the source voltage (S) (saturation region). The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the negative side, a current flows between the source (S) and the drain (D). The vertical axis represents the source (S) -drain (D) current Ii.

[1150] Generally, a TFT formed by the low-temperature polysilicon technique causes a current to flow when the voltage is V0 or less. V
The 0 voltage is 3 to 4V. In general, the P-channel TFT has a voltage of 1 to 1.5 from the voltage V0 at which current starts to flow.
A current of 1 to 10 μA (for example, W / L = 6/9 μm) flows at V. This voltage width is Vc (V). Therefore, in the case of P channel, the gate (G) is displayed when black is displayed.
Current starts to flow at voltage V0, and gate (G) voltage V0 +
A current of 1 to 10 μA flows at Vc. The main part of FIG. 6 is extracted and written in an equivalent circuit diagram, as shown in FIG. 257 (c). The capacitance of the charge holding capacitor 19a is set to Ca.
The capacitance of the capacitor 19b for generating the punch-through voltage is Cb, and the channel capacitance of the TFT 11b is Ct. Further, the capacity obtained by adding Cb and Ct is defined as Cc. TFT1
The gate voltage of 1a is Vg.

[1151] The voltage applied to the gate signal line 17a is
The voltage is divided into Ca and Cc capacitances and applied to the gate terminal of the TFT 11a. For example, if Ca: Cc = 3: 2 and the voltage of the gate signal line changes by 10 V, this voltage becomes
The voltage is divided at 3: 2 and applied as Vg voltage to the gate terminal. That is, if Vdd = 0V, the gate signal line 1
When the potential of 7a changes from 0V to -10V, Vg =-
It becomes 4V.

The same applies when a predetermined voltage is applied to the gate voltage Vg in advance. The change in voltage applied to the gate signal line 17a is divided into Ca and Cc capacitances and applied. However, the punch-through voltage is due to the change in the potential of the gate signal line 17. Further, Ca and Cc are fixed values. Therefore, the change in potential is constant because it is determined by the off voltage Vgh and the on voltage Vgl. For example, the punch-through voltage is a constant value such as 0.1 V regardless of the image display state.

[1153] The gate voltage Vg changes depending on the image. For example, in black display, the gate voltage Vg is -3V, and in white display, it is -4V (see the solid line a in FIG. 257 (a)). However, since the punch-through voltage is a fixed value such as 0.1 V, the punch-through voltage 0.1 V for black display Vg = 3 V and the punch-through voltage 0.1 V for white display Vg = 4 V are contribution factors. Is different. That is,
The ratio of punch-through voltage to black display is higher than that of white display. Therefore, the effect of the punch-through voltage is large in black display and small in white display.

[1154] This operation contributes to the better display of the EL display panel. In other words, if the penetration voltage is large in black display, the program current flowing through the source signal line 18 becomes large due to black display. Therefore, it is preferable that the insufficient writing is eliminated and the influence of the punch-through voltage due to the white display is small.

[1155] When the driving TFT 11 is a P channel, the V0 voltage for displaying black is -3V or less, which is a relatively large absolute value. At least a voltage V0 for generating a current (about 2 to 50 nA) to be flowed at the gradation 1 (first gradation) for black display and a current Ii (μ for flowing at the maximum gradation for white display).
The relation with the voltage V0 + Vc for generating A) preferably satisfies the following equation.

1/2 ≦ | (Vc + V0) / V0 | ≦ 3 More preferably, 1 ≦ | (Vc + V0) / V0 | ≦ 2 is satisfied. This is because the effect of the punch-through voltage is remarkable in the black display, good black display can be realized, and the effect of the punch-through voltage in the white display can be reduced.

Also, in FIG. 257 (a), the conventional voltage width Vc may be made relatively larger than V0. That is, the S value is reduced. Or reduce mobility.

[1158] For the P channel of FIG. 257 (a),
It is preferable to shift the V0 voltage to the 0 potential side as shown by the dotted line b. This shift can be realized by changing the doping amount in the semiconductor layer of the P-channel TFT. The above matters also apply to the case of the N channel of FIG. 257 (b).

When manufacturing the array, the TFTs constituting the gate driver 12 and the like may be doped in the same manner as in the conventional case, and the doping amount of the TFT 11a of the pixel may be changed. This can be formed by using a mask during doping. In addition, the TFT configuring the gate driver 12 and the like is configured by only N channels, and the TFT of the pixel is
11a is a P channel. Conversely, the pixel TFT 11
When a is an N channel, the TFTs and the like forming the gate driver 12 and the like are P channels. The above items can also be applied to the following items.

[1160] FIG. 257 (b) shows the current output when the source voltage (S) and the drain voltage (D) of the N-channel TFT are set to sufficiently high voltages (saturation region). The horizontal axis represents the gate (G) voltage with respect to the source (S) voltage. When the gate voltage is set to the positive side, a current flows between the source (S) and the drain (D). The vertical axis represents the source (S) -drain (D) current Ii.

[1161] Generally, an N-channel TFT formed by the low-temperature polysilicon technique causes a current to flow when the voltage is V0 or higher. The V0 voltage is 1 to 2V. Further, in general, an N-channel TFT has a voltage V0 at which a current starts flowing.
From 1 to 1.5 V from 1 to 10 μA (for example, W / L = 6
/ 9 μm) current flows. This voltage width is Vc (V).

[1162] Therefore, in the case of the N channel, during black display, a current starts to flow at the gate (G) voltage V0, and a current of 1 to 10 μA flows at the gate (G) voltage V0 + Vc.

The gate voltage Vg changes depending on the image. For example, in black display, the gate voltage Vg is 1.5 V from the ground voltage, and in white display, it is 2.5 V (see FIG. 257 (b)). However, the penetration voltage is
For example, since it is a fixed value such as 0.1 V, the penetration voltage is 0.1 V with respect to Vg = 1.5 V for black display.
Penetration voltage 0.1V for Vg = 2.5V displayed in white
And the contribution is different. That is, the ratio of the punch-through voltage to the black display is higher than the ratio of the punch-through voltage to the white display. Therefore, the effect of the punch-through voltage is large in black display and small in white display. That is, the V0 voltage in the N channel is lower than that in the P channel. Therefore, the driving TFT 11a has a larger punch-through voltage in the N channel than in the P channel, that is, in the black display, and a larger program current flowing in the source signal line 18 in the black display. Therefore, the write shortage is resolved.

[1165] The above items can be applied to the pixel configuration of the voltage program shown in FIGS. 75 and 76. That is, it is possible to prevent the current from flowing through the EL element 15 unless the program voltage exceeds a certain level. Therefore, in black display or the like, when the signal fluctuates due to noise, the noise level is removed.
L element 15 does not light up). In addition, the white peak luminance is easily produced, and the image quality is improved.

[1165] Also, in the above embodiment, the capacitor 19b is used.
Although the punch-through voltage is set (set to a desired value) with the capacitance of, the value of the punch-through voltage also changes with the amplitude value of the gate signal line 17. Therefore, the punch-through voltage can be adjusted by adjusting the amplitude value of the gate signal line 17a (in the case of FIG. 6). For example, V of the gate signal line
If the gh voltage = 10V and the Vgl voltage = 0V, the amplitude value is 10V. In this state, if the punch-through voltage is 0.1 V and the Vgh voltage is 12 V, the amplitude value is 12
It becomes V. Therefore, ideally, the penetration voltage is 0.
It will be 12V. That is, the punch-through voltage can be freely changed by adjusting the amplitude of the gate signal line 17, and the base current can be adjusted.

[1166] This control is easy because the power supply circuit for generating the gate voltage may be set with a command to set the value of the Vgh voltage or the Vgl voltage. By adjusting this voltage, the punch-through voltage can be finely adjusted.

[1167] A signal (TF) applied to the gate signal line 17a
If the slew rate (change in voltage with respect to rising and falling times) of the T11 on / off signal) is high, the punch-through voltage tends to increase. Conversely, if the slew rate is low, the punch-through voltage will decrease. That is, the penetration voltage is higher when the slew rate is 40 V / μsec than when it is 20 V / μsec. The slew rate of the gate signal changes depending on the driving capability of the output buffer (inverter circuit, operational amplifier, etc.) of the gate driver 12. By controlling the output current of the output buffer, the slew rate can be adjusted and the punch-through voltage can also be adjusted. The control of the output current of the output buffer can be realized by adjusting the supply voltage of the output buffer and blunting the waveform applied to the gate terminal. Further, adjusting the supply voltage is easy in terms of circuit configuration. The blunting of the waveform applied to the gate terminal can be realized by reducing the size of the buffer in the previous stage (reducing the capacity). Further, the punch-through voltage can be changed by using an on / off signal applied to the gate signal line 17a as a sine curve or sawtooth signal. The above items are also applied to the control of the voltage control signal line and the common signal line described below.

[1168] In FIG. 211 and the like, the capacitor 19b for generating the punch-through voltage has one electrode as the gate signal line 17 (though it is connected to the gate signal line 17), but it is not limited to this. Absent. For example,
A voltage control signal line for controlling the capacitor 19b is separately formed for generating the punch-through voltage. One of the two electrodes of the capacitor 19b may be connected to the gate terminal of the converting TFT 11a, and the other may be connected to the separately formed voltage control signal line. In this configuration, the gate signal line 17a
A pulse signal (not limited to a rectangular wave, but may be a sine curve or a sawtooth signal) may be applied to the voltage control signal line in synchronism with the selected state. Further, the punch-through voltage can be easily adjusted by adjusting the pulse amplitude value.

[1169] This configuration is shown in FIG. 258. A punch-through voltage is applied to the gate terminal of the TFT 11a via the capacitor 19b by the pulse voltage applied to the voltage control signal line 17c.

[1170] The voltage control signal line 17c is the gate signal line 17c.
And the operation is the same. As shown in FIG. 259, the voltage control signal line 17c is configured as an output terminal of the gate driver 12. Further, as described with reference to FIG. 187, the gate signal line 17b is connected to the lighting control line 1791.

If the signal for generating the punch-through voltage is not supplied from the gate signal line 17a but is supplied from the voltage control signal line 17c as shown in FIG. 260, the control of the punch-through voltage becomes easy. FIG. 260 is an explanatory diagram of signal waveforms for driving the display panel of FIG. 259. For ease of explanation, the pixel row selected is the pixel row number (1).
Will be described.

When the pixel row (1) is selected, the gate signal line 17a (1) changes from the Vgh voltage to the Vgl voltage, so that the gate signal line 17a is changed by the capacitor 19b.
The electric potential of goes through. Due to this penetration, the Vg voltage becomes V
It becomes 0.

Next, the TFT 11a is connected to the source driver 1
A current equal to the current Iw absorbed by 4 flows. However, in the case of black display, the value of the current passed through the TFT 11a is small. As an example, it is 30 nA or less. Such a current cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

Next, since the gate signal line 17a (1) changes from the on-voltage Vgl to the off-voltage Vgh, the punch-through voltage is generated again by the capacitor 19b. This penetration voltage shifts the Vg voltage from the Vc voltage to the Va voltage.

[1175] Further, after a time delay of t1, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. Therefore, a penetration voltage is further generated, and the gate terminal voltage Vg of the TFT 11a shifts to the target voltage Vb. By adjusting the shifting voltage, the punch-through voltage can be freely controlled. That is, in the configurations of FIGS. 252 and 253, the change in voltage (amount of punch-through voltage) is restricted by the amplitude of the gate signal line 17a. However, by separately providing the voltage control signal line 17c as shown in FIG. 259, it becomes easy to change the amount of punch-through voltage. Further, it is easy to control the slew rate of the applied signal. Further, since there is no restriction on the potential level of the signal applied to the voltage control signal line 17c, the circuit configuration becomes easy.

[1176] Therefore, the TFT 11a is programmed so that no current flows or a black current having a desired value is supplied. That is, the EL element 15 is programmed so that only a minute current flows. Therefore, the EL display panel of the present invention is free from blackening, and high contrast display can be realized. This Vb voltage is held in one field (one frame), that is, until the pixel is next selected and rewritten.

As described above, according to the present invention, the voltage fluctuation of the voltage control signal line 17c is caused by the TFT via the capacitor 11b.
11a. Therefore, the current flowing through the EL element 15 is controlled. This control is particularly effective for realizing black display.

The difference between FIG. 260 and FIG. 261 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. The other points are the same. With the configuration shown in FIG. 261, the gate signal line 17a and the voltage control signal line 17c are formed.
Since the operation clocks of and can be made the same, the circuit configuration becomes easy.

[1179] Fig. 259 shows the pixel configuration of the current program of Fig. 6. However, the present invention is not limited to the current programming method and can be applied to the pixel configuration of voltage programming. FIG. 262 applies the technical idea of the present invention to the pixel configuration of the voltage program described in FIG. 81 and the like.

[1180] FIG. 262 shows that one terminal of the capacitor 19b is T
It is connected to the drain terminal of the FT 11b and the other terminal is connected to the voltage control signal line 17c. The switching TFT 11b is formed by an N-channel TFT.

[1187] FIG. 263 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. 262. When pixel row (1) is selected,
Since the gate signal line 17a (1) changes from the Vgl voltage to the Vgh voltage, the potential of the gate signal line 17a is penetrated by the capacitor 19b. V due to this penetration
The g voltage changes from the held Vw to V0.

Next, the TFT 11a is connected to the source driver 1
A current equal to the current Iw absorbed by 4 flows. However, the minute current for black display cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage Vb cannot be obtained, and becomes the Vc voltage.

[1187] Next, since the gate signal line 17a (1) changes from the on-voltage Vgh to the off-voltage Vgl, the capacitor 19b again generates a punch-through voltage. Due to this penetration voltage, the Vg voltage further decreases from the Vc voltage and shifts to the Va voltage.

[1184] Further, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage after a delay of t1. Therefore, a punch-through voltage is generated, and the gate terminal voltage Vg of the TFT 11a shifts to the target voltage Vb. Therefore, the target voltage Vb can be applied to the gate terminal of the TFT 11a.

The difference between FIG. 263 and FIG. 264 is that the operation timing t1 of the voltage control signal line 17c is set to 1H. The other points are the same. By configuring as shown in FIG. 264, the gate signal line 17a and the voltage control signal line 17c are
Since the operation clocks of and can be made the same, the circuit configuration becomes easy.

As the configuration using the voltage control signal line 17c, various other configurations are exemplified. For example, FIG. 265 shows the drain terminal of the switching TFT 11c and the voltage control signal line 1
This is a configuration in which a capacitor 19b is arranged (formed) between 7c. The configuration of FIG. 265 is not a configuration in which the punch-through voltage is directly applied to the gate terminal of the TFT 11a. However, the signal waveform applied to the voltage control signal line 17c is
It is applied to the drain terminal of the TFT 11c via 9b. The voltage applied to this drain terminal is TF
It is reflected (affected, operated, controlled) on the gate terminal of the TFT 11a via T11b and the like.

[1187] That is, in the pixel configuration shown in FIG. 265, the drive TFT 11a for supplying a current to the EL element 15 is not directly controlled. However, it is possible to control the current passed by the drive TFT 11a. The present invention provides for controlling the programmed current to be lower (sometimes higher), such as controlling the white peak current to be more flowable, in some way. is there. Therefore, the configuration of FIG. 265 is also within the technical idea of the present invention.

FIG. 266 shows a method in which the voltage control signal line 17c and the punch-through voltage generating capacitor 19b are formed in the pixel configuration of the current mirror of FIG. No particular explanation will be required for this configuration. Therefore, the description is omitted.

[1189] In FIG. 267, the punch-through voltage generating 11a is not formed. The voltage control signal line 17c is connected to one terminal of the holding capacitor 19. Until now, the voltage applied to the punch-through voltage generating capacitor 19b causes the TFT1
It has been described that the potential of the gate terminal of 1a is controlled and the current flowing through the TFT 11a is adjusted.

In FIG. 267, the voltage of the gate terminal of the TFT 11a is controlled by directly controlling the charge holding capacitor 19, and the current flowing through the TFT 11a is controlled. The operation can be applied to the operation described in FIG. 264 as it is or by analogy. Figure 2
In the pixel configuration of 67, the capacitor 19b for generating the punch-through voltage is unnecessary. Therefore, the pixel configuration becomes easy.

[1191] FIG. 268 is an explanatory diagram of drive waveforms in the pixel configuration of FIG. 267. When the gate signal line 17a (1) is selected, the TFT 11c and the TFT 11d are turned on.
Next, the TFT 11a causes a current equal to the current Iw absorbed by the source driver 14 to flow. However, the minute current for black display cannot sufficiently charge and discharge the parasitic capacitance of the source signal line 18 within the 1H period. Therefore, the potential of the source signal line 18 cannot be set to the predetermined voltage within the 1H period. That is, the Vg voltage is also low, and the originally required voltage V
It cannot be set to b and becomes Vc voltage.

Next, gate signal line 17a (1) changes from on-voltage Vgl to off-voltage Vgh. At the same time, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. Therefore, a punch-through voltage is generated and the TFT 11a
The gate terminal voltage Vg of is shifted to the target voltage Vb.
Therefore, the target voltage Vb can be applied to the gate terminal of the TFT 11a.

[1193] Note that in FIG. 268, "gate signal line 17
a (1) changes from the on-voltage Vgl to the off-voltage Vgh. At the same time, the voltage control signal line 17c (1) shifts from the low voltage to the high voltage. However, the present invention is not limited to this, and the signal waveform may be changed after a period of t1 as shown in FIG. 263 or FIG.

It is needless to say that the pixel configuration shown in FIG. 267 can be applied to the pixel configuration shown in FIG. The voltage control signal line 17c is connected to one terminal of the charge holding capacitor 19 (see FIG. 269). Then, this voltage control signal line 17
The gate terminal voltage of the TFT 11a is changed by the signal applied to c to control (adjust) the current flowing through the TFT 11a.

[1195] Also, in the lower layer of the electrode of the capacitor 19a,
A signal line insulated from the electrode may be formed. what if,
This signal line is called a common signal line. If such a configuration is realized, the second capacitor can be formed by the common signal line, the insulating film, and the electrode of the capacitor. This capacitor can be regarded as the capacitor 19b in FIG. Therefore, by applying the pulse signal to the common signal line in the same manner as above, the same action and effect as above can be exhibited. Although the name is called the common signal line, there is no difference in function and configuration from the voltage control signal line 17c described above. Therefore, the matters and contents described for the voltage control signal line 17c can be applied to the common signal line as they are.

Also, in the above embodiments, one terminal of the punch-through voltage generating capacitor 19b is connected to the gate terminal of the TFT 11a. However, the present invention is not limited to this configuration. For example, as shown in FIG. 270, one terminal of the punch-through voltage generating capacitor 19b may be connected to the midpoint of the charge retaining capacitors 19a and 19c. By configuring as shown in FIG. 270, the influence of the punch-through voltage on the gate terminal of the TFT 11a is reduced.

The configuration shown in FIG. 271 is also effective. In FIG. 271, when a pixel is selected, the voltage from the source driver 14 is applied to the drain terminal Vk of the TFT 11b. This voltage (that is, the programming current)
Is divided by the capacitors 19a and 19c to become the gate terminal voltage Vg of the driving TFT 11a.
Therefore, the gate terminal voltage Vg becomes lower than the programmed voltage Vk. Therefore, the current flowing through the TFT 11a (current flowing through the EL element 15) is smaller than the programmed current. Therefore, the program current can be increased and the current flowing through the EL element 15 can be reduced. Therefore, even in black display, insufficient writing is eliminated.

In FIG. 271, the capacitance of the charge holding capacitor 19a is set to Ca, and the capacitor 1 for voltage shift is used.
When the capacitance of 9c is Cc, the high voltage signal applied to the gate signal line is Vgh, and the low voltage signal applied to the gate signal line is Vgl, the following conditions are satisfied: Good black display can be realized.

0.5 ≦ | Vgh−Vgl | × (Ca / Cc) ≦ 10 More preferably, the following conditions are preferably satisfied.

1 ≦ | Vgh−Vgl | × (Ca / Cc) ≦ 5 Further, based on Vc in FIG. 257, 0.05 ≦ | Vc | × (Ca / Cc) ≦ 1 Further preferably, It is preferable to satisfy the condition of.

1 ≦ | Vc | × (Ca / Cc) ≦ 5 The above items are also valid for the pixel configurations shown in FIGS. 142 and 87. For example, in the pixel configuration of the voltage program of FIG. 142, the gate terminal of the TFT 11a and the gate signal line 17a
A capacitor 19b for generating punch-through voltage is formed or arranged in between.

[1202] The above items also apply to the embodiment of FIG. 272. Needless to say, the present invention can be applied to the pixel configuration described in FIG. 19 and the like (see FIG. 273). Further, it can be applied to the pixel configuration of the voltage program shown in FIGS. 86 and 87. The voltage that penetrates the TFT can be compensated. Further, it is possible to operate at the best operating point by shifting the potential.

[1203] FIG. 271 has a configuration in which a capacitor 19b for generating punch-through voltage is added. However, in the configuration of FIG. 271, the ON resistance of the P-channel TFT 11b is generally low, so that the channel width W needs to be relatively large. Therefore, the source-gate capacitance is relatively large. Therefore, the parasitic capacitance generated in the TFT 11b can be used as a substitute without adding the capacitor 19b.

[1204] As shown in FIG. 271, when both the punch-through voltage generating capacitor 19b and the voltage shifting capacitor 19c are manufactured, the operating point Vg may vary. To solve this problem, it is effective to set the switching TFTs (TFTs 11b and 11c in FIG. 6 and TFTs 11c and 11d in FIG. 19) for selecting pixel rows to N channels to reduce the punch-through voltage as much as possible.
This embodiment is shown in FIG. 272. In FIG. 272, by setting the switching TFT 11b to the N channel, P
The penetration voltage can be reduced to 1/2 to 1/5 as compared with the channel. Therefore, the punch-through voltage is unlikely to occur and the Vk voltage shift is unlikely to occur. for that reason,
Variations in the gate terminal voltage Vg of the TFT 11a hardly occur. In FIG. 272, a TFT 11g (switching means) for applying the reverse bias voltage Vm is added.

[1205] The above is the case of the pixel configuration of FIG. 6, but the configuration of FIG. 19 is also the same (see FIG. 274). When a pixel is selected, the TFT 11d is turned on, and the voltage (current) from the source signal line 18 is written in one terminal of the capacitor 19a connected to the drain terminal of the TFT 11d. That is, the voltage from the source driver 14 is the TFT
It is applied to the drain terminal Vk of 11b. This voltage (that is, the program current) is divided by the capacitors 19a and 19c and becomes the gate terminal voltage Vg of the driving TFT 11b. Therefore, the gate terminal voltage Vg is smaller than the programmed voltage Vk,
Therefore, the current flowing through the TFT 11b (current flowing through the EL element 15) becomes smaller than the programmed current. Therefore, the programming current is increased and the EL element 1
The current flowing through 5 can be reduced. Therefore, even in black display, insufficient writing is eliminated.

[1206] As is apparent, as shown in FIG. 274, each pixel 16 has a reverse bias TFT1.
You may add 1 g. It goes without saying that a capacitor 19b for generating punch-through voltage may be added. Of course, it goes without saying that a TFT 11d for controlling on / off of the current flowing through the EL element 15 may be added. As described above, the present invention can mutually combine the configurations, examples, and technical ideas described in this specification.

[1207] Note that the common signal line and the voltage control signal line are formed in parallel with the pixel row. That is, the signal line is formed (arranged) for each pixel row. However, the formation is not necessarily limited to each pixel row. For example, in the case of selecting pixels by two or more pixel rows, the signal line may be formed (or arranged) for each plurality of pixel rows.

[1208] In FIG. 211 and the like, 19b is 2
Although the capacitor of the terminal is used, it is not limited to this. For example, a TFT may be used, and a source-gate capacitance of the TFT may be used to form a capacitor. That is, the element that generates the punch-through voltage is not limited to the capacitor, and may be any element that can change the potential of the gate terminal of the conversion TFT 11a of the EL element 15 in an insulated state. Of course, it goes without saying that a capacitor can also be configured with the junction capacitance of the diode.

[1209] Also, although the capacitor 19b is formed in each pixel, it is not necessarily limited to this. For example, one capacitor 19b may be formed by adjacent pixels.

[1210] Further, a switching element such as a TFT is arranged (formed) at one end of the capacitor 19b, and the switching element is controlled to be turned on / off, thereby the capacitor 1
9b may be separated from the pixel 16.
That is, by disconnecting the capacitor 19b from the pixel 16, the base current can be changed (present or absent). Further, although the capacitor 19b is separated by the switching element, a TFT (switching element) or the like that short-circuits the electrodes of the capacitor 19b is formed (arranged) and the switching element is turned on so that the capacitance of the capacitor 19b becomes zero. You may perform the control.

The target of potential change is not limited to the conversion TFT 11a. Any element may be used as long as it sets the current amount of the EL element 15. That is, the conversion TF
This is because T11a can be configured by MIM, TFD (thin film diode), or the like. E by controlling these
It may be configured so that the current flowing (or flowing) in the L element 15 can be controlled. In this configuration, the cathode electrode is processed (formed) in a horizontal stripe shape as needed.

Also, the reverse bias driving method of preventing deterioration of the EL element 15 by applying the reverse bias voltage Vm has been described with reference to FIGS. 166, 169, 172 to 183 and the like. Needless to say, this reverse bias drive method is combined with the method of controlling the current flowing through the EL element 15 by the punch-through voltage described in FIGS. 275, 276, 277 (called the punch-through drive method). It goes without saying that it is okay.

FIG. 276 shows a TFT1 in which a capacitor 19b for generating punch-through voltage is added to the pixel configuration of the voltage program shown in FIG. 86 and a reverse bias voltage Vm is applied.
This is a configuration in which 1d is added.

[1214] The reverse bias voltage Vm is equal to the TFT 11d.
However, the voltage is not limited to this and may be replaced with a capacitor. In other words, like the punch-through voltage generating capacitor 19b, by applying a pulse voltage to one end of the capacitor, the voltage applied to the electrode of the capacitor may be applied to the EL element 15 by punch-through.

[1215] FIG. 277 shows a configuration in which a reverse bias TFT 11g is added to the current mirror pixel configuration (current programming system) described with reference to FIG. Also, FIG.
Reference numeral 78 is a pixel configuration in which a reverse bias TFT 11g is added to the voltage programming type pixel configuration described in FIG. Further, FIG. 279 shows a pixel configuration in which a reverse bias TFT 11g is added to the pixel configuration (current programming method) of FIG.

In the above embodiments, the punch-through voltage generating capacitor 19b has been described as a two-terminal capacitor, but the present invention is not limited to this. For example, in FIG. 280, the capacitor 19b is configured (formed and manufactured) by the channel capacitance of the transistor 2271. Source-drain capacitance may be used.

Similarly, the charge holding capacitor 19a is not limited to the two-terminal capacitor. As described with reference to FIG. 280, the channel capacitance of the transistor may be used. Further, the capacitance may be formed by a diode (the transistor 2271 (capacitor 19b) in FIG. 280 can be regarded as a diode). In addition, any element may be used as long as it can hold an electric charge. It goes without saying that the above items can be applied to other embodiments of the present invention.

[1218] Also, not only the combination of the punch-through drive system and the reverse bias drive but also the block drive system and N
The present invention described in this specification, such as a double pulse driving method and a multiple pixel row selection method, can be combined with each other.
The above items also apply to the following items.

[1219] Note that the punch-through voltage causes a deviation with respect to the target current. However, as in the present invention,
Program so that double current flows through EL element 15,
Moreover, in the method of intermittently displaying the display image, the deviation from the target value is also about 1 / N. In addition, 1 times the current (normal drive,
Compared with conventional drive), T
Since the FT 11a is operated, the deviation is reduced.
Therefore, better image display can be realized as compared with the conventional case.

Also, the technical idea of the present invention is to control the current flowing through the EL element 15. Therefore, it is not indispensable that the generation timing of the punch-through voltage is always synchronized with the scanning timing of the gate signal line 17a. Asynchronous control may be possible. The punch-through voltage may be dispersed and applied multiple times.

[1221] As shown in FIGS. 111 to 114, D
The current output circuit 1222 including the A circuit 1226 outputs current to the source signal line 18, but FIGS.
2, in the method of driving by generating the punch-through voltage as shown in FIG. 215, it is necessary to add a constant base current and output. For example, when a current of 30 nA is programmed in the pixel 16 at a certain gradation, a current to which a base current due to a punch-through voltage is added is applied to the source signal line 18. If the base current is 40 nA, 30 nA + 40 n
The current of A is applied to the source signal line 18 (absorbed from the source signal line 18 toward the current output circuit 1222).
Therefore, it is necessary to configure the circuit so that the base current is applied and flowed. For example, a configuration in which a current mirror circuit for the base current is added is exemplified.

[1222] In FIGS. 111 to 114, the DA circuit 122 is used.
The current output circuit 1222 including 6 outputs current to the source signal line 18, but the present invention is not limited to this. For example, one first current mirror circuit that generates a reference current is formed in the source driver 14 (FIG. 28).
See 1).

[1223] FIG. 281 shows a main portion of the current output circuit 1222 corresponding to each source signal line 18. In addition,
In FIG. 281, the applied image data is 6 bits (RG
The description will be made assuming that B is 64 gradations each. Image data D (0 to 5) corresponds to 6 bits, MSB (most significant bit) is D5, and LSB (least significant bit) is D0.

As shown in FIG. 281, the image data D0
Causes the switching transistor 2752a to turn on,
One child transistor 2754a turns on. Similarly,
Switching transistor 275 according to image data D1
2b turns on and the two child transistors 2754b turn on. Further, the switching transistor 2752c is turned on by the image data D2, and the four child transistors 27
54c turns on. Further, the switching transistor 2752d is turned on by the image data D3, and the eight child transistors 2754d are turned on. Also, the image data D4
The switching transistor 2752e is turned on, and 1
The six child transistors 2754e turn on. In addition, the switching transistor 2752 is generated by the image data D5.
f is turned on, and the 32 child transistors 2754f are turned on. Therefore, the current Iw expressing 64 gradations according to the input image data D flows from the source signal line 18.
That is, the ON voltage is applied to the gate signal line 17a, and the Idd (=
Iw) Current flows.

In FIG. 281, one parent transistor 2753 is formed (arranged) in the source driver 14. The current flowing through the parent transistor 2753 flows through the child transistor 2754. That is, the source signal line 18
If there are 176 (in case of QCIF) books, 176 ×
63 child transistors 2753 are parent transistors 27
It is connected to 53.

[1226] However, this is one parent transistor 2
Since there are too many connected to 753, an intermediate transistor may be arranged. For example, if the parent transistor is the first transistor, the second transistor and the third transistor are formed, and 63 of the child transistors 2754 are connected to the third transistor to establish a current mirror relationship. Therefore, if QCIF is taken as an example (the number of source signal lines is 176), 16 second transistors having a current mirror relationship with one first transistor (parent transistor) are formed (arranged), and the second transistor is formed. Third transistor in a current mirror relationship with the transistor
11 transistors are formed (arranged). That is, the number of the first to third transistors in the current mirror relationship is 1 × 16 × 11 = 176. The first to third transistors are densely arranged in the source driver 14. This is to eliminate the influence of Vt variation of each transistor. In particular, the first transistor and the second transistor need to be arranged very close to each other.

With the above relationship, the output current amount of the entire IC chip can be adjusted by adjusting the current passed through the first current mirror circuit (parent transistor 2753). The current flowing through the parent transistor 2753 is configured so that it can be adjusted by an electronic volume. Further, as shown in FIG. 281, an external volume (bias resistance) 2751 is arranged in the source driver 14 and the resistance value of this resistance is changed, so that the current flowing through the parent transistor (first transistor) 2753 is reduced. It may be configured to change. In any case, the minimum step of the program current Iw can be easily and simultaneously changed by adjusting the current flowing through the parent transistor 2753.

[1228] Note that in FIG. 45, FIG. 46, FIG. 116, and the like, a plurality of pixel rows are selected at the same time. Even in this case,
This can be dealt with by changing the current flowing through the parent transistor 2753. That is, as compared with the case where one pixel row is selected, a current that is twice as many as the selected pixel row is supplied to the parent transistor 27.
This is because it can be sent to 53. Further, as described with reference to FIG. 121, it is easy to deal with the driving method of changing the current flowing in the source signal line 18 (absorbed from the source signal line 18) in the period of 1H or the like. Parent transistor 2753
This is because it is only necessary to change the current flowing to the.

The brightness of the display panel and the gamma characteristic can be adjusted by adjusting the current of the parent transistor 2753. The reference current flowing through the parent transistor 2753 is configured so that it can be independently adjusted for each of the R, G, and B pixels. This is because the RGB gamma curve and applied current are different. This structure is shown in FIG. As shown in FIG. 282, parent transistors 2753 (2753) of respective colors
The current flowing through R, 2753G, 2753B) can be changed by an electronic regulator or a bias resistor. Of course, the current flowing through the parent transistor 2753 is corrected so as to match the gamma characteristic and the temperature characteristic of the EL element 15.

In addition, one (or more than one) child transistor 2754 is formed for each of data D0 to D5, and the current output is changed by changing the current magnification of the current mirror circuit with the parent transistor 2753. It may be configured. For example, the child transistor 2754 corresponding to D0 has a current multiplication factor of 1 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D1.
And the parent transistor 2753 and the current magnification are 2 times.
Similarly, the child transistor 2754 corresponding to D2 has a current multiplication factor of 4 times that of the parent transistor 2753, and the child transistor 2754 corresponding to D3 is the parent transistor 2753.
The current magnification with 53 is 8 times. Further, the child transistor 2754 corresponding to D4 is the parent transistor 2753.
And the current ratio to the parent transistor 2753 of the child transistor 2754 corresponding to D5 is 32 times.

[1231] As described above, the output current circuit 1222 is
By adopting the configuration of a two-stage or three-stage (first transistor, second transistor, and third transistor) current mirror circuit, each source signal line 1
It is possible to eliminate the variation in current programmed to 8. When the punch-through voltage capacitor 19b is formed as shown in FIGS. 211 and 215, it is necessary to add a constant base current to output. Further, even if the capacitor 19b for punch-through voltage is not arranged (formed), the punch-through voltage is generated by the source-gate terminal capacitance of the TFT 11b. For example, in the same manner as above, when the current of 30 nA is programmed in the pixel 16 at a certain gradation,
A current to which the base current due to the punch-through voltage is added is applied to the source signal line 18. If the base current is 40 nA,
A current of 30 nA + 40 nA is applied to the source signal line 18 (absorbed from the source signal line 18 toward the current output circuit 1222). Therefore, it is necessary to configure the circuit so that the base current is applied and flowed. For example, a configuration in which a current mirror circuit for the base current is added separately is exemplified.

In FIG. 283, the transistors 2752bb and 2754bb for applying the base current are arranged (formed) in the source driver 14. The application of the base current can be switched by the logic signal applied to the terminal Dbb. That is, whether or not the base current is applied is configured to be logically controllable.

Since the gamma curve and the applied current are different for each of the RGB EL elements 15, it is preferable that the base current can be adjusted independently for each RGB and that the ON / OFF control can be performed. This is because when a base current is applied (the current may be absorbed from the source signal line 18), black floating occurs depending on the image. Therefore, by turning the base current on and off, the optimum adjustment can be made. Further, it is preferable that the on / off of the base current can be independently set for each RGB.

[1234] As described above, the parent transistor 2
The reference current supplied to 753 and the base current supplied to the transistor 2754bb are temperature-compensated. The panel (more precisely, the temperature of the EL element 15) is detected, and the values of the reference current and the base current are changed according to the detected temperature. In general, the EL element 15 has a reduced luminous efficiency as the temperature rises, and therefore the current applied to the EL element 15 is increased when the temperature rises. Further, it is preferable that the compensation values of the reference current and the base current can be set independently for each RGB.

In the above embodiments, the capacitor 19b for generating the punch-through voltage is formed in the pixel 16, or T
Although a method has been used in which more bias current for black display is supplied by utilizing the channel capacity of the FT 11b or the like, the above items can be realized by shifting the potential of the source signal line 18. FIG. 284 is an example thereof.

For example, the voltage applied to the switch circuit 1223 is the voltage output circuit 1221 of FIG. 143. That is, according to the image data, the switch circuit 1223 is turned on to shift the potential of the source signal line 18 toward the Vdd voltage. Therefore, the potential Vg of the gate terminal of the TFT 11a becomes high, and the TFT 11a stops flowing current. The timing of closing the switch circuit 1223 is immediately before the selected pixel row is deselected. That is, immediately before the off voltage is applied to the gate signal line 17a. Therefore, after the current is programmed in the capacitor 19a of the pixel 16 and the switch circuit 1223 operates, the potential shift due to the source signal line 18 is superimposed on the capacitor 19a, and then the off voltage is applied to the gate signal line 17a,
The corresponding pixel row is unselected.

[1237] Note that "according to image data" means 64
Of the gradations, the lower 8 gradations close to black display mean that the switch circuit 1223 is closed. This is because in black display, the current flowing through the source signal line 18 is small, and thus insufficient writing is likely to occur. That is,
This is the selective precharge described previously.

[1238] The current output circuit 1222 of FIG.
3, FIG. 144, FIG. 281, FIG. 282, FIG. 283 and the like. Hereinafter, another current output circuit 1222 of the present invention will be described.

[1239] FIG. 285 is a block diagram of a display panel using another current output circuit 1222. Note that, in FIG. 285 and the like, the current output circuit 1222 is arranged on the array substrate 49 in the pixel 1
It may be formed simultaneously with 6. That is, the current output circuit 12
22 may be formed by low temperature polysilicon technology. That is, it goes without saying that it may be formed in the same process as the TFT of the pixel, or may be formed in the source driver 14 of the silicon chip and mounted on the array substrate 49 by using the COG technique or the like. It may also be formed by high temperature polysilicon technology, or by an organic material (organic TF
T).

[1240] The current output circuit 1222 in FIG.
This is a configuration in which the EL element 15 of No. 7 is deleted and the location of the deleted EL element and the source signal line 18 are connected. That is, the source signal line 18 of FIG.
Becomes The output of the current sampling circuit 3001 is connected to the current program line 3002. The current flowing through the current program line 3002 is the current flowing through the source signal line 18. Therefore, the current sampling circuit 300
The current from 1 flows in the current program line 3002, and this current is programmed in the capacitor 19. Then, the programmed current is applied to the source signal line 18 in synchronization with the 1H clock. Therefore, since it is necessary to apply current to the source signal lines 18 all at once in synchronization with the 1H clock, the output stage of the current output circuit 1222 is provided with a switch that turns on and off in synchronization with the 1H clock.

The current output circuit 1222 may have the current mirror pixel 16 configuration of FIG. 159. The current output circuit 1222 of FIG. 285 has a configuration in which the EL element 15 of FIG. 159 is deleted and the location of the deleted EL element and the source signal line 18 are connected. That is, the source signal line 18 in FIG. 159 becomes the current program line 3002.

[1242] In the configuration of the current mirror in FIG. 159, by setting (configuring) the current magnification, the current sampled and written in the current output circuit 1222 and the current value drawn from the source signal line 18 are made different. be able to. Therefore, the write current from the current sampling circuit 3001 can be increased,
Insufficient writing in the current sampling circuit 3001 can be eliminated. On the contrary, the write current to the source signal line 18 can be increased.

[1243] Note that in FIG. 285, FIG. 286, and the like,
Although the current output circuit 1222 is described as a modification of FIGS. 157 and 159, the present invention is not limited to this. For example, a differential configuration may be used in which a difference between currents flowing in two signal lines (one current is a bias current, the other current is a bias current + a signal (writing) current) is written in the current output circuit 1222. In the differential configuration, insufficient current writing from the current sampling circuit 3001 to the current output circuit 1222 does not occur. However, the current program line 30
Two 02 are required.

[1244] In addition, in FIG. 157 and FIG.
71, FIG. 277, FIG. 275, etc.
Bias current can be generated by adding a capacitor 19b for generating punch-through voltage to the six configurations. Therefore, the current flowing through the source signal line 18 can be increased in the black display state or the like.

In the configuration of FIG. 285, the output from the DA circuit (not shown) that converts digital image data into analog current is subjected to current sampling by the current sampling circuit 3001 and is arranged (formed) on the source signal line 18. Held in the current output circuit 1222 (capacitor 1
9). The held current is applied to the source signal line 18 in synchronization with the 1H clock (the current is absorbed from the source signal line 18) and sequentially written in the pixels 16 of each display screen 21. By adopting the above configuration, the operational amplifier described in FIG. 144 and the like becomes unnecessary, and the current mirror circuit described in FIG. 283 becomes unnecessary. Further, since the current output circuit 1222 is easily configured, it can be formed by a low temperature polysilicon technique or the like.

[1246] However, there is a problem. The operating frequency of the current sampling circuit 3001 is high, and the current output circuit 1222
This is because there is a shortage of writing to. To solve this, as shown in FIG. 286, two current output circuits (1222a and 1222b) and two current sampling circuits 3001 (3001a and 3001b) may be arranged (formed).

[1247] By forming two layers in this way, the first H
The current is applied from the current output circuit 1222a to the source signal line 18, and during that period, the current sampling circuit 30
01b is operated to cause the current output circuit 1222b to hold the write current. In the next 2H, the current output circuit 12
A current can be applied from 22b to the source signal line 18, and during that period, the current sampling circuit 3001a can be operated to cause the current output circuit 1222a to hold the write current. That is, the operation speed of the current sampling circuit 3001 can be halved. Note that the display screen may be divided into two display screens 21a and 21b as shown in FIG. 286 (the source signal line 18 is cut at the center of the screen).

Note that the direction in which the current output circuit 1222 described with reference to FIGS. 285 and 286 absorbs the program current Iw or discharges it depends on the pixel 16 configuration. That is, the current output circuit 12 is adapted to the pixel 16 configuration.
22 is set (formed).

In FIG. 286, the gate signal line 17b is shared by a plurality of signal lines as described with reference to FIG. 187.
That is, the block driving method is implemented. As mentioned above,
The present invention can be combined with other configurations described herein. Further, FIG. 287 shows a lighting control line 179.
A plurality of 1s are formed and a reverse bias voltage is applied. As described above, the present invention can be combined with other configurations described in this specification.

[1250] The EL display device does not require a backlight unlike a liquid crystal display device. Therefore, there is a feature that the module thickness can be reduced. The liquid crystal display device turns on a backlight to display an image. In addition, the power consumption of the backlight is 200 ~ for modules used in mobile phones.
It is as large as 300 mW. In comparison, the power consumption used by the EL display panel is as small as 5 to 10 mW. Therefore, when displaying an image, since the backlight is on, there is no difference in the power consumption of the module regardless of which image is displayed.

In the EL display device, there is a close relationship between the image display state and the power consumption. Power consumption is low in normal natural images. However, in white raster display, 3
It consumes ~ 4 times the current. Further, the current flowing through the module constantly changes depending on the display state of the image.

[1252] If the power supply circuit is configured to follow the white raster display and the image display state, the circuit configuration becomes very large. Also, the power supply capacity is increased. The present invention solves these problems and easily realizes the brightness control of the display screen 21.

[1253] FIG. 288 is an explanatory diagram of a display method of a mobile phone of the present invention as an example of an information display device. FIG. 288
(A) has shown the display screen 21 of a mobile telephone. The display screen 21b is a part for displaying the reception state of the antenna, the time, and the like. That is, it is an area in which necessary information is constantly displayed. Similarly, the display screen 21c is also an area in which necessary information such as operation icons is constantly displayed. Display screen 21
“A” is an area for displaying a menu, an image, and the like, and is an area where the displayed image constantly changes.

[1254] In FIG. 288, for ease of explanation, FIG.
It is assumed that the block display method described with reference to FIG. The display screen 21b has three blocks 19
The display screen 21c has three blocks 1
It corresponds to 981c. The display screen 21a corresponds to the remaining blocks 1981a. Therefore, the brightness of the image can be easily adjusted for each block 1981 by controlling the number of selected blocks 1981 and the like. Note that the display screens 21a, 2 are
Brightness adjustment of 1b, 21c, etc., is performed by referring to FIGS.
The block drive is not limited to the block drive described above. Needless to say, the sequential drive described with reference to FIGS. 84, 45, 46, etc. may be used. Even with sequential drive, by controlling the speed of the clock,
This is because the brightness adjustment on the display screen 21 can be easily realized for each part.

[1255] Since the display screens 21b and 21c are the portions which are constantly displayed, it is necessary to maintain a constant display screen brightness. Further, the current consumption is constant. However, it is preferable that the display screen 21a of FIG. 288 (a) controls the brightness of the image according to the type of the image. For example, when a television image is displayed on the display screen 21a and the entire screen suddenly changes to white display (white raster), a current suddenly flows from the power supply circuit to the module. This current may cause the module to generate heat, resulting in deterioration or failure. Note that blocks 1981a and 1 illustrated in FIG.
The 981b and 1981c can individually perform on / off processing (lighting / non-lighting processing), and the brightness of the image can be adjusted. This can be easily realized by controlling the lighting control line 1791.

[1256] Therefore, what kind of image is displayed on the display screen 21a is monitored, and when the power consumption area increases rapidly, the displayed image data is subjected to arithmetic processing or the like to reduce the overall brightness of the display screen 21a. Need to let. For example, when performing white raster display, the size of the image data of the white raster is halved, and the display brightness is reduced to ½. It should be noted that the brightness of the image is set in the non-display area 312 and the image display area 31 as described in FIG.
This is done by changing the ratio of 1. By doing so, the brightness of the image can be adjusted without changing the size of the image data. Of course, it goes without saying that it may be realized by changing the size of the image data.

[1257] FIG. 289 is a circuit for suppressing a change in power consumption due to image data. The frame (field) memory 2621 is divided into two areas (2621a and 2621b), each of which can hold image data of one screen. Frame memory 2621a and frame memory 26
21b are alternately selected. For example, when the image data is being read from the frame memory 2621a to the data conversion circuit 2623, the image data is written from the microcomputer (not shown) to the frame memory 2621b. Conversely, when image data is being read from the frame memory 2621b to the data conversion circuit 2623, the image data is being written to the frame memory 2621a from a microcomputer (not shown). For ease of explanation, it is assumed that the image data DATA (5: 0) is 6 bits (64 gradations) of D5 to D0.

[1258] The image data DATA (5: 0) is written in the frame memories 2621a and 2621b alternately.
The MSB DATA5 is counted by the counter circuit 2622. It is DATA5 that counts DATA5
That is, the number of image data having a bit of, that is, the number of image data having a maximum luminance of ½ or more is counted. Therefore, the larger the count value of the counter circuit 2622, the higher the brightness of the image, and the larger the power consumed by the module.

[1259] Now, the image data is stored in the frame memory 2621.
It is assumed that the data is written in a and is counted by the counter circuit 2622. At this time, the frame memory 26
The image data of 21b is read.

[1260] When the count value of the counter circuit 2622 is greater than or equal to a predetermined value (the predetermined value is configured to be variable by a microcomputer (not shown) or the like), the counter circuit 2
Reference numeral 622 controls the data conversion circuit 2623. This control is processing such as halving the value of the image data from the frame memory 2622 (shifting to the right by 1 bit). That is, the counter circuit counts image data of one screen (image data is written in the frame memory 2621a). Then, this image data is read out from the frame memory 2621a, and this image data is controlled.

[1261] Note that not only D5 but also DAT
It goes without saying that the feature extraction of the image can be more accurately performed by counting A (5: 4) or DATA (5: 3). By accurately performing the feature extraction, the brightness of the display screen 21a can be adjusted more appropriately.

[1262] When the image data has a large power consumption such as white raster, the data conversion circuit 2623 performs the image data conversion process to reduce the image data, and then the converted data is applied to the source driver 14. . If the image is processed frame by frame and the brightness of the display image is adjusted frame by frame, the image will blink (the bright screen and the dark screen are repeated, and the image is in a blinking state). This problem can be dealt with by performing a data conversion control of the data conversion circuit 2623 while delaying the image processing and considering the image change of a plurality of frames.

[1263] Note that in FIG. 289, the brightness of the display screen 21a is adjusted by converting the image data and applying it to the source driver 14. However, the present invention is not limited to this, and the block 1981a in FIG. It goes without saying that it may be realized by controlling the lighting time of. Hereinafter, this implementation will be described.

[1264] FIG. 290 is an explanatory diagram of the embodiment. The frame (field) memory 2681 has two areas (2
681a, 2681b), each of which is 1
It can hold the image data of the screen. Frame memory 268
1a and the frame memory 2681b are selected alternately. For example, when image data is being read from the frame memory 2681a to the source driver 14, image data is being written to the frame memory 2681b from a microcomputer (not shown). Conversely, the frame memory 268
When the image data is read from the source driver 1b to the source driver 14, the image data is written from the microcomputer (not shown) to the frame memory 2681a. The above items are the same as in FIG. 289.

[1265] DATA5 of MSB of image data DATA (5: 0) is counted by adder circuit 2682a.
This is for counting the number of pieces of image data having a maximum luminance of ½ or more, as in the embodiment of FIG. 289. Therefore, the larger the count value of the adder circuit 2682a, the more image data the image brightness is high.

[1266] The addition circuit (arithmetic processing circuit) 2682b is
The display screen 21 is divided into a plurality of blocks, and each block also processes the average luminance distribution. Further, the arithmetic processing circuit 2682c calculates the distribution state of image data having a predetermined brightness or higher and the distribution state of image data having a predetermined brightness or lower. That is, the adder circuit (arithmetic processing circuit) 2682 analyzes the average luminance distribution of the display screen 21, the distribution state of image data, and the like.

The gate driver control circuit 2683 accumulates the calculation result (processing result) from the calculation processing circuit 2682 over a plurality of frames and applies the ST data to the shift register 22 of the gate driver 12 or the ON / OFF data of the lighting control line 1791. Is sent.

[1268] For example, if the brightness of the screen is adjusted by the control of the shift register 22, it becomes as shown in FIG. To darken the image, the number of ST data applied to the shift register 22 is reduced as shown in FIG. Therefore, the ratio of the image display area 311 occupying the display screen 21 decreases and the image becomes dark. When the display screen 21 is relatively brightened, the width of the image display area 311 in FIG. 291 (b) is increased or the number of the image display areas 311 is increased. Further, when the display screen 21 is brightened, the width of the image display area 311 in FIG. 291 (c) is further increased or the number of the image display areas 311 is further increased. It should be noted that the above processing is performed by referring to FIG.
It is obvious that the selection processing of block 1981 can also be realized. Therefore, the description is omitted.

[1269] Also, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and FIG.
The number of one image display area 311 may be adjusted. That is, if it is a moving image, the number of image display areas 311 is reduced to eliminate moving image blur. In the case of a still image, the number of image display areas 311 is increased and the image display areas are dispersed on the display screen 21 in order to suppress the occurrence of flicker.

[1270] In FIG. 289, the number of pieces of image data having a predetermined brightness or higher is counted to control the brightness of the display screen 21. However, similar to FIG. 290, the characteristics of the image are extracted to determine the brightness of the display screen 21. May be changed. This embodiment is shown in FIG. It goes without saying that the embodiments of FIGS. 290 and 292 may be combined.

[1271] FIG. 292 is an explanatory diagram of the embodiment. The frame (field) memory 2621 has two areas (2
621a, 2621b), each of which is 1
It can hold the image data of the screen. Frame memory 262
1a and frame memory 2621b are selected alternately. For example, when image data is being read from the frame memory 2621a to the data conversion circuit 2692, image data is being written to the frame memory 2621b from a microcomputer (not shown). Conversely, the frame memory 2
When the image data is being read from the 621b to the data conversion circuit 2692, the image data is written from the microcomputer (not shown) to the frame memory 2621a.
The above items are the same as in FIG. 289 or FIG. 290.

[1272] DATA5 of the MSB of the image data DATA (5: 0) is counted by the adder circuit 2682a.
The larger the count value of the adder circuit 2682a, the more image data the image brightness is high. As in the previous case, the addition circuit (arithmetic processing circuit) 2682b is
1 is divided into a plurality of blocks, and the average luminance distribution is processed in each block. In addition, the arithmetic processing circuit 2682
In c, the distribution state of image data having a predetermined brightness or higher and the distribution state of image data having a predetermined brightness or lower are calculated. That is, the adder circuit (arithmetic processing circuit) 268
2 analyzes the average luminance distribution of the display screen 21, the distribution state of image data, and the like.

The data control circuit 2691 accumulates the calculation result (processing result) from the calculation processing circuit 2682 over a plurality of frames, controls the data conversion circuit 2692,
Convert image data.

For example, if the brightness of the screen is adjusted, the size of the image data obtained by bit-shifting the data is converted as in the case of FIG. 289. At the same time, the optimum gamma conversion process is performed as shown in FIG. 293 based on the analysis result of the image data.

[1275] FIG. 293 is a gamma table. The horizontal axis represents the gradation number, and the vertical axis represents the relative value of the display brightness. The dotted line in FIG. 293 is a linear case, and the solid line is a case where gradation collapse is generated in the black display area and the white display area. Further, the alternate long and short dash line indicates the case where gradation collapse occurs only in the black gradation part.

As described above, the characteristic of the image is extracted by the arithmetic processing circuit 2682, the gamma curve of the display image is selected based on the result, and the data table conversion is performed. Providing three or more types of gamma tables, select the most suitable one. Then, the converted image data is input to the source driver 14.

As described with reference to FIG. 291, when the image is darkened, the number of ST data applied to the shift register 22 is reduced as shown in FIG. 291 (a).
Therefore, the image display area 311 occupying the display screen 21
It becomes darker due to a decrease in the ratio. When the display screen 21 is relatively brightened, the image display area 311 in FIG.
Or the number of image display areas 311 is increased. Further, when the display screen 21 is brightened, the width of the image display area 311 in FIG. 291 (c) is further increased or the number of the image display areas 311 is further increased. In order to make the displayed image appear relatively bright with low power consumption, the maximum brightness of the display brightness is lowered, the minimum brightness is increased (that is, the contrast of the image is lowered), and the average brightness of the entire display is reduced. Should be small.

[1278] Also, whether the image data is a moving image or a still image is detected (moving image detection and ID processing are performed), and FIG.
The number of one image display area 311 may be adjusted. That is, if it is a moving image, the number of image display areas 311 is reduced to eliminate moving image blur. In the case of a still image, the number of image display areas 311 is increased and the image display areas are dispersed on the display screen 21 in order to suppress the occurrence of flicker.

[1279] In FIG. 288, the display screens are 21a and 2a.
Although the display brightness of the display screen 21a is changed by setting the three regions 1b and 21c, the present invention is not limited to this, and the display screens 21b and 21c may be changed.

Also, as shown in FIG. 294, display screens 21d and 21e may be provided at the edges of the display screen. The display screens 21d and 21e are displayed as simple frames (that is, pixel electrodes are formed, and dot patterns cannot be displayed). Therefore, the display screen 21d,
21e is a simple matrix-like display. That is, when a voltage is applied to the display screens 21d and 21e, the entire screen lights up.

[1281] As shown in FIG. 295, the lighting control line 1
When a voltage is applied to 791a, the EL film of the display screen 21d lights up. Further, when a voltage is applied to the lighting control line 1791b, the EL film of the display screen 21e lights up. The other configurations (1891, etc.) have been described above, and thus description thereof will be omitted.

As shown in FIG. 296, the smoothing film 71 is formed on the gate driver 12 formed by the polysilicon technique. A pixel electrode 48b made of the same material as the pixel electrode 48a is formed thereon, and an organic EL layer 47 is formed on the pixel electrode 48b. A cathode electrode (or an anode electrode) is formed on the organic EL layer 47. The display screens 21d and 21e are turned on by applying a voltage to the pixel electrode 48b.

[1283] In the above embodiments, the EL element 15 is R,
It is assumed that G and B are set, but the present invention is not limited to this.
For example, cyan, yellow, magenta, or any two colors may be used. Six colors of R, G, B, cyan, yellow, and magenta, or any four or more colors may be used. Further, it may be white monochromatic light, or white monochromatic light may be converted into RGB by a color filter. Further, it is not limited to the organic EL element, and may be an inorganic EL element.

In the liquid crystal display panel of the present invention or the display device using the same, it is preferable to integrate a plurality of gate drivers 12 and source drivers 14 (a plurality of types). By doing this, images that come in from any communication network, such as moving images and still images downloaded from mobile phone networks or wireless LANs, images that receive terrestrial TV broadcasting, etc.
Can be displayed without burdening the user. High-definition images are displayed by using a VGA-compatible 6-bit gate driver 12 and source driver 14, and Q is displayed if the definition is reduced.
Switch to VGA and use 1-bit gate driver 12 and source driver 14 for text data.
Separately, NTSC display driver (interlace,
Pseudo interlaced scanning), and it is also preferable to form a progressive display driver (non-interlaced). The gate driver 12 and the source driver 14 having these plural functions are formed of silicon chips,
It goes without saying that it may be mounted by COG technology or the like.

[1285] Note that although an active matrix display panel is described as an example in FIGS. 45 and 46, the invention is not limited to this. From the source driver 14 or the like, N times the predetermined current is applied to (source of) the source signal line 18. In addition, a plurality of pixel rows are simultaneously selected.
Then, a current is passed through the EL element only for a predetermined period,
The concept that no current flows during other periods can be applied to a simple matrix display panel.

[1286] Gate driver 12, source driver 14
In the case of one type, it is necessary to execute signal conversion processing by the MPU in order to display images with different definition. When a large number of gate drivers 12 and source drivers 14 other than the liquid crystal display panel are prepared, it is necessary to individually mount the ICs, which increases the cost and the mounting area. In addition to the gate driver 12 and the source driver 14, many circuits such as an image processing circuit may be integrated in the Si film on the display panel 82.

[1287] In addition, since the EL element has a large characteristic change in the initial stage of lighting, burning or the like is likely to occur. For this measure, after panel formation, for 20 hours to 150 hours,
It is preferable to carry out aging with white raster display and then ship as a product. In this aging, it is preferable to display with a brightness which is about 2 to 10 times higher than the predetermined display brightness.

In the present invention, the pixel configuration described with reference to FIGS. 85 and 87 will be mainly described with reference to the voltage program pixel configuration and the current program pixel configuration described with reference to FIGS. In the above, the signal is supplied and written from the source driver 14 in synchronization with the 1H period, but the present invention is not limited to this. For example, one frame or one field may be divided into a plurality of subframes (fields) and driven in combination with time division driving. Further, an area gradation method in which one pixel is divided into a plurality of pixels may be combined.

[1289] FIG. 21, FIG. 49, FIG. 50 to FIG. 53, FIG.
5, FIG. 60, FIG. 63, FIG. 66, FIG. 67, FIG. 69, FIG.
9, a driving (display) method using FIGS.
Although the drive circuit has been described, a semiconductor chip made of gallium arsenide, silicon, germanium or the like that realizes these technical ideas is also within the scope of the present invention. A display device, an information display device, and the like can be realized by mounting these semiconductor chips on a display panel.

[1290] FIG. 6B, FIG. 20, FIG. 76, and FIG.
As shown in FIG. 67, the terminal for applying the Vbb voltage in FIG.
Good image display can be realized by connecting to.

[1289] The items relating to the power supply voltage Vdd described with reference to FIGS. 185, 226, etc. are also applied to all pixel configurations, display panels, information display devices or driving methods of this specification. In addition, FIGS. 2 to 5 and FIGS.
33, FIG. 37, FIG. 38, FIG. 164, FIG. 169, FIG. 172
-FIG. 183, FIG. 225, FIG. 227-FIG. 229, FIG.
4, FIG. 237, FIG. 239 to FIG. 242, etc., needless to say, they are applied to all pixel configurations, driver arrangements, display panels, information display devices or driving methods in this specification.

[1292] Figs. 45, 46, 84, and 88 to 9
4, the driving method of the present invention described in FIGS. 116 to 141,
Drive circuit and FIGS. 163, 166, 169, and 172
-By combining the method or structure for applying a reverse bias voltage to the EL element 15 described with reference to FIG. 183 and the like, a more characteristic effect is exhibited. In addition, these are shown in FIG. 6, FIG. 19, FIG. 85 to FIG. 87, FIG.
It goes without saying that it can be applied to the pixel configurations described in FIGS. 9 to 183, FIGS. 244 to 247, and FIG. 251. In addition, with these configurations, FIGS.
0, FIG. 63 to FIG. 65, FIG. 68, FIG. 70, FIG. 71, FIG.
It is not necessary to explain that the above can be realized. 23 to 3
It goes without saying that it is also effective to combine it with the configuration of 2 sides and 3 sides free. Also, using these techniques,
2 to 5, FIG. 23 to FIG. 33, FIG. 37, FIG. 38, FIG.
4, FIG. 169, FIG. 172-FIG. 183, FIG. 225, FIG.
7 to 229, 234, 237, 239 to 24
It goes without saying that the present invention can be applied to a display panel such as 2 and the like, an information display device or a driving method.

Also, the method or configuration for applying a reverse bias voltage to the EL element 15 described with reference to FIGS. 163, 169, 172 to 183, etc. is also shown in FIGS.
62, 66, 67, 72 to 76, 79 to 83, 85 to 87, 155 to 162, 16
5, FIG. 169, FIG. 172-FIG. 184, FIG.
It goes without saying that the present invention can be applied to the pixel configuration or the array configuration shown in FIG. Further, with these configurations, FIGS. 48 to 51, 53 to 60, and 63 to 6
It is not necessary to explain that 5, FIG. 68, FIG. 70, FIG. 71, FIG. It goes without saying that it is also effective to combine with the three-side free configuration shown in FIGS. 23 to 32, 187 to 200, and FIGS. 206 to 209. In particular, the three-side free configuration is effective when the pixel is manufactured using the amorphous silicon technology. Further, in the panel formed by the amorphous silicon technique, it is not possible to perform process control of the characteristic variation of the TFT element, so it is preferable to carry out the current driving of the present invention.

[1294] Furthermore, by using these techniques, as shown in FIG.
5, FIG. 23 to FIG. 33, FIG. 37, FIG. 38, FIG. 164, FIG.
69, FIG. 172-FIG. 183, FIG. 225, FIG. 227-FIG.
It goes without saying that the present invention can be applied to the display panel, information display device or driving method of FIG. 29, FIG. 234, FIG. 237, FIG. 239 to FIG.

[1295] FIGS. 168, 169, and 170 to 183.
The pixel configuration described in the above, or the pixel configuration or array configuration in the driving method is not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 may be replaced with a liquid crystal layer or a light modulation layer such as PLZT or LED. For example, in the case of liquid crystal, TN (Twisted N
electronic), IPS (In-Plane Switch)
ching), FLC (Ferroelectric)
Liquid Crystal), OCB (Optic)
ally Compensatory Bend), S
TN (Super Twisted Nemati
c), VA (Vertically Aligne)
d), ECB (Electrically Control)
rolled birefringence) and HA
N (Hybrid Aligned Nematic)
Mode, DSM mode (dynamic scattering mode), and the like.
In particular, since DSM can be optically modulated by the applied current,
Good matching with the present invention.

[1296] Also, the switching element is a TFT
It is not limited to. Further, it goes without saying that the present invention is applied to all pixel configurations, driver arrangements, display panels, information display devices or driving methods in this specification.

1, FIG. 6, FIG. 19, FIG. 28 to FIG. 32, FIG. 49, FIG. 62, FIG. 66, FIG. 67, FIG. 72 to FIG.
9-83, FIGS. 85-87, 95, 100-100.
6, FIG. 109 to FIG. 115, FIG. 155 to FIG. 162, FIG.
5, FIG. 169, FIG. 172-FIG. 184, FIG.
6, FIG. 258 to FIG. 267, FIG. 269, FIG. 270, and FIG.
2, FIG. 273, FIG. 275 to FIG. 280, the pixel configuration or the array configuration, etc. are not limited to the EL display panel. For example, it can be applied to a liquid crystal display panel. In that case, the EL element 15 is replaced by a liquid crystal layer, PLZ.
It may be replaced with a light modulation layer such as T or LED. Also,
The switching element is not limited to the TFT as described above with reference to FIG. 226 and the like.

[1298] Further, FIGS. 3, 10 to 12, 23, 26, 28 to 32, 164, 232, and 23.
4, FIG. 235, FIG. 239 to FIG. 242, FIG. 268, FIG.
8, FIG. 296 and the like, the configuration, device, and method are not limited to those using an EL display panel. For example, PD
It can also be applied to those using a P display panel, a PLZT display panel, a liquid crystal display panel, and the like.

By using the manufacturing method shown in FIGS. 13 to 16, 20 and 43, FIG. 1, FIG. 6 and FIGS.
19, 39, 49, 62, 66, 67, 72 to 76, 79 to 83, 85 to 87, 9
5, FIG. 100 to FIG. 106, FIG. 109 to FIG. 115, FIG.
5 to 162, 165, 169, 172 to 18
4, FIG. 244 to FIG. 256, FIG. 258 to FIG. 267, FIG.
9, FIG. 270, FIG. 272, FIG. 273, FIG.
A display panel having a pixel configuration such as 0 or an array configuration can be easily manufactured. Further, an information display device can be configured using these. Needless to say, the configurations or structures shown in FIGS. 7 to 12 and 17 can be applied to the display panel or display device of the present invention.

[1300] In addition, in the structure of the display panel of FIGS. 101 to 106, 109, and 110 or the driving method thereof, the pixel structure is as shown in FIGS. 1, 6, 10 to 12, 19, and 3.
9, FIG. 49, FIG. 62, FIG. 66, FIG. 67, FIG.
6, FIG. 79 to FIG. 83, FIG. 85 to FIG. 87, FIG. 95, FIG.
0-106, FIGS. 109-115, FIGS. 155-162,
165, 169, 172 to 184, and 244 to
256, 258 to 267, 269, 270,
It goes without saying that any of the configurations shown in FIGS. 272, 273, 275 to 280, etc. can be applied.

[1301] FIGS. 1, 6, 19, 49, 62, 157 to 159, 162, 184, 81, and 1
60, Fig. 161, Fig. 66, Fig. 85, Fig. 86, Fig. 72 to Fig. 75, Fig. 83, Fig. 67, Fig. 76, Fig. 80, Fig. 82, Fig. 7
9, FIG. 183, FIG. 169, FIG. 172-FIG. 182, FIG.
7, FIG. 165, FIG. 155, FIG. 156, FIGS.
7, FIG. 251, FIG. 39, FIG. 248, FIG.
0, FIG. 252 to FIG. 256, FIG. 249, FIG. 250, FIG.
8 to FIG. 267, FIG. 269, FIG. 100 to FIG. 106, FIG.
9 to 115, 270, 273, 272, and 95.
The pixel configuration or array configuration of FIG.
31, FIG. 233, FIG. 238, FIG. 295, FIG. 288, FIG.
It goes without saying that the present invention can be applied to information display devices such as 94.

[1302] Further, FIGS. 6, 19, 49, 62, and 1
57, FIG. 158, FIG. 159, FIG. 162, FIG. 184, FIG.
1, FIG. 160, FIG. 161, FIG. 66, FIG. 85, FIG. 86, FIG. 72 to FIG. 75, FIG. 83, FIG. 67, FIG. 76, FIG. 80, FIG.
2, FIG. 79, FIG. 183, FIG. 169, FIG.
2, FIG. 87, FIG. 165, FIG. 155, FIG. 156, FIG. 244
-FIG. 247, FIG. 251, FIG. 248, FIG.
0, FIG. 252 to FIG. 256, FIG. 249, FIG. 250, FIG.
8 to FIG. 267, FIG. 269, FIG. 100, FIG.
104, 110, 109, 105, 106,
111 to 115, 270, 10 to 12, and 2
73, the pixel configuration or the array configuration of FIG. 272, etc.
FIG. 164, FIG. 232, FIG. 235, FIG. 234, FIG.
3, FIG. 26, FIG. 239, FIG. 240, FIG. 241, FIG.
2, FIGS. 28 to 32, FIGS. 210 to 217, and 230,
231, 233, 238, 218 to 223,
251, 248, 275 to 280, 252 to
256, 249, 250, 258 to 267,
269, FIG. 100, FIG. 1, FIG. 101 to FIG. 104, FIG.
10, FIG. 109, FIG. 105, FIG. 106, FIG.
It goes without saying that it can be adopted in FIG. 15, FIG. 270, FIG. 273, FIG. 272, and FIG.

[1303] Further, the configuration of the source driver in FIGS. 281-283, and the current output circuit 1222 in FIGS. 284-287.
1, FIG. 19, FIG. 49, FIG. 62, FIG. 157, FIG. 158, FIG. 159, FIG. 162, FIG.
84, FIG. 81, FIG. 160, FIG. 161, FIG. 66, FIG.
86, 72 to 75, 83, 67, 76, 80, 82, 79, 183, 169, 172.
~ 182, Fig. 87, Fig. 165, Fig. 155, Fig. 156, Fig. 244-247, Fig. 251, Fig. 248, Fig. 275-Fig.
80, FIG. 252 to FIG. 256, FIG. 249, FIG. 250, FIG.
58 to FIG. 267, FIG. 269, FIG. 100, FIG.
~ FIG. 104, FIG. 110, FIG. 109, FIG. 105, FIG.
6, FIG. 111 to FIG. 115, FIG. 270, FIG. 10 to FIG.
Needless to say, it can be applied to FIGS. 273 and 272. Similarly, FIGS. 107, 108, 110, and 25.
3, FIG. 255, FIG. 256, FIG. 260, FIG. 261, FIG.
It goes without saying that the present invention can also be applied to the driving method or the data processing method shown in FIGS. 3, 264, 289 to 293. 101 to 106, 109, and 110.
The same applies to the driving method and the pixel configuration described in the above. Further, it goes without saying that an information display device or the like can be configured using these.

[1304] The manufacturing method shown in Figs. 13 to 16, 43, 44, etc. is not limited to the manufacturing method of the EL display panel. For example, it can be applied to a manufacturing method of a liquid crystal display panel. Further, it is needless to say that the configurations or methods shown in FIGS. 23 to 32 are not limited to the EL display panel and can be applied to an LED display panel, a liquid crystal display panel, and the like. 49, 48, 53-.
59, 63 to 65, 68, 70, 71, 85, 50, 51, 60, 288, 294,
The same applies to the display method shown in FIG.

[1305] The technical idea described in the embodiments of the present invention can be applied to a video camera, a projector, a stereoscopic television, a projection television, and the like. Further, it is also applicable to a viewfinder, a mobile phone monitor, a PHS, a personal digital assistant and its monitor, a digital camera and its monitor. It can also be applied to electrophotographic systems, head-mounted displays, direct-view monitor displays, notebook personal computers, video cameras, electronic still cameras. Further, it is also applicable to a monitor of an automatic cash drawer, a public telephone, a videophone, a personal computer, a wristwatch and its display device. Further, it goes without saying that the present invention can be applied or expanded to a display monitor of a home electric appliance, a pocket game device and its monitor, a backlight for a display panel, or a lighting device for home or business use. It is preferable that the lighting device is configured so that the color temperature can be changed. In this, the color temperature can be changed by forming RGB pixels in a stripe shape or a dot matrix shape and adjusting the current flowing through these. Further, the present invention can be applied to display devices for advertisements or posters, RGB traffic lights, alarm indicators, etc.

[1306] The organic EL panel is also effective as the light source of the scanner. The object is irradiated with light using the RGB dot matrix as a light source to read an image. Of course, it is needless to say that it may be a single color. Further, the matrix is not limited to the active matrix, and a simple matrix may be used. If the color temperature can be adjusted, the image reading accuracy will be improved.

[1307] The organic EL display device is also effective as a backlight of a liquid crystal display device. It is possible to change the color temperature and easily adjust the brightness by forming the RGB pixels of the EL display device (backlight) in a stripe shape or a dot matrix shape and adjusting the current flowing through them. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured. It is also effective as a backlight for a field-sequential liquid crystal display panel that alternately scans R, G, and B lights. Further, even if the backlight blinks, by inserting black, it can be used as a backlight for a liquid crystal display panel for displaying moving images.

[1308]

EFFECTS OF THE INVENTION The display panel, display device, and the like of the present invention have high image quality, good moving image display performance, low power consumption, and low cost.
A characteristic effect is exhibited according to each structure such as high brightness.

[1309] Note that by using the present invention, a low power consumption information display device or the like can be formed, so that power consumption is not performed.
In addition, since the size and weight can be reduced, resources are not consumed. Further, even a high-definition display panel can be sufficiently dealt with.
Therefore, it is friendly to the global environment and space environment.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a display panel of the present invention.

FIG. 2 is a sectional view of a display device of the present invention.

FIG. 3 is a sectional view of a display panel of the present invention.

FIG. 4 is a sectional view of a display device of the present invention.

FIG. 5 is a sectional view of a display device of the present invention.

FIG. 6 is a circuit configuration diagram of a display panel of the present invention.

FIG. 7 is an explanatory diagram of a display panel of the present invention.

FIG. 8 is an explanatory diagram of a display panel of the present invention.

FIG. 9 is an explanatory diagram of a display panel of the present invention.

FIG. 10 is an explanatory diagram of a display panel of the present invention.

FIG. 11 is an explanatory diagram of a display panel of the present invention.

FIG. 12 is an explanatory diagram of a display panel of the present invention.

FIG. 13 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 14 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 15 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 16 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 17 is an explanatory diagram of a display panel of the present invention.

FIG. 18 is an explanatory diagram of a display panel of the present invention.

FIG. 19 is an explanatory diagram of a display panel of the present invention.

FIG. 20 is an explanatory diagram of a display panel of the present invention.

FIG. 21 is a circuit configuration diagram of a display device of the present invention.

FIG. 22 is an explanatory diagram of a display device of the present invention.

FIG. 23 is an explanatory diagram of a display panel of the present invention.

FIG. 24 is an explanatory diagram of a display panel of the present invention.

FIG. 25 is an explanatory diagram of a display panel of the present invention.

FIG. 26 is an explanatory diagram of a display panel of the present invention.

FIG. 27 is an explanatory diagram of a display panel of the present invention.

FIG. 28 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 29 is an explanatory diagram of a display panel of the present invention.

FIG. 30 is an explanatory diagram of a display panel of the present invention.

FIG. 31 is an explanatory diagram of a display panel of the present invention.

FIG. 32 is an explanatory diagram of a display panel of the present invention.

FIG. 33 is an explanatory diagram of a display device of the present invention.

FIG. 34 is an explanatory diagram of a display panel of the present invention.

FIG. 35 is an explanatory diagram of a display panel of the present invention.

FIG. 36 is an explanatory diagram of a display panel of the present invention.

FIG. 37 is an explanatory diagram of a display device of the present invention.

FIG. 38 is a cross-sectional view of a display device of the present invention.

FIG. 39 is an explanatory diagram of a display panel of the present invention.

FIG. 40 is an explanatory diagram of a display panel of the present invention.

FIG. 41 is an explanatory view of the manufacturing method of the display panel of the present invention.

42 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 43 is an explanatory diagram of a method for manufacturing a display panel of the present invention.

FIG. 44 is an explanatory view of the manufacturing method of the display panel of the present invention.

FIG. 45 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 46 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 47 is an explanatory diagram of a display panel of the present invention.

FIG. 48 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 49 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 50 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 51 is an explanatory diagram of a display panel driving method of the present invention.

52 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 53 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 54 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 55 is a circuit block diagram of a display panel of the present invention.

FIG. 56 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 57 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 58 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 59 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 60 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 61 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 62 is an explanatory diagram of a display panel of the present invention.

FIG. 63 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 64 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 65 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 66 is a circuit block diagram of a display panel of the present invention.

FIG. 67 is a circuit block diagram of a display panel of the present invention.

FIG. 68 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 69 is a circuit block diagram of a display panel of the present invention.

FIG. 70 is an explanatory diagram of a display panel driving method of the present invention.

71 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 72 is an explanatory diagram of a display panel of the present invention.

FIG. 73 is an explanatory diagram of a display panel of the present invention.

FIG. 74 is an explanatory diagram of a display panel of the present invention.

FIG. 75 is an explanatory diagram of a display panel of the present invention.

FIG. 76 is an explanatory diagram of a display panel of the present invention.

77 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 78 is an explanatory diagram of a display panel of the present invention.

FIG. 79 is an explanatory diagram of a display panel of the present invention.

FIG. 80 is an explanatory diagram of a display panel of the present invention.

FIG. 81 is an explanatory diagram of a display panel of the present invention.

FIG. 82 is an explanatory diagram of a display panel of the present invention.

FIG. 83 is an explanatory diagram of a display panel of the present invention.

FIG. 84 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 85 is an explanatory diagram of a display panel of the present invention.

FIG. 86 is an explanatory diagram of a display panel of the present invention

FIG. 87 is an explanatory diagram of a display panel of the present invention.

FIG. 88 is an explanatory diagram of a display panel driving method of the present invention.

89 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 90 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 91 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 92 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 93 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 94 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 95 is an explanatory diagram of a display panel of the present invention.

FIG. 96 is an explanatory diagram of a display panel of the present invention

FIG. 97 is an explanatory diagram of a display panel of the present invention

FIG. 98 is an explanatory diagram of a display panel of the present invention.

99 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 100 is an explanatory diagram of a display panel of the present invention

101 is an explanatory diagram of a display panel of the present invention. FIG.

102 is an explanatory diagram of a display panel of the present invention. FIG.

103 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 104 is an explanatory diagram of a display panel of the present invention

FIG. 105 is an explanatory diagram of a display panel of the present invention

FIG. 106 is an explanatory diagram of a display panel of the present invention

FIG. 107 is an explanatory diagram of a display panel of the present invention

FIG. 108 is an explanatory diagram of a display panel of the present invention.

FIG. 109 is an explanatory diagram of a display panel of the present invention

110 is an explanatory diagram of a display panel of the present invention. FIG.

111 is an explanatory diagram of a display panel of the present invention. FIG.

112 is an explanatory diagram of a display panel of the present invention. FIG.

113 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 114 is an explanatory diagram of a display panel of the present invention.

FIG. 115 is an explanatory diagram of a display panel of the present invention.

FIG. 116 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 117 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 118 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 119 is an explanatory diagram of a display panel driving method of the present invention.

120 is an explanatory diagram of a display panel driving circuit of the present invention. FIG.

FIG. 121 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 122 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 123 is an explanatory diagram of a drive circuit of a display panel of the present invention.

FIG. 124 is an explanatory diagram of a drive circuit of a display panel of the present invention.

FIG. 125 is an explanatory diagram of a display panel driving method of the present invention.

126 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 127 is an explanatory diagram of a display panel driving method of the present invention.

128 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 129 is an explanatory diagram of a method for driving a display panel of the present invention.

FIG. 130 is an explanatory diagram of a display panel driving method of the present invention.

131 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 132 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 133 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 134 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 135 is an explanatory diagram of a display panel driving method of the present invention

FIG. 136 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 137 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 138 is an explanatory diagram of a display panel driving method of the present invention;

FIG. 139 is an explanatory diagram of a driving method of a display panel of the present invention.

FIG. 140 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 141 is an explanatory diagram of a display panel driving method of the present invention.

142 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 143 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 144 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 145 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 146 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 147 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 148 is an explanatory diagram of a display panel of the present invention.

FIG. 149 is an explanatory diagram of a display panel of the present invention.

FIG. 150 is an explanatory diagram of a display panel of the present invention

151 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 152 is an explanatory diagram of a display panel of the present invention

FIG. 153 is an explanatory diagram of a display panel of the present invention

FIG. 154 is an explanatory diagram of a display panel of the present invention.

155 is an explanatory diagram of a pixel configuration of a display panel of the present invention. FIG.

FIG. 156 is an explanatory diagram of a pixel configuration of a display panel of the present invention.

FIG. 157 is an explanatory diagram of a display panel of the present invention

FIG. 158 is an explanatory diagram of a display panel of the present invention.

FIG. 159 is an explanatory diagram of a display panel of the present invention

FIG. 160 is an explanatory diagram of a display panel of the present invention

FIG. 161 is an explanatory diagram of a display panel of the present invention.

162 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 163 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 164 is an explanatory diagram of a display device of the present invention.

FIG. 165 is an explanatory diagram of a pixel configuration of a display panel of the present invention.

FIG. 166 is an explanatory diagram of a display panel of the present invention.

FIG. 167 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 168 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 169 is an explanatory diagram of a display panel of the present invention.

FIG. 170 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 171 is an explanatory diagram of a display panel of the present invention

FIG. 172 is an explanatory diagram of a display panel of the present invention.

FIG. 173 is an explanatory diagram of a display panel of the present invention

FIG. 174 is an explanatory diagram of a display panel of the present invention.

FIG. 175 is an explanatory diagram of a display panel of the present invention.

FIG. 176 is an explanatory diagram of a display panel of the present invention.

FIG. 177 is an explanatory diagram of a display panel of the present invention

FIG. 178 is an explanatory diagram of a display panel of the present invention.

FIG. 179 is an explanatory diagram of a display panel of the present invention

180 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 181 is an explanatory diagram of a display panel of the present invention

FIG. 182 is an explanatory diagram of a display panel of the present invention.

FIG. 183 is an explanatory diagram of a display panel of the present invention.

FIG. 184 is an explanatory diagram of a display panel of the present invention.

FIG. 185 is an explanatory diagram of a display panel of the present invention.

FIG. 186 is an explanatory diagram of a display panel of the present invention.

FIG. 187 is an explanatory diagram of a display panel of the present invention

FIG. 188 is an explanatory diagram of a display panel of the present invention.

FIG. 189 is an explanatory diagram of a display panel of the present invention

190 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 191 is an explanatory diagram of a display panel of the present invention

FIG. 192 is an explanatory diagram of a display panel of the present invention.

FIG. 193 is an explanatory diagram of a display panel of the present invention

FIG. 194 is an explanatory diagram of a display panel of the present invention.

FIG. 195 is an explanatory diagram of a display panel of the present invention.

FIG. 196 is an explanatory diagram of a display panel of the present invention.

FIG. 197 is an explanatory diagram of a display panel of the present invention

FIG. 198 is an explanatory diagram of a display panel of the present invention.

FIG. 199 is an explanatory diagram of a display panel of the present invention

FIG. 200 is an explanatory diagram of a display panel of the present invention

FIG. 201 is an explanatory diagram of a display panel of the present invention.

202 is an explanatory diagram of a display panel of the present invention. FIG.

203 is an explanatory diagram of a display panel of the invention. FIG.

FIG. 204 is an explanatory diagram of a display panel of the present invention

FIG. 205 is an explanatory diagram of a display panel of the present invention

FIG. 206 is an explanatory diagram of a display panel of the present invention

FIG. 207 is an explanatory diagram of a display panel of the present invention

208 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 209 is an explanatory diagram of a display panel of the present invention.

FIG. 210 is an explanatory diagram of a display panel driving method of the present invention.

211 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 212 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 213 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 214 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 215 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 216 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 217 is an explanatory diagram of a driving method of a display device of the present invention.

FIG. 218 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 219 is an explanatory diagram of a driving method of a display panel of the present invention.

220 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 221 is an explanatory diagram of a display panel driving method of the present invention.

222 is an explanatory diagram of a display panel driving method of the present invention. FIG.

FIG. 223 is an explanatory diagram of a display panel driving method of the present invention.

FIG. 224 is an explanatory diagram of an information display device of the present invention.

FIG. 225 is an explanatory diagram of an information display device of the present invention.

FIG. 226 is an explanatory diagram of a display panel of the present invention.

FIG. 227 is a configuration diagram of a display device of the invention.

FIG. 228 is a configuration diagram of a display device of the invention.

FIG. 229 is an explanatory diagram of a display device of the present invention

FIG. 230 is an explanatory diagram of a display panel of the present invention.

FIG. 231 is an explanatory diagram of an information display device of the present invention.

FIG. 232 is a plan view of the information display device of the present invention.

FIG. 233 is an explanatory diagram of an information display device of the present invention.

FIG. 234 is an explanatory diagram of a data transmission method of a display device of the present invention.

FIG. 235 is an explanatory diagram of a data transmission method of a display device of the present invention.

FIG. 236 is an explanatory diagram of a data transmission method of the display device of the present invention.

FIG. 237 is an explanatory diagram of an information display device of the present invention.

FIG. 238 is an explanatory diagram of an information display device of the present invention.

FIG. 239 is a sectional view of the viewfinder of the present invention.

FIG. 240 is a perspective view of the video camera of the present invention.

FIG. 241 is a perspective view of the electronic camera of the present invention.

FIG. 242 is an explanatory diagram of a television of the present invention

[FIG. 243] An explanatory diagram of a television of the present invention

FIG. 244 is an explanatory diagram of a display panel of the present invention

FIG. 245 is an explanatory diagram of a display panel of the present invention

[FIG. 246] An explanatory diagram of a display panel of the present invention

FIG. 247 is an explanatory diagram of a display panel of the present invention

[FIG. 248] An explanatory diagram of a display panel of the present invention

FIG. 249 is an explanatory diagram of a display panel of the present invention

FIG. 250 is an explanatory diagram of a display panel of the present invention

FIG. 251 is an explanatory diagram of a display panel unit of the present invention.

FIG. 252 is an explanatory diagram of a display panel of the present invention.

[FIG. 253] An explanatory diagram of a display panel of the present invention

FIG. 254 is an explanatory diagram of a display panel of the present invention.

255 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 256 is an explanatory diagram of a display panel of the present invention.

FIG. 257 is an explanatory diagram of a display panel of the present invention

FIG. 258 is an explanatory diagram of a display panel of the present invention.

FIG. 259 is an explanatory diagram of a display panel of the present invention

260 is an explanatory diagram of a display panel of the present invention. FIG.

[FIG. 261] An explanatory diagram of a display panel of the present invention

FIG. 262 is an explanatory diagram of a display panel of the present invention.

FIG. 263 is an explanatory diagram of a display panel of the present invention.

FIG. 264 is an explanatory diagram of a display panel of the present invention.

FIG. 265 is an explanatory diagram of a display panel of the present invention.

FIG. 266 is an explanatory diagram of a display panel of the present invention.

FIG. 267 is an explanatory diagram of a display panel of the present invention

FIG. 268 is an explanatory diagram of a display panel of the present invention.

FIG. 269 is an explanatory diagram of a display panel of the present invention

FIG. 270 is an explanatory diagram of a display panel of the present invention.

271 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 272 is an explanatory diagram of a display panel of the present invention

[FIG. 273] An explanatory diagram of a display panel of the present invention

[FIG. 274] An explanatory diagram of a display panel of the present invention

FIG. 275 is an explanatory diagram of a display panel of the present invention

[FIG. 276] An explanatory diagram of a display panel of the present invention

FIG. 277 is an explanatory diagram of a display panel of the present invention

FIG. 278 is an explanatory diagram of a display panel of the present invention.

FIG. 279 is an explanatory diagram of a display panel of the present invention

[FIG. 280] An explanatory diagram of a display panel of the present invention

FIG. 281 is an explanatory diagram of a display panel of the present invention

282 is an explanatory diagram of a display panel of the present invention. FIG.

FIG. 283 is an explanatory diagram of a display panel of the present invention.

FIG. 284 is an explanatory diagram of a display panel of the present invention.

FIG. 285 is an explanatory diagram of a display panel of the present invention.

FIG. 286 is an explanatory diagram of a display panel of the present invention

FIG. 287 is an explanatory diagram of a display panel of the present invention.

FIG. 288 is an explanatory diagram of a display panel of the present invention

FIG. 289 is an explanatory diagram of a display panel of the present invention

FIG. 290 is an explanatory diagram of a display panel of the present invention

FIG. 291 is an explanatory diagram of a display panel of the present invention

FIG. 292 is an explanatory diagram of a display panel of the present invention.

FIG. 293 is an explanatory diagram of a display panel of the present invention

FIG. 294 is an explanatory diagram of a display panel of the present invention

FIG. 295 is an explanatory diagram of a display panel of the present invention

FIG. 296 is an explanatory diagram of a display panel of the present invention.

FIG. 297 is an explanatory diagram of a display panel driving method of the present invention;

298 is an explanatory diagram of a pixel configuration of a display panel of the present invention. FIG.

FIG. 299 is an explanatory diagram of a pixel configuration of a display panel of the present invention.

300 is an explanatory diagram of a pixel structure of a display panel of the present invention

FIG. 301 is an explanatory diagram of a conventional display panel

FIG. 302 is a circuit configuration diagram of a conventional display panel.

[Explanation of symbols]

11 TFT 12 Gate Driver 14 Source Driver 14c 1 Chip Driver IC 15 EL Element 16 Pixel 17 Gate Signal Line 18 Source Signal Line 19 Capacitor 20 Current Supply Line 21 Display Screen 22 Shift Register 23 Inverter Circuit 24 Output Gate 41 Sealing Lid 43 Recess 44 Convex Part 45 Sealant 46 Reflective Film 47 Organic EL Layer 48 Pixel Electrode 49 Array Substrate 50 λ / 4 Plate 51 Cathode Wiring 52 Contact Hole 53 Cathode Electrode 54 Polarizing Plate 55 Drying Agent 61, 62 Connection Terminal 63 Anode Wiring 71 Smoothing Film 72 Transparent electrode 73 Sealing film 74 Circular polarizing plate 81 Edge protection film 82 Display panel 91 Light-shielding film 92 Low resistance wiring 101 Control IC 102 Power supply IC 103 Printed board 104 Flexible board 105 Data signal 141 Error diffusion controller Roller 151 Built-in display memory 152 Arithmetic memory 153 Arithmetic circuit 154 Buffer circuit 191 Antenna 192 Numeric keypad 193 Housing 194 Key 201 Deplexer 202 LNA 203 LO buffer 204 Downconverter 205 Upconverter 206 PA pre-driver 207 PA 230 Laser irradiation spot 241 Glass substrate 242 Positioning marker 251 Convex portion 252 Concavo-convex portion (embossed portion) 311 Image display area 312 Non-display area 351 Counter circuit 352 Luminance memory 353 CPU 354 Frame memory (field memory) 355 Switching circuit 391 Write pixel row 392 Holding pixel row 401 Voltage source 402 current source 403 power supply switching means 404 parasitic capacitance 451 body 452 eyepiece ring 453 magnifying lens 454 positive lens 461 Photographing lens 462 Video camera body 463 Storage section 464 Eyepiece cover 465 Display mode selection switch 466 Viewfinder 467 Cover 468 Support point 471 Shutter 472 Digital camera body 481 Outer frame 482 Fixing member 483 Leg 484 Leg mounting portion 491 Wall 492 Fixing metal fitting 493 Protective film (protective plate) 501 Scanning area 601 ENBL terminal 602 OR circuit 851 Shutter 852 Observation glasses (switching means) 861 Prism 862 Optical coupling material 871 Writing pixel row 1001 Flying capacitor 1221 Voltage output circuit 1222 Current output circuit 1223 Switch circuit ( Analog switch) 1224 Operational amplifier (output buffer) 1225 Adjustment volume 1226 DA circuit (digital-analog conversion means) 1227 Output Transistor (FET) 1228 Resistor 1271 Output stage circuit 1321 Signal wiring 1751 Pixel contact part 1761 Protective film 1771 Mask 1772 Contact hole 1781 Spacer 1791 Lighting control line 1891 Lighting control driver circuit 1981 Block 2041 Speaker 2043 Function switch (FSW) 2044 Microphone 2045 Mirror 2046 Display panel 2111 Reverse bias control line 2271 Transistor 2341 Gate waveform 2471 Dummy pixel row 2561 Insulating film 2621,2681 Frame (field) memory 2622 Counter circuit 2623 Data conversion circuit 2682 Addition circuit (arithmetic processing circuit) 2683 Gate driver control circuit 2691 data Control circuit 2692 Data conversion circuit 2751 Bias resistor (electronic resistor 2752 switching transistor (selection switch) 2753 parent transistor 2754 child transistor 2791 light (trajectory) 2801 refraction sheet (plate, film) 2802 refraction section 2861 transparent film 2862 roller 2863 concavo-convex section (concave section) 2871 convex section 2881 Metal mask 2901 Press plate (press contact means, transfer means) 2902 Light (UV light, visible light) 3001 Current sampling circuit 3002 Current program line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623F 623L 623U 624 624B 631 631A 632 632A 641 641D 641R 642 / 642D 642D 30 3/30 H H05B 33/02 H05B 33/02 33/04 33/04 33/10 33/10 33/12 33/12 B 33/14 33/14 AF term (reference) 3K007 AB02 AB04 AB05 AB11 AB17 AB18 BA06 BB06 BB07 DB03 EA00 EB00 FA01 GA02 GA04 5C080 AA06 BB05 CC03 DD06 DD26 DD27 DD30 EE28 EE32. DA09 DA13 DB01 DB04 EA04 EA07 ED01 FA01 FA02 FB01 FB20 GA10

Claims (20)

[Claims] 1. An active matrix EL display device, characterized in that at least one of an upper side and a lower side of a display region is formed or arranged with a pixel row that does not emit light or blocks emitted light. EL display device. 2. A driving method of an EL display device, comprising a first operation of selecting a plurality of pixel rows at the same time and applying the same image data to the selected pixel rows, and selecting positions of the pixel rows sequentially. A method of driving an EL display device, which comprises performing a second operation of causing a cyst and a third operation of selecting a pixel row formed or arranged in a region other than an image display region when selecting a final pixel row. . 3. A pixel arranged in a matrix, a gate driver circuit for selecting the pixel, and a current output type source driver circuit for outputting image data to be applied to the pixel. The EL display device, wherein the pixel driver rows are sequentially selected, and when the gate driver circuit does not select the pixel rows, the source driver circuit outputs a write current in black display. 4. A pixel arranged in a matrix, a gate driver circuit for selecting the pixel, a current output type source driver circuit for outputting image data to be applied to the pixel, and a pixel formed outside the display area. A second pixel, the gate driver circuit sequentially selects pixel rows, and when the gate driver circuit does not select a pixel row in a display area, the source driver circuit is formed outside the display area. EL device characterized by writing an output current to a selected pixel or absorbing a current from the pixel.
Display device. 5. Pixels arranged in a matrix, a gate driver circuit for selecting the pixels, a current output type source driver circuit for outputting image data applied to the pixels, and a gate driver circuit formed outside the display area. An EL display device comprising: a second pixel, wherein a pixel electrode of the second pixel is electrically short-circuited with a cathode electrode or an anode electrode of an EL element. 6. Pixels arranged in a matrix, a gate driver circuit for selecting the pixels, a current output type source driver circuit for outputting image data applied to the pixels, and a gate driver circuit formed outside the display area. An EL display device comprising: a second pixel, wherein the second pixel is not formed with an EL element or has a light shielding unit for shielding light emitted from the EL element. 7. An EL display panel having pixels arranged in a matrix and second pixels formed outside a display region, a down converter, an up converter, a receiver, and a speaker. An information display device characterized by: 8. An image memory, a counter circuit for counting the number of image data having a predetermined size or more, and a data read from the image memory being small when the count value of the counter circuit is a predetermined value or more. An EL display device comprising a data conversion circuit for converting data. 9. A pixel formed in a matrix, an EL element formed in the pixel, a driving transistor element for supplying a current to the EL element, and a current from the driving transistor element to the EL element. A switching element that controls the flow, a gate driver circuit that sequentially selects the pixels, a counter circuit that counts the number of image data of a predetermined size or more, and a count value of the counter circuit is a predetermined value or more, An EL display device, comprising: a control circuit for controlling the switching element. 10. Pixels formed in a matrix, EL elements formed in the pixels, drive transistor elements for supplying a current to the EL elements, a gate driver circuit for sequentially selecting the pixels, and the gates. An EL display device comprising: an electrode formed on a driver circuit; and an EL film formed on the electrode. 11. An active matrix EL display device, comprising: an EL element formed in each pixel; a drive transistor element for supplying a current to the EL element; and a potential of a gate terminal of the drive transistor element for a predetermined period. A first capacitor for holding, a second capacitor connected to one terminal of the first capacitor, and a control signal line connected to another terminal of the second capacitor, An EL display device characterized in that the potential of the gate terminal is shifted by a voltage applied to a control signal line. 12. An active matrix EL display device, comprising: an EL element formed in each pixel, a drive transistor element for supplying a current to the EL element, a switching transistor element, and a gate terminal of the drive transistor element. And a second capacitor arranged between the gate terminal of the driving transistor element and the drain terminal of the switching transistor element, the first capacitor being arranged between the voltage terminal and the voltage terminal, and the selection of the switching element, An EL display device, wherein a drain terminal of the switching transistor element and a source terminal of the driving transistor are arranged so as to be short-circuited. 13. An active matrix EL display device, comprising: a first EL element that emits red light, a second EL element that emits green light, a third EL element that emits blue light, and the first EL element. A first drive transistor element for supplying a current to the element, a second drive transistor element for supplying a current to the second EL element, and a third drive transistor element for supplying a current to the third EL element A first switching element arranged between the first driving transistor element and the first EL element, and a second switching element arranged between the second driving transistor element and the second EL element. A switching element, a third switching element arranged between the third driving transistor element and the third EL element, the first driving transistor element and the second driving transistor. First controlling a first gate signal line at the same time select the Njisuta element and the third driving transistor element, on and off of said first switching element
And a second control signal line for controlling ON / OFF of the second switching element.
And a third control signal line for controlling ON / OFF of the third switching element.
And a control signal line of the EL display device. 14. A method of driving an active matrix EL display device, comprising: at least one of a cycle of turning on and off a first EL element that emits red light and a time of turning on the second EL element that emits green light. Of at least one of the ON / OFF cycle and the ON time of the third EL element that emits blue light, and at least one of the ON / OFF cycle of the third EL element that emits blue light are different from other EL elements. A method for driving an EL display device, comprising: 15. An EL display device, comprising: an EL element formed in each pixel, a drive transistor element that supplies a current to the EL element, an EL film formed in the pixel, and an EL film formed on the EL film. The light bending means comprises: a formed electrode; a sealing film for preventing water from flowing into the EL film; and a light bending means formed on the sealing film so as to correspond to the pixel shape. Is an EL display device formed or arranged in a hexagonal shape. 16. An EL display device, comprising pixels arranged in a matrix, a current output circuit formed or arranged on each source signal line for outputting a current applied to the pixel, and digital image data analog. An EL display device comprising: an analog current conversion circuit for converting into a current; and a current sampling circuit for sampling a current output from the analog current conversion circuit and holding the current in the current output circuit. 17. A method of manufacturing an EL display device, comprising: a first step of forming an EL film and a sealing film for preventing water from flowing into the EL film on a substrate; A second step of applying a transparent resin on the film; a third step of pressing the roller having an uneven shape corresponding to the shape of the light bending means against the transparent resin to transfer the uneven shape; A method for manufacturing an EL display device, which comprises performing a fourth step of curing a transparent resin. 18. A method of manufacturing an EL display device, comprising: a first step of forming an EL film and a sealing film for preventing water from flowing into the EL film on a substrate; Second, forming a convex portion corresponding to the pixel shape on the film
And a third step of applying a transparent resin on the convex portion and the sealing film, and a fourth step of curing the transparent resin. 19. A method of manufacturing an EL display device, comprising: a first step of forming an EL film and a sealing film for preventing water from flowing into the EL film on a substrate; A second step of disposing a mask having an opening corresponding to the pixel shape at a predetermined distance from the film, and a third step of depositing a transparent material on the sealing film through the mask. A method for manufacturing an EL display device, comprising: 20. A method for manufacturing an EL display device, comprising: a first step of forming an EL film and a sealing film for preventing water from flowing into the EL film on a substrate; A second step of applying a transparent resin on the film; a third step of pressing the transparent resin with a press plate having an uneven shape corresponding to the shape of the light bending means; and the transparent step through the press plate. A method for manufacturing an EL display device, which comprises performing a fourth step of irradiating a resin with light to cure the transparent resin.