JP2003037496A - Signal generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal generation circuit that can reduce the number of tank circuits and their externally mounted components, when the signal generation circuit generates, e.g. a plurality of local signals. SOLUTION: The circuit consists of an LC type voltage-controlled oscillator 6A, a phase comparator 7, a charge pump 8, and a loop filter 9 form a phase- locked loop. A phase shifter 21 receives an output signal oscillated from the LC voltage-controlled oscillator 6A to generate a first signal S5 and a second signal S6, whose phases are shifted to each other by 90-degrees. Switches SW11, SW12 extract the signals, as required. A frequency divider type phase shifter 22 receives the oscillation output signal from the LC type voltage-controlled oscillator 6A to decrease the frequency of the oscillation output signal to a half and to produce a third signal S7 and a fourth signal S8, whose phases are shifted with to other by 90-degrees. Switches SW13, SW14 extract the signals, as required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generation circuit used in a quadrature demodulator or the like and capable of generating a plurality of types of signals.

[0002]

2. Description of the Related Art For example, CDMA (code division multiple access) is known as one of multiple access systems in wireless communication such as mobile communication. For example, in the mobile terminal for this CDMA system, as shown in FIG. 6, a quadrature demodulator 1 that demodulates a baseband signal based on an intermediate frequency signal (IF signal) down-converted by a high frequency amplifier, The quadrature demodulator 1 is provided with a local signal generation circuit 2 for supplying a local signal having a predetermined frequency.

As shown in FIG. 6, the quadrature demodulator 1 is composed of a frequency division type phase shifter 3 and two mixers 4 and 5. The frequency division type phase shifter 3 reduces the frequency of the output signal S1 of the local signal generation circuit 2 to ½ and outputs the first local signals S2 and S3 whose phase difference is different from each other by 90 ° (π / 2). It is generated and output to mixers 4 and 5. The mixer 4 includes an intermediate frequency signal S4 and a local signal S2.
I signal is generated based on and. The mixer 5 generates a Q signal based on the intermediate frequency signal S4 and the local signal S3.

As shown in FIG. 6, the local signal generating circuit 2 includes an LC type voltage controlled oscillator 6, a phase comparator 7, a charge pump 8 and a loop filter 9 to form a phase locked loop. It has become. The LC type voltage controlled oscillator 6 includes two tank circuits 10 and 11 in order to obtain output signals S1 having a plurality of frequencies (two in this example). In addition, the tank circuits 10 and 11 have the switches SW1 and SW2 or the switch S depending on the oscillation frequency.
It can be selected by W3 and SW4.

In the tank circuit 10, a coil L and a capacitor C1 are connected in parallel, and a capacitor C and a varicap CV are connected in series to this. Also, for fine adjustment of the oscillation frequency, the switches SW5 and SW are connected to the capacitor C1.
A capacitor C2 is connected in parallel via 6. The capacity of the variable cap CV can be changed by the output of the loop filter 9.

Similarly, in the tank circuit 11, a coil L'and a capacitor C1 'are connected in parallel, and a capacitor C'and a varicap CV' are connected in series. Further, for fine adjustment of the oscillation frequency, the capacitor C1 'is connected in parallel via the switches SW7 and SW8.
2'is connected. The capacitance of the variable cap CV 'can be changed by the output of the loop filter 9.

In FIG. 6, the right side portion of the broken line is composed of a semiconductor integrated circuit, and the left side portion thereof is externally attached to the semiconductor integrated circuit. That is, the quadrature phase shifter 1
And the LC voltage controlled oscillator 6, the phase comparator 7, and the charge pump 8 in the local signal generation circuit 2,
It is configured as a semiconductor integrated circuit. Further, the loop filter 9 and the tank circuits 10 and 11 of the local signal generating circuit 2 are adapted to be externally attached to the semiconductor integrated circuit.

Next, the operation of the local signal generating circuit 2 having such a configuration will be described. In this local signal generation circuit 2, the reference input signal is supplied to the phase comparator 7 according to the desired output signal S1 of the LC type voltage controlled oscillator 6, and the tank circuit 10 or the tank circuit 1 is correspondingly supplied.
1 is selected. Now, it is assumed that the tank circuit 10 is selected.

In this case, the LC type voltage controlled oscillator 6
Oscillates at a frequency determined by the inductance value and the electrostatic capacitance value of the tank circuit 10, and this oscillation output becomes the output signal S1. The phase comparator 7 outputs an up signal or a down signal according to the phase difference between the oscillation output and the reference input signal. The charge pump 8 outputs a signal according to the up signal and the down signal, and this output is filtered by the loop filter 9. The output of the loop filter 9 is
It is applied to the varicap CV, which changes the capacitance of the varicap CV.

By such an operation, feedback control is performed so that the frequency of the output signal S1 of the LC type voltage controlled oscillator 6 matches the frequency of the reference input signal input to the phase comparator 7. Next, another configuration example of the conventional local signal generation circuit will be described with reference to FIG.

This local signal generating circuit 2A has two LC type voltage controlled oscillators 6A and 6B as shown in FIG.
And two tank circuits 10 and 11 corresponding thereto, the output signals S 1 and S 2 having different frequencies of the LC type voltage controlled oscillators 6 A and 6 B are selectively output by the switches SW 9 and SW 10 to perform the frequency division type phase. It is adapted to be supplied to the container 3.

The structure of the other parts is the same as that shown in FIG. 6, and the description thereof is omitted. Further, in FIG. 7, the right side portion of the broken line is configured by a semiconductor integrated circuit, and the left side portion is externally attached to the semiconductor integrated circuit.

[0013]

As described above, the conventional local signal generating circuit employs the following configuration in order to obtain two local signals. That is, the first configuration has two tank circuits 10, as shown in FIG.
11 is prepared and selected by a switch to generate a local signal of a desired frequency. The second configuration has two LC type voltage controlled oscillators 6 as shown in FIG.
A and 6B and corresponding tank circuits 10 and 11 are prepared, and these are selected by a switch to generate a local signal of a desired frequency.

Further, in order to finely adjust the oscillation frequency, the tank circuits 10 and 11 include capacitors C2 and C2 'and switches SW5 to SW8. Therefore, in the conventional local signal generating circuit, for example, when it is desired to obtain three local signals, the number of tank circuits and LC type voltage controlled oscillators increases correspondingly. Further, as shown in FIGS. 6 and 7, the tank circuit is externally attached, which causes a disadvantage that the number of externally attached parts increases.

Therefore, in view of the above points, an object of the present invention is to provide a signal generation circuit capable of reducing the tank circuit and the like and reducing the number of external parts thereof when, for example, a plurality of local signals are obtained. is there.

[0016]

In order to solve the above problems and achieve the object of the present invention, each of the inventions described in claims 1 to 3 is configured as follows. That is, the invention according to claim 1 receives an oscillation output signal of the LC-type voltage-controlled oscillator, a phase-locked loop including a phase comparator and a loop filter, and the oscillation output signals of the LC-type voltage-controlled oscillator, and their phases are mutually different. A phaser that generates and outputs a first signal and a second signal that are deviated by 90 ° and an oscillation output signal of the LC type voltage controlled oscillator are received, and the frequency of the oscillation output signal is set to 1
A frequency division type phase shifter for generating and outputting a third signal and a fourth signal whose phases are shifted from each other by 90 °, the first signal and the second signal, and Selection means for selecting the third signal and the fourth signal.

The invention described in claim 2 is the same as claim 1.
In the signal generation circuit according to the item (1), the LC type voltage controlled oscillator includes an LC tank circuit, the LC type voltage controlled oscillator excluding the LC tank circuit, the phase comparator, the phase shifter, and the frequency division type. The phase shifter and the phase shifter are composed of a single semiconductor integrated circuit, and the LC tank circuit is an external component of the semiconductor integrated circuit.

Further, in the invention described in claim 3, in the signal generating circuit according to claim 2, the varicap included in the LC tank circuit is a unit voltage applied to the varicap and a ratio of change in capacitance thereof. Is characterized by using a large one. As described above, in the present invention, in addition to the phase locked loop including the LC type voltage controlled oscillator, the phase comparator, and the loop filter, the phase shifter, the frequency division type shifter, and the selection unit are provided.

Therefore, according to the present invention, for example, when three local signals are obtained, the number of tank circuits can be reduced to one, and when the tank circuit is external, the number of external parts is reduced. Can be significantly reduced.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION The configuration of an embodiment of a signal generating circuit of the present invention will be described below with reference to FIG. The local signal generation circuit 2B according to the embodiment of the present invention is shown in FIG.
As shown in, it is used in combination with the quadrature demodulator 1A.

The quadrature demodulator 1A includes a mixer 4 and a mixer 5. The mixers 4 and 5 have a switch S.
When W11 and S12 are closed, they are connected to a phase shifter 21 described later, and when switches SW13 and SW14 are closed, they are connected to a frequency divider type phase shifter 22 described later. That is, when the phase shifter 21 and the mixers 4 and 5 are connected, the mixer 4 shifts the intermediate frequency signal S4 and the phase shifter 21.
I signal is generated and output based on the output S5 of
Generates and outputs a Q signal based on the intermediate frequency signal S4 and the output S6 of the phase shifter 21. On the other hand, the frequency division type phase shifter 22
And the mixers 4 and 5 are connected, the mixer 4 generates and outputs the I signal based on the intermediate frequency signal S4 and the output S7 of the frequency division type phase shifter 22, and the mixer 5 outputs the intermediate frequency signal S4.
And a Q signal is generated and output based on the output S8 of the frequency division type phase shifter 22.

The signal generating circuit 2B, as shown in FIG.
A phase-locked loop (P is composed of an LC type voltage controlled oscillator 6A, a phase comparator 7, a charge pump 8 and a loop filter 9).
In addition to LL), the phase shifter 21, the frequency division type phase shifter 22, and the switches SW11 to SW14 are included. As shown in FIG. 1, the LC type voltage controlled oscillator 6A includes a tank circuit 1
Includes 0A. This tank circuit 10A has a coil L
And capacitor C1 are connected in parallel, and capacitor C
And the variable cap CV are connected in series.

The capacitance of the varicap CV can be changed by the output of the loop filter 9. As the varicap CV, a unit voltage applied to the varicap CV and a capacitance change ratio thereof are large. This is to make the range of the oscillation output of the LC type voltage controlled oscillator 6A wider than in the usual case.

The phase shifter 21 is an LC type voltage controlled oscillator 6A.
The first signal S5 and the second signal S6 whose phases are deviated from each other by 90 ° are generated and output. In addition, the first and second signals S5 and S6 generated by the phase shifter 21 are generated by the switch SW11,
The signals are supplied to the mixers 4 and 5 of the quadrature demodulator 1A via the SW12.

The phase shifter 21 is specifically constituted by an RC-CR type phase shifter as shown in FIG. That is, the phase shifter 21 includes an input terminal 23 and output terminals 24 and 25, as shown in FIG. The capacitor C11 and the resistor R1 are connected in series between the input terminal 23 and the ground, and the common connection portion of the capacitor 11 and the resistor R1 is connected to the output terminal 24. Also, the resistance R2
And the capacitor C12 are connected in series between the input terminal 23 and the ground, and the common connection portion of the resistor 2 and the capacitor 12 is connected to the output terminal 25.

The frequency division type phase shifter 22 receives the output signal S1 of the LC type voltage controlled oscillator 6, divides the frequency of the output signal S1 to reduce the frequency to 1/2, and the phases thereof are 90 ° (π). / 2) The third signal S7 and the fourth signal S8 which are deviated are generated and output. In addition, the third and fourth signals S7 and S generated by the frequency division type phase shifter 22.
8 is supplied to the mixers 4 and 5 of the quadrature demodulator 1A via the switches SW13 and SW14.

The frequency division type phase shifter 22, as shown in FIG.
D flip-flop (hereinafter referred to as DFF) 26 and DF
F27 and F27 are connected in series, and the output of the DFF 27 is fed back to the input side of the DFF 26. More specifically, the input terminal D and the inverting input terminal DN of the DFF 26 are connected to the output terminal Q and the inverting output terminal QN of the DFF 27. The output signal S1 of the LC type voltage controlled oscillator 6 and an inverted signal obtained by inverting the output signal S1 are supplied to the clock terminal CLK and the inverted clock terminal CLKN of the DFFs 26 and 27 (see FIG. 5).

The output terminal Q and the inverting output terminal QN of the DFF 26 are connected to the corresponding input terminal D and the inverting input terminal DN of the DFF 27. The outputs Q1 and Q1N of the output terminal Q of the DFF 26 and the inverting output terminal QN are output as a third signal S7, and the outputs Q2 and Q2N of the output terminal Q of the DFF 27 and the inverting output terminal QN are output to the fourth signal S7.
It is designed to output as 8.

The frequency division type phase shifter 22 having such a configuration.
FIG. 5 shows an example of the waveform of each part of. Next, the DFF 26 and the DFF 27 shown in FIG. 3 are composed of the circuit shown in FIG. That is, this circuit is composed of N-type MOS transistors Q1 to Q7 and resistors R3 and R4.

More specifically, the MOS transistor Q
1 and Q2 form a differential pair, and a differential input signal is supplied to each gate of the differential pair. MOS
The sources of the transistors Q1 and Q2 are commonly connected, and the common connection portion is grounded via the MOS transistor Q3 and the MOS transistor Q4. The output signal S1 of the LC type voltage controlled oscillator 6A is applied to the gate of the MOS transistor Q3, and the bias voltage is applied to the gate of the MOS transistor Q4.

The drain of the MOS transistor Q1 is connected to the drain of the MOS transistor Q5 and the gate of the MOS transistor Q6, and an inverted output signal can be taken out. Furthermore, MOS
The drain of the transistor Q2 is a MOS transistor Q
5 and the drain of the MOS transistor Q6, and a non-inverted output signal can be taken out.

The MOS transistors Q5 and Q6 form a differential pair, their sources are commonly connected, and their common connection is grounded via the MOS transistor Q7 and the MOS transistor Q4. An inverted signal obtained by inverting the output signal S1 of the LC type voltage controlled oscillator 6A is applied to the gate of the MOS transistor Q7.

In the embodiment, as shown in FIG. 1, the components on the right side of the broken line are composed of a single semiconductor integrated circuit, and the components on the left side are externally attached to the semiconductor integrated circuit. It is like this. That is, the quadrature type phase shifter 1A, the LC type voltage controlled oscillator 6A of the local signal generation circuit 2B, the phase comparator 7, the charge pump 8,
The phase shifter 21 and the frequency division type phase shifter 22 are configured as a semiconductor integrated circuit on a single semiconductor substrate. On the other hand, the loop filter 9 and the tank circuit 10A of the local signal generating circuit 2B are externally attached to the semiconductor integrated circuit.

Next, an operation example of the embodiment having such a configuration will be described with reference to the drawings. Below,
A case will be described in which this embodiment is applied to a communication terminal capable of performing communication by selecting one of three different communication standards (communication methods). What are these three communication standards?
S Cellular (personal communication system cellular),
CDMA cellular and AMPS (advanced mobile pho
ne system).

Therefore, in this case, the local signal generating circuit 2B to the quadrature demodulator 1A according to each communication standard.
Different frequencies are required for the signals supplied to the mixers 4 and 5. That is, each frequency is P
210.38 [MHz] in case of CS cellular, CDM
110.00 [MHz] for A-cell, AMPS
In the case of, it becomes 85.38 [MHz].

First, the frequency of the mixers 4 and 5 is 21
When supplying a signal composed of 0.38 [MHz],
The switches SW11 and SW12 are closed, and the phase comparator 7 is supplied with a reference input signal having a frequency of 210.38 [MHz]. As a result, the LC type voltage controlled oscillator 6A oscillates at a frequency determined by the inductance value and the electrostatic capacitance value of the tank circuit 10A, and its frequency range is 170.76 [MHz] to 220 [MHz], which is wider than usual. Has become. This is the Varicap CV
This is because the unit voltage to be applied and the one having a large ratio of change in capacitance are used.

The phase comparator 7 outputs an up signal or a down signal according to the phase difference between the oscillation output of the LC type voltage controlled oscillator 6A and the reference input signal. The charge pump 8 outputs a signal according to the up signal and the down signal, and this output is filtered by the loop filter 9. The output of the loop filter 9 is given to the varicap CV, which changes the capacitance of the varicap CV.

By such a series of operations, feedback control is performed so that the frequency of the output signal S1 of the LC type voltage controlled oscillator 6A matches the frequency of the reference input signal input to the phase comparator 7. The output signal S1 of the LC type voltage controlled oscillator 6A thus obtained is supplied to the phase shifter 21. The phase shifter 21 receives the output signal S1, generates a first signal S5 and a second signal S6 whose phases are deviated from each other by 90 °, and outputs them to the corresponding mixers 4 and 5. The mixer 4 receives the intermediate frequency signal S4
And an I signal based on the first signal S5 and its output, and the mixer 5 outputs the intermediate frequency signal S4 and its second signal S4.
A Q signal is generated based on 6 and output.

Next, for the mixers 4 and 5, the frequency is 11
When supplying a signal composed of 0.00 [MHz],
The switches SW13 and SW14 are closed, and the phase comparator 7 has a frequency of 110.00 [MHz].
A reference input signal of 220.00 [MHz], which is twice that of the above, is supplied. In this case, the operation is the same as in the above case, and the LC type voltage controlled oscillator 6A outputs a frequency of 22
An output signal S1 of 0.00 [MHz] is obtained, and this output signal S1 is supplied to the frequency division type phase shifter 22.

The frequency division type phase shifter 22 divides the output signal S1 to reduce the frequency to 1/2, ie, 110.00 [MHz], and at the same time, shifts the phases thereof by 90 ° (π / 2) from each other. 3 signal S7 and fourth signal S8 are generated and output to the corresponding mixers 4, 5. The mixer 4 generates and outputs an I signal based on the intermediate frequency signal S4 and its third signal S7, and the mixer 5 generates and outputs a Q signal based on the intermediate frequency signal S4 and its fourth signal S8. To do.

Further, the frequency is 8 for the mixers 4 and 5.
When supplying a signal consisting of 5.38 [MHz],
The switches SW7 and SW8 are closed, and the phase comparator 7 is supplied with a reference input signal having a frequency of 170.76 [MHz], which is twice the frequency of 85.38 [MHz]. In this case, the operation is the same as in the above case, and L
From the C-type voltage controlled oscillator 6A, the frequency is 170.76.
An output signal S1 of [MHz] is obtained, and this output signal S1
Are supplied to the frequency division type phase shifter 22.

The frequency division type phase shifter 22 frequency-divides the output signal S1 to reduce the frequency to 1/2, which is 85.38 [MHz], and at the same time, the phases thereof are deviated from each other by 90 ° (π / 2). 3 signal S7 and fourth signal S8 are generated and output to the corresponding mixers 4, 5. The mixer 4 generates an I signal based on the intermediate frequency signal S4 and its third signal S7, and the mixer 5 generates the intermediate signal S4 and its fourth signal S4.
The Q signal is generated based on 8 and output.

As described above, in this embodiment,
In addition to the phase locked loop including the LC type voltage controlled oscillator 6A, the phase comparator 7, the charge pump 8, and the loop filter 9, the phase shifter 21, the frequency division type shifter 22, and the switch S
W11 to SW14 are provided. Therefore, according to this embodiment, when three local signals are obtained as described above, the number of tank circuits 10A can be reduced to one, and the number of externally attached components can be significantly reduced.

[0044]

As described above, according to the present invention,
For example, when three local signals are obtained, the number of tank circuits can be reduced to one, and when the tank circuit is external, the number of external parts can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a signal generation circuit of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of the phase shifter shown in FIG.

FIG. 3 is a block diagram showing a configuration of the frequency division type phase shifter shown in FIG.

FIG. 4 is a circuit diagram showing a specific configuration of the DFF shown in FIG.

FIG. 5 is a waveform chart showing an example of waveforms of respective parts of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional circuit.

FIG. 7 is a block diagram showing another configuration of a conventional circuit.

[Simple explanation of symbols]

SW11 to SW14 switches (selection means) 1A Quadrature demodulator 2B local signal generator 4,5 mixer 6A LC type voltage controlled oscillator 7 Phase comparator 8 Charge pump 9 loop filter 10A tank circuit

Claims (3)

[Claims] 1. A phase-locked loop including an LC-type voltage-controlled oscillator, a phase comparator, and a loop filter; and a first phase-shifted loop that receives an oscillation output signal of the LC-type voltage-controlled oscillator and is 90 ° out of phase with each other. And a phase shifter for generating and outputting the second signal and the second output signal, and receiving the oscillation output signal of the LC type voltage controlled oscillator, lowering the frequency of the oscillation output signal to ½, and the phases thereof being 90 ° to each other. A frequency division type phase shifter for generating and outputting a deviated third signal and a fourth signal, the first signal and the second signal, the third signal and the fourth signal A signal generation circuit comprising: a selection unit for selecting. 2. The LC type voltage controlled oscillator includes an LC tank circuit, the LC type voltage controlled oscillator excluding the LC tank circuit, the phase comparator, the phase shifter, and the frequency division type phase shifter. 2. The signal generating circuit according to claim 1, wherein is formed of a single semiconductor integrated circuit, and the LC tank circuit is an external component of the semiconductor integrated circuit. 3. The varicap included in the LC tank circuit has a large ratio of unit voltage applied to the varicap and its capacitance change. Signal generation circuit.