JP2003037484A - Signal processor, and laser driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processor, which can suppress ripples of pulse width in a generated modulation signal, and a laser driver. SOLUTION: An LVDS receiving circuit 10 is equipped with a differential comparator 12, to which a current control circuit 14 for setting an operation current is connected and also a differential signal is to be inputted, and the differential output signal on plus side is inputted into the plus input side of a bistable circuit 24, with their start and down components being extracted with a plus-side output circuit 16 and a transition output circuit 20, and the differential output signal on negative side is inputted into the negative input side of the bistable circuit 24, with their start and down components extracted with a negative-side output circuit 18 and a transition output circuit 22, and in the bistable circuit 24, a pulse signal without ripples in duty ratio is generated, and a signal, whose pulse width is adjusted with a pulse width adjusting circuit 26 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device and a laser driving device, and more particularly to a driving device for a laser light source such as a surface emitting laser used in an image forming apparatus such as laser xerography. The present invention relates to a signal processing device that transmits a modulation signal of a surface emitting laser using a low voltage differential transmitter such as LVDS, and a laser driving device.

[0002]

2. Description of the Related Art Conventionally, LVDS (Low Voltage Differential S / S) using a dedicated IC for high-speed transmission and EMC countermeasures.
ignaling: Low voltage differential transmission) is used to transmit signals. For high-speed transmission and EMC countermeasures, application of driving a laser light source by transmitting a signal by LVDS to a laser driving device of an image forming apparatus that forms an image with a laser beam such as laser xerography is considered. .

For example, a laser light source used in an image forming apparatus such as laser xerography is an edge emitting type, and the number of beams per chip is as small as 1 to 4, and LV is used for signal transmission.
The use of DS did not directly increase costs.

By the way, recently, application to laser xerography using a surface emitting laser has been studied. Since the surface emitting laser can easily emit a large number of light beams, the resolution can be easily improved without sacrificing the drawing speed by simultaneously modulating and scanning a large number of light beams.

However, if a large number of modulated signals are transmitted by LVDS for such an application, the LVDS IC cost increases in proportion to the number of beams. As a countermeasure against this, an LVDS transmitter circuit (driver) is built into the IC that creates the modulation signal.
Increasing the cost has been suppressed by incorporating a LVDS receiver circuit on the laser drive IC side.

However, since the number of channels is large even in a low power consumption LVDS, the power allowable loss of the IC may be exceeded when the number of beams increases. Therefore, when the LVDS is built in, it is necessary to drive while suppressing power consumption. In this case, the transmission frequency of the LVDS changes depending on the printing speed, the number of beams, the resolution, etc. in the case of an image forming apparatus such as laser xerography. Therefore, if one laser driving IC is required to support all modulation speeds, the fastest modulation speed must be obtained. Since the power consumption and the speed are in a reciprocal relationship, increasing the modulation speed increases the power consumption of the LVDS. Therefore, when designing a circuit with limited power consumption, it is necessary to reduce the number of channels of the essential laser drive circuit.

When the application is limited to the reduced number of channels, the cost is increased due to the use of a plurality of laser driving ICs in order to apply to a large number of channels.
The use of wiring leads to longer wiring and sacrifices modulation characteristics. Therefore, it is desirable that the operating current of the LVDS can be externally set to a level at which the response required for actual modulation can be secured. Such a method of controlling the operating current externally has been conventionally implemented by a programmable operational amplifier.

FIG. 16 shows L from National Semiconductors.
As shown in the application example (A) using M146 and the internal circuit diagram (B), the current of the differential stage can be set from the outside. In this circuit, the operating current of the differential circuit can be adjusted by changing the value of Rset. Similarly to this, the receiving section of the LVDS is basically a differential circuit, and the current consumption can be controlled from the outside by a similar method. An interface circuit shown in FIG. 17 is known as a circuit example on the receiving side of LVDS (see Japanese Patent Laid-Open No. 9-74340).

In order to simulate the interface circuit of FIG. 17, the present inventor simulated the influence of a change in current consumption on a transmission signal by using the equivalent circuit shown in FIG. 18, and the results are shown in FIGS. It was shown to. FIG. 19 shows
20 shows the case where the current to the differential stage formed by the transistors M103 and M104 is set to 2 mA by controlling the current flowing through the current source 100 in the circuit diagram of FIG.
Shows the waveform when set to 0.6 mA.

The circuit on the receiving side of the LVDS of FIG. 17 is shown in FIG.
This can be expressed by the conceptual block diagram shown in FIG. LV
The input signals of the DS are shown as input + and input-, which are inverted signals with a duty of 50%, and these input signals are input to the differential comparator 120. Differential comparator 1
At 20, the comparison signal of the input + and input-input signals is output, and the + side output circuit 122 that receives the comparison signal as an input signal outputs the + side signal (pulse signal).

The differential comparator 120 includes transistors M101, M102, M103, M104, M105, which will be described later.
The positive side output circuit 122 includes transistors M109, M11, which will be described later.
0, M113, M114.

In the circuit of FIG. 18, the transistor M10
5, M106, M107, M108, M109, M11
The source of 0 is one of the power sources IAC and the power sources BT1 and BT2.
Is connected to the negative side of. The gate and drain of the transistor M106 and the gate of M108 are commonly connected, and the gate and drain of the transistor M105 and M1 are connected.
The gate side of 07 is commonly connected. Transistor M1
The drain of 08 is connected to the drain of the transistor M105, and the drain of the transistor M107 is connected to the drain of the transistor M106. Transistor M1
The gate of 09 is connected to the drain of the transistor M105, and the drain is connected to the drain of the transistor M113. The gate of the transistor M110 is connected to the drain of the transistor M106, and the drain is connected to the drain of the transistor M114.

Transistors M101, M102, M11
The sources of M3 and M114 are connected to the positive side of the power source BT1. The gate and drain of the transistor M114 are connected to the gate of the transistor M113, and the gate and drain of the transistor M102 and the drain M
The gate of 101 is connected to the other side of the power supply IAC. The sources of the transistors M103 and M104 are commonly connected, and the drain of the transistor M104 is the transistor M104.
The drain of the transistor M103 is connected to the drain of the transistor M105. The gate of the transistor M104 is connected to the plus side of the power source BT2 via the resistor RA, and the transistor M10
The gate of 3 is connected to the plus side of the power source BT2 via the resistor RB.

A connection point OUTP_X between the drain of the transistor M113 and the drain of the transistor M109 is connected to the output point OUTP_Y via a plurality of inverters.

FIGS. 19A and 20A show a signal waveform at the gate terminal INM_Z of the transistor M104 (that is, the negative side input of LVDS) and a signal waveform at the gate terminal INP_Z of the transistor M103 (that is, LVDS). (+ Side input) and two signal waveforms are shown in an overlapping manner. This signal waveform shows the case where the duty is 50% and the amplitude is 200 mV. 19B and 20B show signal waveforms at the connection point OUTP_X (that is, output waveforms of the LVDS receiving circuit), and FIGS.
In (C), the signal waveform at the output point OUTP_Y (that is, the output signal waveform after the waveform shaping by the four inverter stages) is shown.

As can be seen from FIGS. 19 and 20,
When the current of the differential stage increases, the response speed becomes faster, and the duty of the pulse signal approaches 50% of the duty of the signal waveforms of the input signals INP_Z and INM_Z.

However, even if 2 mA is applied to the differential stage, the signal at the output point OUTP_Y has a duty of 50.
It deviates greatly from%. That is, it is not easy to match the duty between the input and the output of the receiving circuit.
Further, since the duty changes depending on the current of the differential stage, it is difficult to match the input / output pulse widths of the receiving circuit.

The reason why the pulse widths of the input and output circuits of the receiving circuit do not match is that the LVDS is applied to a normal digital circuit, and here the accuracy of the pulse width between the input and output is not necessarily important. . In the specification sheet of the LVDS receiver circuit (receiver), skew (Ske
w) and delay time (delay) are problems, and the specifications are also determined. This is because the set time (setup time) and the hold time (hold time) are important for the digital circuit, and the skew and the delay time are sufficient to confirm whether these specifications are satisfied. Even if there is a deviation in the pulse width between the input and output, as long as these specifications are satisfied, no problem occurs in the digital circuit.

However, when LVDS is used for transmission of a modulated signal in an image forming apparatus such as laser xerography, accuracy of pulse width is important. When controlling the density in an image forming apparatus such as laser xerography, area gradation is used for gradation expression. The density unevenness when using this area gradation will be described.

FIG. 21 shows a pattern of a laser which is actually exposed when the density formed by laser exposure is changed stepwise from level 3 to level 6 (increased density). 21A shows the state of level 3, FIG. 21B shows the state of level 4, FIG. 21C shows the state of level 5, and FIG. 21D shows the state of level 6.

FIG. 21 shows a case in which one dot is formed at one level, and a case in which a dot delay corresponding to 0.5 dots occurs in the fall delay or the rise delay. Further, in the dot formation, in order to make the same behavior as the halftone screen work, the exposure is performed so as to spread the points from the center. In area gradation, the density is controlled by changing the size of the black area in the virtual area, so that the laser is exposed while scanning the area once or a plurality of times. Specifically, when the laser is exposed for a certain length or longer, the location is changed (in the adjacent image forming areas) to expand the exposure area. That is, FIG.
In the first example, exposure is performed on the same scan up to level 4, and after the exposure of level 4 after level 5, adjacent areas are exposed with the level of the difference from level 4.

At this time, if the modulated signal is ideal and the pulse width is shaped short by the transmission by LVDS,
Or conversely, it is assumed that it has been shaped for a long time. 21 is shaped to be short when the rising edge shown on the left side of FIG. 21 is slow, and is shaped to be long when the falling edge shown on the right side of FIG. 21 is delayed. That is, regarding the response characteristics of the signal, the state X in which a delay is generated on the left side in the figure, the state Y in which a delay is equally generated in both the rising and falling sides is the center side in the figure, and the state Z in which a delay is generated in the falling side is in the figure. Shown on the right.

Although it is assumed in FIG. 21 that the density is increased by laser exposure, the same is true when the density is decreased. In FIG. 22, the densities formed by laser exposure for the areas of the highest density are level 3 to level 6.
The pattern of the laser that is actually exposed is shown when it is gradually changed (density reduction) to. In the example of FIG. 22, the pattern is line-symmetric with respect to FIGS.

The monotonicity of the influence of the density on the characteristics of the transmission signal is ensured when the state Y is uniform. Further, when the rise of the state X is slow, if the density is increased from level 3 to level 4, the overall density becomes low but monotonicity is secured. On the other hand, when the density is increased from level 4 to level 5, a new exposure is started in the adjacent area, so the effect of the slow rise occurs once for each of the two exposures, and a total of two exposures occur. The monotony is lost. Similarly, when the fall of the state Z is slow, the monotonicity is lost when the density is increased from level 4 to level 5. When the density is increased from Level 5 to Level 6, monotonicity is maintained because the exposure is simply long.

The above-mentioned monotonicity can be clarified also from the relationship between the duty of laser exposure (lighting) and the exposure ratio. FIG. 23 shows the relationship between the duty for laser exposure and the exposure ratio. In FIG. 23, the X state (slow rise) is shown as a characteristic WU, the Y state (equal) is shown as a characteristic WF, and the Z state (slow fall) is shown as a characteristic WD when the density is increased by laser exposure. X state (slow rise) as a characteristic when decreasing
Is shown as characteristic BU, Y state (equal) is shown as characteristic BF, and Z state (falling slowly) is shown as characteristic BD.

That is, the characteristic W when the rising is slow
As can be understood from U, the exposure ratio with respect to the duty of laser exposure (lighting) increases with the modulation signal (that is, the duty of laser exposure), but exposure is performed in adjacent areas in order to realize area gradation by dot formation. Each start will cause a jump in density. This density jump appears remarkably especially when a gradation is drawn.

On the other hand, the characteristic WD when the trailing edge is slow is the opposite phenomenon to the characteristic WU because the pulse width is longer, but like the above, the density jump occurs when a new laser exposure is started. Cause On the other hand, the characteristic WF in the case where the rising edge and the falling edge are uniform has a delay but no change in the pulse width, and therefore no density jump occurs. Therefore, in the transmission of the laser modulation signal including the LVDS, it is necessary to design the circuit so that the rising and falling are even.

If the responsiveness of the laser driver is poor,
In some cases, a pulse for one dot cannot be formed. In this case, as shown in FIG. 24, it is conceivable that one dot of the previous exposure is deleted from adjacent exposures and two dots are formed in the next exposure. Skips occur.

Next, as prior art for transmitting modulated signals differentially for laser xerography, Japanese Patent Laid-Open No. 11-208.
The problems of the conventional technology will be described with reference to 017. In this prior art, the complementary output differentially input is guided to the laser drive differential current switch as it is, and the laser is driven with the complementary output. An experimental circuit for simulating this circuit is shown in FIG. In this prior art, since no receiver for LVDS is clearly described, the differential circuit to which the image signal 5 and the image signal (bar) 6 in FIG. 2 are input is extracted and the laser is driven by this output. The case will be described. The extracted differential circuit is shown in FIG.
Of 50 g. Although there is a difference between the bipolar circuit and the MOS in the differential circuit of this prior art, the basic configuration of the differential circuit is common. The differential signal input to this is the pulse current source 50.
The output of d is supplied to the resistors 50e and 50f, and the differential voltage 8017-IN is obtained with the common mode voltage source 50c as the center.
Generate P and 8017-INM. Further differential circuit 50
A current mirror circuit 50b for controlling the current value of the differential stage current source is provided at g. This current source is provided separately from this prior art in order to explain how the difference in the operating current of the differential circuit affects the laser driving. In addition, the current mirror circuit 50b
Sets the current in the differential stage current setting 50a.

The current source circuit for setting the differential stage current has a polarity reversed from that of the sink type current source BI shown in FIG. 2 and is a discharge type using PMOS instead of NMOS. The power supply 50c is a power supply for operating the differential circuit.
When a differential signal is input to the differential circuit 50g, the differential circuit 5g
A differential voltage is generated in two resistors of the differential stage load in 0 g, and these voltages 8017-OUTMA and 8017-OUT are generated.
PA passes through the waveform shaping circuits 51 and 52 and is supplied to the laser drive circuit 60 as a laser modulation signal. The laser drive circuit 60 has two current sources, one of which is a bias current source 61a and is provided with a laser bias current control 61b for controlling it. Laser bias current control 6
1b has the same configuration as the current source BI in FIG. Normally, the bias current source is set to a value slightly smaller than the threshold current in order to modulate the laser at high speed. The other is a current source for modulating the laser with the differential current switch 63 by the laser drive current source 62a, which is controlled by the laser drive current control 62a. The laser drive current control 62a has the same configuration as the current source BI in FIG. The differential current switch has complementary outputs, and one output DRV_OUTMC
Is connected to the laser 65a and the other output DRV_OUT
PC is connected to the dummy diode 65b.

The terminal voltage of the laser and the dummy diode is
The drive currents are made as equal as possible when they flow, thereby suppressing distortion of the laser current during modulation. The damping resistors 64a and 64b are provided to suppress ringing that tends to occur when the wiring from the differential current switch to the laser is long. A part of the light emitted from the laser 65a is guided to the photoconductor, but a part of the light is guided to a photodetector (photodiode) for automatic light amount control. The cathode of the photodiode 66a is connected to the plus side of the power source 66c, and the anode is connected to the load resistor 66b. When the laser 65a emits light and light is incident on the photodiode, a current flows through the load resistor 66b, and the amount of light can be monitored by the terminal voltage VpOUT. At the time of automatic light amount control, this output is the reference voltage V of FIG.
6 and the comparison result is compared with the comparator A2 of FIG.
The laser drive current control 62b is controlled by the output, and the laser 65a is controlled to have a constant light amount.

In this circuit, the laser-driven differential current switch is driven by complementary outputs. Looking at each of the complementary outputs, FIGS. 10 (C) (D) and 11 (C) (D) are shown.
Signal (signal drv_outpb or dr in FIG. 9)
v_outmb) and the input pulse signals shown in FIGS. 10A and 11A are different in duty. Therefore, when applied to the current switch, a period (time t shown in FIG. 10) in which both MOS transistors are turned on at the same time occurs, causing waveform distortion (distortion ZZ shown in FIG. 10).

FIG. 11 shows the case where the current of the buffer circuit is reduced from 1 mA to 0.6 mA. Where (A)
Indicates 8017-INP, 8017-IN in FIG.
M, (B) is 8017-OUTMA, 8017-OUT
PA, (C) is drv_outpb, (D) is drv_
outmb, (E) is DRV_OUTMC, (F) is D
RV_OUT-PC, (G) is the laser drive current I (p-
v) and (H) are the receiver output Vpout. In this case, by reducing the differential current from 1 mA to 0.6 mA, the signal waveform is distorted as shown in FIG. 11 (B). When the waveform of this signal is shaped, the duty is greatly reduced from 50% as shown in FIG. Then, the waveform is blunted, the duty is reduced, and as a result, the waveform is shortened as shown by the photodetector output distortion Zy in FIG. That is, in the case of FIG. 11, the pulse width is narrower than the input pulse width due to the decrease of the ON period in contrast with FIG. In this method, the current switch is driven by complementary signals, but the purpose of ensuring reproducibility of pulse width cannot be achieved.

[0034]

As described above, in the circuit using the conventional LVDS, the duty (du) of the modulation signal is increased.
Since ty) is not maintained, density skipping occurs, resulting in image quality deterioration.

In consideration of the above facts, an object of the present invention is to obtain a signal processing device and a laser driving device capable of suppressing the fluctuation of the pulse width of the generated modulation signal.

[0036]

According to the present invention, even when the current consumption of the LVDS changes in accordance with the modulation signal frequency, the L
This is to prevent fluctuations in density and prevent density jumps by preventing fluctuations in the pulse width between the input and output of the VDS on the receiving side.

For example, the LVDS receiver circuit is a differential amplifier and is constructed symmetrically with respect to the plus and minus inputs. In addition to this, by making the output side symmetrical, Q and Qbar
Generates a signal having a symmetrical waveform. Extracting its rising or falling from Q and Qbar, its rising,
Alternatively, at the falling edge, a bistable circuit configured symmetrically with respect to the two signals is provided and input. With such a circuit configuration, the bistable circuit is uniformly inverted with respect to both the − side and + side signals of the LVDS, so that the pulse width of the LVDS input is L.
Maintained at VDS output.

More specifically, the signal processing apparatus according to the first aspect of the present invention is a differential amplifier that differentially amplifies an input differential input signal and outputs a differential output signal while maintaining complementarity. And waveform processing means for generating a pulse signal based on the component in which the signal fluctuation characteristics have the same directional property for each of the differential output signals.

In the signal processing device of the present invention, the differential amplifying means differentially amplifies the input differential input signal and outputs a differential output signal while maintaining complementarity. That is, the differential amplification means amplifies a differential input signal such as a pair of inverted pulse signals and outputs a differential output signal while maintaining its complementarity. The differential output signal is input to the waveform processing means, and the waveform processing means generates a pulse signal based on the component in which the signal fluctuation characteristics have the same directional property for each of the differential output signals. The differential output signals are at least complementary, so that the trend of one signal corresponds to the trend of the other signal. That is, the signal fluctuation characteristics correspond. Therefore, the directionality of the signal variation characteristic of one differential output signal is opposite to the directionality of the signal variation characteristic of the other differential output signal. Therefore, the components that have the same direction,
For example, if a component having the same shape and a corresponding portion are specified, a pulse signal corresponding to the input differential input signal can be generated.

According to a second aspect of the present invention, in the signal processing apparatus according to the first aspect, the waveform processing means extracts the component whose signal fluctuation characteristics have the same direction, and the extracted component. Generating means for generating a pulse signal based on the above.

The waveform processing means generates a pulse signal on the basis of the component in which the signal fluctuation characteristics have the same directional property in each differential output signal. In order to generate this pulse signal, the components having the same direction are extracted by the extracting means, and the pulse signal is generated based on the extracted component by the generating means, so that the extraction and the generation are separated. Therefore, the pulse signal can be stably generated, and the circuit can be easily configured.

According to a third aspect of the present invention, in the signal processing apparatus according to the first or second aspect, the differential amplifying means differentially amplifies the differential input signal and maintains complementarity. , And a plurality of receiving circuits having symmetrical electric circuit configurations.

In order to differentially amplify the differential input signals and maintain their complementarity, it is preferable to use the same electric circuit configuration for each of the differential input signals. Therefore, by configuring the differential amplifying means by a plurality of receiving circuits in which similar electric circuits are configured symmetrically, it is possible to easily differentially amplify the differential input signal and maintain complementarity.

According to a fourth aspect of the present invention, in the signal processing apparatus according to the second or third aspect, the extraction means extracts the rising components or the falling components of the differential output signals. Is characterized by.

In the waveform processing means, the pulse signal is generated based on the component in which the signal fluctuation characteristics have the same directionality in each differential output signal. The component having the same directionality is the rising component or the rising component of the signal. A falling component can be used. By using this rising component or falling component, the unidirectional component of the signal variation characteristic can be easily obtained. The component whose signal variation characteristic has the same directionality can be passed through a differentiating circuit to generate a component whose signal variation characteristic has the same directionality.

According to a fifth aspect of the present invention, in the signal processing apparatus according to the second aspect, the waveform processing means generates a pulse signal having a pulse width according to a timing difference between the extracted components. Is characterized by.

In the waveform processing means, the pulse signal is generated on the basis of the component having the same directionality in the signal fluctuation characteristics in each differential output signal, but the components having the same directionality in the signal fluctuation characteristics are deviated. Therefore, a circuit for generating a pulse signal corresponding to a differential input signal can be easily configured by generating a pulse signal having a pulse width corresponding to the timing difference between the components extracted to absorb the deviation. it can.

According to a sixth aspect of the present invention, in the signal processing apparatus according to the second aspect, the generating means is a bistable circuit.

The generating means generates a pulse signal from the differential output signal, but it is preferable that each of the differential output signals is stably output. Therefore, by adopting a bistable circuit, it is possible to generate a stable signal corresponding to the differential output signal.

According to a seventh aspect of the invention, in the signal processing device according to any one of the first to sixth aspects, the waveform processing means adjusts the pulse width of the generated pulse signal. It is characterized by including adjusting means.

A slight pulse width variation may occur in the generated pulse signal depending on the circuit configuration. Therefore,
Since the waveform processing means includes the adjusting means for adjusting the pulse width of the generated pulse signal, it is possible to absorb the fluctuation of the pulse width generated on the electric circuit and generate the constant pulse width signal.

According to an eighth aspect of the present invention, in the signal processing device according to any one of the first to seventh aspects, the differential amplifying means changes the operating current for the differential amplification. It is characterized in that it includes a variable means for performing.

The differential amplifying means requires a current for its operation, and the current value may be determined by the entire circuit. Therefore, by including a variable means for varying the operating current for differential amplification, the operating current can be positively adjusted. Even in this case, since the pulse signal is generated based on the component in which the signal fluctuation characteristics of each differential output signal have the same directionality, pulse width fluctuation does not occur.

According to a ninth aspect of the present invention, in the signal processing device according to any one of the first to eighth aspects, the differential amplifying means is configured to detect the difference between the laser drive signals for image formation. It is characterized in that it is inputted as a dynamic input signal.

To drive the laser light source, on / off (lighting or light extinction) may be controlled like pulse width modulation. In this case, the control signal is generated from the differential input signal corresponding to the image data. As the signal processing device of the present invention, if the laser drive signal for image formation is input as the differential input signal to the differential amplifier, the laser light source can be stably driven.

According to a tenth aspect of the present invention, there is provided a laser driving device including the signal processing device according to the sixth aspect, wherein the laser driving device is based on one of the differential output signals of the bistable circuit which constitutes the generating means. And driving means for driving a laser for image formation.

That is, the signal processing device according to claim 6 is used, and the driving means uses the laser for image formation based on one of the differential output signals of the bistable circuit constituting the generating means. Is driven, it is possible to provide a laser drive device that can simplify the logic circuit and stably drive the laser light source.

The laser driving device of the invention described in claim 11 is provided with the signal processing device according to claim 6 for image formation based on the differential output signal of the bistable circuit constituting the generating means. Differential drive means for differentially driving the laser.

To drive the laser light source, a pulse signal having a stable pulse width is desired. Therefore, if the differential drive means drives the laser for image formation differentially based on the differential output signal of the bistable circuit forming the generation means, the laser light source can be driven stably. It is possible to provide a laser drive device capable of performing the above.

The laser driving device of the invention described in claim 12 is the laser driving device according to any one of claims 1 to 9 in a number corresponding to a plurality of light emitting portions for driving the surface emitting laser. A reception processing circuit including a signal processing device, and a laser drive circuit that controls each of the light emission of the surface emitting laser by the pulse signal are provided.

At least a plurality of drive circuits are required to drive the light emission of the surface emitting laser. However, when a plurality of drive circuits are operated, a drive signal (modulation signal) is generated in each circuit.
If the duty of is not maintained, the density will be skipped, resulting in deterioration of image quality. Therefore, as described above, if a component having the same directionality, for example, a component having the same shape or a corresponding portion, and a rising component or a falling component of the signal are specified, the pulse signal corresponding to the input differential input signal is determined. Can be generated and the duty maintained. This makes it possible to stably control each of the light emission of the surface emitting laser at an acute angle.

[0062]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a surface emitting laser drive circuit.

First, the LVDS receiving circuit 10 to which the present invention is applicable will be described.

As shown in FIG. 1, the LVDS receiver circuit 10
Includes a differential comparator 12 to which a differential signal is input. A current control circuit 14 for setting an operating current is connected to the LVDS receiving circuit 10, and a setting signal for setting an operating current is input to the current control circuit 14. The signal on the plus side of the differential output signal of the differential comparator 12 is connected to the plus input side of the bistable circuit 24 via the + side output circuit 16 and the transition output circuit 20. On the other hand, the negative signal of the differential output signals of the differential comparator 12 is connected to the negative input side of the bistable circuit 24 via the-side output circuit 18 and the transition output circuit 22. The positive output side of the bistable circuit 24 is connected to the pulse width adjusting circuit 26, and the pulse width adjusting circuit 26 is connected to the LVDS receiving circuit 1.
The output signal of 0 is output. The minus output side of the bistable circuit 24 is connected to the pulse width adjusting circuit 28.

The differential comparator 12 and the current control circuit 14 described above.
Corresponds to the LVDS receiver 30, the + side output circuit 16,
-Side output circuit 18, transition output circuit 20, transition output circuit 2
2, the bistable circuit 24, the pulse width adjusting circuit 26, and the pulse width adjusting circuit 28 correspond to the waveform processing circuit 32.

The LVDS receiver 30 corresponds to the differential amplifying means of the present invention, and the waveform processing circuit 32 corresponds to the waveform processing means of the present invention. The transition output circuits 20 and 22 correspond to the extraction means of the present invention, and the bistable circuit 24 corresponds to the generation means of the present invention. Furthermore, the plurality of receiving circuits of the present invention correspond to the + side output circuit 16 and the − side output circuit 18. Furthermore, the current control circuit 14
Corresponds to the variable means of the present invention, and the pulse width adjusting circuit 2
Reference numerals 6 and 28 correspond to the adjusting means of the present invention.

Further, the correspondence with the elements of the circuit described later in detail in FIG. 2 is that the differential comparator 12 uses the transistors M1 and M.
It corresponds to a circuit composed of 2, M3, M4, M5, M6, M7 and M8. The + side output circuit 16 corresponds to a circuit including transistors M13, M9, M14, and M10. The-side output circuit 18 includes transistors M15 and M
It corresponds to a circuit composed of 11, M16 and M12.
The transition output circuit 20 includes gates G10, G11, G12,
It corresponds to a circuit composed of G13, G14, and G15. The transition output circuit 22 includes gates G17, G18, G1.
It corresponds to a circuit composed of 9, G20, G21 and G22. The bistable circuit 24 corresponds to a circuit including gates G23 and G27. The pulse width adjusting circuit 26 corresponds to a circuit including gates G24, G25, and G26. The pulse width adjusting circuit 28 includes gates G28 and G2.
This corresponds to a circuit composed of 9, G30.

Next, the LVDS receiving circuit 10 will be described in detail.

FIG. 2 shows a detailed circuit of the LVDS receiving circuit 10 and is a circuit to which the circuit shown in FIG. 17 is applied. 3 shows various signal waveforms when the differential current flowing through the transistor M1 in the LVDS receiving circuit 10 is 0.6 mA, and FIG. 4 shows various signal waveforms when the differential current is 2 mA. This current source is set by setting the current source BI in FIG.
It is carried out by changing the set voltage to.

In FIG. 2, one of the differential input signals is applied to the differential input terminal IN +, and the other of the differential input signals is applied to the differential input terminal IN-. In the driver circuit used in the high-speed interface standard of LVDS, a signal is transmitted by switching the current path of a constant signal current, and the signal current flowing through the transmission line is a receiver for impedance matching with the transmission line. A terminating resistor R connected between IN + and IN- between the differential input terminals of the differential comparator which becomes a circuit.
A differential input signal is given to the differential input terminals IN + and IN- due to a voltage drop caused by flowing through 1 and R2.

In this way, the differential input terminals IN +, IN
One of the differential input signals applied to − is applied to the gate terminal of a P-channel transistor M3 forming an input stage, and the other is supplied to the transistor M3 and a P-channel transistor M4 forming a differential pair input stage. Given to the gate terminal of. Among the differential input signals, the transconductance of the transistor M3 or M4 to which the differential input signal of high potential is applied is smaller than the transconductance of the transistor M3 or M4 to which the differential input signal of low potential is applied. As a result, the constant current supplied from the P-channel transistor M1 functioning as a constant current source flows through the transistor M3 or M4 having a large mutual conductance.

The current flowing through the transistor M3 or M4 of the differential pair is cross-coupled and connected to the drain terminal of the transistor M3 and the drain terminal of the transistor M4, and serves as a load circuit of the transistors M3 and M4 of the differential pair. N-channel transistor M5 of the circuit
The potential of the gate terminal, which is supplied to the commonly connected gate terminal of M7 or the commonly connected gate terminals of the N-channel transistors M8 and M6, becomes high level, and the potential of the gate terminal to which no current flows becomes low level. Becomes This potential difference is larger than the potential difference of the input differential input signal.

This potential difference is caused by the fact that the transistors M13 and M9 are connected in series between the high-potential power source and the low-potential power source, and the transistor M1 is connected to the transistor M13.
4 and a transistor M10 are connected in series between a high-potential power source and a low-potential power source, and are amplified to output signals of amplitudes of the power source potential and the ground potential by a push-pull type output circuit using the series connection point as the output terminal of the differential comparator. To be done.

That is, if the potential of the differential input signal applied to the differential input terminal IN +> the potential of the differential input signal applied to the differential input terminal IN-, then the transistor M
The potential of the drain terminal of 3 is high level, the transistor M
The potential of the drain terminal of 4 becomes low level, and the output signal of the differential comparator that sets the power supply potential to high level is obtained at the output terminal OUTP of the output circuit. In addition, the differential input terminal I
Potential of differential input signal applied to N + <differential input terminal I
In the case of the potential of the differential input signal given to N-,
The drain terminal potential of the transistor M3 is low level,
The potential of the transistor M4 becomes high level, and the output signal of the differential comparator whose ground potential is low level is obtained at the output terminal OUTP of the output circuit.

In this embodiment, the transistor M2 is M
It is provided for generating a gate voltage for driving the current source 1. That is, the gate of the transistor M2 is connected to the gate of the transistor M1, and the source of the transistor M2 is connected to the source of the transistor M1. The drain of the transistor M2 is the drain of the transistor M1.
Is connected to the gate of the current source BI.

Further, the LVDS receiver circuit 1 of the present embodiment
0 includes transistors M11, M15, M12 and M16. Transistors M11, M15, M12, M
16 is the transistors M109, M113, M of FIG.
A symmetric circuit is formed with 110 and M114, that is, a symmetric circuit is formed with the transistors M9, M13, M10 and M14 of the present embodiment. The sources of the transistors M11 and M12 are connected to the low power source, and the transistors M15 and M16 are connected.
Source is connected to a high voltage power supply. Transistor M11
And the drains of the transistors M15 are commonly connected. The drains of the transistor M12 and the transistor M16 are commonly connected and reach the output terminal OUTM. Note that the drains of the transistors M9 and M13 are commonly connected and reach the output terminal OUTP. That is, in the present embodiment, the output circuits corresponding to the differential outputs are provided symmetrically and independently. It is preferable that the output circuit maintain symmetry (central symmetry structure) as much as possible not only in the transistor configuration but also in the arrangement.

The output terminal OUTP includes a gate G9, a connection point OUTP1, gates G10, G11, G12, G13,
It is connected to one input side of the gate G23 via G14 and G15. The other input side of the gate G23 is the gate G
27 is connected to the output side. The output side of the gate G23 is
It is connected to one input side of the gate G27. The other input side of the gate G27 is connected to the output terminal OUTM by the gate G16, the connection point OUTM1, the gates G17, G18, and G.
It is connected via 19, G20, G21, and G22. The output side of the gate G23 is connected to one input side of the gate G26 and is connected to the other input side of the gate G26 via the gates G24 and G25. The output side of the gate G27 is connected to one input side of the gate G30 via the gates G28 and G29, and the gate G30
Is connected to the other input side of. The output side of the gate G15 includes the connection point OUTP11, and the output side of the gate G22 includes the connection point OUTM11. Gate G23
The output side of the gate includes the connection point OUTP2, and the gate G2
The output side of 7 includes a connection point OUTM2. The output side of the gate G26 is connected to the output terminal OUTP5, and the output side of the gate G30 is connected to the output terminal OUTM5.

The signal characteristics of each part of the LVDS receiver circuit 10 having the above-mentioned configuration are shown in FIGS. 3 and 4. Figure 3 is LVD
4 shows various signal waveforms when the differential current flowing through the transistor M1 in the S reception circuit 10 is 0.6 mA.
Shows various signal waveforms in the case of 2 mA. Figure 3
(A) and FIG. 4 (A) are signal waveforms of an input differential signal, and the amplitude 2 input to the gate of the transistor M4 is 2
A signal (INM) of 00 mV and a signal (INP) of amplitude 200 mV input to the gate of the transistor M3.
Therefore, as shown in FIGS. 3B and 4B, the output of the output terminal OUTP in which the drains of the transistors M9 and M13 are connected and the inverted signal are the outputs of the drain connection points of the transistors M12 and M16. It is output from the terminal OUTM. Therefore, these output signals are outputs that are mutually inverted.

Here, it is understood that the signal characteristics shown in FIG. 3B, in which the differential current flowing through the transistor M1 is as small as 0.6 mA, rises and falls later. As described above, the rise changes depending on the current of the differential stage, but the amounts of change do not completely match, so that the duty shifts.

In FIG. 3C and FIG. 4C, the output terminal O
Regarding the output signal of the UTP, a signal through the gate G9 (a signal at the connection point OUTP1) is shown. Similarly, FIG.
4D and FIG. 4D, the output signal of the output terminal OUTM is output through the gate G16 (connection point OUTM1
Signal). In addition, FIG.
In (E), the output signal of the gate G15 (connection point OUTP
11), and the output signal of the gate G22 (the signal at the connection point OUTM11) is shown in FIGS. 3 (F) and 4 (F). Furthermore, FIG. 3 (G) and FIG.
In (G), the output signal of the gate G23 (connection point OUTP
2), and the output signal of the gate G27 (the signal at the connection point OUTM2) is shown in FIGS. 3 (H) and 4 (H). Furthermore, FIG. 3 (I) and FIG.
In (I), the output signal of the gate G26 (output terminal OUT
3 (J) and FIG. 4 (J) show the output signal of the gate G30 (the signal at the output terminal OUTM5).

The output signal of the output terminal OUTP is the gate G
After the waveform is shaped in 9, the extraction circuit (pulse width adjusting circuit 2) of the rising portion composed of the gates G10 to G15 is formed.
Input to 6). The output signal from the output terminal OUTM is waveform-shaped by the gate G16 and then input to the rising portion extraction circuit (pulse width adjusting circuit 28) configured by the gates G17 to G22. In this case, FIG. 3 (E) and FIG.
As shown in (E), the signals generated by the gates G10 to G15 (the signals at the connection point OUTP11) are as shown in FIG.
(C), a short pulse signal corresponding to the rising portion of the output signal of the gate G9 (the signal at the connection point OUTP1) shown in FIG. 4C is generated. Similarly, FIG. 3 (F) and FIG.
As shown in (F), the signals generated by the gates G17 to G22 (the signals at the connection point OUTM11) are as shown in FIG.
(D), a short pulse corresponding to the rising portion of the output signal of the gate G16 (the signal at the connection point OUTM1) shown in FIG. 4D is generated.

These FIGS. 3 (E), (F) and FIG.
The differential pulse signals shown in (E) and (F) are gate G23,
It is input to the SR flip-flop circuit composed of G27,
Each time a pulse is alternately input, the flip-flop is inverted and the output signal of the gate G23 (the signal at the connection point OUTP2) and the output signal of the gate G27 (the signal at the connection point OUTM2) are output as complementary signals. Further, as the complementary pulse of the flip-flop, one pulse of the gates G23 and G27 is input to the other and the duty is deviated by the propagation delay of the gate, and the duty becomes larger than the input, so that the gates G24 and G25 are compensated for. , G26, the pulse width is shortened by a delay time of 2 gates, and finally the gate G26
An output signal from the output terminal OUTP5 (output terminal OUTP5) and an output signal from the gate G30 (output terminal OUTM5) are output as modulation signals.

Since the bistable circuit is constructed by using the NAND gates G23 and G27, both inputs are Low.
A transition extraction circuit was required to prevent the transition from occurring, but a bistable circuit that originally inverts only with a transition is used, or both inputs are Lo.
If it is a bistable circuit that is not inverted when w, the transition extraction circuit is not necessary.

As a result, the output waveform of the general LVDS receiver circuit (the signal waveform at the connection point OUTP1) is deviated from the duty of the input pulse of 50%, whereas the output waveform is passed through the LVDS receiver circuit 10 of the present invention. The subsequent output waveform (the signal waveform of the output terminal OUTP5) has the same duty of 50% as that of the input pulse.

When the laser is actually driven, since the threshold value of the laser exists, the gate signal to the transistor for controlling the laser drive current reaches the set light amount at the final stage of rising. Considering this, the gates G24 and G2
It may be more accurate when viewed in terms of the light emission waveform when the output is output as it is without passing through the waveform shaping circuit composed of 5, G26 and is modulated with a pulse having a long duty for one gate. In this case, a waveform shaping circuit for shortening the pulse width can be omitted.

Next, a case where the above-mentioned LVDS receiver circuit is applied to a receiver circuit for driving each of the 36ch surface emitting lasers will be described.

FIG. 5 is a block diagram showing a circuit for driving each of the surface emitting lasers of 36ch, and FIG. 6 shows a driving circuit 40 of the surface emitting lasers of 36ch by the constant voltage driving method. . The LVDS receiver circuit 10 is provided for each channel and includes an LVDS receiver 30 and an LVDS receiver.
The waveform processing circuit 32 receives the differential output of the receiver 30 and outputs an unbalanced output signal. In addition, as shown in FIG. 6, the internal structures of the channels 1 to 36 are the same.

As shown in FIG. 5, the LVDS receiving circuit 10
Is provided with an LVDS receiver 30 and a waveform processing circuit 32 for each channel of 36ch. On channel 1,
The differential signal ch1 ± is input to the LVDS receiver 30, the differential output signal is input to the waveform processing circuit 32, and the output signal ch1d obtained is the laser drive circuit 40.
Is input to. Similarly, channel j (2 ≦ j ≦ 36)
Then, the differential signal chj ± is input to the LVDS receiver 30, the differential output signal is input to the waveform processing circuit 32, and the output signal chjd is obtained. Further, the output signal chjd is combined with a signal from the APC signal pressure control circuit that generates a signal for sequentially turning on each laser light source during automatic light amount control (APC) in the laser drive signal generation circuit, and SWd-1 ~ SWd-36, SWi-1 ~
SWi-36, SWc-1 to SWc-36, SWe-1
To SWe-36 are generated and applied as the switch control signals in FIG.

The laser drive signal generation circuit 40 includes
An APC signal generation circuit 41 for automatic light amount control (APC), to which the APC clock signal and the APC start signal are input, is connected.

The individual circuit of each channel will be described with reference to FIG. The switch SWi is connected (ON) when the laser is turned on (ON) during APC and laser modulation. The switch SWd is switched to the amplifier amp side when the laser is turned on during APC and laser modulation. The switch SWshp and the switches SWsh, SWp, and SWn are interlocked to be turned on, on, off, and off during APC. Of these, the switch SWi is turned on when the laser is turned on and the laser light source is turned on during modulation. Switch SWc
Turns on when the laser is turned on during modulation.

A switch S is provided as a circuit common to the channels.
Wfb1 to SWfb36 and capacitors Cfb1 to Cfb
36 is O according to the APC of each channel at the time of APC.
N, for example, when ch1 is APC, switch S
When Wfb1 is turned on, both ends of the capacitor Cfb1 are connected to the inverting input and the output of the amplifier A2. Power supply Vbia
s determines the voltage to be applied to the laser when the laser is off and increases the modulation speed, so it is set as high as possible under the condition that the laser light source does not emit light. It is set to a voltage slightly lower than the oscillation threshold voltage. Here, the power supply Vbias is common, but when there is a large variation in the oscillation threshold voltage of the laser light source, the power supply Vbias is used.
It is also possible to provide a plurality of as and apply a voltage as close to the optimum as possible. Further, the power supply Vref is a photodetector output voltage (output of the amplifier A5) corresponding to the target laser output.
To set.

In the following description, the switch SWd is OFF in the state shown in the figure, and ON when connected to the amplifier amp.
And Further, the switch SW7 is turned off in the state shown in the figure. The switch SWc is turned on at the same time so that when the laser light source (LD) is turned on, the anode terminal of the laser light source is quickly brought to a specified potential. Further, when the laser light source is turned off, the switch SWe is turned on to the capacitor Cld to charge the laser anode voltage when the laser light source is turned on.

FIG. 7 shows the time chart of FIG. Differential input signals ch1 + to ch36 +, ch1
− To ch36− are converted to unbalanced outputs ch1d to ch36d. The signals of the switches Swd to SWd36 and Swi to Swi36 are generated based on the unbalanced outputs ch1d to ch36d.

In FIG. 7, after the power is turned on (PowerO
N), at time T0-, the switches SWfb_1, SW2, c
SWsh, SWi, SWshp, and SWd of h1 are ON,
The switches SWp, SWn, SWc, and Swe are turned off. At this time, the current Is flows to the laser light source LD-1 via the switch SWi and is turned on, and the current flows through the photodiode PD that receives the laser light, which is converted into a voltage by the resistor R6 and amplified by the amplifier A5 to switch the switch SW2. It is input to the inverting input of the amplifier A2 via For this input signal, the difference between the voltage of the power supply Vref and the voltage of the power supply Vref is amplified by the amplifier A2, the voltage is divided by the resistance Ros with the power supply Vbias,
switch amp to ch1 via switch
It is input via Wsh. Eventually, the output of the photodetector to the amplifier A2 coincides with the voltage of the power supply Vref and converges. After this, the switches SWfb1, SWshp1, SW
When sh1 is turned off, the respective control voltages at that time are held in the capacitors connected in series. At this time, the voltage held in each of the capacitors Cfb1, Cp, Csh becomes the output voltage of the amplifier A2 in ch1, the control voltage for setting the drive current to the laser, and the laser terminal voltage at that time.

The above operation is repeated by the number of laser light sources to hold the control voltage of all the ch control circuits and the capacitors 1 to 36 connected between the inverting input of the amplifier A2 and the output terminal. When the 36-channel APC is completed, the switch SW2 is turned off, and the switch SWf
b1 is turned on and the control voltage for ch1 is prepared for the next APC as the output voltage of the amplifier A2.

The switch SW7 is turned on until the next APC, and the output of the amplifier A5 is supplied with the power supply Vre during the modulation period.
By setting the voltage value to f, the time required for the output of the photodetector to reach a steady state at the start of the next APC is shortened. As a result, when the APC is started next time, the negative feedback control is performed from the final voltage at the time of controlling the light amount, so that it is not always necessary to converge to the final voltage by one control. This is especially important in laser xerography using polygons, and intermittent control can prevent unnecessary exposure to the photoconductor and suppress deterioration of the photoconductor. The resistor Ros connected to the amplifier A2 is provided to adjust the gain of the negative feedback, and is set so as to achieve both stability and accuracy. Further, the power source Vbias is connected to the opposite side of the resistor Ros, which is a measure because the terminal voltage of the laser light source is controlled at the oscillation threshold voltage of the laser or higher. By doing so, even if the gain of the negative feedback loop is reduced, the voltage to the Buffer is prevented from becoming uncontrollable because it becomes the laser oscillation threshold voltage or less.

The capacitance of the capacitor Cld is the switch SWd.
Is turned on and the switch SWc is turned on at the moment when a current flows through the laser light source so that the laser terminal voltage quickly becomes the original drive voltage. However, the capacitor Cl
Since the capacity of d is limited, the terminal voltage will eventually drop and the amount of laser light will also decrease with capacity alone. For this reason, in order to compensate for this, a negatively fed back amplifier amp is connected via the switch SWd to compensate for this. Therefore, the capacitance of the capacitor Cld is determined from the response speed of the amplifier amp. Normally, in a CMOS operational amplifier, it takes about 1 μsec to respond, so the setting is made so that the extent to which the terminal voltage of the capacitor Cld drops within the allowable fluctuation within 1 μsec.

Specifically, if the laser drive current is 1 mA, the voltage fluctuation is 1 / C × 1 mA × 1 μsec = 1 / C.
It becomes x 10 ^-9 . Assuming that the allowable light amount variation is 2%, the internal resistance of the laser is 500Ω, and the voltage variation with respect to the allowable light amount variation is 10 mV, C = 0.1 uF is required.
However, this value is too large when it is attempted to fit the drive circuit into a one-chip IC.

Even if such a capacitor can be realized by connecting it to the outside, for example, the amplifier amp
Since the internal control potential of the output potential of 1 changes due to the load change, the terminal voltage of the laser changes at the moment the switch SWd is turned on. As a countermeasure against this, the drive current Is of the laser is supplied to the laser terminal voltage by the switch SWs in synchronization with the switch SWd. In this way, the fluctuation of the output current from the amplifier amp is suppressed regardless of the state of the switch SWd, so that it is possible to prevent the transient voltage fluctuation when the switch SWd is turned on.

Further, in this way, the capacitor Cl
The time when d maintains the laser terminal voltage is the time when the current source Is starts to flow the current to the laser terminal. Since the current source Is created by the current mirror is much faster than the responsiveness of the operational amplifier, the load on the capacitor Cld is reduced and the capacitance can be reduced. Further, since the laser drive current is supplied as the current Is, the voltage fluctuation due to the ON resistance of the switches SWd and SWc can be reduced to a negligible level.

In FIG. 7, SWd-1 to SWd-36, SWi- generated based on ch + and ch- input to the LVDS receiver after the control voltage A2OUT has converged after repeatedly performing APC. 1 to SWi-
36, SWc-1 to SWc-36, SWe-1 to SWe
The switch of each channel ch of FIG. 6 is controlled by -36, and the laser light source is turned on according to the signal input to the LVDS.

FIG. 8 shows ch1 (ch2 to ch36) of FIG.
3 is an example of a detailed circuit of FIG. The amplifier amp is a transistor M1
This is a single-stage amplifier composed of 4, M17, M18, M16, and M15. Ip is a transistor M
6 and In correspond to the transistor M9, and switches SWp and SWn between them are switches SWp and SW, respectively.
n. Among them, the transistors M6 and M9 form the second stage of the amplifier amp, and two transistors form an operational amplifier. This 2nd stage is controlled by switches SWp and SWn.

The switch SWd is a transistor M14, M
The output of the operational amplifier and the bias Vbias
And are switched to apply a voltage to the laser light source. The switch SWc connects / disconnects the capacitor Cld with the switch SWc. The capacitor Cld is further connected to the output of the operational amplifier by the transistor M13. This is because the output of the operational amplifier charges the capacitor Cld when the drive voltage to the laser light source is OFF, and the capacitor Cld is charged up to that moment. With this voltage, the potential of the laser is instantly raised to the drive potential. Switches SWi are M10, M
A current equal to the laser driving current is supplied to the laser at the moment when the laser is turned on, and the laser is turned on, and otherwise outputs to the complementary output. By making the outputs complementary, the consumption current does not change when the laser light source is turned on and off, and fluctuations in the power supply are prevented.

The current Is is a driving current source at that time and is composed of the transistor M12. The gate potential of the transistor M12 is sampled and held by the capacitor Cp, and is further decoupled to suppress the fluctuation of the current due to the feedthrough from the switch SWi. This gate potential is charged through the switch SWshp, and the potential is obtained by causing the output of the amplifier amp to be absorbed by the transistor M1 and converting the output current to the transistor M19.
It is generated by converting to the gate potential on the PMOS side.

Next, the LVDS receiver circuit 1 of this embodiment
Circuits in the prior art similar to 0 (see FIGS. 9 to 11)
The result of comparison with is explained. FIG. 12 shows a case where the present invention is applied to laser driving based on the circuit of FIG. FIG. 12 shows DRV_OUTMB and DRV_OUTP of FIG.
The configuration is the same after B. In FIG. 12, DRV_OUTM
B can be obtained by waveform shaping from OUTM5 in FIG. 2 by a waveform shaping circuit 51 of four stages of inverters. Also, DRV_OU
The waveform shaping of TPB is performed from OUTM5 in FIG. 2 by a waveform shaping circuit 51 having five stages of inverters. Here, the control signal for the differential switch 63 is generated from one output OUTM5 in FIG. This is because there is a merit that the logic circuit can be simplified because it is only necessary to process one signal. However, when such a process is unnecessary, as shown by the dotted line in FIG.
The output of OUTP5 may be directly used as DRV_OUTPB through the four-stage inverter 52. Even in this manner, the bistable circuit 24 of FIG.
Pulse width of differential signal input to INP and Japanese Patent Laid-Open No. 11-
There is no problem that the pulse width is different from the input pulse, which occurs when the laser is driven as it is without passing the bistable circuit in the differential output in the technology of the 2008080 publication. In the circuit of FIG. 12, the complementary signal is once converted into one signal to generate the complementary signal again. FIG. 13 shows the case where the differential stage current is set to 2 mA, and FIG. 14 shows the case where the differential stage current is set to 0.6 mA.

13 (A) and 14 (A) show the signal waveforms of the input differential signals (INM, IN in FIG. 2).
P), FIG. 13B, and FIG. 14B show the output terminal OUT.
3 is a signal waveform output from P and an output terminal OUTM (FIG. 2). 13C and 14C show the output signal of the output terminal OUTP via the gate (connection point O in FIG. 2).
(Signal in UTP11) is shown in FIG.
4 (D) shows the output signal (the signal at the connection point OUTM11 in FIG. 2) of the output terminal OUTM via the gate. 13E and 14E show the output signal of the gate G24 in FIG. 2, and FIGS.
One output signal (DRV-OUTPC in FIG. 12) from the differential current switch is shown in (F). Further, FIGS. 13G and 14G show the other output signal (DRV-OUTMC in FIG. 12) from the differential current switch. 13 (H) and 14 (H) show the waveforms of the drive current to be passed through the laser.
In (I), the optical output characteristic of the laser beam output from the laser (detection current signal of the photodiode) is shown.

As shown in FIG. 13, the rising edge and the falling edge coincide with each other at time ta, and the waveform is not distorted. Further, as shown in FIG. 14, at time tb, the rising edge and the falling edge coincide with each other without depending on the current of the differential stage, and the waveform is not distorted. As described above, even if the LVDS receiver differential stage current of FIG. 13 is set to 2 mA or to 0.6 mA of FIG. 14, the finally obtained light emission waveform V (vpout) of the laser light source becomes 50% of the duty of the input pulse. It almost agrees. From this, in the present embodiment, it is possible to generate a signal with a stable duty without depending on the current of the differential stage and without causing distortion in the waveform.

As described above, in this embodiment, the LVDS
In a laser driving circuit having a built-in receiving circuit, for example, a laser driving IC, even if the response of the LVDS receiving circuit is changed according to the application to reduce the current consumption, the pulse width given by LVDS and the LVDS receiving circuit amplify it. Since the pulse width of the actual laser drive pulse exactly matches, it is possible to prevent not only density fluctuation but also density jump in gradation.

[0109]

As described above, according to the present invention, the differential amplifying means differentially amplifies the differential input signal and outputs the differential output signal while maintaining the complementarity, and the waveform processing means outputs the differential output signal. Since the pulse signal is generated based on the components extracted from the components having the same directionality in the signal fluctuation characteristics for each of the dynamic output signals, it is possible to generate the pulse signal having a stable pulse width regardless of the operating current. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing an LVDS receiver circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of the LVDS receiver circuit according to the embodiment of the present invention.

FIG. 3 is a timing chart showing a drive waveform (differential stage current 0.6 mA) of the LVDS receiver circuit.

FIG. 4 is a drive waveform of the LVDS receiver circuit (differential stage current 2
3 is a timing chart showing mA).

FIG. 5 is a block diagram showing a circuit for driving each of the 36-ch surface emitting lasers according to the present embodiment.

FIG. 6 is a circuit diagram showing a drive circuit of a surface emitting laser of 36 ch by a constant voltage drive system.

FIG. 7 is a time chart showing the flow of signals in FIG.

8 is a circuit diagram showing details of ch1 in the drive circuit shown in FIG.

FIG. 9 is a circuit diagram of a prior art for comparison with the LVDS receiver circuit of the present embodiment.

10 is a time chart showing a drive waveform (buffer current 1 mA) in the circuit of the prior art shown in FIG.

11 is a timing chart showing drive waveforms (buffer current 0.6 mA) in the prior art circuit shown in FIG.

FIG. 12 is a circuit diagram of an LVDS receiver circuit to which the present embodiment is applied for comparison with the prior art shown in FIG.

13 is a timing chart showing a drive waveform (differential stage current 2 mA) of the LVDS receiver circuit of FIG.

FIG. 14 is a timing chart showing a drive waveform (differential stage current 0.6 mA) of the LVDS receiver circuit of FIG.

FIG. 15 is a block diagram conceptually showing a circuit on the receiving side of a conventional LVDS.

FIG. 16 is a diagram showing a configuration of a programmable operational amplifier capable of externally controlling a differential stage current of a differential amplifier.

FIG. 17 is a circuit diagram showing a configuration of a conventional LVDS receiver circuit.

FIG. 18 is a circuit diagram showing a detailed configuration of a conventional LVDS receiver circuit.

FIG. 19 is a timing chart showing a drive waveform (differential stage current: 0.6 mA) of a conventional LVDS receiver circuit.

FIG. 20 is a timing chart showing a drive waveform (differential stage current 2 mA) of the conventional LVDS receiver circuit.

FIG. 21 is an explanatory diagram for explaining a laser exposure state when the density is low and the rise or fall is slow by half a dot.

FIG. 22 is a case where the density is gradually decreased from solid black to
FIG. 22 is an explanatory diagram for explaining a laser exposure state in the case where the rising edge or the falling edge is delayed by a half dot as in FIG. 21.

FIG. 23 is a characteristic diagram showing the influence on the density when the rising or falling of the modulated pulse is slow.

FIG. 24 is an explanatory diagram for explaining avoidance in the next exposure when laser modulation cannot be performed with a pulse width of half a dot when the density is low.

[Explanation of symbols]

10 LVDS receiver circuit 12 Differential comparator 14 Current control circuit 16+ side output circuit 18-side output circuit 20 Transition output circuit 22 Transition output circuit 24 Bistable circuit 26 Pulse width adjustment circuit 28 Pulse width adjustment circuit 30 receiver 32 Waveform processing circuit 40 Laser drive circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C362 AA07 AA16 CA02 CA09                 5F073 EA13 GA04 GA24 GA37                 5J001 AA04 BB00 BB02 BB10 BB12                       BB14 BB19 DD01                 5J066 AA01 AA12 CA00 FA07 HA05                       HA08 HA09 HA17 HA19 HA25                       HA29 HA38 KA04 KA05 KA06                       KA09 KA12 KA17 KA19 KA33                       KA36 KA38 MA11 ND01 ND12                       ND22 ND23 PD02 SA00 TA01                       TA02 TA06

Claims (12)

[Claims] 1. A differential amplifier that differentially amplifies an input differential input signal and outputs a differential output signal while maintaining complementarity, and a signal variation characteristic for each of the differential output signals A signal processing device comprising: a waveform processing unit that generates a pulse signal based on a component that becomes directional. 2. The waveform processing means includes extraction means for extracting a component whose signal fluctuation characteristics have the same directionality, and generation means for generating a pulse signal based on the extracted component. The signal processing device according to claim 1. 3. The differential amplifying means includes a plurality of receiving circuits having symmetrical electric circuit configurations for differentially amplifying the differential input signals and maintaining complementarity. The signal processing device according to claim 1. 4. The signal processing device according to claim 2, wherein the extraction means extracts rising components or falling components of the differential output signals. 5. The signal processing apparatus according to claim 2, wherein the waveform processing means generates a pulse signal having a pulse width according to a timing difference between the extracted components. 6. The signal processing device according to claim 2, wherein the generating unit is a bistable circuit. 7. The signal processing device according to claim 1, wherein the waveform processing unit includes an adjusting unit that adjusts a pulse width of the generated pulse signal. . 8. The signal processing according to claim 1, wherein the differential amplifying means includes a varying means for varying an operating current for the differential amplification. apparatus. 9. The differential amplifier according to claim 1, wherein a laser drive signal for image formation is input as the differential input signal. Signal processing device. 10. The signal processing device according to claim 6, wherein the laser for image formation is driven based on one output signal of the differential output signals of the bistable circuit constituting the generating means. A laser driving device including driving means. 11. A differential drive unit comprising the signal processing device according to claim 6, and differentially driving a laser for image formation based on a differential output signal of a bistable circuit constituting the generation unit. And a laser drive device. 12. A reception processing circuit comprising the signal processing device according to claim 1, the number of which corresponds to a plurality of light emitting portions, for driving a surface emitting laser. And a laser drive circuit that controls each of the light emission of the surface emitting laser by the pulse signal.