JP2003036694A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a BIST circuit equipped with an analysis function, which simplifies a repair analysis process and reduces the circuit scale of the analysis function by considering handling of failure information of a redundant part. A semiconductor device that can be obtained. A BIST circuit of a semiconductor memory includes an ALP
An address and an expected value for testing the memory array 1 are generated by G5, and the memory array 1 corresponding to the address is generated.
Circuit 6 for comparing the signal read from the memory with the expected value
An address processing unit 7 for forming an internal address in which the address generated by the ALPG 5 is increased by one bit in rows and columns; a defect accumulation unit 8 for accumulating addresses determined to be defective by the comparison circuit 6; A repair analysis section 9 for analyzing the defective addresses stored in the memory 8 and outputting a repair solution is provided so that the repair by the defective redundant section 3 is not performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a BIST (Built-In-Self-Test) circuit having an analysis function.

[0002]

2. Description of the Related Art In conventional memory device analysis processing, an actual array section and a redundant section are tested separately, and defect information thereof is stored in a fail memory provided on a tester, and the actual array section and the redundant section are stored in software. The repair analysis was performed while considering the information of the department.

[0003]

In the above-mentioned prior art,
There is a problem that the redundant analysis becomes complicated because the defect information of the real array part and the redundant part is stored in different areas on the fail memory of the tester. In addition, when the above-described memory device analysis method is implemented in BIST, there is a problem that the circuit scale increases.

The present invention has been made in order to solve the above-mentioned problems, and simplifies the repair analysis process by considering the handling of defect information in the redundant part in a BIST circuit equipped with an analysis function. It is an object of the present invention to obtain a semiconductor device that can be made compact and can reduce the circuit scale of the analysis block.

[0005]

In a semiconductor device according to the present invention, a test signal generating circuit for generating an address and an expected value for testing a memory array including a real array portion and a redundant portion, and a test signal generating circuit A comparison circuit that compares the signal read from the memory array corresponding to the generated address with an expected value, a defect accumulation unit that accumulates the address of the memory array that is determined to be defective by this comparison circuit, and this defect accumulation unit The repair analysis unit includes a repair analysis unit that analyzes the address stored in the real array unit and outputs a repair solution for repairing the defective circuit in the real array unit with the redundant circuit in the redundant unit. The repair solution is output so as not to be used for repairing the defective circuit of the part. In addition, the first repair solution analyzed by the repair analysis section is for repairing the defective first redundant circuit by the second redundant circuit, and the second repair solution is the defective array of the real array section. If the circuit is repaired by the first redundant circuit,
The repair analysis unit changes the second repair solution to a third repair solution that repairs a defective circuit in the actual array unit by the second redundant circuit, and outputs the third repair solution.

Further, there is provided an address processing section for generating an internal address which distinguishes the address of the real array section from the address of the redundant section by using the address generated by the test signal generating circuit. Further, the internal address generated by the address processing unit is one bit more for each of the row address and the column address than the address generated by the test signal generating circuit.

The address of the memory array, which is determined to be defective and is stored in the defective storage unit, is an internal address generated by the address processing unit. Also,
The repair analysis unit does not output a repair solution for repairing a defective redundant circuit in the redundant unit.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing a repair analysis circuit of a semiconductor device according to a first embodiment of the present invention, and this repair analysis circuit is mounted on a BIST. In FIG. 1, 1 is a memory array having a real array section 2 and a redundant section 3, 4 is a repair analysis circuit mounted in BIST, and 5 is a memory array 1 mounted in BIST.
ALPG (Algorithmic) for generating test signals such as addresses and expected values for testing
(Pattern Generator, test signal generation circuit). The repair analysis circuit 4 is composed of the following 6-9. Reference numeral 6 is a comparison circuit for comparing the read data from the real array unit 2 or the redundant unit 3 with the expected value of the ALPG 5 to judge whether the real array unit 2 or the redundant unit 3 is defective.
An address processing unit that receives an address signal and a redundant unit test signal from the LPG 5 and generates an internal address for the redundant unit 3, and 8 is a defective storage unit that stores defective information of the memory array 1 according to the judgment of the comparison circuit 6. It has a defective address storage unit that is expanded by one bit in the row and column directions from the array size, and has a structure in which even if the redundant unit 3 has a defect, it can be stored in the same manner as the defect in the actual array unit 2. . Therefore, the defect storage section 8 has a configuration having four times as many virtual memory writing areas as the actual array section 2. A repair analysis unit 9 executes a repair analysis based on the information stored in the defect storage unit 8. The repair solution for repairing the defective circuit of the memory array 1 by the redundant circuit of the redundant section is held in the temporary repair analysis section 9, but if the repair solution is the defective redundant circuit of the redundant section 3 during reading, another Output the repair solution of. FIG. 2 is a schematic diagram showing a defective portion of the semiconductor device according to the first embodiment of the present invention. In FIG.
Reference numeral 10 is a defect in the actual array unit 2, and 11 is a defect in the redundant unit 3.

Next, the operation will be described. ALP now
It is assumed that the memory test is executed from G5 and the defect shown in FIG. 2 occurs. The defect 10 generated at the time of testing the address (0, 0) is judged as fail in the comparison circuit 6. At this time, the redundancy processing test signal = L and the address signal (0,0) (n and m bits for the row and column addresses, respectively) are input to the address processing unit 7, and the output address (1 bit is increased with the highest bit as 0). 0, 0) (n + 1 and m + 1 bits for row and column addresses, respectively) are output, and defective address information of (0, 0) (n + 1 and m + 1 bits for both row and column addresses) is stored in the defect storage section 8. Also, by testing on redundant rows,
The defect 11 is detected. At this point in time, the redundancy side test signal on the row side is H, so the address output from the address processing unit 7 is set to 1 (1000.
.., 0) (n + 1 and m + 1 for both row and column addresses)
Bit). Therefore, (1000
.., 0) (n + 1 and m + 1 for both row and column addresses)
Bit) is stored as bad. By executing the repair analysis process, the defect 10 is redundant ROW0 and the defect 11 is redundant R
The repair solution to be repaired by OW1 is held in the temporary repair analysis unit 9. However, when the repair solution is output, since the redundant ROW0 has a defect, the redundant ROW1 outputs the optimum solution for repairing the defect 10.

According to the first embodiment, in the past, when the redundant part was included, a complicated repair analysis process was executed, but before the defect accumulation in the defect accumulation part, the address process is executed and the redundant part is formed. By performing the address allocation, the repair analysis process can be simply performed without paying attention to the redundant part.

Embodiment 2. FIG. 3 is a schematic diagram showing address generation for a redundant portion of a semiconductor device according to a second embodiment of the present invention. In FIG. 3, 7 is an address processing section, 12 is an address signal generated by the ALPG 5, 13 is a row side redundant section test signal, and 14 is a column side redundant section test signal. 12 to 14 are input to the address processing unit 7. Reference numeral 15 is an AND gate forming the address processing unit 7, and 16 is an inverter.

Next, the operation will be described. When the redundancy section 3 on the row side is being tested, the redundancy section test signal 13
Becomes HIGH, and the test address output from the address processing unit 7 becomes {1000 ... 0}. When the redundancy section 3 on the row side is not tested, the redundancy section test signal 13 is LOW, the most significant bit (n + 1 bit) of the test address is 0, and the other addresses remain the address signal 12. If there are multiple row redundancy lines, it is possible to remove the AND gates corresponding to the number of row redundancy lines from the least significant side of the address so that the least significant address does not pass through the AND gate. . The same applies to the column side.

According to the second embodiment, by using the circuit of FIG. 3, address allocation can be internally performed.

Embodiment 3. FIG. 4 is a schematic diagram showing a defect accumulating portion of the semiconductor device according to the third embodiment of the present invention. 4, 1 to 3 are the same as those in FIG. Reference numeral 18 denotes each analysis area of the memory array 1, which includes the real array section 2 and the redundant section 3. In the memory array 1, there are 1 to x repair analysis blocks, that is, analysis areas 18, and for each of them there is an area of the real array section 2 of n bits in the row direction and m bits in the column direction. The defect accumulating unit for accumulating defect information of each analysis area has a defect information storage unit commensurate with the number of redundant lines, and stores the address of the defective redundant circuit of the redundant unit 3, so that for each defect, The row side has an area of n + 1 bits and the column side has an area of m + 1 bits. Also,
If redundant compression is applied, it is sufficient to have a defective storage space from which the bit width to be compressed is subtracted.

According to the third embodiment, n + is stored in the defective storage portion.
By having an address space of 1 and m + 1 bits, it becomes possible to store a defect in the redundant part.

Fourth Embodiment FIG. 5 is a flowchart showing the operation of the repair analysis unit of the semiconductor device according to the fourth embodiment of the present invention. FIG. 6 is a schematic diagram showing repair analysis of a semiconductor device according to a fourth embodiment of the present invention. 6, 10 and 11 are the same as those in FIG. (A), (b), (c) are examples of repair solutions,
The repair solution (a) is a repair solution (second repair solution) that repairs the address 0 (defective circuit of the actual array section) with the redundant ROW0, and the repair solution (b) is the redundant ROW1 (second redundant circuit). The repair solution (first repair solution) and the repair solution (c) for repairing the redundant ROW0 (first redundant circuit) are the address 0 at the redundant ROW1.
It is a remedy solution (third remedy solution). In the repair analysis, the memory array 1 is analyzed in an address space of n + 1 bits in the row direction and m + 1 bits in the column direction. Therefore, as shown in repair solutions (a) and (b) of FIG. There is a possibility that a repair solution for repairing a defect in the redundant circuit used for repairing the actual array portion may occur. here,
When applied to the flow of FIG. 5, the repair solution (a) applies to step S4 and is not output as a repair solution, and the repair solution (b) applies to step S5 and outputs address 0 as a repair solution.

This will be described in more detail with reference to FIGS.
Will be explained. In step S1 of FIG. 5, n repair solutions of the analysis result of the repair analysis unit are read. In step S2,
The repair solution for the output target is set, and it is determined in step S3 whether or not the repair solution is used for the repair. If it is used, the procedure proceeds to step S4, and the repair solution set as the output target in step S2. Depending on whether or not it has been repaired by another redundancy circuit, a redundancy R as shown in repair solution (b).
If OW0 is repaired by ROW1 of another redundant circuit, the repair solution (a) is not output in step S6, and the process returns to step S2. Further, in step S3, even when the repair solution is not used, the repair solution is not output (step S6), and the process returns to step S2.

If it is determined in step S4 that the redundancy address has not been repaired by another redundant circuit, the process proceeds to step S5 to determine whether or not the repair address of the repair solution that is repairing points to the redundancy section. (Repair solution (b)) is step S
In step 7, the repair address (address 0) of the redundant part (ROW0) being repaired is output as the repair solution (c), and the process returns to step S2. If the repair address is not the redundant portion in step S5, the repair solution is output in step S8.

According to the fourth embodiment, even if there is a repair solution for repairing the redundant portion as shown in FIG. 6, only the optimum solution is output at the time of output, and the processing after output from the BIST block can be simplified. .

[0020]

Since the present invention is constructed as described above, it has the following effects. A test signal generating circuit for generating an address and an expected value for testing a memory array including a real array portion and a redundant portion, and an expected value for a signal read from the memory array corresponding to the address generated by the test signal generating circuit. And a defective storage unit that stores the address of the memory array determined to be defective by this comparison circuit, and an address stored in this defective storage unit to analyze the defective circuit of the actual array unit as a redundant unit. Since the repair analysis section outputs a repair solution for repairing with the redundant circuit, the repair analysis section outputs the repair solution so that the defective redundant circuit in the redundant section is not used for repairing the defective circuit in the actual array section. With the built-in repair analysis unit, the repair analysis process including the redundant part can be simply performed.

The first repair solution analyzed by the repair analysis section is for repairing the defective first redundant circuit by the second redundant circuit, and the second repair solution is the real array. When remedying a defective circuit of a partial array with the first redundant circuit, the repair analysis unit changes the second repair solution to a third repair solution of repairing the defective circuit of the actual array section with the second redundant circuit. Therefore, the output of the repair solution for repairing the defective circuit in the actual array section by the defective redundant circuit can be prevented.

Further, since the address processing section for generating the internal address which distinguishes the address of the real array section from the address of the redundant section is provided by using the address generated by the test signal generating circuit, it is redundant with the real array section. It is possible to form a unified internal address that can distinguish the addresses of the parts. Further, the internal address generated by the address processing unit has one more bit for each of the row address and the column address than the address generated by the test signal generating circuit. Therefore, this one bit distinguishes the real array unit from the redundant unit. You can

Since the address of the memory array determined to be defective in the defective accumulating unit is the internal address generated by the address processing unit, the addresses of the real array unit and the redundant unit should be treated in common. Therefore, the repair analysis of the repair analysis unit can be simply performed. Further, since the repair analysis unit does not output the repair solution for repairing the defective redundant circuit in the redundant unit, it can output only the repair solution for repairing the defective circuit in the actual array unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a repair analysis circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a defective portion of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic diagram showing address generation for a redundant portion of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram showing a defect accumulating portion of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a flowchart showing an operation of a repair analysis section of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a schematic diagram showing repair analysis of a semiconductor device according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 memory array, 2 real array section, 3 redundant section, 4
Repair analysis circuit, 5 ALPG, 6 comparison circuit, 7 address processing unit, 8 defect storage unit, 9 repair analysis unit, 10,
11 defectives, 12 address signals, 13, 14 redundant part test signals, 15 AND gates, 16 inverters,
18 Analysis area.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/822 H01L 27/04 T 27/04 21/82 RF term (reference) 2G132 AA08 AB01 AG01 AK07 AK29 5F038 DT08 DT14 DT17 DT18 EZ20 5F064 BB12 BB31 FF12 FF15 FF41 5L106 CC01 CC17 DD22 DD23 DD24 DD25 EE03 EE07

Claims (6)

[Claims] 1. A test signal generation circuit for generating an address and an expected value for testing a memory array including a real array section and a redundant section, and a memory array corresponding to an address generated by the test signal generation circuit. A comparison circuit that compares the signal with the expected value, a defect storage unit that stores the address of the memory array that is determined to be defective by this comparison circuit, and an address that is stored in this defect storage unit is analyzed to detect a defect in the actual array unit. The repair analysis unit outputs a repair solution for repairing the circuit with the redundant circuit of the redundant unit, and the repair analysis unit does not use the defective redundant circuit of the redundant unit for repairing the defective circuit of the actual array unit. A semiconductor device characterized by outputting 2. The first repair solution analyzed by the repair analysis unit is for repairing a defective first redundant circuit by a second redundant circuit, and the second repair solution is a real array. In the case of repairing a defective circuit of the real part by the first redundant circuit, the repair analysis unit repairs the defective circuit of the actual array part by the second redundant circuit. The semiconductor device according to claim 1, wherein the solution is changed to a solution and outputted. 3. An address processing section for generating an internal address which distinguishes an address of the real array section from an address of the redundant section by using the address generated by the test signal generating circuit. 1 or claim 2
The semiconductor device described. 4. The semiconductor device according to claim 3, wherein the internal address generated by the address processing unit is one bit more for each of the row address and the column address than the address generated by the test signal generating circuit. 5. The semiconductor device according to claim 3, wherein the address of the memory array, which is determined to be defective and is accumulated in the defect accumulating unit, is an internal address generated by the address processing unit. . 6. The semiconductor device according to claim 1, wherein the repair analysis section does not output a repair solution for repairing a defective redundant circuit in the redundant section.