JP2003036041A - Flat panel display - Google Patents

Abstract

(57) [Problem] To provide a flat display device in which a defect of a point defect caused by a current leak between a metal electrode and an auxiliary capacitance semiconductor layer is prevented. SOLUTION: A storage capacitor semiconductor layer via a gate insulating film
A metal electrode 54 is formed on 37. The metal electrode 54 has a longitudinal shape parallel to the scanning line 53, and both sides of the auxiliary capacitance semiconductor layer 37 in the longitudinal direction are located inside the both sides of the metal electrode 54 in the longitudinal direction. The portion does not overlap with the metal electrode 54 in the plane direction. Even if a stress occurs between the metal electrode 54 and the gate insulating film due to a difference in stress between the metal electrode 54 and the gate insulating film during a high-temperature heat treatment such as annealing, the metal electrode that receives the strongest stress is applied.
Since the side edges in the longitudinal direction of 54 do not overlap the auxiliary capacitance semiconductor layer 37, cracks are less likely to occur in the gate insulating film on the auxiliary capacitance semiconductor layer 37. Current leakage between the auxiliary capacitance semiconductor layer 37 and the metal electrode 54 through cracks in the gate insulating film is prevented, and the occurrence of point defect defects is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a flat panel display device having an S-structure auxiliary capacitance.

[0002]

2. Description of the Related Art Generally, a typical flat display device is, for example, a liquid crystal display device. This liquid crystal display device is thin, lightweight, and has low power consumption, and is used as a display for notebook personal computers, mobile terminals, and the like. In addition, a liquid crystal display device has display elements arranged in a matrix, and as a driving method, a simple matrix type that does not have an active switching element that controls these display elements to control a liquid crystal layer, and a display element There is an active matrix type having an active type switching element for controlling the liquid crystal layer by controlling the liquid crystal layer by controlling the liquid crystal layer. Among them, the active matrix type, which can obtain a high quality image in a large area, is the mainstream. One of the characteristics of this active matrix type is a memory holding operation for holding a drive voltage supplied via a switching element for a predetermined period, and each display element has an auxiliary capacitance for memory holding. That is, in the active matrix type, since the drive voltage for controlling the liquid crystal layer can be held by the auxiliary capacitance even after the switching element is turned off, a high quality image can be obtained.

As described above, the auxiliary capacitance is used to obtain a high quality image, and in particular, in order to simplify the manufacturing process, a MOS (Metal) in which a dielectric layer is sandwiched between a semiconductor layer and a metal electrode is used. Oxide Semiconductor) Auxiliary capacitance of the structure is often used.

Further, as a conventional auxiliary capacitor of this type,
For example, the configurations shown in FIGS. 4 and 5 are known.

In the auxiliary capacitance shown in FIGS. 4 and 5, an undercoat layer 2 is formed on an insulating substrate 1 such as a glass substrate, and an auxiliary capacitance semiconductor layer 3 made of a semiconductor is formed on the undercoat layer 2. Are formed. Further, a dielectric layer 4 is formed on the auxiliary capacitance semiconductor layer 3, and a long metal electrode 5 is formed on the auxiliary capacitance semiconductor layer 3 of the dielectric layer 4.
Are formed. The auxiliary capacitance semiconductor layer 3 is wider than the width of the metal electrode 5 and protrudes in the width direction from both side edges of the metal electrode 1 in the longitudinal direction. The auxiliary capacitance semiconductor layer 3 is laminated with the metal electrode 5 sandwiching the dielectric layer 4. There is.

Then, the auxiliary capacitance semiconductor layer 3 and the metal electrode 5
And the auxiliary capacitance is formed with the dielectric layer 4 interposed therebetween.

[0007]

However, in the auxiliary capacitance in which the dielectric layer 4 having the structure shown in FIGS. 4 and 5 is sandwiched between the auxiliary capacitance semiconductor layer 3 and the metal electrode 5, the auxiliary capacitance semiconductor layer 3 is formed. There is a possibility that a leak current may increase or a short circuit may occur between the metal electrode 5 and the metal electrode 5, and a point defect defect may occur to deteriorate display quality and reliability.

According to experiments, such point defect defects are
As shown in FIG. 5, a crack C is generated in the dielectric layer 4 at the edge of the metal electrode 5 of the auxiliary capacitance, which causes a current leak between the auxiliary capacitance semiconductor layer 3 and the metal electrode 5. I knew it was.

That is, the dielectric layer 4 is replaced by the auxiliary capacitance semiconductor layer 3
In the auxiliary capacitor having a structure sandwiched between the metal electrode 5 and the metal electrode 5, a stress is applied to the dielectric layer 4 because a difference in stress occurs between the metal electrode 5 and the dielectric layer 4 during high-temperature heat treatment such as annealing. And, in the case of the auxiliary capacitance shown in FIG.
Side edges in the longitudinal direction of the auxiliary capacitance semiconductor layer 3 via the dielectric.
Is the strongest at the edge of the metal electrode 5 in the longitudinal direction, and cracks occur in the dielectric layer 4 along the edge of the metal electrode 5 in the longitudinal direction. Current leakage may occur between the capacitive semiconductor layer 3 and the metal electrode 5, and a point defect defect may occur.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a flat display device capable of preventing a defect of a point defect caused by a current leak between a metal electrode and an auxiliary capacitance semiconductor layer. And

[0011]

The present invention comprises a plurality of display elements arranged in a matrix and an auxiliary capacitance for holding a voltage for driving the display element, wherein the auxiliary capacitance is
Long metal electrodes arranged in common for each row of the display elements and island-shaped electrodes provided for each of the display elements so that their ends are located inside both longitudinal edges of the metal electrodes. And a dielectric layer located between the metal electrode and the auxiliary capacitance semiconductor layer. The auxiliary capacitance semiconductor layer has an end located inside both side edges in the longitudinal direction of the metal electrode. Since the auxiliary capacitance semiconductor layer and the metal electrode do not overlap the auxiliary capacitance semiconductor layer on both sides in the longitudinal direction of the metal electrode via the dielectric layer, even if a difference in stress occurs between the metal electrode and the dielectric layer, the auxiliary capacitance Stress is hard to be applied to the dielectric layer on the semiconductor layer, and even if a crack occurs in the dielectric layer at the end of the metal electrode, current leakage does not occur between the auxiliary capacitance semiconductor layer and the metal electrode, and point defects are less likely to occur. .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type liquid crystal display device according to an embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 3, the liquid crystal display device 10 has a pixel portion 12 in which display elements 11 are arranged in a matrix.
A frame portion 13 is formed around two adjacent sides of the pixel portion 12, and an X-driver portion 14X and a Y-driver portion which are drive circuit portions for driving the pixel portion 12 are formed on each side of the frame portion 13. 1
4Y is formed.

The liquid crystal display device 11 is constructed as shown in FIG. 2, in which the matrix array substrate 15 and the counter substrate 16 are provided so as to face each other, and the light is provided between the matrix array substrate 15 and the counter substrate 16. A liquid crystal layer 17 is sandwiched and formed as a modulation layer. In this way, the display element 11 is configured by sandwiching the liquid crystal layer 17 in a pair of electrodes.

First, in the matrix array substrate 15, an undercoat layer 22 having a film thickness of 50 nm is formed on an insulating substrate 21 such as transparent glass, and on the undercoat layer 22,
Pixel thin film transistor (Th
An in-film transistor 23, an auxiliary capacitor 24, a P-type drive circuit thin film transistor 25, and an N-type drive circuit thin film transistor 26 are formed.

In the pixel thin film transistor 23, a semiconductor layer 31 of polycrystalline silicon having a film thickness of 50 nm to be an active layer is formed on the undercoat layer 22, and the semiconductor layer 31 has a source region 33 containing impurities of a predetermined concentration. And a drain region 34, a channel portion 32 formed at a position corresponding to the gate electrode and containing an impurity at a concentration lower than a predetermined concentration or in an intrinsic state, and an LDD disposed between the channel portion 32 and the source region 33. (Lightly Doped Drain) Area 35,
And an LDD region 36 arranged between the channel portion 32 and the drain region 34.

Further, as one electrode of the auxiliary capacitor 24, an auxiliary capacitor semiconductor layer 37 of polycrystalline silicon containing an impurity having a concentration substantially equal to a predetermined concentration is formed in an island shape corresponding to each display element 11, As shown in FIG. 1, the auxiliary capacitance semiconductor layer 37 has a long rectangular shape, and a connecting portion is provided at the substantially center on one side in the longitudinal direction.
38 is formed to project. The auxiliary capacitance semiconductor layer 37 has a taper angle (an inner angle of the semiconductor layer formed by the main surface of the insulating substrate 21 and the sidewall surface of the semiconductor layer) θ of 45 ° or less in order to prevent leakage at the end. ing.

Further, a thin film transistor for a P-type drive circuit
25 is a film thickness of 50 n which becomes an active layer on the undercoat layer 22.
m semiconductor layer 41 is formed, and the semiconductor layer 41 includes a drain region 43 and a source region 44 containing impurities of a predetermined concentration,
And a channel portion 42 which is formed at a position corresponding to the gate electrode and contains an impurity having a concentration lower than a predetermined concentration or is in an intrinsic state.

Further, in the N-type drive circuit thin film transistor 26, a semiconductor layer 45 is formed on the undercoat layer 22, and the semiconductor layer 45 includes a drain region 47 and a source region 48 containing impurities of a predetermined concentration, and a gate electrode. And an LDD region 49 formed between the channel region 46 and the drain region 47, which is formed at a position corresponding to the above and contains an impurity at a concentration lower than a predetermined concentration or is in an intrinsic state, and a channel region.
46 and a LDD region 50 disposed between the source region 48, respectively, and formed in the same structure as the pixel thin film transistor 23.

Further, the semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, the semiconductor layer 41 having a film thickness of 50 nm which becomes the active layer of the P-type drive circuit thin film transistor 25, and the N-type drive circuit thin film transistor. A gate insulating film 51 of silicon oxide (SiO _x ) as a dielectric layer that also functions as a dielectric is formed on the semiconductor layer 45 of 26.

Furthermore, on the channel portion 32 of the semiconductor layer 31 of the pixel thin film transistor 23 via the gate insulating film 51, for example, molybdenum tungsten (Mo) having a film thickness of 300 nm is used.
A gate electrode 52 of W) alloy is formed. Further, as shown in FIG. 1, the gate electrode 52 is formed so as to project in a direction orthogonal to the longitudinal direction of the scanning line 53, and the scanning lines 53 are provided in parallel.

Further, a metal electrode 54 of molybdenum-tungsten alloy having a film thickness of 300 nm is formed on the auxiliary capacitance semiconductor layer 37 via the gate insulating film 51. The metal electrode 54 is, as shown in FIG. The storage capacitor semiconductor layer 37 has a longitudinal shape and is arranged in parallel with the display elements 11 in parallel with the display elements 11.
Both sides in the longitudinal direction are located inside both side edges in the longitudinal direction of the metal electrode 54, and edges on both sides in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 are formed so as not to overlap with the metal electrode 54 in the plane direction.

That is, the end portion of the metal electrode 54 and the auxiliary capacitance semiconductor layer 37 are planarly overlapped only on the connection portion 38.
Except for 38, the metal electrode 54 is at the end of the auxiliary capacitance semiconductor layer 37.
Is formed on the inner side of the end portion of. With such a structure, even if the dielectric is damaged at the end of the metal electrode 54,
Leakage between the metal electrode 54 and the auxiliary capacitance semiconductor layer 37 can be suppressed.

Further, the channel portion 42 of the semiconductor layer 41 of the P-type drive circuit thin film transistor 25 via the gate insulating film 51.
A gate electrode 52 of molybdenum-tungsten alloy having a film thickness of 300 nm is formed thereon, and molybdenum having a film thickness of 300 nm is formed on the channel portion 46 of the semiconductor layer 45 of the transistor 26 for the N-type drive circuit via the gate insulating film 51. A gate electrode 56 of tungsten alloy is formed.

Further, on the gate electrode 52 of the pixel thin film transistor 23, the metal electrode 54 of the auxiliary capacitance semiconductor layer 37, the gate electrode 52 of the P type drive circuit thin film transistor 25 and the gate electrode 56 of the N type drive circuit thin film transistor 26. An interlayer insulating film 57 of silicon oxide having a film thickness of 600 nm is formed.

Further, the interlayer insulating film 57 and the gate insulating film
The source region 33 of the pixel thin film transistor 23 is penetrated through 51.
Reaching contact hole 61, thin film transistor for pixel
A contact hole 62 reaching the drain region 34 of 23 and a contact hole reaching the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24.
63, drain region of thin film transistor 25 for P-type drive circuit
A contact hole 64 reaching 43 and a contact hole reaching the source region 44 of the P-type drive circuit thin film transistor 25.
65, drain region of thin film transistor 26 for N-type drive circuit
A contact hole 66 that reaches 47 and a contact hole 67 that reaches the source region 48 of the N-type drive circuit thin film transistor 26 are formed.

Here, the contact hole 63 is a metal electrode.
It is arranged outside both ends of 54 and has no structure in the metal electrode 54 on the auxiliary capacitance semiconductor layer 37. As described above, by reducing the portion where the side wall of the metal electrode 54 is formed on the auxiliary capacitance semiconductor layer 37, the occurrence of current leakage can be prevented.

The contact hole 66 has a source electrode contacting the source region 33 of the pixel thin film transistor 23.
71, a signal line 72 is integrally provided on the source electrode 71, and the signal line 72 is a scanning line as shown in FIG.
Plural pieces are provided in a direction orthogonal to 53 and the metal electrode 54. Therefore, the pixel thin film transistors 23 are arranged at the respective intersections of the signal lines 72 and the scanning lines 53.

Further, a drain electrode 73 which also serves to connect the drain region 34 of the pixel thin film transistor 23 and the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24 to each other is provided in the contact hole 62 and the contact hole 63, and the contact hole 64 is provided. Is a drain electrode 74 connected to the drain region 43 of the P-type drive circuit thin film transistor 25, and a contact hole 65 is a source electrode 75 connected to the source region 44 of the P-type drive circuit thin film transistor 25 and a contact hole 66.
Is the drain region of the thin film transistor 26 for N-type drive circuit
A drain electrode 76 connected to 47 and a contact hole 67 are provided with a source electrode 77 connected to the source region 48 of the N-type drive circuit thin film transistor 26. In addition,
These source electrode 71, drain electrode 73, drain electrode 7
4, source electrode 75, drain electrode 76 and source electrode 77
Is formed of a simple substance such as aluminum (Al) or a laminated film or an alloy film with a film thickness of 600 nm.

Further, the source electrode 71, the drain electrode 73, the drain electrode 74, the source electrode 75, and the drain electrode 76.
And silicon nitride (SiN _x ) on the source electrode 77.
A protective insulating film 78 is formed, and a contact hole 79 exposing the drain electrode 73 of the pixel thin film transistor 23 is formed in the protective insulating film 78.

On the protective insulating film 78, a color filter layer 80 having a film thickness of 2 μm, which is an organic insulating film in which pigmented red, green, or blue colored layers of three colors are formed in stripes, is formed. A contact hole 81 exposing the drain electrode 73 of the pixel thin film transistor 23 is also formed in the color filter layer 80.

Further, in a portion surrounded by the scanning line 53 and the signal line 72 shown in FIG. 1 of the color filter layer 80, ITO (Indium tin Oxid) having a film thickness of 1 μm as a display electrode is used.
The pixel electrode 82 of e) is formed, and this pixel electrode 82 is electrically connected to the drain electrode 73 of the pixel thin film transistor 23.

A color filter layer including the pixel electrode 82
An alignment film 83 that has been rubbed by printing and applying low temperature cure type polyimide is formed on the surface 80.

On the other hand, the counter substrate 16 is an ITO counter electrode having a thickness of 100 nm on a transparent insulating glass substrate 91.
93 is formed, and a rubbing-treated alignment film 94 is formed on the counter electrode 93.

A liquid crystal layer 17 is sealed and sandwiched between the matrix array substrate 15 and the counter substrate 16, and deflection plates 96 and 97 are attached to the opposite surfaces of the matrix array substrate 15 and the counter substrate 16, respectively. Has been done.

Next, a method of manufacturing the liquid crystal display device 10 will be described.

First, by a plasma CVD (Chemical Vapor Deposition) method on an insulating substrate 21 such as glass,
Undercoat layer 22 of silicon oxide film, semiconductor layer 31 of pixel thin film transistor 23, auxiliary capacitance semiconductor layer 37 of auxiliary capacitance 24, semiconductor layer 41 of P-type drive circuit thin film transistor 25, and semiconductor layer of N-type drive circuit thin film transistor 26. An amorphous silicon thin film to be 45 is formed with a film thickness of about 50 nm.

The amorphous silicon film is ion-doped by an accelerating voltage of 10 keV, a dose of 4 × 10 ¹¹ atoms / cm ² , and B ₂ H ₆ / H ₂ as a source gas of boron (B). ) Is injected at a low concentration.

Next, the amorphous silicon film is polycrystallized by an ELA (excimer laser-annealing) method to form a polycrystal silicon film, and the polycrystal silicon film is etched into an island shape by a photolithography process to form a pixel. The semiconductor layer 31 of the thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, the semiconductor layer of the P-type drive circuit thin film transistor 25.
41 and semiconductor layer of thin film transistor 26 for N-type drive circuit
Forming 45.

Thereafter, the semiconductor layer 31 of the pixel thin film transistor 23, the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, and the P-type drive circuit thin film transistor 25 are formed by the plasma CVD method.
Semiconductor layer 41 and thin film transistor 26 for N-type drive circuit
A gate insulating film 51 of silicon oxide having a film thickness of 140 nm is formed on the entire surface of the undercoat layer 22 including the semiconductor layer 45.

Next, a resist film is formed on the gate insulating film 51, and the resist film is patterned into a predetermined shape to serve as a mask, and the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24,
Source region 33 of the semiconductor layer 31 of the pixel thin film transistor 23
And the drain region 34, and the drain region 47 and the source region 48 of the semiconductor layer 45 of the N-type drive circuit thin film transistor 26.
And acceleration voltage 70 keV, 2 × 10 ¹⁵ atoms / cm
The PH ₃ / H ₂ is injected at a high concentration of phosphorus (P) as the source gas in the ^second dose.

Then, the resist used as the mask is removed,
A molybdenum-tungsten alloy film is deposited to a thickness of about 300 nm on the entire surface of the gate insulating film 51 by the sputtering method. The molybdenum-tungsten alloy film on the channel portion 42 of the P-type drive circuit thin film transistor 25 is patterned into a predetermined shape by a photolithography process to form a gate electrode 55. Then, using the gate electrode 55 as a mask, an acceleration voltage of 80 keV and a dose of 2 × 10 ¹⁵ a
thin film transistor for P-type drive circuit by injecting boron at a high concentration with B ₂ H ₆ / H ₂ as source gas at toms / cm ^2.
25 drain regions 43 and source regions 44 are formed.

Further, the molybdenum-tungsten alloy film on the pixel thin film transistor 23, the auxiliary capacitor 24 and the N-type driving circuit thin film transistor 26 is patterned into a predetermined shape, and the gate electrode 52, N of the pixel thin film transistor 23 is formed.
The gate electrode 56 of the thin film transistor 26 for the mold drive circuit and the metal electrode 54 of the auxiliary capacitance 24 are formed. At this time, the metal electrode 54 of the auxiliary capacitance 24 sufficiently covers the auxiliary capacitance semiconductor layer 37, and the side edge in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 is located inside the longitudinal side edge of the metal electrode 54 in plan view. Pattern.

After this, the gate of the pixel thin film transistor 23 is
Gate electrode 52 and the thin film transistor 26 for N-type drive circuit
With the gate electrode 56 as a mask, the acceleration voltage is 80 keV, 5 ×
10 ¹³atoms / cm²PH at the dose amount of₃/ H₂By
Injecting phosphorus at a low concentration,
Thin film transistor for LDD regions 35 and 36 and N type drive circuit
LDD regions 49, 50 of the data 26 are formed. After this, 600
Activate the implanted impurities by annealing for 1 hour at ℃
Turn into

Next, a gate including the gate electrode 52 of the pixel thin film transistor 23, the metal electrode 54 of the auxiliary capacitor 24, the gate electrode 55 of the P type drive circuit thin film transistor 25 and the gate electrode 56 of the N type drive circuit thin film transistor 26. A film thickness of 60 is formed on the entire surface of the insulating film 51 by using the plasma CVD method.
An 0 nm silicon oxide interlayer insulating film 57 is deposited.

Subsequently, a contact hole 61 reaching the source region 33 of the pixel thin film transistor 23 is formed in the interlayer insulating film 57 and the gate insulating film 51 by photoetching.
A contact hole 62 reaching the drain region 34 of the pixel thin film transistor 23, a contact hole 63 reaching the auxiliary capacitance semiconductor layer 37 of the auxiliary capacitance 24, a contact hole 6 reaching the drain region 43 of the P-type drive circuit thin film transistor 25.
4. Source region 44 of P-type driving circuit thin film transistor 25
To reach the drain region 47 of the N-type drive circuit thin film transistor 26.
66, and a contact hole 67 reaching the source region 48 of the N-type drive circuit thin film transistor 26 is formed.

Next, a simple substance such as aluminum or a laminated film or an alloy film is deposited to a thickness of about 600 nm and patterned into a predetermined shape by a photo-etching method, and the source electrode 71 of the pixel thin film transistor 23 and a signal integrated with the source electrode 71. The line 72 and the drain electrode 73, the drain electrode 74 and the source electrode 75 of the P-type drive circuit thin film transistor 25,
The drain electrode 76 and the source electrode 77 of the N-type drive circuit thin film transistor 26 are formed.

Furthermore, these pixel thin film transistors 23
Source electrode 71, a signal line 72 and a drain electrode 73 integrated with the source electrode 71, a drain electrode 74 and a source electrode 75 of the P-type drive circuit thin film transistor 25, and a drain electrode 76 and a source electrode 77 of the N-type drive circuit thin film transistor 26.
A protective insulating film 78 of silicon nitride is formed on the inter-layer insulating film 57 containing silicon by a plasma CVD method, and a contact hole 79 exposing the drain electrode 73 of the pixel thin film transistor 23 is formed by a photoetching method.

Next, a transparent organic insulating film of three colored layers of red, green and blue in which pigments are dispersed is applied in a stripe pattern to a thickness of 2 μm to form a color filter layer 80.
Similarly, a contact hole 81 exposing the drain electrode 73 of the pixel thin film transistor 23 is formed.

Then, ITO is sputtered to a film thickness of 1
A film having a thickness of about 00 nm is formed and patterned into a predetermined shape by a photoetching method to form a pixel electrode 82.

Finally, low temperature cure type polyimide is printed and applied on the protective insulating film 78 including the pixel electrodes 82, and the alignment film 83 is formed by rubbing to form the matrix array substrate 15.

On the other hand, on the counter substrate 16, ITO is formed into a film having a thickness of about 100 nm by a sputtering method to form a counter electrode 93.

On the counter electrode 93, polyimide is applied by printing, and a rubbing process is performed to form an alignment film 94, whereby the counter substrate 16 is formed.

Matrix array substrate formed in this way
The liquid crystal layer 17 is formed by injecting liquid crystal into the gap between the matrix array substrate 15 and the counter substrate 16 and sealing them by making 15 and the counter substrate 16 face each other through a gap to form a cell.

Then, the liquid crystal display device 10 is formed by attaching the deflection plates 96 and 97 to the opposite sides of the matrix array substrate 15 and the counter substrate 16.

According to the above-described embodiment, both sides in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 are located inside the both side edges in the longitudinal direction of the metal electrode 54, and the edges on both sides in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 are made of metal. Since it is formed so as not to overlap the electrode 54 in the planar direction, it is a metal electrode during high temperature heat treatment such as annealing.
There is a difference in stress between the gate insulating film 51 and the gate insulating film 51.
Even if stress is applied to the metal electrode 54
Since the side edges in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 do not overlap with each other, even if a crack occurs in the gate insulating film 51, a current flows between the auxiliary capacitance semiconductor layer 37 and the metal electrode 54 through the crack in the gate insulating film 51. Leakage is prevented and point defect defects are suppressed.

Further, the auxiliary capacitance semiconductor layer 37 is positioned inside the metal electrode 54 in the width direction, and there are portions on both sides in the longitudinal direction of the auxiliary capacitance semiconductor layer 37 where the metal electrode 54 does not overlap with the auxiliary capacitance semiconductor layer 37. Therefore, even if a break occurs in the metal electrode 54 at the portion that goes over the step due to the edge of the auxiliary capacitance semiconductor layer 37, the metal electrode 54 at the portion that does not overlap with the auxiliary capacitance semiconductor layer 37 should be cut off. Since it does not extend, it is possible to prevent the metal electrode 54 which is a disconnection of the auxiliary capacitance line.

In the above-mentioned embodiments, the liquid crystal display device has been described as an example of the flat display device, but the present invention is not limited to this, and can be applied to, for example, a self-luminous display device having a light emitting layer as a light modulation layer.

[0059]

According to the present invention, the end portion of the auxiliary capacitance semiconductor layer is located inside both side edges in the longitudinal direction of the metal electrode, and the auxiliary capacitance semiconductor layer and the metal electrode are disposed in the longitudinal direction of the metal electrode via the dielectric layer. Since both sides of the auxiliary capacitance semiconductor layer do not overlap with the auxiliary capacitance semiconductor layer, even if a difference in stress occurs between the metal electrode and the dielectric layer, stress is less likely to be applied to the dielectric layer on the auxiliary capacitance semiconductor layer and Even if cracks occur, current leakage does not occur between the auxiliary capacitance semiconductor layer and the metal electrode, and it is possible to prevent point defects and the like from occurring.

[Brief description of drawings]

FIG. 1 is a plan view showing approximately one pixel of a matrix array substrate of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a liquid crystal display device of the above.

FIG. 3 is a plan view showing the above-mentioned liquid crystal display device.

FIG. 4 is a plan view showing a relationship between a metal electrode and a storage capacitor semiconductor layer in a conventional example.

5 is a sectional view taken along line AA of FIG.

[Explanation of symbols]

11 Display element 17 Liquid crystal layer 23 Thin film transistor for pixel as switching element 24 Auxiliary capacitance 37 Auxiliary capacitance semiconductor layer 38 Connection part 51 Gate insulating film as dielectric layer 54 Metal electrode 82 Pixel electrode as display electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/336 H01L 27/08 331E 21/822 29/78 612D 27/04 27/04 C 27/08 331 29/786 F-term (reference) 2H092 JA25 JA34 JA37 JA41 JA46 JB22 JB31 JB63 KB04 KB13 KB25 MA08 MA13 MA18 MA27 MA30 NA16 NA22 NA24 NA29 PA06 5C094 AA03 AA25 BA03 BA43 CA19 DA15 EA04 EA07 HA08 5F038 AC05 AC15 AC20 AV10 E6 AV20 E15 AV06 E15 BB09 BB12 BC06 BC11 BF03 BF11 BF16 5F110 AA26 BB02 BB04 CC02 DD02 DD13 EE06 EE44 FF02 FF30 GG02 GG13 GG25 GG32.

Claims (5)

[Claims] 1. A display device, comprising: a plurality of display elements arranged in a matrix; and an auxiliary capacitance for holding a voltage for driving the display element, wherein the auxiliary capacitance is commonly arranged for each row of the display elements. A long metal electrode; an auxiliary capacitance semiconductor layer which is provided for each of the display elements and is formed in an island shape so that the end portions thereof are located inside both side edges of the metal electrode in the longitudinal direction; A flat panel display device comprising: a dielectric layer located between the auxiliary capacitance semiconductor layers. 2. The flat display device according to claim 1, wherein the display electrodes are provided in a matrix and each of the display electrodes includes a switching element connected to the display electrode. 3. The flat display device according to claim 1, wherein the auxiliary capacitance semiconductor layer has a connecting portion which projects from a side edge in the longitudinal direction and intersects a side edge in the longitudinal direction of the metal electrode. 4. The flat-panel display device according to claim 1, wherein the semiconductor layer for auxiliary capacitance has an entire surface in which impurities are implanted at a high concentration. 5. The flat panel display device according to claim 1, further comprising a liquid crystal layer that operates based on the display electrode.