JP2003031423A - Laminated chip component - Google Patents
Laminated chip componentInfo
- Publication number
- JP2003031423A JP2003031423A JP2001210959A JP2001210959A JP2003031423A JP 2003031423 A JP2003031423 A JP 2003031423A JP 2001210959 A JP2001210959 A JP 2001210959A JP 2001210959 A JP2001210959 A JP 2001210959A JP 2003031423 A JP2003031423 A JP 2003031423A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- chip component
- planes
- extraction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010030 laminating Methods 0.000 claims abstract description 10
- 238000000605 extraction Methods 0.000 claims description 72
- 238000005452 bending Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 10
- 229910000859 α-Fe Inorganic materials 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 238000007639 printing Methods 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- 238000010304 firing Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000004804 winding Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Coils Or Transformers For Communication (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、内部電極を積層し
た積層構造のチップ部品に関し、特に、積層方向に略直
交する平面に形成された引出電極を有する積層チップ部
品に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component having a laminated structure in which internal electrodes are laminated, and more particularly to a laminated chip component having an extraction electrode formed on a plane substantially orthogonal to the laminating direction.
【0002】[0002]
【従来の技術】従来、積層方向にコイルを形成するいわ
ゆる縦巻型積層構造のチップコイルでは、内部電極と外
部電極を接続するための引出電極の構造として図8のよ
うな積層方向に垂直な平面の一方向に電極を引出した帯
状の引出電極51が公知である。しかし、かかる構造で
は焼成時における電極収縮のために接続不良が発生し易
く、かかる不具合を低減させるため電極の引出幅を大き
くとる目的で、図9(a)のように積層方向に垂直な外
部平面61と62の隅部に三角形状の引出電極52を形
成したり、図9(b)のように外部平面61と62の略
全幅にL字状の引出電極53を形成した引出電極構造が
公知である(特開平11−162737号公報参照)。2. Description of the Related Art Conventionally, in a so-called vertical winding type laminated coil in which a coil is formed in the stacking direction, the structure of an extraction electrode for connecting an internal electrode and an external electrode is perpendicular to the stacking direction as shown in FIG. A strip-shaped extraction electrode 51 in which an electrode is extracted in one direction of a plane is known. However, in such a structure, connection failure is likely to occur due to electrode contraction during firing, and in order to increase the electrode withdrawal width in order to reduce such a problem, an external portion perpendicular to the stacking direction as shown in FIG. 9A is used. An extraction electrode structure in which triangular extraction electrodes 52 are formed at the corners of the flat surfaces 61 and 62, or an L-shaped extraction electrode 53 is formed over substantially the entire width of the outer flat surfaces 61 and 62 as shown in FIG. It is known (see Japanese Patent Laid-Open No. 11-162737).
【0003】ところが、引出電極自体は積層構造におい
ては非密着部分となり、図9(a),(b)のように、
外部平面に引き出され露出する電極全体の周長が長くな
り過ぎると、非密着部分が外部平面で多くなるためチッ
プ実装時におけるたわみ強度や抗折強度が低下し、例え
ば外部平面に露出する線状の電極部分がクラック発生の
起点になって割れ易くなる傾向になるという問題があっ
た。However, the extraction electrode itself is a non-adhesive portion in the laminated structure, and as shown in FIGS. 9 (a) and 9 (b),
If the circumference of the entire electrode exposed and exposed to the external plane becomes too long, the non-adhesive area will increase in the external plane, and the bending strength and bending strength during chip mounting will decrease. There was a problem that the electrode part of (1) became a starting point of crack generation and tended to be easily broken.
【0004】[0004]
【発明が解決しようとする課題】本発明は、上述のよう
な従来技術の問題に鑑み、積層方向に略直交する平面に
形成した引出電極において接続不良を防止しかつ実装時
におけるたわみ強度や抗折強度を向上させることのでき
る積層チップ部品を提供することを目的とする。SUMMARY OF THE INVENTION In view of the problems of the prior art as described above, the present invention prevents the connection failure in the extraction electrode formed on the plane substantially orthogonal to the stacking direction, and prevents the bending strength and the resistance during mounting. It is an object of the present invention to provide a laminated chip part capable of improving folding strength.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明による積層チップ部品は、外部電極と積層さ
れた内部電極とを接続するための引出電極を積層方向に
略直交する少なくとも2つの内部平面に形成して前記積
層方向と略平行な外部平面に引き出した積層チップ部品
であって、前記引出電極は前記各内部平面において前記
外部平面から内側にずれた位置で前記外部平面に引き出
された外面電極部よりも幅広に形成されていることを特
徴とする。In order to achieve the above object, a laminated chip component according to the present invention has at least two lead electrodes for connecting an external electrode and a laminated internal electrode which are substantially orthogonal to the laminating direction. A multilayer chip component formed on two internal planes and drawn out to an external plane substantially parallel to the stacking direction, wherein the extraction electrodes are drawn out to the external planes at positions displaced inward from the external planes in the internal planes. It is characterized in that it is formed wider than the outer surface electrode portion.
【0006】この積層チップ部品によれば、外部平面に
引き出されて露出する外面電極部が比較的幅狭に構成さ
れるので、外部平面において外面電極部の周長が長くな
り過ぎずに積層構造における非密着部分が少なくなり密
着し、従来構造よりも実装時におけるたわみ強度や抗折
強度が向上する。更に、外部平面から内部に入った位置
では引出電極は比較的幅広に構成されるので、接続不良
を防止でき、引出電極により確実に内部電極と外部電極
とを接続することができる。According to this laminated chip component, since the outer surface electrode portion that is pulled out and exposed to the outer flat surface is configured to have a relatively narrow width, the peripheral length of the outer surface electrode portion on the outer flat surface does not become too long and the laminated structure is obtained. The non-adhered portion in the area is reduced and adhered, and the flexural strength and bending strength during mounting are improved as compared with the conventional structure. Further, since the extraction electrode is relatively wide at the position where the extraction electrode enters the inside from the external plane, it is possible to prevent connection failure, and it is possible to reliably connect the internal electrode and the external electrode by the extraction electrode.
【0007】また、前記少なくとも2つの内部平面に形
成された引出電極は前記各外面電極部が対称位置になる
ように互いに異なる外部平面に引き出されることが好ま
しい。これにより、積層チップ部品の実装時における実
装方向の違いによる電気特性差の発生を回避できる。Further, it is preferable that the lead-out electrodes formed on the at least two inner planes are led out on different outer planes so that the outer surface electrode portions are located at symmetrical positions. As a result, it is possible to avoid the occurrence of a difference in electrical characteristics due to a difference in mounting direction when mounting the laminated chip component.
【0008】また、前記各引出電極は複数の前記外面電
極部を有し、前記各外面電極部がそれぞれ複数の異なる
外部平面に引き出されることが好ましい。これにより、
接続不良の発生を更に低減することができ、より確実に
引出電極を外部電極に接続することができる。Further, it is preferable that each of the extraction electrodes has a plurality of the outer surface electrode portions, and each of the outer surface electrode portions is extracted to a plurality of different outer planes. This allows
Occurrence of connection failure can be further reduced, and the extraction electrode can be more reliably connected to the external electrode.
【0009】また、前記外部電極は前記外面電極部の形
成された外部平面部分と前記外部平面と略直交する端面
とに形成される。Further, the external electrode is formed on an external plane portion where the external electrode portion is formed and an end surface which is substantially orthogonal to the external plane.
【0010】[0010]
【発明の実施の形態】以下、本発明による実施の形態の
積層チップ部品について図面を用いて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, laminated chip parts according to embodiments of the present invention will be described with reference to the drawings.
【0011】図1は本実施の形態による積層チップ部品
の製造工程を説明するために各電極を示す平面図であ
り、図2は図1の製造工程を示すフローチャートであ
り、図3は図1、図2の製造工程により製造された積層
チップ部品の積層体を示す斜視図であり、図4は図3の
積層体に外部電極を形成して完成した積層チップ部品を
示す斜視図である。FIG. 1 is a plan view showing each electrode for explaining the manufacturing process of the laminated chip part according to the present embodiment, FIG. 2 is a flow chart showing the manufacturing process of FIG. 1, and FIG. 2 is a perspective view showing a laminated body of laminated chip components manufactured by the manufacturing process of FIG. 2, and FIG. 4 is a perspective view showing a laminated chip component completed by forming external electrodes on the laminated body of FIG.
【0012】図4に示す積層チップ部品9は、内部電極
を図の積層方向mに多数積層して巻線状にコイル部を形
成してから図3の両端面5,6に外部電極7,8を形成
し全体として矩方体状に形成した積層構造を持つ小型チ
ップ部品であり、電子機器等のプリント基板等に実装さ
れる。積層チップ部品9の内部には積層方向mにコイル
中心を有するコイル部が形成される。In the multilayer chip component 9 shown in FIG. 4, a large number of internal electrodes are stacked in the stacking direction m in the figure to form a coil portion in a winding shape, and then the external electrodes 7, 6 are formed on both end surfaces 5, 6 of FIG. It is a small chip component having a laminated structure in which 8 is formed to have a rectangular parallelepiped shape as a whole, and is mounted on a printed circuit board or the like of an electronic device or the like. Inside the laminated chip component 9, a coil portion having a coil center in the laminating direction m is formed.
【0013】図1,図2を参照しながら図4の積層チッ
プ部品9の製造工程を説明しながら内部構造について説
明する。まず、図1(a)のように、第1の引出電極1
1を形成するため銀ペーストをフェライト板10の平面
上に公知の印刷法で塗布する(S01)。フェライト板
は比較的広く、図1(a)の同様のパターンが多数形成
され、各パターンの上に後述のように複数のパターンが
積層されていく。The internal structure will be described with reference to FIGS. 1 and 2 and the manufacturing process of the layered chip component 9 of FIG. First, as shown in FIG. 1A, the first extraction electrode 1
In order to form No. 1, silver paste is applied on the flat surface of the ferrite plate 10 by a known printing method (S01). The ferrite plate is relatively wide, and many patterns similar to those of FIG. 1A are formed, and a plurality of patterns are laminated on each pattern as described later.
【0014】図1(a)に示すように、上述の第1の引
出電極11は、図3、図4のように完成後の積層チップ
部品9の積層方向mに平行な外部平面1〜4の内の外部
平面4に引き出され露出するように幅狭の帯状に形成さ
れた外面電極部11aと、外部平面4の幅方向に沿って
内面側にずれた位置に外面電極部11aよりも幅広に形
成された内面電極部11bと、外部平面3に引き出され
露出するように幅狭の帯状に形成された外面電極部11
cと、外部平面3の幅方向に沿って内面側にずれた位置
に外面電極部11cよりも幅広に形成された内面電極部
11dとを一体に備えているAs shown in FIG. 1A, the above-mentioned first extraction electrode 11 has external planes 1 to 4 parallel to the laminating direction m of the completed laminated chip component 9 as shown in FIGS. Of the outer surface electrode portion 11a formed in a narrow band so as to be drawn out and exposed to the outer flat surface 4 of the inner surface, and wider than the outer surface electrode portion 11a at a position displaced toward the inner surface side along the width direction of the outer flat surface 4. The inner surface electrode portion 11b formed on the outer surface and the outer surface electrode portion 11 formed in a narrow strip shape so as to be drawn out and exposed on the outer flat surface 3.
c and an inner surface electrode portion 11d that is wider than the outer surface electrode portion 11c at a position displaced inward along the width direction of the outer flat surface 3 are integrally provided.
【0015】次に、図1(a)の第1の引出電極11を
塗布したフェライト板10の図の右半面にフェライトペ
ーストを印刷法で塗布し(S02)、次に、その上に、
図1(b)のように、コイル部を形成する半ターン分の
パターン13を形成するため銀ペーストを塗布する(S
03)。このとき、パターン13の一端部13aが図1
(a)の第1の引出電極11の内面電極部11bの一端
部11eと接続するように塗布する。Next, a ferrite paste is applied by a printing method to the right half surface of the drawing of the ferrite plate 10 on which the first extraction electrode 11 of FIG. 1 (a) is applied (S02), and then, thereon.
As shown in FIG. 1B, silver paste is applied to form a pattern 13 for a half turn forming a coil portion (S
03). At this time, one end portion 13a of the pattern 13 is shown in FIG.
It is applied so as to be connected to one end portion 11e of the inner surface electrode portion 11b of the first extraction electrode 11 of (a).
【0016】次に、上述の半ターン分のパターン13を
塗布した図1(b)の左半面にフェライトペーストを印
刷法で塗布し(S02)、次に、その上に、図1(c)
のように、コイル部を形成するもう1つの半ターン分の
パターン14を形成するため銀ペーストを印刷法で塗布
する(S03)。このとき、パターン14の一端部14
aが図1(b)のパターン13の他端部13bと接続す
るように塗布する。このようにして形成したパターン1
3とパターン14とでコイル部の1ターン(1巻線)分
が形成される。Next, a ferrite paste is applied by a printing method to the left half surface of FIG. 1 (b) on which the pattern 13 for the above-mentioned half turn is applied (S02), and then on top of that, FIG. 1 (c).
As described above, the silver paste is applied by the printing method to form the pattern 14 for another half turn forming the coil portion (S03). At this time, one end portion 14 of the pattern 14
It is applied so that a is connected to the other end 13b of the pattern 13 of FIG. 1 (b). Pattern 1 formed in this way
3 and the pattern 14 form one turn (one winding) of the coil portion.
【0017】上述のようにして、フェライトペーストの
塗布及びコイル部形成のための銀ペーストの塗布の各工
程(S02、S03)を所定の巻数のコイル部を形成す
るまで繰り返し(S04)、コイル部を図3,図4の積
層方向m(図1の紙面垂直方向)に積層して形成する。As described above, the steps of applying the ferrite paste and the silver paste for forming the coil portion (S02, S03) are repeated until the coil portion having a predetermined number of turns is formed (S04), and the coil portion is formed. Are stacked in the stacking direction m shown in FIGS. 3 and 4 (the direction perpendicular to the paper surface of FIG. 1).
【0018】次に、上述のようにして形成されたコイル
部の図1(c)のパターン14と同様の最上層のパター
ンを塗布した図1(c)と同様の右半面にフェライトペ
ーストを印刷法で塗布し(S05)、次に、その上に、
図1(d)のように、第2の引出電極12を形成するた
め銀ペーストを印刷法で塗布する(S06)。Next, a ferrite paste is printed on the right half surface of FIG. 1 (c) in which the uppermost layer pattern similar to the pattern 14 of FIG. 1 (c) of the coil portion formed as described above is applied. Method (S05), and then,
As shown in FIG. 1D, silver paste is applied by a printing method to form the second extraction electrode 12 (S06).
【0019】図1(d)に示すように、上述の第2の引
出電極12は、第1の引出電極11と同様に構成され、
図3,図4のように外部平面1〜4の内の外部平面1に
引き出され露出するように幅狭の帯状に形成された外面
電極部12aと、外部平面1の幅方向に沿って内面側に
ずれた位置に外面電極部12aよりも幅広に形成された
内面電極部12bと、外部平面2に引き出され露出する
ように幅狭の帯状に形成された外面電極部12cと、外
部平面2の幅方向に沿って内面側にずれた位置に外面電
極部11cよりも幅広に形成された内面電極部11dと
を一体に備えている。As shown in FIG. 1D, the above-mentioned second extraction electrode 12 has the same structure as the first extraction electrode 11,
As shown in FIGS. 3 and 4, the outer surface electrode portion 12a is formed in a narrow strip shape so as to be drawn out and exposed to the outer flat surface 1 of the outer flat surfaces 1 to 4, and the inner surface along the width direction of the outer flat surface 1. The inner surface electrode portion 12b formed to be wider than the outer surface electrode portion 12a at a position displaced to the side, the outer surface electrode portion 12c formed in a narrow band so as to be drawn out to the outer surface 2 and exposed, and the outer surface 2 The inner surface electrode portion 11d, which is formed wider than the outer surface electrode portion 11c, is integrally provided at a position displaced toward the inner surface side along the width direction.
【0020】上述の銀ペースト塗布時(S06)に第2
の引出電極12の内面電極部12bの一端部12eが図
1(c)のパターン14の一端部14bと同様の最上層
のパターンの一端部に接続するように塗布される。When the above-mentioned silver paste is applied (S06), the second
The one end 12e of the inner electrode portion 12b of the extraction electrode 12 is applied so as to be connected to one end of the uppermost layer pattern similar to the one end 14b of the pattern 14 of FIG.
【0021】図1(d)に示すように、上述の第2の引
出電極12は対角線cに関し図1(a)の第1の引出電
極11とほぼ対称の形状に構成され、外面電極部11a
と12cは互いに平行な外部平面4,2にそれぞれ形成
され図1の平面上で対称位置にあり、また外面電極部1
1cと12aは互いに平行な外部平面3,1にそれぞれ
形成され図1の平面上で対称位置にある。As shown in FIG. 1 (d), the above-mentioned second extraction electrode 12 is formed in a shape substantially symmetrical to the first extraction electrode 11 of FIG. 1 (a) with respect to the diagonal line c, and the outer surface electrode portion 11a.
And 12c are respectively formed on the outer planes 4 and 2 which are parallel to each other and are located symmetrically on the plane of FIG.
1c and 12a are respectively formed on outer planes 3 and 1 which are parallel to each other, and are located symmetrically on the plane of FIG.
【0022】次に、第2の引出電極12を形成した平面
上にフェライトペーストを全面に塗布してから(S0
7)、図1の四角形の破線に沿って切断し(S08)、
900℃程度の温度で焼成する(S09)。Next, a ferrite paste is applied to the entire surface on which the second lead electrode 12 is formed (S0
7), cut along the broken line of the quadrangle of FIG. 1 (S08),
Baking is performed at a temperature of about 900 ° C. (S09).
【0023】上述のようにして一対の引出電極11,1
2及びコイル部が積層され、図3のような矩方体の積層
体9’が形成されるが、次に、図3の積層体9’の端面
5を下面にして銀ペースト液に第2の引出電極12の外
面電極部12a、12cのレベルまで浸漬し乾燥させて
から(S10)、積層体9’の端面6を下面にして銀ペ
ースト液に第1の引出電極11の外面電極部11a、1
1cのレベルまで浸漬し乾燥させる(S11)。As described above, the pair of extraction electrodes 11, 1
2 and the coil portion are laminated to form a rectangular parallelepiped laminated body 9 ′ as shown in FIG. 3. Next, the end surface 5 of the laminated body 9 ′ of FIG. The outer surface electrode portions 12a and 12c of the extraction electrode 12 are soaked and dried (S10), and then the end surface 6 of the laminated body 9'is made a lower surface and the outer surface electrode portion 11a of the first extraction electrode 11 is immersed in the silver paste solution. 1
It is dipped to a level of 1c and dried (S11).
【0024】次に、900℃程度の温度で焼成する(S
12)ことにより、図4のように、端面5,6側にそれ
ぞれ第1の外部電極7及び第2の外部電極8が形成され
た積層チップ部品9が得られ、その完成品のサイズは、
例えば、幅0.8×幅0.8×長さ1.6(mm)であ
る。Next, firing is performed at a temperature of about 900 ° C. (S
12) As a result, as shown in FIG. 4, a laminated chip component 9 is obtained in which the first external electrode 7 and the second external electrode 8 are formed on the end surfaces 5 and 6, respectively, and the size of the finished product is
For example, width 0.8 x width 0.8 x length 1.6 (mm).
【0025】以上のようにして得られた積層チップ部品
9では、図3のようにコイル部の導体の両端を引出電極
11,12によりチップの積層方向mと垂直な外部平面
1〜4に引き出し、その外面電極部11a、11c、1
2a、12cと外部電極7,8とを図4のように接続
し、チップ部品を構成している。これにより、いわゆる
縦巻型積層構造のチップ部品にでき、高周波対応のコイ
ルチップ部品とすることができる。In the laminated chip component 9 obtained as described above, both ends of the conductor of the coil portion are drawn out to the external planes 1 to 4 perpendicular to the chip stacking direction m by the extraction electrodes 11 and 12, as shown in FIG. , Their outer surface electrode portions 11a, 11c, 1
2a, 12c and the external electrodes 7, 8 are connected as shown in FIG. 4 to form a chip component. As a result, a chip component having a so-called vertical winding type laminated structure can be obtained, and a coil chip component compatible with high frequency can be obtained.
【0026】また、図1(a)において、第1の引出電
極11の外面電極部11a、11cの幅a(外部平面
4、3に露出する線状の幅)は、焼成後で100〜15
0μmの範囲内にあり、内面電極部11b、11dの外
部平面4、3から内側へのずれ量bは、焼成後で100
〜150μmの範囲内にある。また、第2の引出電極1
2においても同様である。Further, in FIG. 1A, the width a (the linear width exposed on the outer flat surfaces 4 and 3) of the outer surface electrode portions 11a and 11c of the first extraction electrode 11 is 100 to 15 after firing.
Within the range of 0 μm, the amount b of displacement of the inner surface electrode portions 11b and 11d from the outer flat surfaces 4 and 3 is 100 after firing.
˜150 μm. In addition, the second extraction electrode 1
The same applies to 2.
【0027】以上のように、本実施の形態の積層チップ
部品によれば、従来構造と比較すると、図8のように積
層方向に垂直な平面の一方向に形成した引出電極では、
チップ部品を焼成した際に、引出電極自体のボリューム
が小さいため、収縮し引き込まれる接続不良を発生する
ことがあり、また図9のように引出電極の引出幅を大き
くとると、引出電極の外部平面付近におけるチップ基体
素地同士の密着面積が小さくなることによりチップ実装
時のたわみ強度や抗折強度が低下するという問題があっ
たのに対し、図1〜図4のような構造にすることで、比
較的幅狭の外面電極部により引出電極の外部平面付近に
おけるチップ基体素地同士の密着を損なうことがなくな
り、従来よりもチップ実装時におけるたわみ強度や抗折
強度が向上し、さらには、比較的幅広の内面電極部で電
極ボリュームを確保することで引出電極の収縮引込によ
る接続不良を防止することが可能となる。As described above, according to the laminated chip component of the present embodiment, as compared with the conventional structure, in the extraction electrode formed in one direction of the plane perpendicular to the lamination direction as shown in FIG.
When the chip component is fired, the volume of the extraction electrode itself is small, which may cause a connection failure in which the extraction electrode contracts and is drawn in. When the extraction width of the extraction electrode is increased as shown in FIG. Although there is a problem that the bending strength and the bending strength at the time of chip mounting are reduced due to the reduction of the contact area between the chip base materials in the vicinity of the plane, the structure shown in FIGS. , The relatively narrow outer surface electrode part does not impair the adhesion between the chip base materials in the vicinity of the outer flat surface of the extraction electrode, and the bending strength and bending strength during chip mounting are improved as compared with the conventional one. By securing the electrode volume with the wide inner electrode portion, it is possible to prevent the connection failure due to the contraction and drawing of the extraction electrode.
【0028】また、引出電極の引き出し方向を図1のよ
うに2方向とすることで引出電極の接続不良の発生度を
さらに低減することが可能である。また、積層方向の上
下にそれそれ積層チップ部品の入力端子と出力端子が引
出電極11,12として構成されるが、その入力端子側
及び出力端子側において、図1(a)、(d)のように
それぞれ対称の方向になるように引出電極の外面電極部
の位置パターンを構成したので、積層チップ部品9の実
装時の実装方向の違いによる特性差の発生を回避でき、
好ましい。Further, by setting the extraction directions of the extraction electrodes to two directions as shown in FIG. 1, it is possible to further reduce the occurrence of connection failure of the extraction electrodes. In addition, the input terminals and the output terminals of the laminated chip component are formed as the extraction electrodes 11 and 12 above and below in the stacking direction, respectively. Since the position patterns of the outer surface electrode portions of the extraction electrodes are configured so as to be symmetrical with each other, it is possible to avoid the occurrence of characteristic differences due to the difference in the mounting direction when mounting the laminated chip component 9.
preferable.
【0029】次に、図5(a)〜(e)により引出電極
の変形例を説明する。図5の例は外面電極部を1つと
し、一方向に引き出すものであり、図1と同様に印刷法
で銀ペーストとフェライトペーストの塗布を繰り返して
形成する。即ち、図5(a)に示すように、引出電極2
1をフェライト板の平面上に形成するが、この引出電極
21は、図3の外部平面1に引き出され露出するように
幅狭の帯状に形成された外面電極部21aと、外部平面
1の幅方向に沿って内面側にずれた対置に外面電極部1
2aよりも幅広に形成された内面電極部12bとを一体
に備える。Next, a modified example of the extraction electrode will be described with reference to FIGS. In the example of FIG. 5, one outer surface electrode portion is provided and is drawn out in one direction, and similarly to FIG. 1, silver paste and ferrite paste are repeatedly applied by a printing method. That is, as shown in FIG. 5A, the extraction electrode 2
1 is formed on the plane of the ferrite plate. The extraction electrode 21 has an outer surface electrode portion 21a formed in a narrow strip shape so as to be extracted and exposed on the outer plane 1 of FIG. The outer electrode portion 1 is placed opposite to the inner surface along the direction.
The inner surface electrode portion 12b formed wider than 2a is integrally provided.
【0030】次に、図5(b)、(c)、(d)のよう
に、コイル部を形成するための半ターン分のパターン2
3,24を所定の巻数となるように積層して形成し、最
上面にパターン25を形成してから図5(e)のような
第2の引き出し電極部22を形成する。引出電極22
は、図3の外部平面3に引き出され露出するように幅狭
の帯状に形成された外面電極部22aと、外部平面3の
幅方向に沿って内面側にずれた対置に外面電極部22a
よりも幅広に形成された内面電極部22bとを一体に備
える。Next, as shown in FIGS. 5 (b), 5 (c) and 5 (d), a pattern 2 for half a turn for forming a coil portion is formed.
3 and 24 are laminated so as to have a predetermined number of turns, a pattern 25 is formed on the uppermost surface, and then a second lead electrode portion 22 as shown in FIG. 5E is formed. Extraction electrode 22
Is an outer surface electrode portion 22a formed in a narrow strip shape so as to be drawn out and exposed to the outer flat surface 3 in FIG. 3, and an outer surface electrode portion 22a that is offset to the inner surface side along the width direction of the outer flat surface 3.
The inner surface electrode portion 22b formed wider than that is integrally provided.
【0031】図5の構成によれば、図1〜図4と同様の
効果を得ることができるとともに、引出電極が一方向に
引き出す構成であるので、引出電極構成が簡単になもの
となる。According to the configuration of FIG. 5, the same effects as those of FIGS. 1 to 4 can be obtained, and since the extraction electrode is configured to be drawn out in one direction, the extraction electrode structure is simplified.
【0032】次に、図6,図7によりそれぞれ別の変形
例を説明する。図6の例は、外面電極部を3つとし、三
方向に引き出すものであり、引出電極31は、図3の外
部平面1,2,3にそれぞれ引き出され露出するように
幅狭の帯状に形成された外面電極部31a、31c、3
1eと、外部平面1,2,3の幅方向に沿ってそれぞれ
内面側にずれた対置に外面電極部31a、31c、31
eよりも幅広に形成された内面電極部31b、31d、
31fとを一体に備える。Next, different modified examples will be described with reference to FIGS. The example of FIG. 6 has three outer surface electrode parts and is drawn out in three directions. The extraction electrode 31 is formed into a narrow strip shape so as to be extracted and exposed on the outer flat surfaces 1, 2, and 3 of FIG. 3, respectively. The formed outer surface electrode portions 31a, 31c, 3
1e and the outer surface electrode portions 31a, 31c, 31 on opposite sides of the outer surfaces 1, 2 and 3 which are displaced inward along the width direction.
inner electrode portions 31b, 31d formed wider than e.
31f and 31f are integrally provided.
【0033】図6の構成によれば、図1〜図4と同様の
効果を得ることができるとともに、三方向に引き出す引
出電極構成としたので、引出電極の接続不良の発生度を
一層低減することが可能となる。なお、もう一方の引出
電極は外面電極部31cと対応する外面電極部が外部平
面4に引き出され露出するように形成され、互いに対称
位置に配置される。According to the configuration of FIG. 6, the same effects as those of FIGS. 1 to 4 can be obtained, and since the extraction electrode configuration is drawn out in three directions, the occurrence of connection failure of the extraction electrodes is further reduced. It becomes possible. The other extraction electrode is formed such that the outer surface electrode portion corresponding to the outer surface electrode portion 31c is drawn out to the outer flat surface 4 and is exposed, and are arranged at symmetrical positions.
【0034】また、図7の例は、外面電極部を4つと
し、四方向に引き出すものであり、引出電極41は、図
3の外部平面1,2,3,4にそれぞれ引き出され露出
するように幅狭の帯状に形成された外面電極部41a,
41c,41e,41gと、外部平面1〜4の幅方向に
沿ってそれぞれ内面側にずれた対置に外面電極部41
a,41c,41e,41gよりも幅広に形成された内
面電極部41b、41d、41f、41hとを一体に備
える。内面電極部41b、41d、41f、41hは全
体としてリング状に形成されている。Further, the example of FIG. 7 has four outer surface electrode parts and is drawn out in four directions. The extraction electrode 41 is extracted and exposed on the outer planes 1, 2, 3 and 4 of FIG. 3, respectively. The outer surface electrode portion 41a formed in a narrow strip shape,
41c, 41e, 41g and the outer surface electrode portion 41 in a pair opposite to the inner surface side along the width direction of the outer flat surfaces 1 to 4, respectively.
The inner surface electrode parts 41b, 41d, 41f, 41h formed wider than a, 41c, 41e, 41g are integrally provided. The inner surface electrode portions 41b, 41d, 41f, 41h are formed in a ring shape as a whole.
【0035】図7の構成によれば、図1〜図4と同様の
効果を得ることができるとともに、四方向に引き出す引
出電極構成としたので、引出電極の接続不良の発生度を
一層低減することが可能となる。なお、図6及び図7の
引出電極構成を有する積層チップ部品は、図1〜図4と
同様に印刷法により製造することができる。According to the structure of FIG. 7, the same effects as those of FIGS. 1 to 4 can be obtained, and since the extraction electrode structure is drawn out in four directions, the occurrence of connection failure of the extraction electrode is further reduced. It becomes possible. The layered chip component having the extraction electrode structure of FIGS. 6 and 7 can be manufactured by the printing method as in FIGS. 1 to 4.
【0036】以上のように本発明を実施の形態により説
明したが、本発明はこれらに限定されるものではなく、
本発明の技術的思想の範囲内で各種の変形が可能であ
る。例えば、本実施の形態では積層チップ部品の基体を
磁性体としたが、誘電体であってもよく、また製造方法
としては印刷法のみならずシート法であってもよい。Although the present invention has been described above with reference to the embodiments, the present invention is not limited to these.
Various modifications are possible within the scope of the technical idea of the present invention. For example, in the present embodiment, the base body of the laminated chip component is a magnetic body, but it may be a dielectric body, and the manufacturing method may be not only a printing method but also a sheet method.
【0037】[0037]
【発明の効果】本発明の積層チップ部品によれば、積層
方向に略直交する平面に形成した引出電極において接続
不良を防止しかつ実装時におけるたわみ強度及び抗折強
度を向上させることができる。According to the laminated chip component of the present invention, it is possible to prevent defective connection in the lead electrode formed on the plane substantially orthogonal to the laminating direction and to improve the flexural strength and bending strength during mounting.
【図1】本実施の形態による積層チップ部品の製造工程
(a)〜(d)を説明するために各電極を示す平面図で
ある。FIG. 1 is a plan view showing each electrode for explaining manufacturing steps (a) to (d) of a laminated chip part according to the present embodiment.
【図2】図1の製造工程を示すフローチャートである。2 is a flowchart showing the manufacturing process of FIG. 1. FIG.
【図3】図1、図2の製造工程により製造された積層チ
ップ部品の積層体を示す斜視図である。FIG. 3 is a perspective view showing a laminated body of a laminated chip component manufactured by the manufacturing process of FIGS. 1 and 2.
【図4】図3の積層体に外部電極を形成して完成した積
層チップ部品を示す斜視図である。FIG. 4 is a perspective view showing a laminated chip component completed by forming external electrodes on the laminated body of FIG.
【図5】本実施の形態の変形例による積層チップ部品の
製造工程(a)〜(e)を説明するために各電極を示す
平面図である。FIG. 5 is a plan view showing each electrode for explaining manufacturing steps (a) to (e) of the laminated chip part according to the modification of the present embodiment.
【図6】本実施の形態の別の変形例による積層チップ部
品における引出電極を示す平面図である。FIG. 6 is a plan view showing an extraction electrode in a layered chip component according to another modification of the present embodiment.
【図7】本実施の形態の更に別の変形例による積層チッ
プ部品における引出電極を示す平面図である。FIG. 7 is a plan view showing extraction electrodes in a laminated chip component according to still another modification of the present embodiment.
【図8】従来の積層チップ部品における引出電極の平面
図である。FIG. 8 is a plan view of an extraction electrode in a conventional layered chip component.
【図9】従来の別の積層チップ部品における引出電極の
平面図(a),(b)である。FIG. 9 is a plan view (a) and (b) of an extraction electrode in another conventional laminated chip component.
1〜4 外部平面
5,6 端面
7,8 第1の外部電極、第2の外部電
極
9 積層チップ部品
9’ 積層体
11,12 第1の引出電極、第2の引出電
極
13,14 半ターン分のパターン(内部電
極)
11a,11c 第1の引出電極の外面電極部
12a,12c 第2の引出電極の外面電極部
11b、11d 第1の引出電極の内面電極部
12b、12d 第2の引出電極の内面電極部
21,22 第1の引出電極、第2の引出電
極
23,24,25 半ターン分のパターン(内部電
極)
31,41 引出電極
m 積層方向
a 外面電極部の幅
b 内面電極部の内面側へのずれ量1 to 4 external planes 5 and 6 end surfaces 7 and 8 first external electrode, second external electrode 9 laminated chip component 9 ′ laminated body 11,12 first extraction electrode, second extraction electrode 13,14 half turn Minute pattern (internal electrode) 11a, 11c Outer surface electrode portions 12a, 12c of the first extraction electrode Outer surface electrode portions 11b, 11d of the second extraction electrode Inner surface electrode portions 12b, 12d of the first extraction electrode Second extraction Inner electrode parts 21, 22 of the first extraction electrode, second extraction electrodes 23, 24, 25 Half turn pattern (internal electrode) 31,41 Extraction electrode m Stacking direction a Width of outer electrode part b Inner surface electrode Amount of inward displacement of part
Claims (4)
するための引出電極を積層方向に略直交する少なくとも
2つの内部平面に形成して前記積層方向と略平行な外部
平面に引き出した積層チップ部品であって、 前記引出電極は前記各内部平面において前記外部平面か
ら内側にずれた位置で前記外部平面に引き出された外面
電極部よりも幅広に形成されていることを特徴とする積
層チップ部品。1. A laminated structure in which lead-out electrodes for connecting an external electrode and a laminated internal electrode are formed on at least two internal planes substantially orthogonal to the laminating direction and are drawn out to an external plane substantially parallel to the laminating direction. A chip component, wherein the extraction electrode is formed to be wider than the external electrode portion drawn to the external plane at a position displaced inward from the external plane in each of the internal planes. parts.
れた引出電極は前記各外面電極部が対称位置になるよう
に互いに異なる外部平面に引き出されていることを特徴
とする請求項1に記載の積層チップ部品。2. The lead-out electrodes formed on the at least two inner planes are led out on different outer planes so that the outer-surface electrode portions are in symmetrical positions. Multilayer chip parts.
を有し、前記各外面電極部がそれぞれ複数の異なる外部
平面に引き出されていることを特徴とする請求項1また
は2に記載の積層チップ部品。3. The extraction electrode according to claim 1, wherein each of the extraction electrodes has a plurality of outer surface electrode portions, and each of the outer surface electrode portions is drawn out to a plurality of different outer planes. Multilayer chip parts.
れた外部平面部分と前記外部平面と略直交する端面とに
形成されていることを特徴とする請求項1,2または3
に記載の積層チップ部品。4. The outer electrode is formed on an outer flat surface portion where the outer electrode portion is formed and an end surface which is substantially orthogonal to the outer flat surface.
The laminated chip component according to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001210959A JP3810291B2 (en) | 2001-07-11 | 2001-07-11 | Coil chip parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001210959A JP3810291B2 (en) | 2001-07-11 | 2001-07-11 | Coil chip parts |
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| Publication Number | Publication Date |
|---|---|
| JP2003031423A true JP2003031423A (en) | 2003-01-31 |
| JP3810291B2 JP3810291B2 (en) | 2006-08-16 |
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|---|---|---|---|
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003088284A1 (en) * | 2002-04-16 | 2003-10-23 | Murata Manufacturing Co., Ltd. | Electronic component |
| JP2016048714A (en) * | 2014-08-27 | 2016-04-07 | Tdk株式会社 | Multilayer coil parts |
| US12400785B2 (en) | 2021-03-24 | 2025-08-26 | Tdk Corporation | Multi-layer coil component |
-
2001
- 2001-07-11 JP JP2001210959A patent/JP3810291B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003088284A1 (en) * | 2002-04-16 | 2003-10-23 | Murata Manufacturing Co., Ltd. | Electronic component |
| JP2016048714A (en) * | 2014-08-27 | 2016-04-07 | Tdk株式会社 | Multilayer coil parts |
| US12400785B2 (en) | 2021-03-24 | 2025-08-26 | Tdk Corporation | Multi-layer coil component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3810291B2 (en) | 2006-08-16 |
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