JP2003029979A - Signal processing device and signal processing method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A signal processing device for processing a plurality of asynchronous video signals, wherein the circuit scale does not increase with higher image quality,
And a signal processing method. SOLUTION: A signal input asynchronously from the outside is stored in buffers 2 and 4 for each synchronous signal, and when a certain amount of data is stored, each buffer control unit 1
3 to output a transfer request signal to the memory 5, arbitrate the transfer request signal from each of the buffers 2 and 4 in the memory control unit 6, and transfer the data stored in each of the buffers 2 and 4 to the memory 5; The data transferred to the memory 5 is input to the processor 11 together with the control signal cnt22, and the processing program corresponding to the input data is
Signal processing is performed by reading from the instruction memory 14 storing a plurality of processing programs for each synchronization signal, outputting data after the signal processing to the memory 5, and reading the data after the signal processing from the memory 5 into the buffers 8 and 10. Output to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor for digitally processing a video signal such as a television signal, and more particularly to a processor for processing a video signal by inputting a plurality of asynchronous signals.

[0002]

2. Description of the Related Art As a conventional video signal processing processor that handles a plurality of video signals, there is a signal processing processor disclosed in JP-A-5-73516. Below, Figure 1
The conventional signal processor applied for image signal processing, which is disclosed in Japanese Patent Laid-Open No. 5-73516, will be described with reference to FIG. FIG. 13 is a configuration diagram of a conventional signal processing processor.

As shown in FIG. 13, a conventional signal processor 30 has a multi-port memory 40 having a plurality of simultaneously accessible ports or a memory capable of simulating them. , A plurality of sub-processors connected to the multi-port memory 40 by the above-mentioned ports, here two each of input and output ports
It is composed of two sub-processors 50 and 60 connected by one and processes a plurality of asynchronous video signals input via the multiport memory 20.

The multiport memory 40 and the sub processors 50 and 60 will be described in detail below.
Since the sub-processors 50 and 60 have the same configuration, only one will be described.

The sub-processor 50 performs a predetermined arithmetic operation or logical operation process on the input data and continues the shift for a certain scanning period, and stores the input image data during that period. And a first memory 52 and a second memory 54 that receive data in parallel from the input shift register 51 at regular scanning intervals.
When necessary, the data stored in the first and second memories are read out and operated as needed, and the first and second memories are read again.
SIMD control (Single Instructio)
An output shift register 55 that receives data from the first and second memories in parallel with a processor array unit 53 that has been subjected to an n stream multi data stream) every fixed scanning period.
And a program control section 56 for controlling the processor array section 53 and the first and second memories. Here, it is assumed that the sub-processor 50 has a register for the number of horizontal pixels and shifts data for each horizontal period.

The multiport memory 40 includes four input registers IR1 to IR4 corresponding to the four input ports PI1 to PI4, four output registers OR1 to OR4 corresponding to the four output ports PO1 to PO4, and one field. Alternatively, it has a memory capacity corresponding to the number of pixels in one frame, and at least one horizontal scanning period (1
H) and a semiconductor memory 41 in which memory cells having the number of pixels are arranged. By appropriately controlling these, the programmability of the signal processing procedure by the sub-processors 50 and 60 is maintained. It is a thing.

The above-described conventional signal processing processor 30 having the above-mentioned configuration uses the sub-processors 50 and 60 each having a processing capability which can be called a processor itself, and converts the input image data into one image. By processing every horizontal scanning period, even an arithmetic unit of the current semiconductor technology can process a large number of instructions in one horizontal scanning period, and the programmability is maintained by the multiport memory 40. This makes it possible to process a plurality of asynchronous video signals by frame synchronization.

[0008]

However, the conventional signal processing processor 30 described above includes a multi-port memory 40 having a large area and a sub-processor 50 which requires a register for one horizontal pixel of an input video signal. Since the number of horizontal pixels is 60, the signal processing processor 30 is
However, there was a problem that the area of the

The present invention has been made in view of the above problems, and allows a plurality of asynchronously input video data to be processed by an arithmetic unit having one horizontal pixel or less, and the number of image data increases. An object of the present invention is to provide a signal processing device and a signal processing method that do not increase the area.

[0010]

In order to solve the above problems, a signal processing device according to claim 1 of the present invention is a signal processing device for processing a plurality of signals input asynchronously from the outside. A plurality of first storage means for storing a plurality of asynchronous signals for each synchronization signal and outputting a transfer request signal when the data stored for each synchronization signal reaches a certain amount; The transfer request signals output from the plurality of first storage means are arbitrated in accordance with a preset priority order, and a predetermined amount of the transfer request signals output from the first storage means having a high priority order are stored. Control means for transferring the data to the second storage means for storing the pixel position so that the pixel position can be managed by an address, and a signal processing program corresponding to each of the plurality of asynchronous signals. The case Data from the third storage means and the second storage means, the signal processing program corresponding to the data is read from the third storage means, and a signal is output by a parallel arithmetic unit including a plurality of arithmetic means. Signal processing means for performing processing and outputting the signal-processed data again to the second storage means; and a plurality of fourth storages for reading the signal-processed data from the second storage means and outputting the data to the outside. Means for using the transfer request signal as an activation signal of the signal processing program in the signal processing means.

A signal processing device according to a second aspect of the present invention is the signal processing device according to the first aspect, wherein the plurality of fourth storage means are signals read from the second storage means. The transfer request signal is output to the control means when the processed data reaches a certain amount and is output to the outside, and the control means includes the plurality of first storage means and the plurality of storage means. When the transfer request signals output from the fourth storage means are arbitrated according to a preset priority order, and the transfer request signals from the plurality of fourth storage means are received, the second storage means is received. Is to transfer the signal-processed data stored in the fourth storage means to the fourth storage means, and the transfer request signals from the plurality of fourth storage means also activate the signal processing program in the signal processing means. Belief It is an.

According to a third aspect of the present invention, there is provided a signal processing device for processing a plurality of asynchronously input signals from the outside, wherein the plurality of asynchronous signals are synchronized signals. Data is stored for each synchronization signal, and when the data stored for each synchronization signal reaches a certain amount, the data is transferred to the second storage means composed of a plurality of areas defined for each synchronization signal and an interrupt signal is output. When a first storage means, a third storage means for storing a signal processing program corresponding to each synchronous signal of the plurality of asynchronous signals, and the interrupt signal are input, the second storage means is provided. Data is fetched from a defined area of the storage means, the signal processing program corresponding to the data is read from the third storage means, signal processing is performed by a parallel arithmetic unit including a plurality of arithmetic means, Signal processing means for outputting the data after management in defined regions of the second storage means, the second
A plurality of fourth storage means for reading the data after the signal processing from the defined area of the storage means and outputting the data to the outside, and storing a certain data when the interrupt signal is input to the signal processing means. When the processing of (1) is executed, the data being processed is made to wait and the processing by the interrupt signal is performed.

A signal processing device according to a fourth aspect of the present invention is the signal processing device according to the first or third aspect, further comprising fifth storage means for generating delay data, and the fifth signal processing device. The data transfer to the storage means is included in the processing program.

A signal processing method according to a fifth aspect of the present invention is a signal processing method for processing a plurality of asynchronous signals input from the outside using a parallel arithmetic unit including a plurality of arithmetic means. , A storage step of storing a plurality of asynchronously input data for each synchronization signal, and an amount of data required when the data of each synchronization signal stored in the storage step is calculated by the parallel arithmetic unit When reaching, the flag generation step for generating a flag for each synchronization signal, the flag confirmation step for confirming the generation of the flag for each synchronization signal, and the flag confirmation step in the flag confirmation step If at least one of the confirmed flags is confirmed by the parallel computing unit, a predetermined amount of data indicated by a flag having a high priority set in advance among the confirmed flags. A signal processing step of performing signal processing, and after the signal processing step, returns to the flag confirmation step, and forms a loop.

A signal processing apparatus according to a sixth aspect of the present invention is a signal processing method for processing a plurality of asynchronous signals input from the outside using a parallel arithmetic unit including a plurality of arithmetic means. , A storage step of storing a plurality of asynchronously input data for each synchronization signal, and an amount of data required when the data of each synchronization signal stored in the storage step is calculated by the parallel arithmetic unit When a flag is reached, a flag generation step for generating a flag for each synchronization signal, and an interrupt generation step for generating an interrupt by the generated flag when the flag for each synchronization signal is generated in the flag generation step, The flag confirmation step for confirming the flag for each synchronization signal generated in the interrupt generation step and the flag for each synchronization signal are confirmed. Then, the parallel processing unit saves data being processed, and performs signal processing of a predetermined amount of data indicated by the confirmed flag, and after the signal processing step, This is to return to the execution of signal processing of the data saved in the signal processing step.

According to a seventh aspect of the present invention, there is provided a signal processing method, wherein a parallel arithmetic unit including a plurality of arithmetic units receives a plurality of asynchronous signals input from the outside during execution of other processing. In the signal processing method of processing by using the storage step of storing a plurality of asynchronously input data for each synchronization signal, the data of each synchronization signal stored in the storage step is When a data amount necessary for calculation is reached, a flag generation step for generating a flag for each synchronization signal, and at least one synchronization signal generated in the flag generation step, a preset priority order Interrupt generation step that generates an interrupt with a high flag of, and when the above interrupt is generated, other interrupts are prohibited and A signal processing step for performing signal processing of the data of the predetermined amount indicated by higher the priority flag,
After the signal processing is completed in the signal processing step, the other interrupt that has been prohibited is permitted, and the process returns to the execution of the other processing that was being performed when the interrupt occurred.

According to a eighth aspect of the present invention, there is provided a signal processing method, wherein a parallel arithmetic unit including a plurality of arithmetic units receives a plurality of asynchronous signals input from the outside during execution of other processing. In the signal processing method of processing by using the storage step of storing a plurality of asynchronously input data for each synchronization signal, the data of each synchronization signal stored in the storage step is When a data amount necessary for calculation is reached, a flag generation step for generating a flag for each synchronization signal, and at least one synchronization signal generated in the flag generation step, a preset priority order Interrupt generation step that generates an interrupt with a high flag, and when the interrupt is generated, the data being executed at that time is saved and the parallel The adder has a signal processing step for performing signal processing of the data of the predetermined amount indicated by higher the priority flag, and in the signal processing step,
When an interrupt with a higher priority than the signal processing being executed occurs, the processing being executed in the signal processing step is interrupted to save the data, and the signal processing with the interrupt with a higher priority is performed. After the signal processing is completed in the signal processing step, the processing is returned to the execution that was being performed when the interrupt occurred.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) A signal processing apparatus according to Embodiment 1 of the present invention will be described below with reference to FIGS. 1 to 4. First, the configuration of the signal processing device according to the first embodiment will be described with reference to FIG. 1 is a configuration diagram of a signal processing device according to Embodiment 1 of the present invention.

In FIG. 1, the buffer control unit 1 includes a sync1 which includes a horizontal synchronizing signal and a vertical synchronizing signal from the outside.
A signal is input, and the input / output of the data 1 stored in the buffer 2 of the video signal input from the outside is controlled. Further, the buffer 2 has a capacity for storing 128 pieces of data1 input by 8 bits in synchronization with clk1 in synchronization with the sync1 signal in the video signal, and 64 pieces of data, which is half the capacity of the buffer 2, is stored. Every 8 seconds, the stored 8 bits × 64 pieces of data are synchronized with clkp (processor clock).
The data 25, which is 1, is output to the memory 5. The buffer control unit 3 has the same configuration as the buffer control unit 1 to which the sync2 signal is input, and controls the input / output of data2 stored in the buffer 4 in the video signal input from the outside. Is. The buffer 4 has the same configuration as the buffer 2, and clk2 is synchronized with the sync2 signal in the video signal.
Every time 64 data2 of 8 bits input is stored according to, data25 which is 8 bits × 64 data2 stored according to clkp.
Is output to the memory 5. The memory 5 stores the data 25 output from each of the buffers 2 and 4 and outputs the data 27 to the processor 11, or inputs the data 27 from the processor 11, and the memory control unit 6 inputs and outputs the data from the memory 5. Is controlled by a control signal output from each buffer. The data 25 is 8 bits × 64 pieces of data 1 or data output from the buffers 2 and 4.
The data 27 is 8 bits × 64 pieces of data input / output between the memory 5 and the processor 11, and is stored in the memory 5 here.
The data means data, data, or data processed by the processor 11.

Further, the buffer control unit 7 receives a sn signal from the outside.
The yc3 signal is input, and the input / output of the signal-processed data 26 stored in the buffer 8 from the memory 5 is controlled. Further, the buffer 8 is c
8 bits x 6 transferred from the memory 5 according to lkp
It has a capacity to store 128 pieces of 4 data 26, and sync3 is stored every time 64 pieces of data, which is half of that, is stored.
The data of 8 bits × 64 stored in the buffer 8 is externally output as data3 in synchronization with clk3. The buffer control unit 9 has the same configuration as the buffer control unit 7 to which the sync4 signal is input, and controls the input / output of the data 26 stored in the buffer 10 from the memory 5. Further, the buffer 10 has the same structure as the buffer 8, and
8bit x transferred from the memory 5 according to lkp
64 pieces of data 26 are stored, and every time 64 pieces of data are stored, 8 bits × 64 pieces of data stored in the buffer 10 are d-matched with clk4 in synchronization with sync4.
It is output to the outside as ata4.

The processor 11 performs video signal processing on the data 27 input from the memory 5, and then outputs the signal-processed data 27 to the memory 5, and controls the program counter 12 and the program counter 12. A program counter control unit 13, an instruction memory 14 for storing a processing program corresponding to each of the sync system data, a decoder 15 for decoding the processing program read from the instruction memory 14,
A parallel arithmetic unit 16 composed of 64 arithmetic units that perform the same operation according to a control signal from the decoder 15, and a register file 17 for storing the data from the memory 5 and the result of the arithmetic data of the parallel arithmetic unit 16. It is composed of. Although not shown, the instruction memory 14 can set an instruction code from the outside.

The buffer 18 includes the memory 5 and SDRA.
Dat which is 16 bit data between M21 and
The SDRAM 21 and the buffer 18 output and output a19, and the SDRAM 21 and the buffer 18 output a control signal cnt20 including RAS, CAS, wen (write enable), address and the like, and a clock signal c.
It is controlled by lksd. The above c
The frequency of lksd is the same frequency as clkp in the first embodiment, but may be a frequency different from clkp as long as the timing of data transfer is met.

Next, the operation of the signal processing apparatus according to the first embodiment will be described with reference to FIGS. 1 to 4. 2 is a waveform diagram showing the operation of the signal processing device according to the first embodiment, FIG. 3 is a flowchart showing the operation of the processor in the signal processing device according to the first embodiment, and FIG. 3 is a flow of each program stored in an instruction memory in the processor according to the first embodiment.

In the first embodiment, the processor 1
It is assumed that the parallel arithmetic unit 16 in 1 is composed of 64 arithmetic units, and can process 64 data at the same time. Therefore, here, the arithmetic processing is executed by the processor 11 when 64 pieces of data are input to the register file 17.

First, among a plurality of asynchronously input video signals, a sync1 system signal including sync1 signal, clk1 and data1 is a sync1 signal input to the buffer control unit 1 and a sync1 signal including vertical sync signal. The signal recognizes the horizontal and vertical data positions of the video data. Next, the buffer control unit 1 outputs a wen signal (write enable signal) to the buffer 2 while the input data is valid, and the buffer 2 receives 8 bits in accordance with clk1 during the valid period of the wen signal. The data data1 is sequentially stored. Then, when 64 pieces of the data 1 which is half the capacity of the buffer 2 are input to the buffer 2 from the outside, a control signal c for notifying that 64 pieces of data have been stored in the buffer 2
Output nt1.

Of the plurality of asynchronously input video signals, the sync1 signal and the sync signal which is different from the sync signal.
The same applies to the case of a 2-system signal, and the buffer control unit 3
When the sync2 signal is input to the
The en signal is output while the input data is valid,
8 bits of data2 are input to the buffer 4 in accordance with clk2 while a signal is input, and when 64 pieces of data2, which is half the capacity, are stored, the buffer 4 outputs 6 bits.
Control signal cn notifying that four pieces of data have been stored
It outputs t2 to the memory control unit 6.

When the memory control unit 6 receives the control signal cnt1 from the buffer control unit 1 or the control signal cnt2 from the buffer control unit 3, a control signal including a wen signal and a ren signal (read enable signal) is received. The cnt 24 is output to the memory 5, and the pixel position of each sync signal system data is stored in the memory 5 so that it can be managed by an address. For example, when the control signal cnt1 is input to the memory control unit 6, when the transfer of 8 bits × 64 data1 stored in the buffer 2 to the memory 5 is started and the data1 is stored in the memory 5, If the left end of the image is written at address 0 in the memory 5 and one line consists of 760 pixels,
By storing the data at the right end of the screen at the address 759 and writing the data at the left end of the next line to the address 760 in the memory 5, it is possible to access the data at the required pixel position by specifying the address in the memory 5. To

Although not shown, the data output from the signal processing device according to the first embodiment can be performed by the same process as the data input operation described above. That is, when the sync3 signal is input to the buffer control unit 7, the control signal cnt3 is output to the memory control unit 6, or when the sync4 signal is input to the buffer control unit 9, the control signal cnt4 is input to the memory control unit 6. Is output. Then, the memory control unit 6 causes the control signal cnt
When receiving 3, cnt4, the memory control unit 6
The control signal cnt24 including the signal and the ren signal is output to the memory 5, and the memory control unit 6 outputs the control signal cnt24, for example.
When nt3 is received, the processed data stored in the memory 5 is post-processed by the processor 11, and 8 bit × which is output next from the signal processing device after the post-processing is finished.
When the data 26, which is 64 pieces of data, is transferred to the buffer 8 and the control signal cnt4 is received, the data 26 is transferred from the memory 5 to the buffer 10 in the same manner.

Further, the memory control section 6 receives the control signals cnt1, cnt2, c from the buffer control sections.
Priorities are set in advance for nt3 and cnt4, and the control signals cnt1 to cnt are supplied to the memory control unit 6 described above.
When 4 are input at the same time, the order of data transfer is determined according to the priority order of the predetermined control signal, and the data transfer is started. At this time, the memory control unit 6 uses the control signal cnt22 to send the sync1 signal system and the sync signal system.
The processor 11 is notified of which data transfer of the c2 signal system, the sync3 signal system, and the sync4 signal system is activated.

Here, for example, the memory control unit 6 receives the control signal cnt1 and transfers from the buffer 2 to the memory 5 to syn.
When the transfer of data1 which is the c1 signal system is activated, the memory control unit 6 outputs the control signal cnt22 indicating cnt1 to the processor 11 to notify that the data transfer of the sync1 signal system has been activated. When the processor 11 receives the control signal cnt22, s is output from the plurality of processing programs stored in the instruction memory 14.
The program 1 corresponding to the data of the ync1 signal system is selected, and as shown in FIG. 2, the selected program 1 is used to transfer d from the buffer 2 to the memory 5 one before.
Signal processing for ata1 is performed.

As described above, the instruction memory 14 is stored in FIG.
As shown in, program 1 for sync1 system signals and program 2 for sync2 system signals.
As described above, a processing program for data of each synchronization signal system is input and stored in advance via an external I / F (not shown). Therefore, when the program counter control unit 13 receives the control signal cnt22 from the memory control unit 6, the data transfer started from the control signal cnt22 is the sync1 signal system, the sync2 signal system, or the sync signal system.
Determine which of the c3 signal system and the sync4 signal system,
The address of the processing program corresponding to the data whose transfer is started in the instruction memory 14 is set to the program counter 1
The data is processed using the selected processing program by selecting it by designating in 2.

The signal processing operation in the processor 11 according to the first embodiment will be described below with reference to FIGS. 1 and 4 according to the flowchart of FIG. As shown in FIG. 3, in the processor 11, the control signal cn
A program for checking the state at t22 is running. First, if no signal is input to the control signal cnt22 for the processor 11, initialization is performed with a reset signal or the like (step 301), and then an infinite loop operation that passes through the determination routine is performed (steps 302, 303, 304, 30).
5). That is, the processor 11 performs an endless loop operation and always checks the state of the control signal cnt22 that is input.

When the program counter control unit 13 is notified by the control signal cnt22 of the transfer of, for example, cnt1, the process proceeds to step 302, and the program counter 12 is set to the address of the program 1 stored in the instruction memory 14. The instruction is changed and the instructions of the program 1 are sequentially read from the instruction memory 14. Read program 1
The instruction of is decoded by the decoder 15 and input as a control signal to the 64 parallel arithmetic units 16, and at this time the data transferred to the memory 5 is 8 bits × 64 stored in the memory 5. Data1 is transferred to the register file 17, and the parallel computing unit 16 controlled by the program 1 performs the signal processing required for data1.

As shown in FIG. 4, the instruction of the program 1 has a data input step, a calculation step, and a data output step. First, in the data input step, it is stored in the memory 5 by a load instruction. From the data area, the data 27 to be processed is registered in the register file 1
7, the arithmetic operation of the above data is executed between the register file 17 and the parallel arithmetic unit 16 in the arithmetic step, and the arithmetic result executed in the arithmetic step is registered by the store instruction in the data output step. The file 17 is transferred to the memory 5.

The programs 2 to 4 have the same steps as the steps of the program 1 described above. For example, in the case of the program 3, the memory 5 is used.
A data input step of inputting the data after processing by the processor 11 stored in the register file 17 to the register file 17, a calculation step of performing post-processing on the data, and a data output step of outputting the calculation result to the buffer 8. It includes. In addition, in the program 1 and the like of the first embodiment, there is a calculation step between the input step and the output step, but it may be a process of simply transferring data. Further, when processing data is not stored in the memory 5 from each buffer due to field delay or the like and data is required, each program executes SD in the data input step.
A data load instruction from the RAM 21 is described and the data in the SDRAM 21 is stored in the memory 5 via the buffer 18 so that the data transfer is completed at the next execution of each program. Then, in the data output step, S
Describes a data storage instruction to the DRAM 21.

In the above description, it is assumed that each buffer control unit outputs a control signal and the memory control unit 6 inputs / outputs data according to the control signal. Areas for writing or reading data are defined by 8, 10, and 18, respectively, and each buffer control section 1, 3, 7, 9 and SDRAM control section 22 sets each buffer to empty or full.
In this case, it is possible to store the data in the memory 5 without the control of the memory control unit 6 by performing the DMA transfer for directly writing or reading the data in the memory 5.

The case where the data transfer from each buffer to the memory 5 is performed by the DMA transfer as described above will be described below with reference to FIGS. 5 and 6. FIG. 5A is a flow chart showing the operation when interrupt control is performed in the processor in the signal processing apparatus of the first embodiment, and FIG. 5B is the interrupt of FIG. 5A. FIG. 6 is a flowchart showing a series of processing flows, and FIG. 6 is a diagram showing a series of processing flows of each program of FIG. 5B.

For example, when the buffer 2 becomes full with the data 1 input from the outside, the buffer control unit 1
Writes data in the defined area of the buffer 2 defined in the memory 5, causes the processor 11 to generate an interrupt signal, and notifies that the data has been transferred to the memory 5. The processor 11, which has received the interrupt signal, saves the values of the program counter 12 and the register file 17 that are currently being executed, and then detects from which buffer control unit the interrupt processing is from. As the detection method, the level of the interrupt signal generated from each buffer control unit is changed, or the buffer control unit that has completed the data transfer sets 1 to the register provided in each buffer control unit. The processor 11 may refer to the register to detect from which buffer control unit the interrupt signal is generated. Then, when the processor 11 detects that the interrupt processing is from the buffer control unit 1, the program 1 is selected, necessary video processing is executed on the written data, and the calculation result is stored in the memory 5. To do. Then, after the interrupt processing as described above is completed, the processing is continued by returning to the saved address of the data processing.
Also, the buffer 10 outputs data4 to the outside and em
In the case of pty, the buffer control unit 9 causes an interrupt to the processor 11, and after the above-described processing is completed, the buffer control unit 9 inputs again into the definition area of the buffer 10 on the memory 5, and the data from the definition area is input. Read and buffer 1
It is taken into 0 and output to the outside as data4.

By such processing, each buffer control unit DMA-transfers the video signal input asynchronously to the processing clock of the processor 11 to the memory 5 by the DMA transfer.
The data is stored in the memory, the processor 11 is notified by the interrupt that the data has been written or read, and the processor 11 can perform the processing at a necessary timing.

It should be noted that, instead of generating an interrupt signal from each buffer control unit and interrupting the signal processing being executed by the processor 11, a register is provided in each buffer control unit,
When the buffer controller has finished transferring the data, for example, the register is set to 1, and the processor 11 reads the data written in the register at an appropriate cycle as shown in FIG. Control by polling is also possible.

As described above, in the first embodiment, the control signal cnt is sent from each buffer control unit to the memory control unit 6 when the required number of data is prepared in the input situation of a plurality of asynchronous data to each buffer. Is output, and at the same time that the certain amount of data is transferred to the memory 5, the memory control unit 6 outputs to the processor 11 a control signal cnt22 indicating which sync signal data has been transferred to the memory 5,
The processor 11 determines data to be processed from the control signal cnt22, and outputs a processing program corresponding to the data from the instruction memory 14 to the program counter controller 13
Since the signal processing of the above-mentioned data is performed while switching in the above, the data is processed in the processor 11 at the stage when the required number of a plurality of asynchronous data are prepared, and the asynchronous data is synchronized by the frame synchronization function or the like. Since it is possible to eliminate the need for data conversion, there is an effect that the area of the signal processing device does not increase even if the number of horizontal pixels of image data increases as the image quality of the image increases. Even when a certain amount of data is stored in each buffer and the control signal cnt is input to the memory control unit 6 at the same time, the memory control unit 6 sends each control signal cnt to the memory 5 according to a predetermined priority.
Since the input / output of data to and from arbitration is performed and the signal processing is performed from the data with the highest priority, it is possible to perform the processing of a plurality of asynchronous signals in the processor 11 while switching the processing programs by the control signal cnt22. Becomes

In the first embodiment, two data input systems and two data output systems are used, but the same can be handled even if the number increases. Further, the bit width of data can also be realized by a configuration other than that of the first embodiment.

Also, the number of arithmetic units in the parallel arithmetic unit 16 may be determined according to the required arithmetic performance. If the arithmetic performance of the arithmetic units is improved, a memory other than 64 will be stored at the stage where the data required for the arithmetic is prepared. This can be realized by transferring data from the control unit 6 or starting the processor 11. The SDRAM 21 is also the SDRAM
A memory other than the above can be configured. In addition, in the first embodiment, 12 bits of data input is 8 bits.
In a buffer having a capacity of storing eight data, the stored data is output to the memory 5 every time 64 data, which is half the capacity, is input, but if the data transfer is in time, , Not necessarily 64,
The data may be output each time another number of data is input to the buffer.

(Second Embodiment) A signal processing apparatus according to the second embodiment will be described below with reference to FIGS. 8 and 9. In the first embodiment described above, the input of the control signal cnt22 output from the memory control unit 6 in the processor 11 is always confirmed in the program as shown in FIG. 4, whereas in the second embodiment, ,
As shown in FIG. 8, for example, when the control signal cnt22 is output from the memory control unit 6 during the OSD processing, an interrupt is generated.

First, the configuration of the signal processing apparatus according to the second embodiment is similar to that of the first embodiment.
The description is omitted here. Next, using FIG. 8 and FIG.
The operation of the signal processing device according to the second embodiment will be described. FIG. 8A is a flowchart showing the operation of the processor in the signal processing apparatus according to the second embodiment, and FIG. 8B shows a series of flows of the interrupt processing of FIG. 8A. 9 is a flowchart of FIG.
It is the figure which showed the series of flow of each program process of (b).

Unlike the image processing, the video signal processing needs to be processed in real time to continuously output data. That is, in the method of the first embodiment described above,
Since the processor 11 needs to always check the control signal cnt22 so that the processing can be started as soon as the data amount of the video signal is uniform and the parallel computing unit 16 can perform the computation, for example, an on-screen display (OS)
D) Other processing such as processing cannot be executed at the same time.

However, as in the second embodiment,
In the method of using an interrupt, even if processing such as OSD processing is performed, the OSD processing is interrupted by issuing an interrupt with the control signal cnt22, and a processing program corresponding to the synchronization signal system indicated by the control signal cnt22, for example, a control signal. If cnt22 indicates cnt1, the processing by the program 1 can be performed.

The operation of the processor 11 according to the second embodiment will be described below with reference to the flowchart of FIG. First, if the control signal cnt22 is not input, initialization is performed with a reset signal or the like in step 510, and then OSD processing is performed in step 520. Then, while the OSD processing is being performed, the control signal cnt22
Interrupt occurs, the OSD process is interrupted and
The process moves to the interrupt handler shown in (b).

In the interrupt processing, first, in step 521, interrupt is prohibited during execution of interrupt processing to facilitate interrupt control, and the state of the control signal cnt22 input to the processor 11 is changed to step 52.
2 to step 525, the control signal cnt
A processing program is selected according to the state of 22, and signal processing is performed.

Then, as shown in FIG. 9, signal processing by the selected processing program, for example, cnt2 in this case.
If 2 is cnt1 and the program 1 is selected from the instruction memory 14, the signal processing by the program 1 is performed in step 5221, and the interrupt is prohibited in step 521 in step 5222 after the processing is completed. After the interrupt processing is completed, the interrupt is permitted, and the OSD processing of step 520 is resumed.

As described above, according to the second embodiment,
When performing other processing such as OSD processing, control signal cn
When the interrupt at t22 occurs, the OSD process is interrupted and the processing program corresponding to the sync signal system indicated by the control signal cnt22 is executed, so that the data is continuously processed and output in real time like the video signal processing. In the necessary signal processing, other processing can be performed at the same time. Also, during the interrupt processing, the control signal c
By prohibiting the interrupt by nt22, the interrupt control can be facilitated.

In the interrupt processing of the second embodiment, as shown in FIG. 8B, it is sequentially confirmed which of the control signals cnt22 to cnt1 to cnt4 matches (step 522 to step 522). 525), it has been described that the programs 1 to 4 are selected, but the value of the control signal cnt22 as an interrupt signal is 0 in the case of the processing of the program 1 and 1 in the case of the processing of the program 2.
The value is set in advance such as, and the control signal cn
If t22 = 0, it is possible to directly proceed to the processing of program 1.

(Third Embodiment) Hereinafter, FIG. 10 to FIG.
The signal processing device according to the third embodiment will be described with reference to FIG. In the second embodiment described above, FIG.
As shown in (b), while other processing such as OSD processing is being executed,
When an interrupt is generated by the control signal cnt22, other interrupt processing is prohibited in step 521 during processing by the interrupt, but in the third embodiment, during interrupt processing executed by the interrupt by the control signal cnt22. In addition, if an interrupt of the control signal cnt22 occurs, the difference is that the interrupt is permitted.

First, the configuration of the signal processing apparatus according to the third embodiment is similar to that of the first embodiment, and
The description is omitted here. Next, the operation of the signal processing device according to the third embodiment will be described with reference to FIGS. 10 to 12. FIG. 10 is a waveform diagram showing the operation of the signal processing device according to the third embodiment, and (X) is a waveform diagram of the signal processing according to the second embodiment described above without interruption during the processing program processing. , (Y) are interruptions during processing program processing, that is, waveform diagrams of signal processing in the third embodiment. In addition, FIG.
11 is a flowchart showing the operation of the processor in the signal processing device according to the third embodiment, and FIG.
11 is a flowchart showing a series of flows of the interrupt processing of FIG. 11A, and FIG. 12 is a view showing a series of flows of the respective processing programs of FIG. 11B.

Here, the signal processing according to the above-described second embodiment and the signal processing according to the present third embodiment will be compared with each other with reference to FIG. However, in FIG. 10, cl
The input rate of data2 that is input according to k2 is c
It is assumed that it is faster than data1 input according to lk1 and that the execution time for program 1 to process data1 is longer than the execution time for processing data2 of program 2.

C indicating the control signal cnt2 during the OSD processing
An interrupt by nt22 occurs, and then c indicating cnt1
An interrupt by nt22 occurs, an interrupt by cnt22 indicating cnt2 occurs, and cn indicating cnt1.
When an interrupt due to t22 occurs, if processing is performed by the processing method of the above-described second embodiment, as shown in FIG. 10 (X), the processing of the second input data2 is not completed, and Since data2 of will be input,
Processing may fail.

On the other hand, in the third embodiment, since the interrupt is permitted even during the processing of the processing program, as shown in FIG.
The interrupt level of the program 2 corresponding to the control signal cnt2 is increased during the signal processing execution by the program 1.
When the interrupt by the cnt22 indicating the is generated, the processing by the program 1 is interrupted, the processing of the program 2 is performed first, and after the signal processing is completed, the interrupted signal processing by the program 1 is restarted.

The operation of the processor 11 in the third embodiment will be described below with reference to the flowcharts of FIGS. 11 and 12. First, if the control signal cnt22 is not input, initialization is performed with a reset signal or the like in step 810, and then OSD processing is performed in step 820. Then, when an interrupt of the control signal cnt22 occurs during the OSD process, the OSD process is interrupted and the process proceeds to the interrupt handler shown in FIG. 11B. In interrupt processing, first, step 821.
, The control signal c is stored after the data being processed is saved.
A processing program is selected according to the state of nt22, and signal processing is performed.

Further, in the processing by each of the programs 1 to 4 by the interrupt shown in FIG. 12, for example, when the interrupt by the cnt22 indicating the cnt2 occurs during the processing by the program 1 in step S8221, FIG. Move to the interrupt handler of.
Then, in step 821, data1 being processed
After saving, the state of the control signal cnt22 is confirmed in steps 822 to 825. In this case, the program 2 is selected according to the state of the control signal cnt22,
Signal processing by program 2 is performed. After the processing by this interrupt is completed, in step 8222, the data1 saved in step 821 is restored, and the signal processing by the program 1 is restarted.

As a result, the signal processing of the program 2 is interrupted and executed during the signal processing of the program 1 shown in FIG. 10 (Y), and after the signal processing by the program 2 is completed, the processing by the program 1 is restarted. After the signal processing is completed, it becomes possible to start the processing by the program 2 for the next input data2, and before the processing of the previously input data2 is completed, the next data2 is input and the processor 11 It is possible to avoid the breakdown of the output image due to the malfunction of.

As described above, according to the third embodiment,
Since a high-priority interrupt is allowed not only during execution of other processing such as OSD processing but also during signal processing by an interrupt, a certain sync signal among a plurality of asynchronous signals input from the outside. It is possible to prevent malfunction of the processor 11 due to input of data of the same sync signal system during processing of system data, and avoid image corruption.

[0062]

As described above, according to the signal processing device of the first aspect of the present invention, in the signal processing device for processing a plurality of asynchronously input signals from the outside,
A plurality of first storage means for storing the plurality of asynchronous signals for each synchronization signal, and outputting a transfer request signal when the data stored for each synchronization signal reaches a certain amount; A fixed amount stored in the first storage means that arbitrates the transfer request signals output from the plurality of first storage means in accordance with a preset priority order and outputs a transfer request signal with a high priority order. Means for transferring the data of (1) to the second storage means for storing the pixel position so that the pixel position can be managed by an address, and signal processing corresponding to each of the plurality of asynchronous signals. Third storage means for storing a program, data is fetched from the second storage means, the signal processing program corresponding to the data is read out from the third storage means, and the parallel processing means includes a plurality of arithmetic means. A signal processing unit that performs signal processing with a calculator and outputs the signal-processed data again to the second storage unit; and a plurality of units that read the signal-processed data from the second storage unit and output the data to the outside. A fourth storage means is provided, and the transfer request signal is used as an activation signal of the signal processing program in the signal processing means, so that a plurality of asynchronous data are synchronized by frame synchronization or the like. Since the signal processing can be performed for each synchronization signal in which data is complete without performing the conversion processing, it is possible to reduce the circuits of the signal processing device.

According to a second aspect of the present invention, there is provided the signal processing apparatus according to the first aspect, wherein the plurality of fourth storage means are read from the second storage means. The signal processing device outputs a transfer request signal to the control means when the data after the signal processing reaches a certain amount and outputs the data to the outside, and the control means includes the plurality of first storage means and the plurality of first storage means. When the transfer request signals output from the plurality of fourth storage means are arbitrated according to a preset priority order and the transfer request signals from the plurality of fourth storage means are received, the second transfer request signals are received. The signal-processed data stored in the storage means is transferred to the fourth storage means, and transfer request signals from the plurality of fourth storage means are also processed by the signal processing program in the signal processing means. of Since such a motion signal, it can also be controlled in the control means for the output not only the input data.

According to a third aspect of the present invention, there is provided a signal processing device for processing a plurality of asynchronously input signals from the outside, wherein each of the plurality of asynchronous signals is processed. The data is stored for each sync signal, and when the data stored for each sync signal reaches a certain amount, it is transferred to the second storage means composed of a plurality of areas defined for each sync signal, and the interrupt signal is transferred. When the first storage means for outputting, the third storage means for storing a signal processing program corresponding to each synchronous signal of the plurality of asynchronous signals, and the interrupt signal are input, the third storage means Data is fetched from a defined area of the second storage means, the signal processing program corresponding to the data is read from the third storage means, and signal processing is performed by a parallel arithmetic unit including a plurality of arithmetic means. Signal processing means for outputting the data after the signal processing to the defined area of the second storage means,
A plurality of fourth storage means for reading the data after the signal processing from the defined area of the second storage means and outputting the data to the outside, when the interrupt signal is input to the signal processing means. , When a certain data is being processed, the data being processed is made to wait and the processing by the interrupt signal is performed. Therefore, data conversion is performed so that a plurality of asynchronous data are synchronized by frame synchronization or the like. It is possible to perform signal processing for each synchronization signal in which data is complete, without performing the processing to
Storage means, or a plurality of fourth storage means, and the second storage means.
The data can be DAM-transferred to and from the storage means. As a result, the circuit of the signal processing device can be further reduced.

According to a fourth aspect of the present invention, there is provided the signal processing device according to the first or third aspect, further comprising fifth storage means for generating delay data, Since the data transfer to the fifth storage means is included in the processing program, it is possible to perform signal processing in real time even when there is no necessary data due to field delay or the like.

Further, according to the signal processing method of the fifth aspect of the present invention, signal processing for processing a plurality of asynchronous signals input from the outside by using a parallel arithmetic unit including a plurality of arithmetic means. In the method, a step of storing a plurality of asynchronously input data for each synchronous signal,
A flag generation step of generating a flag for each synchronization signal when the data for each synchronization signal stored in the storage step reaches the amount of data required for calculation by the parallel arithmetic unit; If at least one of the flags for each of the synchronization signals is confirmed in the flag confirmation step for confirming the generation of each flag, and the flag confirmation step, the A signal processing step of performing signal processing of a predetermined amount of data indicated by a flag having a high priority set in advance, and after the signal processing step, returns to the flag confirmation step to form a loop. Therefore, even if you do not perform data conversion to synchronize asynchronous data input from the outside with frame synchronization etc.,
It becomes possible to perform signal processing when data is prepared for each synchronization signal.

According to the signal processing method of the sixth aspect of the present invention, signal processing for processing a plurality of asynchronous signals input from the outside by using a parallel arithmetic unit including a plurality of arithmetic means. In the method, a step of storing a plurality of asynchronously input data for each synchronous signal,
A flag generation step of generating a flag for each synchronization signal when the data for each synchronization signal stored in the storage step reaches a data amount necessary for calculation by the parallel arithmetic unit, and the flag generation step In the above, when the flag for each synchronization signal is generated, an interrupt generation step for generating an interrupt by the generated flag; a flag confirmation step for confirming the flag for each synchronization signal generated in the interrupt generation step; When the flag for each synchronization signal is confirmed, a signal processing step of saving the data being processed in the parallel computing unit and performing signal processing of a predetermined amount of data indicated by the confirmed flag is included. After the above signal processing step, the processing is returned to the execution of the signal processing of the data saved in the signal processing step. In, even without data conversion so as to synchronize a plurality of asynchronous data such as a frame sync in, DMA when the data is aligned for each synchronization signal
It becomes possible to transfer and perform signal processing.

According to the seventh aspect of the signal processing method of the present invention, a parallel arithmetic unit including a plurality of arithmetic units receives a plurality of asynchronous signals input from the outside during execution of other processing. In the signal processing method for processing using the above, a storage step of storing a plurality of asynchronously input data for each synchronization signal, and the data for each synchronization signal stored in the storage step is the parallel arithmetic unit. When a data amount necessary for the calculation is reached, a flag generation step for generating a flag for each synchronization signal, and at least one synchronization signal generated in the flag generation step, a preset priority is set. An interrupt generation step that generates an interrupt with a flag with a high order, and when the above interrupt is generated, other interrupts are prohibited and
A signal processing step of performing signal processing of a predetermined amount of data indicated by the high priority flag by the parallel computing unit, and another interrupt which is prohibited after the signal processing is completed in the signal processing step. Is enabled and the processing is returned to the execution of the other processing that was being performed when the interrupt occurred, so multiple asynchronous data signals input from outside can be processed in real time like a video signal. Even when it is necessary to continue to output the data, the data is collected for each synchronization signal without performing the data conversion so as to synchronize with the frame synchronization while performing other processing such as OSD processing. It is possible to generate an interrupt and perform signal processing.

According to the signal processing method of the eighth aspect of the present invention, during execution of other processing, a plurality of asynchronous signals input from the outside are subjected to parallel operation including a plurality of operation means. In a signal processing method for processing using a signal processing device, a storage step of storing a plurality of asynchronously input data for each synchronization signal, and the data for each synchronization signal stored in the storage step is calculated in parallel. When the amount of data required for arithmetic operation is reached, a flag generation step of generating a flag for each synchronization signal and at least one synchronization signal generated in the flag generation step are set in advance. An interrupt generation step that generates an interrupt with a flag with a high priority, and when the above interrupt is generated, save the data being executed at that time and A signal processing step of performing signal processing of a predetermined amount of data indicated by the flag having a high priority by the parallel arithmetic unit, and the interrupt having a higher priority than the signal processing being executed in the signal processing step. Occurs, the processing being executed in the signal processing step is interrupted to save the data, the signal processing is performed by the interrupt with the higher priority, and the interrupt is performed after the signal processing is completed in the signal processing step. Since the processing is returned to the processing that was being performed at the time of occurrence of, the signal processing is performed by generating an interrupt when a plurality of asynchronous signals input from the outside are ready for each synchronous signal. It is possible to prevent a malfunction that occurs when performing, and to prevent the image from collapsing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation of the signal processing device according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of a processor in the signal processing device according to the first embodiment of the present invention.

FIG. 4 is a flowchart of each processing program stored in an instruction memory in the processor according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing an operation example of the processor in the signal processing device according to the first embodiment of the present invention.

FIG. 6 is a flowchart of each processing program stored in the instruction memory in the processor according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing another operation example of the processor in the signal processing device according to the first embodiment of the present invention.

FIG. 8 is a flowchart showing an operation of the processor in the signal processing device according to the second embodiment of the present invention.

FIG. 9 is a flowchart of each processing program stored in the instruction memory in the processor according to the second embodiment of the present invention.

FIG. 10 is a waveform diagram showing the operation of the signal processing device according to the third embodiment of the present invention.

FIG. 11 is a flowchart showing an operation of the processor in the signal processing device according to the third embodiment of the present invention.

FIG. 12 is a flowchart of each processing program stored in an instruction memory in the processor according to the third embodiment of the present invention.

FIG. 13 is a block diagram of a conventional signal processing device.

[Explanation of symbols]

1,3,7,9 buffer controller 2,4,8,10,18 buffer 5 memory 6 Memory controller 11 processors 12 program counter 13 Program counter controller 14 instruction memory 15 decoder 16 Parallel computing unit 17 register file 21 SDRAM 22 SDRAM control unit 30 Signal processing processor 40 multi-port memory 41 Semiconductor memory 50,60 sub-processor 51,61 Input shift register 52,62 First memory 53, 63 Processor array section 54, 64 second memory 55,65 output shift register 56,66 Program control unit

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B045 AA03 BB36 GG11                 5B098 BA01 BA12 BA14 CC00 CC08                       DD01                 5C021 PA72 PA82 PA83 PA87 PA89                       SA01 YC03 YC04 YC13 ZA01

Claims (8)

[Claims] 1. A signal processing device for processing a plurality of asynchronously input signals from the outside, wherein the plurality of asynchronous signals are stored for each synchronization signal and stored for each synchronization signal. A plurality of first storage means for outputting a transfer request signal when data reaches a certain amount, and the transfer request signals output from the plurality of first storage means are arbitrated according to a preset priority order. Then, the fixed amount of data stored in the first storage means, which has output the transfer request signal having the higher priority, is transferred to the second storage means which stores the pixel position so that the pixel position can be managed by the address. Control means, a third storage means for storing a signal processing program corresponding to each synchronous signal of the plurality of asynchronous signals, and data from the second storage means, and the third storage means. Record A signal processing means for reading the signal processing program corresponding to the data from the means, performing signal processing by a parallel arithmetic unit including a plurality of arithmetic means, and outputting the signal-processed data to the second storage means again. A plurality of fourth storage means for reading the data after the signal processing from the second storage means and outputting the data to the outside, wherein the transfer request signal is a start signal of the signal processing program in the signal processing means. The signal processing device according to the above. 2. The signal processing apparatus according to claim 1, wherein when the signal-processed data stored in the second storage means is post-processed by the signal processing means and then output to the outside, The fourth storage means outputs a transfer request signal to the control means when the signal-processed data read from the second storage means reaches a certain amount and the data is output to the outside, and the control means Arbitrates the transfer request signals output from the plurality of first storage means and the plurality of fourth storage means, respectively, according to a preset priority order, and transfers the transfer request signals from the plurality of fourth storage means. When the transfer request signal is received, the signal-processed data stored in the second storage means is transferred to the fourth storage means, and the data is transferred from the plurality of fourth storage means. Request signal The activation signal of the signal processing program in the signal processing means, the signal processing apparatus characterized by. 3. A signal processing device for processing a plurality of asynchronously input signals from the outside, wherein the plurality of asynchronous signals are stored for each synchronization signal and stored for each synchronization signal. When the data reaches a certain amount, the data is transferred to the second storage means composed of a plurality of areas defined for each of the synchronization signals, and the first storage means for outputting an interrupt signal, and the plurality of each of them are asynchronous. Third storage means for storing a signal processing program corresponding to each synchronization signal of the signal, and, when the interrupt signal is input, fetches data from a defined area of the second storage means, The signal processing program corresponding to the data is read from the storage means of No. 3 and signal processing is performed by a parallel arithmetic unit including a plurality of arithmetic means, and the data after the signal processing is defined in the second storage means. Signal processing means for outputting the signal processed area from the defined area of the second memory means and a plurality of fourth memory means for reading the data after the signal processing from the defined area of the second memory means and outputting the data to the outside. A signal processing apparatus, characterized in that, when processing of certain data is being executed when the interrupt signal is input to the means, the data being processed is made to wait and processing by the interrupt signal is performed. 4. The signal processing apparatus according to claim 1 or 3, further comprising: fifth storage means for generating delay data, wherein the processing program includes data transfer to the fifth storage means. A signal processing device characterized by the above. 5. A signal processing method for processing a plurality of asynchronous signals input from the outside using a parallel arithmetic unit including a plurality of arithmetic means, wherein a plurality of asynchronously input data are synchronized signals. A storage step of storing each of the synchronization signals, and a flag for generating a flag of each of the synchronization signals when the data of each of the synchronization signals stored in the storage step reaches the amount of data required for calculation by the parallel arithmetic unit In the generation step, in the flag confirmation step for confirming the generation of the flag for each of the synchronization signals, and in the flag confirmation step, if at least one of the flags for each of the synchronization signals is confirmed, the parallel computing unit A signal processing step of performing signal processing of a predetermined amount of data indicated by a flag having a high priority set in advance among the confirmed flags. After the signal processing step, returns to the flag confirmation step, the signal processing method of forming a loop, characterized in that. 6. A signal processing method for processing a plurality of asynchronous signals input from the outside using a parallel arithmetic unit including a plurality of arithmetic means, wherein a plurality of asynchronously input data are synchronized signals. A storage step of storing each of the synchronization signals, and a flag for generating a flag of each of the synchronization signals when the data of each of the synchronization signals stored in the storage step reaches the amount of data required for calculation by the parallel arithmetic unit In the generating step and in the flag generating step, when a flag for each of the synchronization signals is generated, an interrupt generation step for generating an interrupt by the generated flag, and a flag for each synchronization signal generated in the interrupt generation step are When the flag confirmation step to confirm and the flag for each of the above synchronization signals are confirmed, processing is being executed in the parallel computing unit. A signal processing step of saving data, and performing a signal processing of a predetermined amount of data indicated by the confirmed flag, the signal processing of the data saved in the signal processing step after the signal processing step. Returning to execution, a signal processing method characterized by the above. 7. A signal processing method for processing a plurality of asynchronous signals input from the outside by using a parallel arithmetic unit including a plurality of arithmetic means during execution of other processing, wherein the plurality of asynchronous signals are asynchronously processed. When the storage step of storing the input data for each synchronization signal and the data for each synchronization signal stored in the storage step reaches the data amount necessary for the calculation by the parallel arithmetic unit, the synchronization is performed. A flag generation step for generating a flag for each signal, and at least one flag for each synchronization signal is generated in the flag generation step, and a flag having a high priority set in advance among the generated flags. Interrupt generation step for generating an interrupt by the above, and when the above interrupt is generated, other interrupts are prohibited, A signal processing step of performing signal processing of a predetermined amount of data indicated by a flag with a high order, and after the signal processing is completed in the above signal processing step, another interrupt that has been prohibited is enabled and an interrupt occurs. A signal processing method characterized by returning to the execution of the above-mentioned other processing that was being performed at the time point. 8. A signal processing method for processing a plurality of asynchronous signals input from the outside by using a parallel arithmetic unit including a plurality of arithmetic means while executing another process, wherein the plurality of asynchronous signals are asynchronously processed. The storing step of storing the input data for each synchronization signal, and the synchronization for each synchronization signal when the data stored for each synchronization signal in the storage step reaches the data amount required for calculation by the parallel arithmetic unit A flag generating step of generating a flag for each signal; and an interrupt generating step of generating an interrupt by a preset high priority flag when at least one of the synchronization signals is generated in the flag generating step, When an interrupt is generated, the data being executed at that time is saved, and the parallel computing unit indicates the flag with the higher priority. A signal processing step of performing signal processing of a predetermined amount of data, and when an interrupt with a higher priority than the signal processing being executed occurs in the signal processing step, the signal processing step is executed in the signal processing step. Interrupt the internal processing to save the data, perform the signal processing by the interrupt with higher priority, and after the signal processing in the above signal processing step is completed, return to the execution of the processing performed at the time of the interrupt A signal processing method characterized by the following.