JP2003023770A - Switched capacitor type stabilized power supply - Google Patents

Abstract

(57) [Problem] To provide a switched capacitor type stabilized power supply device which outputs a reset signal when an output voltage is abnormal and has a small mounting area. SOLUTION: A capacitor C1 and a switching element S are provided.
Includes a booster circuit consisting of W1～SW4, and outputs the boosted DC voltage V _in by switching the charging and discharging of the capacitor C1 by the switching operation of the switching element SW1~SW4 is applied to the input terminal IN during discharge of the capacitor C1 switches In the stabilized capacitor type power supply, an output voltage monitoring circuit 13 for monitoring the presence or absence of an output abnormality in which the voltage of the capacitor C3 is out of a predetermined range and transmitting an output abnormality occurrence signal S2 when an output abnormality occurs, Signal S
2 and a reset signal transmission circuit 14 for transmitting a reset signal S3 to the terminal 7 when mounted on the one-chip semiconductor integrated circuit device 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor type stabilized power supply device.

[0002]

2. Description of the Related Art A conventional switched capacitor type stabilized power supply device will be described with reference to FIG. Input terminal I
N and the positive polarity side of the capacitor C2 are connected via the terminal 2 to one end of the switching element SW1 and the switching element SW4.
Connected to one end of the connection node. The negative side of the capacitor C2 is grounded.

The other end of the switching element SW1 is connected to one end of the switching element SW2, and the switching element S1
The other end of W2 is connected to terminal 1. Switching element S
The other end of W4 is connected to one end of switching element SW3, and the other end of switching element SW3 is grounded via terminal 4. One end of the capacitor C1 is connected to the connection node between the switching element SW1 and the switching element SW2 via the terminal 6, and the other end of the capacitor C1 is connected to the connection node between the switching element SW3 and the switching element SW4 via the terminal 5. Connected.

Terminal 1 has one end of resistor R1 and capacitor C3
Is connected to the output terminal OUT. The other end of the capacitor C3 is grounded. The other end of the resistor R1 is grounded via the resistor R2.

The connection node between the resistors R1 and R2 is connected to the non-inverting input terminal of the comparator 10 via the terminal 3. The positive side of the constant voltage source 11 that outputs the reference voltage V _ref1 is connected to the inverting input terminal of the comparator 10. The negative side of the constant voltage source 11 is grounded via the terminal 4. The output terminal of the comparator 10 is connected to the control circuit 12, which controls the switching elements SW1 to S1.
It is connected to the control terminal of W4. The comparator 10 has a hysteresis function. And the input terminal I
N, output terminal OUT, capacitors C1 to C3, resistor R
Parts other than 1 and the resistor R2 are mounted on the one-chip semiconductor integrated circuit device 30.

The operation of the conventional switched capacitor type stabilized power supply device having such a configuration will be described. A DC power supply (not shown) is connected to the input terminal IN, and the input terminal I
The input voltage V _in is applied to N. The control circuit 12 controls ON / OFF of the switching elements SW1 to SW4 according to the level of the output signal S1 of the comparator 10 described later. The control circuit 12 has an internal oscillator and has a period T
The level of the output signal S1 of the comparator 10 is determined every time.

The output signal S1 of the comparator 10 is low.
In case of the level, the control circuit 12 controls the switching element SW.
1 and SW3 are turned on, and the switching element SW2
And the discharge control operation of turning off the switching elements SW1 and SW3 and the ON state of the switching elements SW2 and SW4 are switched every cycle T.

On the other hand, when the output signal S1 of the comparator 10 is at the high level, the control circuit 12 does not switch the control operation for each cycle T, and the switching elements SW1 and S1.
W3 is turned on and switching elements SW2 and SW
Only the charging control operation for turning OFF the No. 4 is performed.

When the control circuit 12 performs the charge control operation, the capacitor C1 is charged and its charging voltage is V
It is _in. During this charging period, since the output current flows from the output terminal OUT toward the load (not shown) connected to the output terminal OUT, the capacitor C3 is discharged and the output voltage V
_o decreases.

On the other hand, when the control circuit 12 performs the discharge control operation, the negative polarity side of the capacitor C1 becomes the input terminal IN.
Therefore, the potential on the negative polarity side of the capacitor C1, which was zero when the control circuit 12 was performing the charge control operation, becomes V _in . Accordingly, the control circuit 12
There potential of the positive polarity side of capacitor C1 was V _in becomes 2 × V _in when had done charging control operation. In this way, during the discharge control operation, the voltage doubled is supplied to the capacitor C3, and the output voltage V _o increases.

[0011] resistor R1 and the resistor R2 is a voltage detecting means for detecting the output voltage V _o, and outputs the partial pressure V _a of the output voltage to the comparator 10. When the comparator 10 compares the divided voltage V _a and the reference voltage V _ref1 of the output voltage, the partial pressure V _a of the output voltage is the reference voltage V _ref1 or more, the output signal S1
To High level.

Since the comparator 10 is a comparator having a hysteresis function, the output signal S1 is temporarily set to Hi.
When it is set to the gh level, the divided voltage V _a of the output voltage becomes the reference voltage V a.
Even if it becomes less than _{ref1, the} output signal S1 is maintained at the high level. Then, the partial pressure V _a of the output voltage V _o is lowered output voltage becomes smaller than _{V ref1 '(<V ref1)} , it changes the output signal S1 from the High level to the Low level.

By performing such an operation, the output
Voltage division V_aTo V_ref1'To V_{ref 1}Up to the range
Output voltage V_oCan be converted to a constant voltage within a specified range.
it can.

However, the DC power source connected to the input terminal IN is a battery, and the input voltage V _in
If There greater than the upper limit of the predetermined range of the output voltage is the output voltage V _o of the DC power source connected to the case or the input terminal IN that too low (using the rated voltage), out of the range output voltage V _o is given Become. In this way, when the output voltage V _o is out of the predetermined range, I connected to the output terminal OUT
Since C (hereinafter referred to as load side IC) may malfunction, it is necessary to send a reset signal that resets the load side IC to restore the load side IC to normal operation. Therefore, the reset signal transmission circuit is used as the semiconductor integrated circuit device 30.
It was installed outside of.

[0015]

However, when the reset signal transmission circuit is provided outside the semiconductor integrated circuit device 30, there is a problem that the number of external parts and the mounting area increase. In recent years, a switched capacitor type stabilized power supply device has a blue LED or a white LE used as a backlight of a liquid crystal display mounted on a mobile phone.
The use as a drive power source of D is increasing. Since miniaturization is required for mobile phones, an increase in mounting area has been a particular problem.

In view of the above problems, it is an object of the present invention to provide a switched capacitor type stabilized power supply device which outputs a reset signal when the output voltage is abnormal and has a small mounting area.

[0017]

To achieve the above object, a switched capacitor type stabilized power supply device according to the present invention has an input terminal to which a DC voltage is applied, a capacitor and a switching means. A boosting means for switching charging / discharging of the capacitor by the switching operation of the switching means to boost and output the DC voltage when the capacitor is discharged, an output side capacitor for charging the output voltage of the boosting means, and the output side Voltage detection means for detecting the voltage of the capacitor, and ON / O of the switching means based on the voltage detected by the voltage detection means.
FF control means, monitoring means for monitoring the presence or absence of an output abnormality in which the voltage of the output side capacitor is out of a predetermined range, and transmitting an output abnormality occurrence signal when an output abnormality occurs, and receiving the output abnormality occurrence signal Then, a reset signal transmitting means for transmitting a reset signal is provided, and at least the switching means, the control means, the monitoring means, and the reset signal transmitting means are mounted on a one-chip semiconductor integrated circuit device.

Further, the monitoring means may input the voltage detected by the voltage detecting means, and when the voltage detected by the voltage detecting means is out of a predetermined setting range, the output may be abnormal.

Further, the monitoring means may detect the DC voltage, and if the DC voltage is out of a predetermined set range, the output may be abnormal. Further, a current detection unit that detects a current output from the output-side capacitor may be provided, and a lower limit value of the predetermined setting range may be changed according to the current detected by the current detection unit. The means may comprise a current mirror circuit.

Further, there is provided time detecting means for measuring the time from the time when the output abnormality occurs and controlling the control means so as to stop the boosting operation of the boosting means when the output abnormality continues for a predetermined time. It may be provided. Further, a switch is provided between the output side capacitor and the output terminal connected to the load, and when the time detecting means controls the control means so as to stop the boosting operation of the boosting means, the switch is simultaneously operated. The switch may be turned off. Further, an operation restoring means may be provided for controlling the control means and for turning on the switch so as to restart the boosting operation of the boosting means when a predetermined voltage or more is applied.

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to the drawings. The configuration of the switched capacitor type stabilized power supply device of the first embodiment according to the present invention is shown in FIG. The parts of the conventional switched capacitor of FIG. 10 that are the same as those of the power supply device are designated by the same reference numerals, and description thereof will be omitted.

The connection node between the resistors R1 and R2 is connected to the output voltage monitoring circuit 13 via the terminal 3. The output voltage monitoring circuit 13 is connected to the reset signal transmitting circuit 14, and the reset signal transmitting circuit 14 is connected to the terminal 7.
The terminal 7, the output voltage monitoring circuit 13, and the reset signal transmission circuit 14 are provided in the one-chip semiconductor integrated circuit device 30.

The output voltage monitoring circuit 13 and the reset signal transmitting circuit 14 operate as follows. Resistor R1 and resistor R2
Is a voltage detecting means for detecting the output voltage V _o , and outputs the divided voltage V _a of the output voltage to the output voltage monitoring circuit 13. The output voltage monitor circuit 13 previously stores the set range of the partial pressure V _a of the output voltage, the partial pressure V _a of the output voltage outputted from the voltage detecting means comprising a resistor R1 and the resistor R2 is in the set range If it is out of the set range, the output abnormality occurrence signal S2 is sent to the reset signal transmission circuit 14.
The setting range is determined such that the output voltage V _o is within a predetermined range (used rated voltage) within the setting range of the output voltage division voltage V _a stored in advance by the output voltage monitoring circuit 13.

When the reset signal transmission circuit 14 receives the output abnormality occurrence signal S2 from the output voltage monitoring circuit 13, it generates a reset signal S3, and outputs the reset signal S3 from the terminal 7 to the load side IC (not shown). send.

Since the switched-capacitor type stabilized power supply device of the first embodiment is provided with the output voltage monitoring circuit 13 and the reset signal transmitting circuit 14, it is reset when the output voltage V _o is out of the predetermined range and the output is abnormal. The signal S3 can be output. In addition, switching elements SW1 to SW
4, control circuit 12, comparator 10, constant voltage source 11,
Since the output voltage monitoring circuit 13 and the reset signal transmission circuit 14 are provided in the one-chip semiconductor integrated circuit device 30 in which the control circuit 12 is mounted, the switch having a smaller mounting area than the conventional switched capacitor type stabilized power supply device is provided. It is possible to realize a stabilized capacitor type power supply device.

Next, a switched capacitor type stabilized power supply device according to a second embodiment of the present invention will be described. The structure of the switched capacitor type stabilized power supply device of the second embodiment is shown in FIG. The same parts as those of the switched capacitor type stabilized power supply device of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The output voltage monitoring circuit 13 is connected to the reset signal transmission circuit 14 and the time detection circuit 15. Further, the time detection circuit 15 is connected to the control circuit 12 and the reset signal transmission circuit 14. The time detection circuit 15 is provided in the one-chip semiconductor integrated circuit device 30.

The operations of the output voltage monitoring circuit 13, the reset signal transmission circuit 14, and the time detection circuit 15 will be described with reference to the configuration diagram of FIG. 2 and the time chart of FIG.
At time t1, the output voltage V _o is less than the lower limit value V _thl of a predetermined range (using the rated voltage). Since partial pressures V _a of the output voltage at this time is less than the set range, the output voltage monitor circuit 13 sends an output abnormality occurrence signal S2 to the reset signal generation circuit 14 and the time detector circuit 15.

Upon receiving the output abnormality occurrence signal S2 from the output voltage monitoring circuit 13, the reset signal transmission circuit 14 generates a reset signal S3 and outputs the reset signal S3 from the terminal 7 to the load side IC (not shown). send. Therefore,
As shown in FIG. 3, the rising edge of the reset signal S3 appears at time t1. Further, when the time detection circuit 15 receives the output abnormality occurrence signal S2, it starts time measurement.

Unless the stop signal S4 described later is input, the reset signal transmission circuit 14 continues to output the reset signal S3 and the time detection circuit 15 while the output abnormality monitoring signal S2 is being output from the output voltage monitoring circuit 13. Continue to measure time.

Then, a predetermined time Tc has elapsed from time t1 without interruption of the output abnormality occurrence signal S2 and time t
When it becomes 2, the time detection circuit 15 sends the stop signal S4 to the control circuit 12 and the reset signal transmission circuit 14.
When the control circuit 12 receives the stop signal S4, it turns off the switching elements SW1 and SW3 and turns on the switching elements SW2 and SW4. Therefore, the charging control operation is not performed regardless of the level of the output signal S1 of the comparator 10. That is, the boosting operation is stopped. The control circuit 12 resumes the normal operation after a lapse of a predetermined time after the stop signal S4 is not output from the time detection circuit 15.

In this way, the switching elements SW1 and SW3 are in the OFF state, and the switching elements SW2 and SW3.
After 4 is turned on, the electric charge stored in the capacitor C3 is discharged in the load side IC and the resistors R1 and R2. Therefore, after the time t2, the output voltage V _o sharply decreases and becomes zero when the discharge of the capacitor C3 is completed. Further, when the reset signal transmitting circuit 14 receives the stop signal S4, it stops transmitting the reset signal S3. Therefore, as shown in FIG. 3, the falling edge of the reset signal S3 appears at time t2.

Before the predetermined time Tc elapses from the time t1, the output voltage V _o is within the predetermined range, that is, the lower limit value V.
_When it returns to the range above _{thl and} below the upper limit value V _thh , the stop signal S4 is _sent from the time detection circuit 15 to the control circuit 12.
Is never sent.

That is, in the case of a momentary fluctuation of the output voltage V _o such that the output voltage V _o goes out of the predetermined range and then returns to the predetermined range immediately, the reset signal is generated at the moment when the fluctuation occurs. S3 is transmitted, and then the load side I continues
It provides an output voltage V _o to C. On the other hand, when the output voltage V _o does not return to the predetermined range within the predetermined time after it goes out of the predetermined range, for example, the DC power source connected to the input terminal IN is a battery, and the battery is exhausted. Output voltage V
_{When o} decreases, the voltage supply to the load side IC is stopped by stopping the boosting operation. As a result, the output voltage outside the predetermined range is not supplied to the load side IC for a long time, and the load side IC is less likely to be damaged.

Next, a switched capacitor type stabilized power supply device according to a third embodiment of the present invention will be described. The configuration of the switched capacitor type stabilized power supply device of the third embodiment is shown in FIG. The same parts as those of the switched capacitor type stabilized power supply device of the second embodiment shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

The switched capacitor type stabilized power supply device of the third embodiment is different from the switched capacitor type stabilized power supply device of the second embodiment in that instead of the terminal 1, terminals 1 ', 1'', And 1 ′ ″, and further, a terminal 8, a switching element 16, a comparison circuit 17, and a constant voltage source 18. In addition, terminals 1 ', 1'',
1 ″ ′, the terminal 8, the switching element 16, the comparison circuit 17, and the constant voltage source 18 are provided in the one-chip semiconductor integrated circuit device 30.

One end of the switching element 16 is connected to the switching element SW2. Then, the connection node is connected to one end of the capacitor C3 via the terminal 1 ″,
It is connected to one end of the resistor R1 via the terminal 1 ″. Further, the other end of the switching element 16 is connected to the output terminal OUT via the terminal 1 '.

The terminal 8 and the positive side of the constant voltage source 18 are connected to the comparison circuit 17. The negative electrode side of the constant voltage source 18 is grounded via the terminal 4. Then, the time detection circuit 15 and the comparison circuit 17 are connected to the control terminal of the switching element 16. The comparison circuit 17 is also connected to the control circuit 12.

The output voltage monitoring circuit 13, the reset signal transmitting circuit 14, the time detecting circuit 15, the switching element 16,
The operation of the comparator circuit 17 and the configuration of FIG. 4 and FIG.
This will be described with reference to the time chart of. At time t1, the output voltage V _o is less than the lower limit value V _thl of a predetermined range (using the rated voltage). Since partial pressures V _a of the output voltage at this time is less than the set range, the output voltage monitor circuit 13
Outputs an output abnormality occurrence signal S2 to the reset signal transmission circuit 14 and the time detection circuit 15.

When the reset signal transmitting circuit 14 receives the output abnormality occurrence signal S2 from the output voltage monitoring circuit 13, it generates a reset signal S3 and outputs the reset signal S3 from the terminal 7 to the load side IC (not shown). send. Therefore,
As shown in FIG. 5, the rising edge of the reset signal S3 appears at time t1. Further, when the time detection circuit 15 receives the output abnormality occurrence signal S2, it starts time measurement.

Unless the stop signal S4 described later is input, the reset signal transmission circuit 14 continues to output the reset signal S3 while the output abnormality monitoring signal S2 is output from the output voltage monitoring circuit 13, and the time detection circuit 15 Continue to measure time.

Then, a predetermined time Tc elapses from the time t1 without interruption of the output abnormality occurrence signal S2, and then the time t
When it becomes 2, the time detection circuit 15 sends the stop signal S4 to the control circuit 12, the reset signal transmission circuit 14, and the switching element 16. The control circuit 12 uses the stop signal S
When 4 is received, the switching elements SW1 and SW3 are turned off.
Since the FF state and the switching elements SW2 and SW4 are turned on, the charge control operation is not performed regardless of the level of the output signal S1 of the comparator 10. That is, the boosting operation is stopped. Incidentally, unlike the case of the switched capacitor type stabilized power supply device of the second embodiment, the control circuit 12
Does not resume the normal operation even if a predetermined time elapses after the stop signal S4 is no longer output from the time detection circuit 15.

Further, the switching element 16 has the stop signal S
4 turns from the ON state to the OFF state. The switching element 16 maintains the OFF state even after the stop signal S4 is no longer output from the time detection circuit 15.

Thus, the switching elements SW1 and S
W3 is OFF, switching elements SW2 and SW4
Is turned on and the switching element 16 is turned off, the electric charge stored in the capacitor C3 is discharged in the resistors R1 and R2. Switching element 16 is OF
Since it is in the F state, unlike the switched capacitor type stabilized power supply device of the second embodiment, it is not discharged in the load side IC. Further, the reset signal transmission circuit 14 causes the stop signal S4
When receiving the, the transmission of the reset signal S3 is stopped. Therefore, as shown in FIG. 5, at time t2, the reset signal S
A falling edge of 3 appears.

Before the predetermined time Tc elapses from the time t1, the output voltage V _o is within the predetermined range, that is, the lower limit value V.
_When it returns to the range of _thl or more and the upper limit value V _thh or less, the stop signal S is transmitted from the time detection circuit 15 to the control circuit 12, the reset signal transmission circuit 14, and the switching element 16.
4 is never sent.

That is, in the case of a momentary change in the output voltage such that the output voltage V _o goes out of the predetermined range and then immediately returns into the predetermined range, the reset signal S2 is output at the moment when the change occurs. After that, the output voltage V _o is continuously supplied to the load side IC. On the other hand, if the output voltage V _o does not return to the predetermined range after the predetermined time elapses after the output voltage V _o goes out of the predetermined range, for example, the DC power source connected to the input terminal IN is a battery, and the battery is exhausted. Output voltage V
When o decreases, the boosting operation is stopped and the load side I
The power supply to C is cut off. As a result, the time during which the output voltage outside the predetermined range is supplied to the load-side IC can be limited to the time Tc shown in FIG. 5, and the risk of damage to the load-side IC can be further reduced.

The comparison circuit 17 sends a return signal S5 to the switching element 16 and the control circuit 12 if the voltage signal input from the terminal 8 is equal to or higher than the voltage V _ref2 sent from the constant voltage source 18. Upon receiving the return signal S5, the switching element 16 is turned on and the control circuit 12 resumes the normal control operation. The switching element 16 is turned on even after the return signal S5 is not output from the comparison circuit 17.
Stay in the state.

In the switched-capacitor type stabilized power supply device of the second embodiment, the control circuit 12 may restart the normal operation in the abnormal output state where the output voltage V _o is outside the predetermined range. In the switched capacitor type stabilized power supply device of the embodiment, the voltage V _ref2 sent by the constant voltage source 18
If the above voltage signal is not input from the terminal 8 to the comparison circuit 17, the switching element 16 will not be in the ON state, and the control circuit 12 will not restart the normal control operation. As a result, in the switched capacitor type stabilized power supply device of the third embodiment, it is possible to prevent the output voltage V _o from recovering in an abnormal output state outside the predetermined range.

Next, a switched capacitor type stabilized power supply device according to a fourth embodiment of the present invention will be described. The configuration of the switched capacitor type stabilized power supply device of the fourth embodiment is shown in FIG. The same parts as those of the switched capacitor type stabilized power supply device of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The input terminal IN is connected to the input voltage monitoring circuit 19 via the terminal 2. The input voltage monitoring circuit 19 is connected to the reset signal transmitting circuit 14, and the reset signal transmitting circuit 14 is connected to the terminal 7. The input voltage monitoring circuit 1
9 is provided in the one-chip semiconductor integrated circuit device 30.

The input voltage monitoring circuit 19 and the reset signal transmitting circuit 14 operate as follows. Input voltage monitoring circuit 19
Detects an input voltage V _in applied to the input terminal IN.
Input voltage monitoring circuit 19 previously stores the setting range of the input voltage V _in, input voltage V _in detected it is determined that it is within the setting range, if it is outside the range is the reset signal transmitting circuit 14 The output abnormality occurrence signal S2 is transmitted. It should be noted that the output voltage V _o is within a predetermined range (used rated voltage) within the setting range of the input voltage V _in stored in advance by the input voltage monitoring circuit 19.
The setting range is determined so that

When the reset signal transmission circuit 14 receives the output abnormality occurrence signal S2 from the input voltage monitoring circuit 19, it generates a reset signal S3 and sends the reset signal to the load side IC (not shown) via the terminal 7. Send S3.

The switched capacitor type stabilized power supply device of the fourth embodiment is provided with the input voltage monitoring circuit 19 and the reset signal transmission circuit 14, and therefore is reset when the output voltage V _o is out of the predetermined range and the output is abnormal. The signal S3 can be output. In addition, switching elements SW1 to SW
4, control circuit 12, comparator 10, constant voltage source 11,
Since the input voltage monitoring circuit 19 and the reset signal transmission circuit 14 are provided in the one-chip semiconductor correction machine path device 30 in which the control circuit 12 is mounted, the mounting area is larger than that of the conventional switched capacitor type stabilized power supply device. It is possible to realize a switched-capacitor type stabilized power supply device having a small power consumption.

Next, a switched capacitor type stabilized power supply device according to a fifth embodiment of the present invention will be described. The configuration of the switched capacitor type stabilized power supply device of the fifth embodiment is shown in FIG. The same parts as those of the switched capacitor type stabilized power supply device of the second embodiment of FIG. 2 and the switched capacitor type stabilized power supply device of the fourth embodiment of FIG. Omit it.

The input voltage monitoring circuit 19 is connected to the reset signal transmission circuit 14 and the time detection circuit 15. Further, the time detection circuit 15 is connected to the control circuit 12 and the reset signal transmission circuit 14.

Input voltage monitoring circuit 19, reset signal transmission
The operation of the circuit 14 and the time detection circuit 15 will be described.
It Fifth Embodiment Switched Capacitor Stabilized Power Supply
Since the boosting ratio of the device is fixed at 2 times, the output voltage
V_oCan be greater than or equal to the lower limit of the specified range (operating rated voltage).
Input voltage V_inHas a lower limit. In addition, in the fifth embodiment
Switched capacitor type stabilized power supply can only boost
There is no output voltage V _oWithin the specified range (used rated voltage)
Input voltage V that can be less than or equal to the upper limit of_inHas an upper limit. Servant
Output voltage V_oWithin the prescribed range (rated voltage)
Corresponding input voltage V_inThe setting range of can be set.
The input voltage monitoring circuit 19 uses the input voltage V_inSetting range of
Is stored in advance. Input voltage V_inGoes out of the setting range
And the input voltage monitoring circuit 19 uses the reset signal transmission circuit 14
And an output abnormality occurrence signal S2 to the time detection circuit 15
It

When the reset signal transmitting circuit 14 receives the output abnormality occurrence signal S2 from the input voltage monitoring circuit 19, it generates a reset signal S3 and outputs the reset signal S3 from the terminal 7 to the load side IC (not shown). send. When the time detection circuit 15 receives the output abnormality occurrence signal S2,
Start time measurement.

Unless the stop signal S4 described later is input, the reset signal transmission circuit 14 continues to output the reset signal S3 while the output abnormality occurrence signal S2 is being output from the input voltage monitoring circuit 19, and the time detection circuit 15 is Continue to measure time.

When the output abnormality occurrence signal S2 is not interrupted and a predetermined time has elapsed, the time detection circuit 15
Sends a stop signal S4 to the control circuit 12 and the reset signal transmission circuit 14. When the control circuit 12 receives the stop signal S4, it turns off the switching elements SW1 and SW3 and turns on the switching elements SW2 and SW4. Therefore, the charging control operation is not performed regardless of the level of the output signal S1 of the comparator 10. That is, the boosting operation is stopped. The control circuit 12 resumes the normal operation after a lapse of a predetermined time after the stop signal S4 is not output from the time detection circuit 15.

In this way, the switching elements SW1 and SW3 are in the OFF state, and the switching elements SW2 and SW3.
After 4 is turned on, the electric charge stored in the capacitor C3 is discharged in the load side IC and the resistors R1 and R2. Further, the reset signal transmission circuit 14 causes the stop signal S4
When receiving the, the transmission of the reset signal S3 is stopped.

It should be noted that the output of the reset signal S3 is started from a predetermined time.
Input voltage V before _inWithin the setting range
When returned, the time detection circuit 15 and the control circuit 12 and
The stop signal S4 is sent to the set signal transmission circuit 14.
Not.

That is, _in the case of a momentary fluctuation of the input voltage _in which the input voltage V _in goes out of the setting range and then immediately returns into the setting range, a reset signal is transmitted at the moment when the fluctuation occurs. After that, the output voltage is continuously supplied to the load side IC. On the other hand, when the input voltage V _in does not return to the set range within the predetermined time after it goes out of the set range, for example, the DC power source connected to the input terminal IN is a battery, and the input is caused by exhaustion of the battery. If the voltage V _in decreases stops the voltage supply to the load side IC by stopping the boosting operation. As a result, the output voltage outside the predetermined range is not supplied to the load side IC for a long time, and the load side IC is less likely to be damaged.

Next, a switched capacitor type stabilized power supply device according to a sixth embodiment of the present invention will be described. FIG. 8 shows the configuration of the switched capacitor type stabilized power supply device of the sixth embodiment. The same parts as those of the switched capacitor type stabilized power supply device of the third embodiment shown in FIG. 4 and the switched capacitor type stabilized power supply device of the fifth embodiment shown in FIG. Omit it.

The switched capacitor type stabilized power supply device of the sixth embodiment is different from the switched capacitor type stabilized power supply device of the fifth embodiment in that instead of terminal 1, terminals 1 ', 1'', 1 ″ ′, and further includes a terminal 8, a switching element 16, a comparison circuit 17, a constant voltage source 18, and an output current detection circuit 20. The output current detection circuit 20 is a one-chip semiconductor integrated circuit device 30.
To be installed on.

One end of the switching element 16 is connected to the switching element SW2. Then, the connection node is connected to one end of the capacitor C3 via the terminal 1 ″,
It is connected to one end of the resistor R1 via the terminal 1 ″. Further, the other end of the switching element 16 is connected to the output terminal OUT via the terminal 1 '.

The terminal 8 and the positive side of the constant voltage source 18 are connected to the comparison circuit 17. The negative electrode side of the constant voltage source 18 is grounded via the terminal 4. Then, the time detection circuit 15 and the comparison circuit 17 are connected to the control terminal of the switching element 16. The comparison circuit 17 is also connected to the control circuit 12. Further, the output current detection circuit 20 is connected to the input voltage monitoring circuit 19.

Reset signal transmission circuit 14, time detection circuit
15, switching element 16, comparison circuit 17, and input
The operation of the voltage monitoring circuit 19 will be described. Sixth embodiment
Boosting Factor for a Switched-Capacitor Stabilized Power Supply in Normal State
Is fixed at twice, the output voltage V_oThe prescribed range
Input voltage V that can exceed the lower limit of the enclosure (rated voltage)_{i n}
Has a lower limit. In addition, the switched capacitor of the fifth embodiment.
Since the Pashita type stabilized power supply can only boost the voltage, the output
Voltage V_oBelow the upper limit of the specified range (operating rated voltage)
Possible input voltage V_inHas an upper limit. Therefore, the output voltage
V_oInput voltage corresponding to the specified range (rated voltage)
V_inThe setting range of can be set. Input voltage monitoring times
Path 19 has this input voltage V_inPre-store the setting range of
There is. Input voltage V_inIs outside the setting range, the input voltage monitor
The visual circuit 19 includes a reset signal transmission circuit 14 and a time detection circuit.
The output abnormality occurrence signal S2 is sent to the path 15.

When the reset signal transmission circuit 14 receives the output abnormality occurrence signal S2 from the input voltage monitoring circuit 19, it generates a reset signal S3 and outputs the reset signal S3 from the terminal 7 to the load side IC (not shown). send. When the time detection circuit 15 receives the output abnormality occurrence signal S2,
Start time measurement.

Unless the stop signal S4 described later is input, the reset signal transmission circuit 14 continues to output the reset signal S3 while the output abnormality occurrence signal S2 is being output from the input voltage monitoring circuit 19, and the time detection circuit 15 is Continue to measure time.

When the output abnormality occurrence signal S2 is not interrupted and a predetermined time has elapsed, the time detection circuit 15
Sends a stop signal S4 to the control circuit 12, the reset signal transmission circuit 14, and the switching element 16. When the control circuit 12 receives the stop signal S4, the switching element S
W1 and SW3 in OFF state, switching element SW2
Since SW4 and SW4 are turned on, the charge control operation is not performed regardless of the level of the output signal S1 of the comparator 10. That is, the boosting operation is stopped. Unlike the case of the switched capacitor type stabilized power supply device of the fifth embodiment, the control circuit 12 causes the time detection circuit 15 to output the stop signal S4.
The normal operation is not restarted even if a predetermined time elapses after is not output.

Further, the switching element 16 has the stop signal S
4 turns from the ON state to the OFF state. The switching element 16 maintains the OFF state even after the stop signal S4 is no longer output from the time detection circuit 15.

Thus, the switching elements SW1 and S
W3 is OFF, switching elements SW2 and SW4
Is turned on and the switching element 16 is turned off, the electric charge stored in the capacitor C3 is discharged in the resistors R1 and R2. Switching element 16 is OF
Since it is in the F state, unlike the switched capacitor type stabilized power supply device of the fifth embodiment, it is not discharged in the load side IC. Further, the reset signal transmission circuit 14 causes the stop signal S4
When receiving the, the transmission of the reset signal S3 is stopped.

It should be noted that a predetermined period has elapsed since the output of the reset signal S3 was started.
Input voltage V before _inWithin the setting range
When returned, the time detection circuit 15 and the control circuit 12 and
The stop signal S4 is sent to the set signal transmission circuit 14.
Not.

That is, _{in the} case of a momentary fluctuation of the input voltage such that the input voltage V _in goes out of the setting range and then returns to the setting range immediately, a reset signal is transmitted at the moment of the fluctuation. After that, the output voltage is continuously supplied to the load side IC. On the other hand, when the input voltage V _in does not return to the set range within the predetermined time after it goes out of the set range, for example, the DC power source connected to the input terminal IN is a battery, and the input is caused by exhaustion of the battery. If the voltage V _in decreases stops the boosting operation, and to cut off the power supply to the load side IC. As a result, the output voltage outside the predetermined range can be supplied to the load-side IC only for a predetermined time from the output of the reset signal to the output of the stop signal, which may damage the load-side IC. Can be further reduced.

The comparison circuit 17 sends a return signal S5 to the switching element 16 and the control circuit 12 if the voltage signal input from the terminal 8 is equal to or higher than the voltage V _ref2 sent from the constant voltage source 18. Upon receiving the return signal S5, the switching element 16 is turned on and the control circuit 12 resumes the normal control operation. The switching element 16 is turned on even after the return signal S5 is not output from the comparison circuit 17.
Stay in the state.

In the switched capacitor type stabilized power supply device of the fifth embodiment, the control circuit 12 may restart the normal operation in the abnormal output state where the output voltage V _o is out of the predetermined range. In the switched capacitor type stabilized power supply device of the embodiment, the voltage V sent from the constant voltage source 18
Unless the voltage signal of _ref2 or more is input from the terminal 8 to the comparison circuit 17, the switching element 16 is not turned on, and the control circuit 12 does not restart the normal control operation. As a result, in the switched capacitor type stabilized power supply device of the sixth embodiment, it is possible not to recover in the output abnormal state.

Then, the output current detection circuit 20 detects the output current flowing from the output terminal OUT to the load side IC. Input voltage monitoring circuit 19 varies the lower limit of the setting range of the input voltage V _in in accordance with the output current detected by the output current detecting circuit 20. When the output current is large, the power conversion efficiency of the switched capacitor type stabilized power supply device is deteriorated. Therefore, when the output current is small, the lower limit value of the setting range of the input voltage V _in is reduced, and when the output current is large, the input voltage is large. V
_Increase the lower limit of the in setting range. Thus, for example, the DC power source connected to the input terminal IN is a battery,
At the time when the input voltage V _in has decreased by depletion or the like of the battery can be used longer battery.

Here, one embodiment of the output current detection circuit 20 will be described with reference to the configuration diagram of FIG. The output current detection circuit 20 is provided at the position of the switching element 16. That is, the terminal 21 is connected to the switching element SW2, the terminal 1 ″, and the terminal 1 ′ ″, the terminal 22 is connected to the terminal 1 ′, and the terminal 23 is connected to the time detection circuit 15 and the comparison circuit 17. And MOS-FET25
Operates as the switching element 16.

The stop signal S4 and the return signal S5 are input between the terminal 23 and the time detection circuit 15 and the comparison circuit 17, and the signal sent to the terminal 23 is initially set to the low level to set the stop signal S4. A circuit (not shown) for inverting the signal to be sent to the terminal 23 is provided only when either of the reset signal S5 and the return signal S5 is input.

Drain of MOS-FET 25 and MOS
The drain of the FET 26 is connected to the terminal 22. MO
The gate of the S-FET 25 and the gate of the MOS-FET 26 are connected to the terminal 23. The source of the MOS-FET 25 is connected to the terminal 21, the source of the MOS-FET 26 is connected to one end of the resistor R3, and the other end of the resistor R3 is MOS.
-Connected to the source of FET 25 and terminal 21. The non-inverting input terminal of the operational amplifier OP1 is connected to one end of the resistor R3, and the inverting input terminal of the operational amplifier OP1 is connected to the other end of the resistor R3. The output terminal of the operational amplifier OP1 is connected to the terminal 24.

The MOS-FETs 25 and 26 form a current mirror circuit having a 1: N ratio.
A current of 1 / N of the current flowing in 5 flows in the MOS-FET 26. The operational amplifier OP1 amplifies the potential difference across the resistor R3 and outputs it to the terminal 24. As a result, a voltage signal corresponding to the output current of the switched capacitor type stabilized power supply device can be output from the terminal 24. Further, the output current detection circuit 20 includes a current mirror circuit, and by increasing the value of N which is the current ratio of the current mirror, it is possible to suppress Joule heat generated in the resistor R3.

Although the switched-capacitor type stabilized power supply devices of the above-described first to sixth embodiments are the switched-capacitor type boosted stabilized power supply circuits having a boosting ratio of 2, the capacitor and the switching element are It is also possible to use a switched capacitor type boosted stabilized power supply circuit having an arbitrary boosting ratio such as 1.5 times or 3 times in which the combination is different.

[0082]

According to the present invention, since at least the switching means, the control means, the monitoring means, and the reset signal transmitting means are mounted on the one-chip semiconductor integrated circuit device, the resetting is performed when the output voltage is abnormal. It is possible to realize a switched capacitor type stabilized power supply device that outputs a signal and has a small mounting area.

Further, according to the present invention, when the monitoring means inputs the voltage detected by the voltage detecting means for detecting the voltage of the output side capacitor and the voltage detected by the voltage detecting means is outside the predetermined setting range. Since the output is abnormal, the presence or absence of the output abnormality can be monitored with a simple configuration.

Further, according to the present invention, the monitoring means detects the DC voltage applied to the input terminal, and when the DC voltage is out of the predetermined set range, the output is abnormal. Can be monitored.

Further, according to the present invention, the current detecting means for detecting the current output from the output side capacitor is provided, and the predetermined value for the DC voltage applied to the input terminal is provided according to the current detected by the current detecting means. Since the lower limit value of the setting range is variable, the predetermined setting range for the DC voltage applied to the input terminal can be corrected according to the power conversion efficiency of the switched capacitor type stabilized power supply device.
Thereby, for example, the DC power source connected to the input terminal IN is a battery, and the input voltage V
Batteries can be used longer when _in is decreasing.

Further, according to the present invention, since the current detecting means includes the current mirror circuit, the Joule heat generated in the current detecting means can be reduced by increasing the current ratio of the current mirror circuit.

Further, according to the present invention, the time for measuring the time from the time when the output abnormality occurs and for controlling the control means so as to stop the boosting operation of the boosting means when the output abnormality continues for a predetermined time. Since the detection unit is provided, the output voltage outside the predetermined range is not supplied to the load side IC for a long time, and the load side IC is less likely to be damaged.

Further, according to the present invention, a switch is provided between the output side capacitor and the output terminal connected to the load, and the time detecting means controls the control means so as to stop the boosting operation of the boosting means. At this time, since the switch is turned off at the same time, the time when the output voltage outside the predetermined range is supplied to the load side IC can be limited to the predetermined time measured by the time detecting means. This can further reduce the risk of damage to the load side IC.

Further, according to the present invention, since the operation recovery means for controlling the control means and for turning on the switch is controlled so that the boosting operation of the boosting means is restarted when a predetermined voltage or more is applied, an output abnormality occurs. It is possible not to recover in the state.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a switched capacitor type stabilized power supply device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a switched capacitor type stabilized power supply device of a second embodiment according to the present invention.

FIG. 3 is a time chart showing the operation of the switched capacitor type stabilized power supply device of the second embodiment.

FIG. 4 is a diagram showing a configuration of a switched capacitor type stabilized power supply device according to a third embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the switched capacitor type stabilized power supply device of the third embodiment.

FIG. 6 is a diagram showing a configuration of a switched capacitor type stabilized power supply device of a fourth embodiment according to the present invention.

FIG. 7 is a diagram showing a configuration of a switched capacitor type stabilized power supply device of a fifth embodiment according to the present invention.

FIG. 8 is a diagram showing a configuration of a switched capacitor type stabilized power supply device of a sixth embodiment according to the present invention.

FIG. 9 is a diagram showing one embodiment of an output current detection circuit included in the switched capacitor type stabilized power supply device of the sixth embodiment.

FIG. 10 is a diagram showing a configuration of a conventional switched capacitor type stabilized power supply device.

[Explanation of symbols]

1-8 terminals 10 comparator 11, 18 constant voltage source 12 Control circuit 13 Output voltage monitoring circuit 14 Reset signal transmission circuit 15 hours detection circuit 16 switching elements 17 Comparison circuit 19 Input voltage monitoring circuit 20 Output current detection circuit 30 1-chip semiconductor integrated circuit device

Claims (8)

[Claims] 1. An input terminal to which a DC voltage is applied, a capacitor and a switching means are provided, and the charging / discharging of the capacitor is switched by the switching operation of the switching means to boost the DC voltage when the capacitor is discharged. Boosting means for outputting, output side capacitor for charging the output voltage of the boosting means, voltage detecting means for detecting the voltage of the output side capacitor, and the switching means being turned on based on the voltage detected by the voltage detecting means. / OF
F control means, a monitoring means for monitoring the presence or absence of an output abnormality in which the voltage of the output side capacitor is out of a predetermined range, and transmitting an output abnormality occurrence signal when an output abnormality occurs, and receiving the output abnormality occurrence signal. Then, a reset signal transmitting means for transmitting a reset signal is provided, and at least the switching means and the control means,
A switched-capacitor type stabilized power supply device characterized in that the monitoring means and the reset signal transmitting means are mounted on a one-chip semiconductor integrated circuit device. 2. The output means according to claim 1, wherein the monitoring means inputs the voltage detected by the voltage detecting means, and the output is abnormal when the voltage detected by the voltage detecting means is out of a predetermined set range. Switched capacitor type stabilized power supply device. 3. The switched capacitor type stabilized power supply device according to claim 1, wherein the monitoring means detects the DC voltage, and when the DC voltage is out of a predetermined set range, an output abnormality occurs. 4. The method according to claim 3, further comprising current detecting means for detecting a current output from the output side capacitor, wherein the lower limit value of the predetermined setting range is variable according to the current detected by the current detecting means. The switched capacitor type stabilized power supply device described. 5. The switched capacitor type boosted stabilized power supply device according to claim 4, wherein the current detection means includes a current mirror circuit. 6. The time is measured from the time when the output abnormality occurs,
The switched capacitor type stability according to any one of claims 1 to 5, further comprising time detection means for controlling the control means so as to stop the boosting operation of the boosting means when the output abnormality continues for a predetermined time. Power supply. 7. A switch is provided between the output side capacitor and an output terminal connected to a load, and the time detecting means controls the control means so as to stop the boosting operation of the boosting means. 7. The switched capacitor type boosted stabilized power supply device according to claim 6, wherein the switch simultaneously turns off the switch. 8. The switch according to claim 7, further comprising operation returning means for controlling the control means and for turning on the switch so as to restart the boosting operation of the boosting means when a predetermined voltage or more is applied. Boost capacitor stabilized power supply device.