JP2003023080A - Design method of semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To provide a method of designing a semiconductor integrated circuit device which can have a desired chip speed at the time of design, despite an increase in design labor being suppressed. SOLUTION: In arranging cells, the ratio of a design value to a desired value of the driving capability of a transistor in a cell is increased as the distance between the cell and an adjacent cell is increased. If the design value of the driving capability of the transistor is uniform, as the distance between adjacent cells increases,
Although the driving capability of the transistor is reduced by mask manufacturing and lithography, a transistor having a desired driving capability at the time of design can be realized by adjusting the ratio as described above.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit device having cells including transistors as constituent elements.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor integrated circuit devices typified by LSI and the like has advanced more and more, and the processing limit is approaching. On the other hand, it is called a system-on-chip (so-called system LSI) and has various functional blocks.
Demand for products that are made into chips is also increasing, and development of technology that does not sacrifice high integration based on miniaturization, high functionality for system-on-chip, high performance, and low power consumption Is being promoted.

Among them, in microprocessors and image processing LSIs, it is important to increase the speed of chips, and it has been achieved that simulations such as system and chip design, mask fabrication, and wafer fabrication have been achieved as intended. It is an essential element for maintaining the delay performance (chip speed) predicted by. As a design method, a standard cell method, which is expected to have higher efficiency and higher performance than the gate array method and has a shorter development period than the full custom method, is generally used.

In the standard cell system, cells each having a logic gate and a necessary driving capability are incorporated as individual units. After designing a cell block that plays a functional role with a set of cells, the cell blocks between cell blocks are designed. In some cases, the design is performed in the flow of connecting the layers with wiring.
For wiring between cell blocks, usually the chip speed is calculated by delay simulation after temporary wiring, and inverter cells and buffer cells are rearranged between locations with large delays, that is, cell blocks with large delays to improve drive capability. Let

At this time, regarding the channel length in the cell which influences the driving capability, the relationship between the dimension of line and space (L / S), that is, the density and the variation of the channel length from the design value (the density dependence) is TEG. The dependency of the transistor characteristics on the layout is reduced by using the optical proximity effect correction, which is obtained in advance by evaluation by (Test Element Group) and this relationship is taken into consideration when manufacturing a mask. FIG. 3 shows a conventional example of such a design method.

[0006]

However, even if only the optical proximity effect correction that reduces only the influence of the density of L / S is reduced in order to reduce the dependence of the transistor characteristics on the layout, it will be It has been found that it is difficult to suppress the delay disparity with the design simulation. For example, when buffer cells are arranged inside a cell block and outside a cell block on a path within a chip of a certain data path, the distance between adjacent lines is a processing element in the optical proximity correction algorithm, so The channel length in the treated wafer should be the same in every cell.

However, as shown in FIG. 2, there is a difference of about 7% in the channel length in the manufactured wafer between these cells, and there is a difference between the actual product after manufacturing and the simulation at the time of design. This is a factor that widens the delay gap.
It is considered that this is due to at least one of the variation in etching of the chrome pattern in the fabrication of the mask and the variation in the light intensity in the excimer laser lithography using this mask. It is considered that it is theoretically difficult to further reduce the difference in the mask manufacturing process and the lithography process.

For this reason, in the semiconductor integrated circuit device designed according to the conventional example shown in FIG. 3, the difference in driving capability due to the difference in channel length between the cells inside the cell block and the cells outside the cell block is large. Because of this, there was a difference in the characteristics of the cells, and it was difficult to have the desired chip speed at the time of design. Therefore, the object of the present invention is to
It is an object of the present invention to provide a method for designing a semiconductor integrated circuit device that can have a desired chip speed at the time of designing, while suppressing an increase in designing labor.

[0009]

In a method of designing a semiconductor integrated circuit device according to a first aspect of the present invention, when arranging cells, the driving of transistors in the cells is increased as the distance from the adjacent cells at the location of the cells increases. Increase the ratio of the design value to the desired value of capacity. If the design value of the driving capability of the transistor is uniform, the driving capability of the transistor will decrease due to mask fabrication or lithography as the distance from the adjacent cell increases. Therefore, when arranging the cells, by increasing the ratio of the design value to the desired value of the driving ability of the transistor in advance as the distance from the adjacent cell increases, the desired driving ability at the time of design can be obtained. A transistor having the same can be realized.

Moreover, the ratio of the design value to the desired value of the driving ability of the transistor in the cell is adjusted not in the fabrication of the mask for lithography but in the placement of the cell. Units such as cells and cell blocks are easier to identify at the stage when functional / logical information exists, so this adjustment can be made by adjusting the ratio of the driving capability of the transistors in the cells when arranging the cells. Done efficiently.

In the semiconductor integrated circuit device designing method according to the second aspect, the channel length is selected as the driving capability. Since the channel length has a great influence on the drivability, the ratio of the design value to the desired value of the drivability of the transistor in the cell can be easily obtained from the distance to the adjacent cell.

In the method of designing a semiconductor integrated circuit device according to a third aspect, when arranging cells, the ratio of the design value to the desired value of the drivability of the transistor in the cells having the same logic is adjusted. Since the cells having the same logic have the same distance between the transistors in each cell, the ratio of the design value to the desired value of the driving capability of the transistor in the cell can be accurately obtained from the distance to the adjacent cell.

In the method for designing a semiconductor integrated circuit device according to a fourth aspect, the ratio of the design value to the desired value of the drivability of the transistor is adjusted in the cell for wiring driving arranged outside the cell block when the cell is arranged. It Since the drivability of the transistor in the cell for wiring driving has a great influence on the drivability of the entire semiconductor integrated circuit device, the ratio of the design value to the desired value of the drivability of the transistor in the cell can be easily calculated from the distance between adjacent cells. Can be obtained.

In the method for designing a semiconductor integrated circuit device according to a fifth aspect, when arranging cells, the ratio of the design value to the desired value of the drive capacity of the transistors in the cell is adjusted based on the drive capacity of the manufactured transistor. To be done.
Since it is the drive capacity of the transistor after manufacturing that is finally desired to be adjusted, the cell drive capacity can be adjusted by adjusting the ratio of the design value to the desired value of the drive capacity of the transistor in the cell based on the drive capacity of the manufactured transistor. The ratio of the design value to the desired value of the driving capability of the transistor in the above can be accurately obtained from the distance to the adjacent cell.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The first to third embodiments of the invention of the present application, which are applied to the design and manufacture of an LSI composed of a plurality of cell blocks and having a design standard of 0.15 μm, will be described below.
A description will be given with reference to FIGS. As shown in FIG. 1, the first to third embodiments are included in this one prior art example in addition to the same design process and manufacturing process as the one prior art example shown in FIG. Not included The following design process is included.

That is, in the first embodiment, for example, the density of cells is measured in advance by the evaluation TEG using the average value of the distances to the adjacent cells on all sides as an index, and 140 nm depending on the density of the cells, That is, a buffer cell including a transistor having a channel length shorter than the design standard by 10 nm was prepared. Then, as shown by the path in FIG. 1, this buffer cell was inserted as a repeater of a long wiring between cell blocks during layout design. As a result, the channel length in the wafer manufactured as shown in FIG. 2 is substantially uniform regardless of the cell density, and the delay difference between the actual product after manufacturing and the simulation at the time of design is 5 as well.
It was contained within%.

In the second embodiment, for example, the cell density is evaluated TE using the average value of the distances from adjacent cells on all sides as an index.
It was investigated in advance by G, and a buffer cell including a transistor having a channel length of 140 nm was prepared according to the density of the cell. Then, as shown by the path in FIG. 1, when the layout was corrected, this buffer cell was inserted as a repeater at a portion which did not satisfy the standard of the delay value of the timing verification in the long wiring between the cell blocks. . As a result, the channel length in the wafer manufactured as shown in FIG. 2 is substantially uniform regardless of the cell density, and the delay difference between the actual product after manufacture and the design simulation is within 5%. It was stored.

In the third embodiment, for example, the cell density is evaluated TE using the average value of the distances to the adjacent cells on all sides as an index.
It was investigated in advance by G, and an inverter cell including a transistor having a channel length of 140 nm was prepared according to the density of the cell. Then, as shown by the path in FIG. 1, when the layout was corrected, this inverter cell was inserted as a repeater at a portion which did not satisfy the standard of the delay value of the timing verification in the long wiring between the cell blocks. . As a result, the channel length in the wafer manufactured as shown in FIG. 2 is substantially uniform regardless of the cell density, and the delay difference between the actual product after manufacture and the design simulation is within 5%. It was stored.

In any of the above first to third embodiments, the invention of the present application is applied to a cell for driving capacity adjustment outside a cell block, but cells or cells other than cells for driving capacity adjustment are used. The invention of the present application can be applied to cells in a block. However, since the ratio of isolated cells in the cell block is small, even if trying to reflect the cell density in the cells in the cell block, not only the effect is small but also the design becomes complicated. It is preferable to apply it to the cell of.

Further, as shown in FIG. 1, in the first to third embodiments described above, a conventional channel length correction method such as optical proximity correction may be used. If the channel length correction method in the embodiment and the conventional channel length correction method are used together, the effect is increased. Further, although only the channel length is corrected in any of the above first to third embodiments, both the channel width and both the channel length and the channel width may be corrected.

The invention of the present application is preferably applied to a method of designing a semiconductor integrated circuit device by a standard cell method, but the invention of the present application is also applied to a method of designing a semiconductor integrated circuit device by a full custom method. be able to. Further, the types of LSI, chip, cell block, cell, transistor, etc. are not limited to the first to third embodiments described above.

[0022]

According to the method of designing a semiconductor integrated circuit device according to the first aspect of the present invention, since a transistor having a driving capability desired at the time of design can be realized, a semiconductor integrated circuit having a chip speed desired at the time of design. A circuit device can be realized. Moreover, since the ratio of the design value to the desired value of the driving ability of the transistor in the cell is efficiently adjusted, the increase in design labor is suppressed.

In the method for designing a semiconductor integrated circuit device according to the second aspect, the ratio of the design value to the desired value of the driving ability of the transistor in the cell can be easily obtained from the distance to the adjacent cell. It is possible to easily realize a semiconductor integrated circuit device having the above chip speed.

In the method for designing a semiconductor integrated circuit device according to a third aspect of the present invention, the ratio of the design value to the desired value of the driving ability of the transistor in the cell can be accurately obtained from the distance to the adjacent cell. It is possible to realize a semiconductor integrated circuit device having an accurate chip speed.

In the method for designing a semiconductor integrated circuit device according to the fourth aspect, since the ratio of the design value to the desired value of the driving ability of the transistor in the cell can be easily obtained from the distance to the adjacent cell, the desired value at the time of design can be obtained. It is possible to easily realize a semiconductor integrated circuit device having the above chip speed.

In the method for designing a semiconductor integrated circuit device according to the fifth aspect, the ratio of the design value to the desired value of the driving ability of the transistor in the cell can be accurately obtained from the distance to the adjacent cell, so that the desired value at the time of design can be obtained. It is possible to realize a semiconductor integrated circuit device having an accurate chip speed.

[Brief description of drawings]

FIG. 1 is a flow chart showing first to third embodiments of the invention of the present application.

FIG. 2 is a graph showing the relationship between the distance to an adjacent cell and the difference in channel length in the first to third embodiments of the invention of the present application and one conventional example.

FIG. 3 is a flow chart showing a conventional example of the invention of the present application.

Claims (5)

[Claims] 1. When arranging cells, a semiconductor integrated circuit device in which a ratio of a design value to a desired value of a driving capability of a transistor in the cell is increased as a distance from an adjacent cell in a position of the cell is increased. Design method. 2. The method for designing a semiconductor integrated circuit device according to claim 1, wherein a channel length is selected as the driving capability. 3. The method for designing a semiconductor integrated circuit device according to claim 1, wherein cells having the same logic are the cells. 4. The method for designing a semiconductor integrated circuit device according to claim 1, wherein the wiring driving cell arranged outside the cell block is the cell. 5. The method for designing a semiconductor integrated circuit device according to claim 1, wherein the ratio is adjusted in the arrangement based on the drive capability of the manufactured transistor.