JP2003017679A - Solid-state imaging device - Google Patents

Abstract

(57) Abstract: A driving voltage of a horizontal CCD shift register is reduced by suppressing a signal charge remaining in a read gate electrode. SOLUTION: A horizontal CCD shift register for transferring signal charges generated by light incident on a light receiving section, and a horizontal CCD shift register.
A read gate electrode (OG) 14 provided on the output side of the CD shift register, and a first gate insulating film in a region adjacent to the horizontal CCD shift register below the read gate electrode (OG) 14 The thicknesses of the first gate insulating film 26, the second gate insulating film 25, and the third gate insulating film 24 in the region on the side opposite to the horizontal CCD shift register are smaller than the thicknesses of the first gate insulating film 26 and the second gate insulating film 25a. Is also set thin.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an image sensor,
The present invention relates to a solid-state image pickup device (CCD image pickup device) used for a delay element or the like, and more particularly to a solid-state image pickup device capable of reducing uncharged charges when reading charges from a charge transfer unit to a charge detection unit.

[0002]

2. Description of the Related Art A solid-state image pickup device transfers a signal charge generated by light incident on a light-receiving portion to transfer a signal charge from a horizontal CCD shift register composed of a plurality of storage gates and transfer gates. It has a read gate for transferring to the charge detecting unit, a charge detecting unit for detecting the transferred signal charges, and the like.

FIG. 3 (a) is a schematic plan view of a two-phase drive horizontal CCD shift register which is an output part of a conventional CCD image sensor, and FIG. 3 (b) is a sectional view taken along line XX '. is there.

The two-phase drive horizontal CCD shift register has n
It is formed in the horizontal CCD shift register channel region 111 which is an n-type silicon layer provided on the type silicon substrate 113. A p-type silicon layer 112 is stacked between the horizontal CCD shift register channel region 111 and the n-type silicon substrate 113.

Horizontal CCD shift register channel region 1
A first gate electrode 109 composed of a storage gate 105 and a transfer gate 106 which are parallel to each other is provided on 11, and a storage gate 107 and a transfer gate 108 which are parallel to each other.
And a second gate electrode 110 composed of and are alternately and repeatedly formed, and the first CCD electrode 109 and the second gate electrode 110 form a horizontal CCD shift register 115.

A readout gate electrode (OG) 104 is provided on the output side of the horizontal CCD shift register 115,
The readout gate electrode (OG) 104 has a floating diffusion (FD) 1 that constitutes a charge detection unit that detects a signal charge from the horizontal CCD shift register 115.
05 is connected. A reset gate electrode (RG) 102 to which a reset pulse voltage (φRG) for resetting the potential of the floating diffusion (FD) 105 is applied is connected to the floating diffusion (FD) 105, and the reset gate electrode (R) is connected.
The reset drain (RD) 101 is connected to the G) 102.

Transfer gate 106 of first gate electrode 109
And the transfer gate 108 of the second gate electrode 110 is formed on the n ⁻ type silicon regions 120 and 121 in the horizontal CCD shift register channel region 111, respectively, and the floating diffusion (FD) 105 and the reset drain (RD) 101 are , On the n ⁺⁺ type silicon regions 122 and 123 in the horizontal CCD shift register channel region 111, respectively.

FIGS. 4 (a) and 4 (b) show the respective parts of FIG. 3 (b) during operation when a normal drive voltage is applied to the two-phase drive horizontal CCD shift register and when the drive voltage is lowered. It is a potential diagram of. The transfer of the signal charges in the two-phase drive horizontal CCD shift register will be described by focusing on the first gate electrode 109.

In the two-phase drive horizontal CCD shift register of FIG. 4A, a constant voltage is applied to the read gate electrode (OG) 104, and this voltage value causes a channel potential below the read gate electrode (OG) 104. (Potential potential) is also fixed at a constant potential.
In this case, when the applied voltage of the first gate electrode 109 adjacent to the read gate electrode (OG) 104 is at the HIGH level (φHhigh), the channel below the accumulation gate 105 and the transfer gate 106 of the first gate electrode 109 is The channel potential becomes deeper to form a potential packet (potential well: solid line portion), and the channel potential below the read gate electrode (OG) 104 functions as a potential barrier against the signal charge, so that the first gate electrode 109 is formed. Storage gate 1
Signal charges (hatched portion) are accumulated in the potential packet below 05.

Further, the read gate electrode (OG) 104
When the applied voltage of the first gate electrode 109 adjacent to the first gate electrode 109 is at the LOW level (φHlow), the first gate electrode 109
The channel potential below the storage gate 105 and the transfer gate 106 becomes shallow (dotted line portion). This time,
The channel potential below the read gate electrode (OG) 104 is the storage gate 105 of the first gate electrode 109.
Is set to be deeper than the channel potential on the lower side by a potential potential difference (ΔφOG) considering the transfer efficiency of signal charges. Therefore, from the storage gate 105 of the first gate electrode 109 adjacent to the read gate electrode (OG) 104 to the read gate electrode (OG) 104.
Further, a potential gradient (potential gradient) directed from the read gate electrode (OG) 104 to the floating diffusion (FD) 103 is formed, and the signal charge is transferred from the storage gate 105 of the first gate electrode 109 to the floating diffusion. (FD) 103.

As described above, the read gate electrode (OG)
The applied voltage to the first gate electrode 109 adjacent to 104 becomes HIGH level (φHhigh),
The signal charges transferred to the horizontal CCD shift register 115 are accumulated in a potential packet below the accumulation gate 105 of the first gate electrode 109, and then the applied voltage is L.
When it reaches the OW level (φHlow), it is transferred to the floating diffusion (FD) 103 via the read gate electrode (OG) 104.

Here, the horizontal CCD shift register 115
In order to transfer the signal charges in the inside, the first gate electrode 109 and the second gate electrode 110 are alternately applied with driving pulses of opposite phases, so that The signal charges transferred to the horizontal CCD shift register 115 sequentially pass through the storage gates 105 and 107 of the first gate electrode 109 and the second gate electrode 110 and are adjacent to the read gate electrode (OG) 104. Is transferred to the storage gate 105 on the output side.

In FIG. 4B, the driving voltage ΔφH (ΔφH = φHhigh− of the two-phase driving horizontal CCD shift register).
Since φHlow) becomes low, the effective potential difference (ΔφOG) between the channel potential below the read gate electrode (OG) 104 and the channel potential below the storage gate 105 of the adjacent first gate electrode 109 becomes small. . Therefore, from the storage gate 105 of the first gate electrode 109 adjacent to the read gate electrode (OG) 104 to the read gate electrode (OG) 10.
Floating diffusion (FD) 103 through 4
The electric field intensity based on the potential gradient (potential gradient) directed to the
The amount of signal charges transferred from the storage gate 105 of No. 9 to the floating diffusion (FD) 103 decreases.

[0014]

By the way, FIG. 3 (a)
The two-phase drive horizontal CCD shift register shown in FIG.
As shown in (b), when the driving voltage ΔφH becomes low, the amount of signal charges output to the floating diffusion (FD) 103 decreases, and thus the signal charges are left unsolved.

FIG. 5 shows the horizontal CCD shift register 115.
6 is a graph showing the relationship between the drive voltage ΔφH and the amount of uncharged electric charge when the signal charges are transferred. The graph in FIG. 5 shows the horizontal C
When the drive voltage ΔφH of the CD shift register 115 decreases, the transfer efficiency of the signal charge decreases, so that the read gate electrode (OG) 104 and the first gate electrode 109 adjacent to the read gate electrode (OG) 104 are accumulated. It is shown that the amount of charge left behind in the gate 105 increases.

When such a residual signal charge is left, for example, in an image sensor, the charge signal packet of one pixel is mixed with the charge remaining in the charge signal packet of the next pixel, which causes a problem in the image. Occurs. Therefore, in an image sensor or the like in which it is desired to drive the horizontal CCD shift register at a low voltage, the phenomenon that the signal charges are left behind is caused by the driving edge pressure Δ of the horizontal CCD shift register.
This will impede lowering of φH voltage.

The present invention is intended to solve such a problem, and an object thereof is to provide a solid-state image pickup device capable of reducing the driving voltage of the horizontal CCD shift register by suppressing the signal charge remaining in the read gate electrode. To provide.

[0018]

A solid-state image pickup device according to the present invention includes a charge transfer section for transferring signal charges generated by light incident on a light receiving section, and a read gate provided on the output side of the charge transfer section. And a solid-state imaging device respectively provided on a semiconductor substrate via an insulating film, wherein the thickness of the insulating film in a region below the read gate and adjacent to the charge transfer unit is the same as that of the charge transfer unit. Is set to be thinner than the film thickness of the insulating film on the opposite side.

The insulating film in the region close to the charge transfer portion has a single-layer or two-layer structure.

The insulating film in the region opposite to the front charge transfer portion has a three-layer structure or more.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a cross-sectional view of one gate electrode and its periphery of the solid-state imaging device according to the embodiment of the present invention, and FIG. 1B is a diagram showing the potential state thereof.

The solid-state imaging device shown in FIG. 1A has a horizontal CCD shift register channel region in which a p-type well layer 30 is laminated on an n ^- type silicon substrate 31 and an n ^- type silicon layer is formed on the p-type well layer 30. 29 are formed. The gate electrode 19 is provided on the horizontal CCD shift register channel region 29.

A horizontal CCD shift register which is an n-type silicon layer.
In the transistor channel region 29, n ^-Type silicon region 2
8, n⁺⁺Type silicon regions 27 are respectively formed
It

Horizontal CCD shift register channel region 2
The first to third gate insulating films 26 having a three-layer structure are formed on
A gate electrode 19 having a storage gate 15 and a transfer gate 16 serving as an output portion of the horizontal CCD shift register is formed via 25 and 24. The storage gate 15 is
It is composed of a first polysilicon film. The transfer gate 16 has a horizontal CCD shift register channel region 29.
Are provided on the respective n − type silicon regions 28, and are constituted by the second polysilicon film. On the output side of the horizontal CCD shift register, area A (floating diffusion side) 14a and area B (horizontal C)
A read gate electrode (OG) 14 having a CD shift register side) 14b is provided. The read gate electrode (OG) 14 is composed of a third polysilicon film. The readout gate electrode (OG) 14 has a floating diffusion (FD) that constitutes a charge detection unit that detects the signal charge from the horizontal CCD shift register.
13 is connected. The floating diffusion (FD) 13 is formed on the n ⁺⁺ type silicon region 27.

Horizontal CCD shift register channel region 2
The first gate insulating film 26 stacked on the substrate 9 has a thickness of 30
nm silicon oxide film (SiO₂),
The second gate insulating layer laminated on the first gate insulating film 26 is removed.
The edge film 25 is a silicon nitride film (SiN) having a thickness of 30 nm.
It is composed by. On the second gate insulating film 25
The stacked third gate insulating film 24 has a thickness of 2 nm.
Recon oxide film (SiO ₂).

A second gate insulating film 25a having a thickness of 20 nm is laminated on the first gate insulating film 26 below the B region 14b adjacent to the storage gate 15 of the read gate electrode (OG) 14. , The third gate insulating film 24 is
Not laminated. Then, a part of the read gate electrode (OG) 14 is stacked on the third gate insulating film 24.

As described above, the read gate electrode (OG)
In FIG. 14, the thickness tB of the gate insulating film in the B region 14b adjacent to the storage gate 15 is equal to the read gate electrode (O
G) Area A 1 on the floating diffusion side of 14
4A smaller than the film thickness tA of the gate insulating film,
It is set so as to satisfy the relationship of B. As a result, the channel potential below the A region 14a and the B region 14b of the read gate electrode (OG) 14 can be set deeper than the channel potential below the B region 14b.

Next, the operation of the solid-state image pickup device of the present invention will be described with reference to the potential diagram of FIG. Figure 1 (b)
As shown in the potential diagram of FIG. 3, in order to transfer the signal charge from the horizontal CCD shift register to the gate electrode 19 of the horizontal CCD shift register, φHlow = 0V and φHhigh which are binary voltage values of LOW / HIGH level.
h = 3.0V is applied alternately. This alternately applied voltage is the driving voltage of the horizontal CCD shift register ΔφH =
It is set to 3.0 V (ΔφH = φHhigh−φHlow). At this time, an arbitrary voltage is applied to the read gate electrode (OG) 14. This arbitrary voltage (V
og) may satisfy the conditions that the maximum transfer charge capacity of the horizontal CCD shift register and the transfer efficiency of signal charges do not deteriorate.

Based on this arbitrary voltage value, the A region 14a and the B region 14b of the read gate electrode (OG) 14 are formed.
The channel potential (potential potential) below is also fixed to a constant potential. In this case, when the voltage applied to the gate electrode 19 adjacent to the read gate electrode (OG) 14 is at the HIGH level (φHhigh = 3.0V), the channel below the accumulation gate 15 and the transfer gate 16 of the gate electrode 19 is The channel potential becomes deeper to form a potential packet (potential well: solid line portion), and B of the read gate electrode (OG) 14 is formed.
Since the channel potential below the region 14b functions as a potential barrier against signal charges, signal charges (hatched portion) are accumulated in the potential packet below the accumulation gate 15 of the gate electrode 19.

The voltage applied to the gate electrode 19 adjacent to the read gate electrode (OG) 14 is at the LOW level (φ
When Hlow = 0V), the channel potential below the storage gate 15 and the transfer gate 16 of the gate electrode 19 becomes shallow (dotted line portion). At this time, the A region 14a and the B region 14b of the read gate electrode (OG) 14
Is set deeper than the channel potential below the storage gate 15 of the gate electrode 19 by a potential potential difference (ΔφOG1 + ΔφOG2 and ΔφOG1) considering the transfer efficiency of signal charges. ΔφOG2 is ΔφOG2 = 0.5V
Is set to. Therefore, the read gate electrode (O
G) 14 adjacent to the storage electrode 15 of the gate electrode 19 to the read gate electrode (OG) 14, and further from the read gate electrode (OG) 14 to the floating diffusion (FD) 13 a steep potential gradient ( A potential gradient) is formed, and the signal charges are transferred from the storage gate 15 of the gate electrode 19 to the floating diffusion (FD) 13.

As a result, even if the driving voltage ΔφH of the horizontal CCD shift register is lowered, the channel potentials below the A region 14a and the B region 14b of the read gate electrode (OG) 14 are below the A region 14a. Is more than the channel potential below the B region 14b, the potential difference (Δφ
Since OG2 = 0.5 V) is set deep, it is possible to suppress the amount of charge left behind in the read gate electrode (OG) 14 and the storage gate 15 of the gate electrode 19 adjacent to the read gate electrode (OG) 14. Becomes

FIG. 2 shows the difference in film thickness of the gate insulating film and the amount of residual charge in the region of the read gate electrode (OG) 14 when the horizontal CCD shift register of the present invention is operated at the drive voltage ΔφH = 3.0V. It is a graph which shows the relationship of. From FIG. 2, the amount of charge left behind in the conventional horizontal CCD shift register is equivalent to a value where the thickness difference of the gate insulating film is 0. Therefore, in the horizontal CCD shift register of the present invention, the amount of left charge left is significantly reduced. It is understood that there is.

In the present embodiment, the horizontal CC of the gate insulating film below the read gate electrode (OG) 14 is used.
The B region 14b on the D shift register side has a two-layer structure of a first gate insulating film 26 which is a silicon oxide film (SiO ₂ ) and a second gate insulating film 25a which is a silicon nitride film (SiN), and a floating layer. Area A 1 on the fusion side
4a is a first gate insulating film 26 which is a silicon oxide film (SiO ₂ ), a second gate insulating film 25 which is a silicon nitride film (SiN) and a third gate insulating film which is a silicon oxide film (SiO ₂ ). Although the description has been given on the film 24,
The B region 14b is an insulating film composed of a single layer, and the A region 14
A may be a laminated insulating film having a three-layer structure.

In the present embodiment, the gate insulating film below the read gate electrode (OG) 14 has been described as the laminated insulating film having a multi-layer structure, but a single-layer gate insulating film may be used.

[0036]

The solid-state image pickup device of the present invention has a charge transfer section for transferring signal charges generated by the light incident on the light receiving section, and a read gate provided on the output side of the charge transfer section. In the insulating film below the read gate, the film thickness of the insulating film in the region close to the charge transfer unit is set to be smaller than the film thickness of the insulating film in the region opposite to the charge transfer unit. The driving voltage of the horizontal CCD shift register can be lowered by suppressing the signal charge remaining in the read gate electrode.

[Brief description of drawings]

FIG. 1A is a cross-sectional view of one gate electrode and its periphery of a solid-state imaging device according to an embodiment of the present invention, and FIG.
FIG. 6 is a diagram showing a state of the potential.

FIG. 2 is a graph showing a relationship between a difference in film thickness of a gate insulating film and a residual charge amount in a region of a read gate electrode (OG) 14 of a horizontal CCD shift register of the present invention.

FIG. 3A is a schematic plan view of a two-phase drive horizontal CCD shift register which is an output unit of a conventional CCD image sensor, and FIG. 3B is a cross-sectional view taken along line XX ′ thereof.

FIG. 4 (a) is a potential diagram of each part in FIG. 3 (b) at the time of operation when a normal drive voltage is applied to a two-phase drive horizontal CCD shift register, and FIG. 4 (b) shows that the drive voltage is low. FIG. 4 is a potential diagram of each part of FIG. 3B during the operation in the case of.

FIG. 5: Driving voltage Δ of a conventional horizontal CCD shift register
6 is a graph showing the relationship between φH and the amount of uncharged electric charge when transferring signal charges.

[Explanation of symbols]

13 Floating Diffusion (FD) 14 Read Gate Electrode (OG) 14a A Region (Floating Diffusion Side) 14b B Region (Horizontal CCD Shift Register Side) 15 Storage Gate 16 Transfer Gate 19 Gate Electrode 24 Third Gate Insulating Film 25 Second gate insulating film 25a Second gate insulating film 26 First gate insulating film 27 n ⁺⁺ type silicon region 28 n ⁻ type silicon region 29 horizontal CCD shift register channel region 30 p type well layer 31 n ⁻ type silicon Substrate 101 Reset drain (RD) 102 Reset gate electrode (RG) 103 Floating diffusion (FD) 104 Read gate electrode (OG) 105 Storage gate 106 Transfer gate 107 Storage gate 108 Transfer gate 109 First gate electrode 110 Second gate Gate electrode 111 horizontal CCD shift register channel region 112 p-type silicon layer 113 n-type silicon substrate 115 horizontal CCD shift register 120 n ^- -type silicon region 121 n ^- -type silicon region 122 n ⁺⁺ type silicon region 123 n ⁺⁺ type silicon region

Claims (3)

[Claims] 1. A charge transfer section for transferring a signal charge generated by light incident on a light receiving section and a read gate provided on an output side of the charge transfer section are respectively provided on a semiconductor substrate via an insulating film. In the solid-state imaging device provided, the thickness of the insulating film in a region close to the charge transfer unit below the read gate is smaller than the thickness of the insulating film in a region opposite to the charge transfer unit. The solid-state imaging device is also characterized by being set thin. 2. The solid-state imaging device according to claim 1, wherein the insulating film in a region near the charge transfer portion has a single-layer or two-layer structure. 3. The solid-state imaging device according to claim 1, wherein the insulating film in the region opposite to the front charge transfer portion has a three-layer structure or more.