JP2003017593A - Semiconductor storage device - Google Patents

Abstract

(57) [Problem] To provide a mask R while suppressing an increase in layout area
The data read time of the OM is shortened and the power consumption is reduced. SOLUTION: The four sides of a drain region 11 of a memory cell 9 are surrounded by a gate electrode 4 composed of gate electrodes 4a, 4b and 4c. These are connected in the direction of the word line 1 to form a ladder-shaped memory block.
The ladder-type gate electrode 4 is connected to the word line 1 via a gate contact 7 provided on a common connection portion 4d for electrically connecting the gate electrode 4a and the gate electrode 4b. Memory cells 9 connected to the same word line 1 share a source region 10, and the source region 10 is connected to a ground line 3 via a source contact 6. The drain regions 11 of adjacent transistors are separated by the gate electrode 4c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a mask ROM which has a high data read speed and low power consumption.

[0002]

2. Description of the Related Art In recent years, with the increase in the size of LSIs, a system LS in which a system of electric equipment is constructed on one LSI
The design of I is popular. Such a system LS
In I, from microcomputer to SRAM, DR
The memories such as AM and mask ROM are integrated on one chip. The mask ROM is a nonvolatile read-only memory, and data is written using a mask pattern in the manufacturing process. In the mask ROM mounted on such a system LSI, not only high integration but also short TAT (turnaround time), high speed access, and low power consumption are required.

As a method of a mask ROM having a short TAT,
The contact program type is widely used. The contact program type mask ROM is a system for storing data of "1" or "0" depending on whether or not there is a contact connected to a bit line. In this contact program type mask ROM, by making the layer of the contact to be programmed an upper layer, it is possible to reduce the manufacturing process after programming.

The mask ROM can be highly integrated by miniaturizing the manufacturing process, but at the same time, it is difficult to increase the speed. The majority of the data read time of the NOR type mask ROM is that the charges precharged in the parasitic capacitance of the bit line are transferred to the MOSFE of the memory cell.
It is the time taken to discharge at T. Parasitic capacitance of the bit line due to the fact that the distance between bit lines is shortened due to the miniaturization of the manufacturing process and the wiring capacitance per unit length is increased, and the number of memory cells connected to one bit line is increased due to high integration. The larger value leads to an increase in the data read time.

FIG. 6 is a plan view showing a memory cell portion of a semiconductor memory device having a conventional mask ROM. Also,
FIG. 7 is an equivalent circuit diagram showing a memory cell portion of the conventional mask ROM as shown in FIG. 6 and 7, 51 is a word line, 52 is a bit line, 53 is a ground line, 54 is a polysilicon gate, 55 is a drain contact, 56 is a source contact, 57 is a gate contact, 59 is a memory cell, and 60 is a memory cell. The source region and 61 are drain regions.

In this conventional mask ROM, each memory cell 59 is composed of one n-type MOSFET 58. The source region 60 is the source contact 56.
To the ground line 53, the polysilicon gate 54 to the word line 51 via the gate contact 57, and the drain region 61 to the drain contact 55.
Data of "1" or "0" is stored depending on whether or not it is connected to the bit line 52 via.

FIG. 8 is a circuit diagram showing an operating state of a memory cell portion of a conventional mask ROM. In FIG. 8, 51
Is a word line, 52 is a bit line, 53 is a ground line, 62
Is a program contact, 63 is a parasitic capacitance, and 64 is a current path. The parasitic capacitance 63 of the bit line 52 is precharged in advance, and when the word line 51 goes high, the n-type MOSFET 58 is turned on. At this time, n
Type MOSFET 58 is connected to bit line 52 by program contact 62, bit line 52
Potential changes to low level because it is grounded through the current path 64, and the potential of the bit line 52 remains the precharged potential when not connected to the bit line 52. The change of the potential of the bit line 52 is detected by a sense amplifier connected to the outside, so that the data "1" is output.
Alternatively, "0" is determined.

[0008]

However, in the configuration of the semiconductor memory device having the conventional mask ROM as described above, the charge precharged in the parasitic capacitance 63 of the bit line 52 is discharged by one n-type MOSFET 58. To be done. Therefore, the parasitic capacitance 63 of the large bit line 52 (the capacitance between the bit lines, the drain junction capacitance of the memory cell, etc.)
Since the electric charge accumulated in is discharged only by the n-type MOSFET 58 having a small gate width size and a small current driving capability, the bit line potential changes to a potential at which "1" or "0" is detected by the sense amplifier. The problem was that it took time.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of speeding up the data reading time while suppressing an increase in the layout area of the mask ROM. Furthermore, under the same data read time condition as the conventional one, lowering the power supply voltage enables low power consumption.

[0010]

A semiconductor memory device according to the present invention comprises a first gate electrode formed on a semiconductor region and a first gate electrode formed on the semiconductor region in parallel with the first gate electrode. A second gate electrode, a common connection portion that electrically connects the first gate electrode and the second gate electrode, and a semiconductor region sandwiched between the first gate electrode and the second gate electrode. A plurality of drain regions, a first source region formed in the semiconductor region so as to face the drain region with the first gate electrode sandwiched therebetween, and a drain region with the second gate electrode sandwiched therebetween. And a second source region formed in the semiconductor region.

According to this structure, the current path from the drain region is in the two directions of the first source region side and the second source region side due to the first and second gate electrodes.
The current drive capability per memory cell can be increased, and the data read time can be shortened. Also, the power supply voltage is reduced by the amount that the speed has increased,
It is possible to reduce power consumption.

In the above semiconductor memory device, the drain regions of the plurality of drain regions are separated from each other by an element isolation layer formed in the semiconductor region.

Further, in the above semiconductor memory device, a plurality of drain regions are separated from each other between adjacent drain regions under a third gate electrode connecting the first gate electrode and the second gate electrode. The gate electrode is formed in a ladder shape by the first, second and third gate electrodes.

According to this structure, the drain region is first,
Since the four sides are surrounded by the second and third gate electrodes, the equivalent gate width per memory cell can be three to four times larger than that of one MOSFET in the conventional memory cell. it can. Therefore, the current driving capability per memory cell is increased, and the data read time can be shortened. Further, under the same speed condition, the power supply voltage can be lowered to reduce the power consumption.

In the above semiconductor memory device, the first
And the second gate electrode is connected to the word line through a gate contact provided in the common connection portion,
The second source region is connected to the ground line via the source contact, and the bit line is connected to the desired drain region of the plurality of drain regions via the drain contact.

Further, a semiconductor layer on the oxide film layer in the SOI substrate may be used as the semiconductor region. As described above, by using the semiconductor layer on the oxide film layer, the junction capacitance of the drain region is reduced to 1/7 to 1/10, so that the parasitic capacitance of the bit line can be reduced and the data read time can be reduced. It is possible to achieve high speed and low power consumption.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a semiconductor memory device having a memory cell portion of a mask ROM according to a first embodiment of the present invention, in which (a) is a plan view. ,
(B) is sectional drawing of the XX 'place of (a).

As shown in FIG. 1, the mask ROM of the present invention.
Are a plurality of word lines 1, a plurality of bit lines 2 arranged to intersect the word lines 1, a ground line 3 arranged in parallel to the bit lines 2, and a ground line 3 arranged in parallel to the word line 1 direction. Further, a ladder-shaped gate electrode 4 including the gate electrodes 4a and 4b and the gate electrode 4c connecting the gate electrodes 4a and 4b is formed on the silicon substrate 15.

Then, on the silicon substrate 15, a plurality of drain regions 11 formed between the gate electrodes 4a and 4b and the drain region 1 with the gate electrodes 4a sandwiched therebetween.
1, a source region 10a formed at a position facing the drain electrode 11, a source region 10b formed at a position facing the drain region 11 with the gate electrode 4b interposed therebetween, and a common connection for commonly connecting the gate electrode 4a and the gate electrode 4b. The element isolation layer 8 formed under the portion 4d is formed.

The gate electrode 4 is connected to the word line 1 through the gate contact 7 formed on the common connection portion 4d, and the drain contact 5 is formed only in a desired drain region among the plurality of drain regions 11. Connected to the bit line 2 via the source regions 10a and 10
b is connected to the ground line 3 via a source contact 6 formed on the source regions 10a and 10b.
The memory cells 9 connected to the same word line 1 are configured to share the source region 10 including the source regions 10a and 10b. Further, the presence or absence of connection between the drain region 11 and the bit line 2 is determined by whether or not the contact 7a immediately below the bit line 2 is formed in the case of the configuration of FIG.

According to this structure, the N-type M of the memory cell 9 is
Each drain region 11 of the OSFET is surrounded by the gate electrode 4 composed of the gate electrodes 4a, 4b and 4c on four sides, and the gate electrode 4 is provided between the adjacent drain regions 11.
They are arranged adjacent to each other in the word line 1 direction so as to be separated under c. Therefore, the gate electrode 4 has a so-called ladder shape because a plurality of gate electrodes 4c that connect the gate electrodes 4a and the gate electrodes 4b arranged in parallel to each other are arranged at a constant interval. There is. Therefore, in this ladder-shaped gate electrode 4, when the word line 1 connected via the gate contact 7 provided on the common connection portion 4d is turned on, the four gate electrodes 4 surrounding the drain region 11 are All are turned on.

FIG. 2 is an equivalent circuit diagram of the memory cell portion of the mask ROM according to the first embodiment of the present invention. Further, FIG. 3 shows a mask R according to the first embodiment of the present invention.
It is a circuit diagram which shows the operation state of the memory cell part of OM.

2 and 3, 1 is a word line and 2 is a word line.
Is a bit line, 3 is a ground line, 9 is a memory cell, 12 is a program contact, 13 is a parasitic capacitance, 14a to 14
f is a current path, and 17a and 17b are n-type MOSFETs. One memory cell is composed of two upper and lower n-type MOSFETs 17a connected to the ground line 3 and two left and right n-type MOSFETs 17b connected to the drain regions of the adjacent memory cells.

As shown in FIG. 3, the bit line 2 is previously set.
The parasitic capacitance 13 of is precharged and the word line 1
All n-type MOs that share a word line when goes high
The SFET turns on. At this time, if the drain region of the memory cell 9 is not connected to the bit line 2 by the program contact 12, the potential of the bit line 2 remains the precharged potential. On the other hand, the memory cell 9
When the drain region of the bit line 2 is connected to the bit line 2 by the program contact 12, the electric charge accumulated in the bit line 2 is discharged through the n-type MOSFETs 17a and 17b connected to the upper, lower, left and right sides of the memory cell, and the potential of the bit line 2 becomes Change to low level. At this time, since the current is discharged through the n-type MOSFETs 17a and 17b on the upper, lower, left and right sides of the memory cell 9, the potential of the bit line 2 is faster than that in the case of discharging only one conventional n-type MOSFET. Since it changes, the data reading speed becomes faster.

The n-type M of the memory cell in this embodiment
Conventional n-type MOSFET whose gate width size is OSFET
N-type MOS that discharges the bit line, assuming the same as
The driving force of the FET is estimated to be three times or more that of the conventional case (the amount of discharge through the adjacent memory cell is 2
The driving force was estimated as half, considering it as a series n-type MOSFET). The time when bit line 2 changes is CV / I
Since C is proportional to the parasitic capacitance of the bit line, V is the bit line potential, and I is the drive current of the n-type MOSFET of the memory cell, the change time is improved to about 1/3. Further, under the condition of the data read time equivalent to the conventional one, the power supply voltage can be lowered to reduce the power consumption.

FIG. 4 is a process chart showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.
1) to (d1) are plan views, and (a2) to (d2) are (a).
It is sectional drawing of XX 'location of 1)-(d1). In FIG. 4, 1 is a word line, 2 is a bit line, 3 is a ground line, 4 is a gate electrode, 8 is an element isolation layer, 10 is a source region, 11 is a drain region, 12 is a program contact, and 16 is an oxide film. is there.

First, in the steps shown in FIGS. 4A1 and 4A2, STI (Shallow Trench Isola) is formed on the silicon substrate 15.
section) or an LOCOS oxide film is formed.

Next, in the steps shown in FIGS. 4 (b1) and 4 (b2), an oxide film and a polysilicon film are sequentially formed on the p-type silicon substrate 15, and then the oxide film and the polysilicon film are patterned by etching. A gate insulating film 16 made of an oxide film and a gate electrode 4 made of a polysilicon film.
To form. At this time, the gate electrode 4 has a so-called ladder shape in which two gate electrodes 4a arranged in parallel and the gate electrode 4b are connected by a gate electrode 4c provided at regular intervals. There is. And the gate electrode 4
The gate electrode 4b and a are commonly connected by a common connection portion 4d provided on the element isolation layer 8.

Next, in the step shown in FIGS. 4 (c1) and 4 (c2), the gate electrode 4 is used as an implantation mask to perform ion implantation of a group V impurity such as arsenic, thereby the silicon substrate 1 is implanted.
A source region 10 and a drain region 11 are formed at 5.
At this time, the drain region 11 is formed inside the ladder gate electrode 4, that is, in a region surrounded by the gate electrodes 4a, 4b, and 4c, and the source region 10 is formed outside the ladder gate electrode 4 facing the drain region 11. Is formed.

Next, in the steps shown in FIGS. 4D1 and 4D2, a contact and a metal wiring are alternately formed to form a semiconductor memory device having a multilayer wiring structure. In the metal wiring in this embodiment, the ground line 3 is formed in the first layer wiring, the bit line 2 is formed in the third layer wiring, and the word line 1 is formed in the fourth layer wiring. The program contact 12 is composed of a contact (via) of the third layer, and the presence or absence of the program contact 12 causes the presence or absence of the connection between the bit line 2 and the drain region 11 of the n-type MOSFET. Bit line 2
If the bit line 2 and the drain region 11 are not connected, the data becomes "1". If the bit line 2 and the drain region 11 are not connected, the data becomes "0".

As described above, according to the present embodiment, it is possible to shorten the data read time while suppressing the increase in the layout area of the mask ROM. That is, since the periphery of each drain region 11 is surrounded by the gate electrode 4 on all sides, two n-type MOSFETs 17a in which the source region 10 is connected to the ground line 3 as shown in FIG.
Current paths 14a and 14b flowing through the gate and the gate electrode 4
Source region 10 (ground line 3) of an adjacent transistor via two n-type MOSFETs 17b whose gates are c
Since the current paths 14c, 14d, 14e, and 14f flowing through the capacitor can discharge the charges that have been precharged in the parasitic capacitance 13, the speed can be increased.
Furthermore, under the same data read time condition as the conventional one, lowering the power supply voltage enables low power consumption.

(Second Embodiment) FIG. 5 is a configuration diagram of a memory cell portion of a mask ROM according to a second embodiment of the present invention, in which (a) is a plan view and (b) is (). a) X-
It is sectional drawing of X'place. The second embodiment basically has the same configuration as that of the first embodiment.
1, 1 is a word line, 2 is a bit line, 3 is a ground line, 4 is a gate electrode, 5 is a drain contact, 6 is a source contact, 7 is a gate contact, 8 is an element isolation layer, 9 is a memory cell, 10 is The source region 11 is a drain region.

In this second embodiment, the gate electrode 4
Is composed of two gate electrodes 4a and 4b arranged in parallel to the word line 1 direction, and the drain region 11 is formed inside by being sandwiched between the gate electrode 4a and the gate electrode 4b. The source region 10 is formed at a position facing the drain region 11 with the gate electrode 4b interposed therebetween. Also, unlike the first embodiment,
The same element isolation layer 8a as the element isolation layer 8 is provided between the drain regions 11 of the adjacent memory cells 9, and the element isolation layer 8a separates the element isolation layer 8a.

Therefore, as compared with the first embodiment, since there is no current path flowing through the adjacent transistor,
The current drive capability per memory cell is poor. However, since the gate capacitance per word line is reduced, the parasitic capacitance of the word line is reduced, and if the gate width size of the buffer that drives the word line is the same as in the first embodiment, the word width is the same. The line potential changes faster.

Therefore, according to the second embodiment, the charges can be discharged to the source region 10 in the two directions by the gate electrodes 4a and 4b, so that the data read time can be suppressed while suppressing the increase in the layout area of the mask ROM. It enables speeding up. Under the same data read time as before, lower power consumption is possible by lowering the power supply voltage.

(Third Embodiment) First and Second Embodiments
In the embodiment, a normal silicon substrate is used as the substrate, but an SOI substrate including a supporting substrate, an oxide film layer formed on the supporting substrate, and a semiconductor layer formed on the oxide film layer may be used. good. When the semiconductor layer of this SOI substrate is used, the bottom surface of the source region and the drain region of the MOSFET is in contact with a thick buried oxide film layer (Buried Oxide: BOX layer), so that the MOSF formed on a normal silicon substrate is used.
Junction capacitance of source and drain regions is 1 compared to ET
It is reduced to about / 7 to 1/10.

Therefore, of the parasitic capacitance of the bit line, the junction capacitance of the drain region is reduced, so that the parasitic capacitance of the bit line is reduced and the data read time can be shortened and the power consumption can be reduced. .

As described above, according to the present embodiment, it is possible to shorten the data read time while suppressing the increase in the layout area of the mask ROM, reduce the parasitic capacitance of the bit line, and reduce the power consumption. It can be performed. Under the same data read time condition as before, lowering the power supply voltage enables further power consumption reduction.

[0039]

According to the present invention, the number of MISFETs serving as a current path for each memory cell of the mask ROM is increased, so that the current driving capability can be increased and the data read time can be shortened. become. In addition, the power supply voltage can be lowered and power consumption can be reduced by the increased speed.

As another effect of the present invention, by forming the mask ROM on an SOI substrate, it is possible to reduce the parasitic capacitance of the bit line and to speed up the data read time and reduce the power consumption. Become.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device having a memory cell portion of a mask ROM according to a first embodiment of the present invention, in which (a) is a plan view and (b) is a position XX ′ in (a). Cross section of

FIG. 2 is an equivalent circuit diagram showing a memory cell portion of the mask ROM according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of an operating state of a memory cell portion of the mask ROM according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor memory device having the memory cell portion of the mask ROM according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a memory cell portion of a mask ROM according to a second embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view taken along the line XX ′ in (a).

FIG. 6 is a plan view showing the configuration of a semiconductor memory device having a memory cell portion of a conventional mask ROM.

FIG. 7 is an equivalent circuit diagram showing a memory cell portion of a conventional mask ROM.

FIG. 8 is a circuit diagram showing an operating state of a memory cell portion of a conventional mask ROM.

[Explanation of symbols]

1 word line 2 bit lines 3 ground lines 4 gate electrode 5 Drain contact 6 Source contact 7 Gate contact 8 element isolation layer 9 memory cells 10 Source area 11 drain region 12 Program contact 13 Parasitic capacitance 14 Current path 15 Silicon substrate 16 Gate insulating film 17a, 17b n-type MOSFET

Claims (5)

[Claims] 1. A first gate electrode formed on a semiconductor region, a second gate electrode formed on the semiconductor region in parallel with the first gate electrode, and the first gate electrode. A common connection portion that electrically connects a gate electrode and the second gate electrode, and a plurality of drains formed in the semiconductor region sandwiched between the first gate electrode and the second gate electrode A region, a first source region formed in the semiconductor region so as to face the drain region with the first gate electrode sandwiched therebetween, and a drain region that faces the drain region with the second gate electrode sandwiched therebetween. And a second source region formed in the semiconductor region. 2. The semiconductor memory device according to claim 1, wherein in the plurality of drain regions, adjacent drain regions are separated by an element isolation layer formed in the semiconductor region. Semiconductor memory device. 3. The semiconductor memory device according to claim 1, wherein the plurality of drain regions connect the first gate electrode and the second gate electrode between adjacent drain regions. The semiconductor memory device is characterized in that the gate electrode is separated under the gate electrode, and the gate electrode is formed in a ladder shape by the first, second and third gate electrodes. 4. The semiconductor memory device according to claim 1, wherein the first and second gate electrodes are word lines via a gate contact provided in the common connection portion. The first and second source regions are connected to a ground line via a source contact, and only the desired drain region of the plurality of drain regions is connected via a drain contact. A semiconductor memory device characterized in that bit lines are connected. 5. The semiconductor memory device according to claim 1, wherein the semiconductor region is a semiconductor layer on an oxide film layer in an SOI substrate. .