JP2003016988A - Focused ion beam apparatus and focused ion beam processing method using the same - Google Patents

Abstract

(57) [PROBLEMS] To provide an FIB apparatus and a FIB processing method capable of accurately cutting and connecting wiring by FIB processing on the surface of a sample such as an LSI having a flat surface. A FI placed on a stage is irradiated with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
In the apparatus B, alignment mark forming means for irradiating the FIB around the processing position to form an alignment mark, an optical microscope image of a region of the processing position where the alignment mark is formed, and FIB irradiation to the region Processing position detecting means for superimposing a scanning ion microscope image (SIM image) obtained by the method on the basis of the alignment mark image and detecting a processing position in accordance with the superimposed image. I do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a focused ion beam (FIB) apparatus and a FIB processing method using the same, and more particularly to an FIB processing for an LSI having a flattened fine multilayer wiring. And a FIB processing method using the same.

[0002]

2. Description of the Related Art Previous FIB devices have been used to cut a desired position of an LSI to expose a section for taking a scanning electron microscope (SEM) photograph. In such an application, the FIB machining position covers a relatively wide area, so that not so high accuracy is required for detecting the machining position.

However, in recent years, the FIB device has been
A wiring pattern is irradiated with a focused Ga ion beam on a sample to be processed such as an LSI in a device in a high vacuum atmosphere, and sputter etching is performed to break the wire.
By forming a new wiring pattern by VD (organic metal gas containing W) and connecting the wirings, it has come to be used for partially changing the wiring pattern.
In this way, in order to partially disconnect or connect the wiring patterns of the miniaturized LSI, it is necessary to detect the processing position with high accuracy and irradiate the FIB.

On the other hand, in order to realize a more miniaturized LSI, flattening of multi-layer wiring has become common. In the conventional multi-layered wiring, the height difference of the step portion increases, and there is a problem of disconnection failure due to a decrease in the coverage of the wiring film at the step portion or disconnection due to electromigration. Therefore, in recent years, a process of forming a wiring pattern, planarizing an interlayer insulating film covering the wiring pattern by a chemical mechanical polishing (CMP) method, and further forming a wiring pattern on the flattened layer is performed by a process such as Flattening of the multilayer wiring structure is being carried out.

Such a flattened structure of the LSI makes it very difficult to detect the processing position with high accuracy. The surface observation of the LSI loaded into the FIB device is performed by a scanning ion microscope (SIM, Scanning Ion Mic) using the FIB of the device.
This is done by scanning the beam on the LSI surface and detecting the reflected secondary electrons using the roscope function. The processing position of the surface can only be detected by relying on the surface shape of the LSI thus detected. Therefore, if there is no unevenness in the processing position, the processing position cannot be specified from the SIM image.

Therefore, it has been proposed to detect the unevenness of the connection pad usually provided around the chip by SIM and detect the processing position by moving the stage with the coordinates of the processing position as a target. In that case, the wiring pattern position of the processing target cannot be accurately specified due to the stage error caused by the stage movement.

Further, an FIB using a conventional FIB device
In processing, an image overlay method and a CAD navigation method have been proposed as methods for obtaining a processing position. In the image overlay method, an image of the processing position is acquired in advance by an optical microscope, the sample is loaded into the FIB device, and the stage is driven to move to the coordinates of the processing position of the sample. Are superposed by adjusting the magnification and rotation, and the processing position is detected and FIB processing is performed by relying on the superposed optical microscope images. Since the optical microscope can detect not only the surface shape but also the Al wiring pattern shape of the lower layer, it is effective for detecting the wiring pattern position under the area where the surface is flat. Moreover, both the images corresponding to the concavo-convex pattern existing on the LSI surface of the sample are used for superimposing the SIM image and the optical microscope image.

In the CAD navigation method, the FI
By linking the stage coordinates of the B device with the CAD data that is the pattern data of the LSI design data, the machining position is changed to C
By designating on the AD data, the stage automatically moves to the processing position of the sample. In the linking process above,
A CAD data image is superimposed on the SIM image based on a predetermined pattern such as a connection pad provided around the LSI.

[0009]

In the image overlay method described above, it is necessary that the uneven pattern of the uppermost layer exists around the processing position on the LSI surface. Therefore, when there is no concave-convex pattern on the surface over a wide area, the optical microscope image in the processed area cannot be overlaid on the SIM image, and the processing position in that area cannot be detected. Further, in the CAD navigation method, there is a case where a stage displacement occurs due to a stage accuracy error as the stage moves from a connection pad position provided on the periphery of the chip to a processing position inside the chip. It is difficult to detect the machining position. Further, even in the CAD navigation method, it is necessary to superimpose the CAD data image on the SIM image with reference to the uneven pattern around the processing position, which results in accurate processing position in the flattened area with few uneven patterns. Difficult to detect.

Therefore, it is an object of the present invention to provide a FIB apparatus capable of accurately detecting the FIB processing position on the flattened sample surface, and a FIB processing method using the FIB apparatus.

A further object of the present invention is to provide a method for forming an LSI capable of accurately detecting a FIB processing position in a FIB device and a FIB processing method using the method.

[0012]

In order to achieve the above object, the first aspect of the present invention is directed to a focused ion beam (FI) for a sample mounted on a stage.
In the FIB apparatus that irradiates B) to perform etching or pattern formation at the irradiation position, the F
Alignment mark forming means for forming an alignment mark by irradiating IB, an optical microscope image of a region of a processing position where the alignment mark is formed, and FIB to the region.
Scanning ion microscope image (SIM
Image) and a processing position detecting means for detecting a processing position according to the superimposed image.

In the above-mentioned FIB apparatus, even if the surface of the sample to be processed is flattened, an alignment mark is formed on the flattened surface by utilizing the etching function or the pattern forming function for the fine region which the FIB apparatus has. Can be formed automatically. Therefore, the alignment mark is formed in the region of the processing position, and the optical microscope image and the SIM image of the region where the alignment mark is formed are overlapped based on the alignment mark to increase the processing position. It is possible to accurately detect and irradiate the FIB there. The alignment mark may be either a concave pattern etched by FIB processing or a convex pattern formed by FIB processing.

In a more preferred embodiment of the above invention, the automatic alignment mark forming means processes the alignment marks having a size and an interval substantially inversely proportional to the machining magnification by designating the machining position and the magnification of the machining region. It is characterized in that it is formed around the position. When the processing magnification is low, the alignment pattern has a large shape and a large gap, and when the processing magnification is high, the alignment pattern also has a small shape and a small gap. As a result, the alignment mark can be formed in the periphery of the processing area where the SIM image is acquired without covering the processing target pattern.

In order to solve the above-mentioned object, the second aspect of the present invention is that the LSI of the sample to be processed, the cover insulating film of the uppermost layer, have a size and an interval according to the design rule. The alignment mark is formed on the entire surface, and the processing position of the LSI is detected in the FIB device. In the processing position detecting step, the SIM image of the area including the processing position and the optical microscope image or the CAD image are
It is characterized in that the processing positions are detected by superposing them on the basis of the position alignment marks and irradiating them with FIB.

Even if the LSI of the sample to be processed is flattened in the multi-layered wiring structure, the size of the insulating cover film such as the silicon oxide film or the silicon nitride film of the uppermost layer has a size according to the design rule and has a space. By forming the alignment mark on the entire surface, it is possible to ensure that the alignment mark exists around the processing position.
The alignment mark can be formed simultaneously with the step of etching and removing the connection pad region with respect to the uppermost insulating cover film, or can be formed by an additional etching step. Therefore, CAD data for the alignment mark is added.

Therefore, according to the alignment mark, not only the electron microscope image but also the CAD data image can be superposed on the SIM image. If images can be superposed in the processing area, the superposed electron microscope image or CAD data image
Even if the surface is flat, the machining position can be detected accurately and FIB
Can be irradiated to process.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments,
The invention extends to the inventions described in the claims and their equivalents.

FIG. 1 is an overall configuration diagram of the FIB device according to the present embodiment. FIG. 1 shows a FIB lens barrel unit 10 for generating a focused ion beam (FIB) and irradiating the beam on the sample surface to be processed.
And a control unit 12 including a computer for controlling the lens barrel portion. Further, the FIB device of the present embodiment has an optical microscope 14 inside or adjacent to the FIB barrel unit 10.

An ion beam gun 16, a beam blanker 18 composed of a deflector, a focus lens 20 for narrowing the ion beam, and a deflector 22 for deflecting and scanning the beam at a desired position are provided in the FIB barrel 10. , Gas generating means 24 for generating a gas for FIB processing, and L of a sample to be processed
A secondary electron detection means 26 for detecting secondary electrons reflected from SI and a stage 28 on which a sample to be processed is placed and movable in the X and Y directions are provided. Also, stage 28
Can move between the optical microscope 14 utilizing infrared rays and the FIB lens barrel 10. Therefore, an optical microscope image can be obtained for the sample to be processed placed on the stage 28, and the F
SIM images can also be acquired from the secondary electrons reflected by scanning the IB.

The control unit 12 is a kind of computer system, and the controller 30 has an arithmetic function such as a CPU. The beam gun drive unit 32 drives the ion beam gun 16 by a command signal from the controller 30, the blanking drive unit 34 drives the beam blanker 18, the lens drive unit 36 drives the focus lens 20, and the deflector drive. The section 38 drives the deflector 22. Also,
The stage drive control unit 44 also drives a stage drive motor (not shown) according to a command signal from the controller. The detection signal from the secondary electron detection means 26 is input to the secondary electron input section 42 and supplied to the controller 30.

The control unit 12 has a control program 48
By executing the above, the alignment mark is automatically formed on the LSI surface of the FIB processing target, and the FIB processing is automatically performed at the designated processing position. For that purpose, a setting value file 52 in which setting values to be described later are stored, and an image data file 5 in which an optical microscope image and a SIM image are stored
0 and a CAD design data file 46 that stores LSI design data are accessible from the controller 30.

FIG. 2 is a flow chart of the FIB processing method according to this embodiment. The FIB apparatus and the FIB processing method using the FIB apparatus according to the present embodiment will be described below with reference to FIG. First, the LSI, which is the sample to be processed, is placed on the stage 28 in the FIB device (S10).

FIG. 3 is a plan view and a cross-sectional view showing an example of an LSI which is a sample to be processed. 3A is a plan view and FIG. 3B is a sectional view taken along line X1-Y1. The insulating film 62 and the first wiring layer are formed on the surface of the silicon semiconductor substrate 60.
An Al-I, interlayer insulating films 64 and 66, a second wiring layer Al-II, a second interlayer insulating film 68, and a cover insulating film 70 are formed. The first-layer wiring pattern Al-I is formed in the horizontal direction of the plan view of FIG. 3A, the second-layer wiring pattern Al-II is formed in the vertical direction, and a via hole VIA is appropriately formed between them.
And has a multilayer wiring structure. Second
A third layer wiring pattern (not shown) is also formed on the layer wiring pattern, and an interlayer insulating film is also formed there, but the third layer wiring pattern does not exist in the region of FIG. The interlayer insulating film after the second layer wiring pattern is formed is flattened by a flattening process. Therefore, if the third layer wiring pattern is not formed, the surface of the cover film 70 is flattened as shown in the drawing.

When such a surface is flattened, as shown in FIG.
In the SIM image of the area shown in (A), there is no change in the reflected secondary electrons generated on the surface due to irradiation with FIB,
The image becomes black. On the other hand, in the optical microscope image of this region, the wiring pattern below the cover insulating film 70 can also be detected. However, since there is no mark that serves as a reference for superimposing both images, they cannot be superposed.

Returning to FIG. 2, with respect to the LSI mounted on the stage 38 in the FIB barrel 10, the origin position is detected from the connection pad exposed on the chip surface (S).
12). FIG. 4 is a diagram showing the entire chip. A plurality of connecting pads 81 are provided around the LSI chip 80. Any one of these pads 81
Is defined as the chip origin, and the origin 82 is detected from the SIM image obtained by FIB scanning. Then, the relative relationship between the stage coordinate system and the chip origin is specified.
As a result, it becomes possible to move to the processing position 84 in the chip 80 by moving the stage.

When the origin position in the chip is detected and the relative positional relationship between the stage coordinate system and the chip coordinate system is specified, the operator sets the FIB processing position (S14).
Then, the observation magnification of the processing area is set (S16). This setting is an initial value setting necessary to form the alignment mark around the processing position. The setting value data required for this setting is stored in the setting value data file 52.

When the FIB processing position and the observation magnification are set as described above, the controller 30 moves the stage 38 via the stage drive control section 44 to move the processing position 84 in the chip 80 to the FIB lens barrel. To the observation area of. Then, the controller 30 changes the pattern of the alignment mark determined by the set observation magnification to
It is automatically formed by FIB processing (S18). In the case of FIB processing by the CVD method, the alignment mark becomes a convex pattern formed on the LSI surface, and in the case of FIB processing by the sputter etching method, the alignment mark is LS.
The concave pattern is formed on the I surface.

FIG. 5 is a diagram for explaining the automatic formation of alignment marks formed around the processing position in the observation area. FIG. 6 is a chart showing the relationship between the observation magnification and the alignment mark size in the automatic formation of the alignment mark. The center (X, Y) of the processing position in the chip set in the above step S14 is the center 90 of the observation region 86.
Therefore, the size of the alignment mark is uniquely determined from the set values in the chart of FIG. 6 according to the observation magnification set in step S16. For example, when the observation magnification is set to 100,000 times, the processing region, which is the observation region, is set to 24 μm square, and the size of the alignment mark is set to 2.4 μm square.

Along with this, as shown in FIG. 5, rectangular patterns 88 of alignment marks are formed at four corners ± 10 μm above and below the center 90 of the observation region 86. The observation magnification depends on the degree of miniaturization of the LSI, which is the sample to be processed, and corresponds to the design rule. When the miniaturization is high, the observation magnification is set high, and when the miniaturization is low, the observation magnification is set low. Furthermore, the alignment mark 8
It is preferable that the pattern size of No. 8 is set to about 1/10 of the processing region 86 which is the observation region. In this way, by setting the observation magnification according to the design rule of the LSI, it is possible to form the alignment mark pattern 88 that does not cover the wiring pattern of the FIB processing target in the observation region. This is because if the pattern of the alignment mark overlaps the wiring pattern to be processed, FIB processing becomes difficult.

As shown in FIG. 6, when the observation magnification is low (when the miniaturization is low according to the design rule), the size of the observation area (processing area) is large and the size of the alignment mark is accordingly large. On the other hand, if the observation magnification is high (when the miniaturization is high according to the design rule), the observation area (processing area)
Is small, and the size of the alignment mark is also small. The size of the observation area and the alignment mark is almost inversely proportional to the observation magnification.

In step S18, the controller 30 is moved along with the previously set machining position and observation magnification of the machining area.
Moves the stage 38 so that the processing position center 90 is located in the observation region, and further, the controller 30
The FIB is deflected by using the deflector 22 or the like, and at least three alignment marks 8 are provided at the four corners in the processing area 86.
8 is formed.

FIG. 7 is a diagram showing the LSI in the state where the alignment mark is formed. 7 is similar to FIG. 3,
A plan view is shown in (A) and a sectional view is shown in (B). However, FIG.
A sectional view taken along line X2-Y2 of (A) is shown in FIG. 7 (B).

As shown in the right corner of FIG.
A convex alignment mark 8 is formed on the flat surface 72 of I.
8 is formed. In the case of this convex shape, CVD is performed by irradiating with FIB in an organometallic gas atmosphere containing W.
The alignment mark 88 is formed by the method. Alternatively, the alignment mark 88 may have a concave shape as shown in the left corner of FIG. In this case, the alignment mark 88 is formed by the sputter etching method by irradiating the FIB in the etching gas atmosphere.

Returning to FIG. 2, when the pattern forming step (S18) for the alignment mark is completed, the controller 30
Moves the stage 38 to move the LSI to the optical microscope 14 side and acquires an optical microscope image (S20). The optical microscope 14 scans, for example, infrared rays with respect to the LSI, and acquires the transmitted light by the infrared imaging element. Such an image is digitized and is stored in the image data file 50 in a form that can be enlarged / reduced and rotated later. The optical microscope image includes a plane pattern and a wiring pattern under the cover insulating film 70 even if the plane is flat.

The controller 30 drives the stage 38 to move the LSI into the FIB lens barrel portion 10 so that the center 90 of the processing region is located at the center position of the FIB lens barrel. Then, this time, the controller 30 scans the processing area with the FIB, and acquires the SIM image from the reflected secondary electrons (S21). At this time, since the convex or concave alignment mark 88 is formed on the surface of the LSI, the image of the alignment mark 88 is always included in the SIM image. This SIM image is also stored in the image data file 50.

FIG. 8 is a diagram showing a SIM image and an optical microscope image. FIG. 8 (A) is a SIM image, LS
Since the alignment mark 88 is formed on the I surface in advance, the image of the alignment pattern 88 is included in the SIM image obtained by scanning the FIB. In an actual SIM image, this alignment pattern 88 is captured as a slightly blurred image.

FIG. 8B is an optical microscope image. 9 is an image of the LSI shown in FIG. 7, an image of the alignment mark 88 formed on the surface, and the wiring pattern of the first layer
An image of Al-I and the second layer wiring pattern Al-II is included.

Therefore, the magnification of the optical microscope image is enlarged, reduced, and the rotation is adjusted.
The size and tilt of the optical microscope image are adjusted so that they can be superimposed on the SIM image (S22). And both images
Superposition is performed using the alignment mark 88 as a reference (S24). The superimposed images are as shown in FIG. 8 (B), for example.

Since the controller 30 specifies the position of the alignment mark 88 in the coordinate system of the FIB device, by superimposing the optical microscope images on the basis of the alignment mark, the wiring pattern of the FIB coordinate system is determined. The position can be easily detected. Therefore, finally, the controller 30 performs FIB processing by irradiating the processing position with FIB according to the superimposed image (S26). This FIB processing can be automatically performed by creating a program appropriately according to the processing content and having the controller 30 execute the processing program.

9 and 10 are views showing an example of the FIB processing process. In both figures, (A) is a plan view and (B) is a sectional view taken along line X2-Y2. In this example, the FIB processing is performed to connect the first layer wiring pattern Al-I on the top in the drawing and the second layer wiring pattern Al-I on the second side. First, as shown in FIG. 9, the insulating films 70, 68, 66 and 64 are removed by a sputter etching method using FIB irradiation to expose the exposure holes 100 and 102 that expose a part of the wiring pattern Al-I.
To form. The controller 30 drives the deflector 22 and irradiates the regions 100 and 102 with FIB to form the exposure holes 100 and 102. The FIB irradiation position at this time is detected using the above-mentioned superimposed image.

Next, as shown in FIG.
A connection pattern 104 containing W is formed on the surface 0, 102 and the surface 72 connecting them. That is, the controller 30
While supplying the organometallic gas containing W for CVD from the gas gun 24, the deflector 22 is driven to expose the exposure holes 100, 102.
The connection pattern 104 can be formed by irradiating FIB on the surface 72 connecting the two. F at this time
The IB irradiation position is also detected using the above-mentioned superimposed image.

Next, the FIB processing method according to the second embodiment will be described. In the first embodiment, the FI
Area where the surface is flattened by forming the alignment mark in the processing area by using the FIB processing function originally possessed by the B-apparatus and superimposing the SIM image by the FIB and the optical microscope image on the basis of the registration mark. The processing position inside can be detected. On the other hand, in the second embodiment, the cover insulating film is etched at the end of the LSI manufacturing process to form the alignment mark on the entire surface of the chip. Along with that, even if flattening technology is adopted in the multilayer wiring structure,
Since the alignment mark having irregularities is formed on the surface in the final step, it is possible to superimpose the FIB image and the optical microscope image or the CAD data image during the subsequent FIB processing.

FIG. 11 is a diagram showing an example of the alignment mark formed on the chip in the second embodiment. A plurality of connection pads PAD are formed around the chip 80. On the other hand, in the present embodiment, the matrix-shaped alignment pattern 114 is regularly formed on the entire inner region of the connection pad. The shape of this pattern is preferably rectangular in order to reduce the amount of CAD data. However, the alignment pattern 114 may be a grid pattern.

Also, as shown in FIG.
A chip center pattern 110 is also formed at the center of the. C
In the AD data, the pattern data is usually defined with the center of the chip as the origin. Therefore, if the chip center pattern 110 is formed, it is possible to reduce the number of steps required to move to the processing position by moving the stage. In addition, the chip center pattern 110 is the alignment pattern 114.
In order to distinguish it from, it is preferable to adopt, for example, a cross shape. Further, in order to have versatility, the chip 80
The reference pattern 112 is formed inside the pad PAD at the four corners of the pad to facilitate the movement to the processing position.

FIG. 12 shows the size of the alignment pattern,
It is a chart which shows the relationship between a space | interval and a design rule. The pattern size and arrangement interval of the alignment pattern 114 in the second embodiment are set according to the design rule. As shown in the chart of FIG. 12, when the design rule is 0.35 μm (minimum pattern size is 0.35 μm), the size of the alignment pattern 114 is 3.5 μm.
m, and the arrangement interval is set to 35 μm. Therefore,
The patterns 114 are formed between the adjacent alignment patterns 114 at intervals such that about 50 minimum wiring patterns are formed. In addition, when the design rule reaches a higher miniaturization level, the alignment pattern 1
The size of 14 becomes small and the arrangement interval becomes narrow.

The size and spacing of this alignment pattern are based on the same concept as in the first embodiment. That is,
When the degree of miniaturization is low, the size of the alignment pattern is large and the arrangement interval is large, but when the degree of miniaturization is high,
The size of the alignment pattern is small, and the placement interval is also narrow. As a result, the alignment pattern 114 surely exists in the processing area, and the possibility that the alignment pattern 114 covers the pattern to be processed is reduced.

FIG. 13 shows F in the second embodiment.
It is a flowchart figure of an IB processing method. Before explaining this flowchart, the LS in the second embodiment is described.
A method of manufacturing I will be described. At the end of the LSI manufacturing process, there is an etching process for removing the cover insulating film on the pad region after forming the cover insulating film. In the present embodiment, after the pad region etching step, as shown in FIG.
An exposure process and an etching process for forming the alignment pattern 114 and the chip center pattern 110 shown in 1 are added. That is, the resist on the cover insulating film is exposed using an exposure mask formed from CAD data having the alignment pattern 114 and the chip center pattern 110, and the cover film is partially removed by a predetermined etching process. As a result, a concave pattern as shown in the sectional view of FIG. 7 is formed.

Returning to FIG. 13, first, an optical microscope image of the processed area on the surface of the LSI, which is the sample to be processed, is acquired (S30). This image data is stored and saved in the storage means. Next, the LS of the sample to be processed is set in the FIB device.
I is transported and placed on the stage 38 (S34). Then, the optical microscope image data is transferred to the control unit 12 of the FIB device and stored in the image data file 50 (S36). This data transfer may be performed before the LSI is transported.

Then, the controller 30 drives the stage to move from the chip center pattern 110 of the LSI to the processing position (S38). In this movement, since the chip center pattern 110 is formed in the center of the LSI chip in advance, the SIM obtained by the FIB scanning is acquired.
This chip center pattern 110 can be identified from the image. Therefore, the CAD data defined from the chip center can be used to move the stage to the processing position coordinates with a small number of steps. When the stage is moved based on the pad position around the chip, it is necessary to convert the coordinates on the CAD data whose origin is the chip center into a new coordinate system whose origin is the pad position.
The process becomes complicated.

Thereafter, the controller 30 scans the FIB and detects the reflected secondary electrons to obtain a SIM image of the processing area including the processing position (S40). Then, the magnification and rotation of the previously obtained optical microscope image are adjusted so as to match the SIM image (S4).
2). Accordingly, the SIM image and the optical microscope image are
Similar to the one shown in FIG. 8, both become images including the alignment pattern. Therefore, both images are easily overlaid on the basis of the alignment pattern (S4).
6).

Finally, the controller 30 specifies the FIB processing position according to the superimposed images,
By irradiating FIB there, it is possible to freely disconnect or connect the wiring pattern (S50). The wiring pattern connection method is as shown in FIGS.
To cut the wiring pattern, sputter etching can be performed only on the FIB irradiation region by irradiating FIB and introducing an etching gas.

In the second embodiment, an alignment pattern is formed on the surface of an LSI pattern using CAD data. Therefore, in order to specify the FIB processing position,
It is also possible to superimpose the CAD data image and the SIM image. In that case, as shown in FIG. 13, instead of step S30, step S32 includes steps S42 and S46.
Instead of, steps S44 and S48 are respectively executed.
Since the alignment pattern also exists in the CAD data, it is possible to superimpose the CAD data image on the FIB image.

As a known example related to the second embodiment, there is JP-A-5-90370. In this known example, it is described that a grid-shaped concave-convex pattern for positioning is formed on the surface of a chip and the position is detected during FIB processing with reference to the pattern. However, it is not described that the size and interval of the alignment concave-convex pattern are set differently according to the design rule. Further, there is no description that the optical microscope image or the CAD data image and the FIB image are superposed on each other based on the alignment concave-convex pattern, and the processing position is detected according to the superposed image.

As described above, in the second embodiment, the process of forming the alignment pattern in the final step of the manufacturing process is added to the LSI surface whose surface is flattened, and the subsequent FIB processing is performed. It is possible to easily detect the machining position. FIB processing is generally not a mass-produced product, but is generally used for partly changing the circuit of a prototype or the like, and the addition of such manufacturing process is exclusively necessary for the prototype. It does not increase the cost of mass-produced products.

The above embodiments are summarized as follows.

(Supplementary Note 1) In a FIB apparatus for irradiating a sample placed on a stage with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position, a sample is formed around a processing position. Positioning mark forming means for irradiating FIB to form a positioning mark on the surface of the sample, an optical microscope image of a processing position region in which the positioning mark is formed, and FIB irradiation to the region. A scanning ion microscope image (SIM image) to be overlapped with the alignment mark image as a reference, and processing position detection means for detecting a processing position according to the superimposed image,
The FI is located at the position detected by the processing position detecting means.
An FIB apparatus, which irradiates B to perform the etching or pattern formation.

(Supplementary Note 2) In Supplementary Note 1, there is further provided an image pickup means for acquiring the optical microscope image, and the image pickup means and the FIB lens barrel portion provided with the mark forming means and the processing position detecting means. An FIB device, wherein the stage is provided so as to be movable between the two.

(Supplementary Note 3) In Supplementary Note 1, the alignment mark forming means is responsive to the designation of the processing position and the magnification of the processing region including the processing position, and the position having a size and interval inversely proportional to the magnification. An FIB device characterized by forming alignment marks.

(Supplementary Note 4) In Supplementary Note 3, when the magnification is low, the alignment pattern has a large size and a large interval, and when the magnification is high, the alignment mark is in inverse proportion to the magnification. The FIB device is characterized in that the size is small and the intervals are also small.

(Supplementary note 5) In the supplementary note 1, the alignment mark has a convex shape in which a pattern is formed on the sample surface or a concave shape in which the sample surface is etched.

(Supplementary Note 6) In a FIB processing method of irradiating a sample placed on a stage with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position, the sample is subjected to FIB processing. An alignment mark forming step of forming an alignment mark on the surface of the sample by irradiating the FIB around the processing position after being loaded into the apparatus, and optical processing of a region of the processing position where the alignment mark is formed. Processing for superimposing a microscope image and a scanning ion microscope image (SIM image) acquired by FIB irradiation on the region with the alignment mark image as a reference, and detecting a machining position according to the superimposed image. The position detecting step and the position detected by the processing position detecting step are irradiated with the FIB to perform the etching or the etching. FIB processing method characterized by having a FIB processing step of performing pattern formation.

(Supplementary Note 7) In Supplementary Note 6, in the step of forming the alignment mark, the processing position and the magnification of the processing region including the processing position are designated, the sample surface is moved to the processing position, and the magnification is changed to the above-mentioned magnification. FI characterized by forming alignment marks of inversely proportional size and spacing
B processing method.

(Supplementary Note 8) In Supplementary Note 6, the sample is an integrated circuit device having a multilayer wiring structure,
The FIB processing method, wherein the wiring pattern in the multilayer wiring structure is cut or connected in the IB processing step.

(Supplementary note 9) A control unit of a FIB processing apparatus that irradiates a sample placed on the stage with a focused ion beam (FIB) and performs etching or pattern formation at the irradiation position is executed. In a computer program according to the present invention, the FI is placed around the processing position for the sample loaded into the FIB processing apparatus.
B is irradiated to obtain an alignment mark on the surface of the sample, a registration mark forming procedure, an optical microscope image of an area of a processing position where the alignment mark is formed, and FIB irradiation to the area. With a scanning ion microscope image (SIM image) to be processed, the processing position detecting procedure for detecting a processing position according to the superimposed image, based on the alignment mark image. Computer program for control unit of FIB processing device.

(Supplementary Note 10) Focused ion beam (FI) is applied to the integrated circuit device mounted on the stage.
In the FIB processing method of irradiating B) to perform etching or pattern formation at the irradiation position, a step of forming a plurality of alignment patterns of a predetermined size and a predetermined interval on the surface of the integrated circuit device; An optical microscope image of the processing position region where the alignment mark is formed and a scanning ion microscope image (SIM image) acquired by FIB irradiation to the region are overlaid on the basis of the alignment mark image. A processing position detecting step of detecting a processing position according to the superimposed image, and a FIB processing step of irradiating the position detected by the processing position detecting step with the FIB to perform the etching or pattern formation. The FIB processing method characterized by the above.

(Supplementary Note 11) Focused ion beam (FI) is applied to the integrated circuit device mounted on the stage.
In the FIB processing method of irradiating B) to perform etching or pattern formation at the irradiation position, the alignment is performed on the surface of the integrated circuit device according to CAD data having a plurality of alignment patterns with a predetermined size and at a predetermined interval. A step of forming a pattern, a CAD data image based on the CAD data of a processing position region in which the alignment mark is formed, and a scanning ion microscope image (SIM image) obtained by FIB irradiation to the region. ,
Superimposing on the basis of the alignment mark image,
A machining position detecting step of detecting a machining position according to the superimposed image; and a FIB machining step of irradiating the FIB to the position detected by the machining position detecting step to perform the etching or pattern formation. Characteristic FIB processing method.

(Supplementary Note 12) In Supplementary Note 10 or 11, in the step of forming the alignment pattern, the size and interval of the alignment pattern are set in accordance with the design rule of miniaturization of the integrated circuit device. FIB processing method characterized by the above.

(Supplementary Note 13) In Supplementary Note 12, when the degree of miniaturization is low in the design rule of miniaturization, the alignment pattern has a large size and a large interval,
The FIB processing method characterized in that, when the degree of miniaturization is high, the alignment marks are also small in size and small in spacing in proportion to the degree of miniaturization.

(Supplementary Note 14) In the supplementary note 10 or 11, the FIB processing method further comprising forming a chip center pattern at the center of the chip in the alignment pattern forming step.

[0071]

As described above, according to the present invention, it is possible to detect a processing position with high accuracy even for a sample to be processed such as an LSI whose surface is flattened, and it is possible to perform FIB processing on a fine pattern. To

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a FIB device in the present embodiment example.

FIG. 2 is a flowchart of a FIB processing method according to the present embodiment.

FIG. 3 is a plan view and a cross-sectional view showing an example of an LSI that is a sample to be processed.

FIG. 4 is a diagram showing an entire chip.

FIG. 5 is a diagram illustrating automatic formation of alignment marks formed around a processing position in an observation region.

FIG. 6 is a chart showing a relationship between an observation magnification and an alignment mark size in automatic formation of an alignment mark.

FIG. 7 is a diagram showing an LSI in which an alignment mark is formed.

FIG. 8 is a diagram showing a SIM image and an optical microscope image.

FIG. 9 is a diagram showing an example of a FIB processing process.

FIG. 10 is a diagram showing an example of a FIB processing process.

FIG. 11 is a diagram showing an example of an alignment mark formed on a chip in the second embodiment example.

FIG. 12 is a chart showing the relationship between the size and spacing of alignment patterns and design rules.

FIG. 13 is a flowchart of a FIB processing method according to the second embodiment.

[Explanation of symbols]

10 FIB barrel 12 FIB control unit 30 controller 46 CAD data file 48 control program 50 image data files 52 Setting data file

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Claims (10)

[Claims] 1. A FIB for irradiating a sample placed on a stage with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
In the apparatus, an FIB is irradiated around the processing position to form an alignment mark on the surface of the sample, and an optical microscope image of an area of the processing position where the alignment mark is formed. Machining position detecting means for superimposing a scanning ion microscope image (SIM image) acquired by FIB irradiation on the region on the basis of the alignment mark image, and detecting a machining position according to the superimposed image. And an FIB apparatus for irradiating the position detected by the processing position detecting means with the FIB to perform the etching or pattern formation. 2. The FI according to claim 1, further comprising an image pickup means for obtaining the optical microscope image, the image pickup means, the mark forming means and the processing position detecting means being provided.
The FIB apparatus, wherein the stage is movably provided between the B lens barrel portion. 3. The alignment mark forming means according to claim 1, in response to designation of the processing position and a magnification of a processing region including the processing position, alignment of a size and an interval inversely proportional to the magnification. An FIB device characterized by forming marks. 4. The alignment pattern according to claim 3, wherein when the magnification is low, the alignment pattern has a large size and a large interval, and when the magnification is high, alignment marks are also inversely proportional to the magnification. FIB device characterized by small size and small intervals. 5. A FIB for irradiating a sample placed on a stage with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
In the processing method, the sample is loaded into an FIB device, FIB is irradiated around the processing position, and an alignment mark is formed on the surface of the sample, and the alignment mark is formed. The optical microscope image of the area of the processed position and the scanning ion microscope image (SIM image) acquired by FIB irradiation to the area are superposed on each other with the alignment mark image as a reference, and the superposition is performed. An FIB processing step of detecting a processing position according to an image, and a FIB processing step of irradiating the position detected by the processing position detecting step with the FIB to perform the etching or pattern formation. Processing method. 6. In appendix 5, in the alignment mark forming step, the processing position and a magnification of a processing region including the processing position are designated, the sample is moved to the processing position on the sample surface, and is inversely proportional to the magnification. An FIB processing method characterized by forming alignment marks of size and spacing. 7. A FIB for irradiating a sample placed on a stage with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
A computer program executed by a control unit of a processing apparatus irradiates the sample carried into the FIB processing apparatus with FIB around the processing position to form an alignment mark on the surface of the sample. The alignment mark forming procedure, the optical microscope image of the region at the processing position where the alignment mark is formed, and the scanning ion microscope image (SIM image) acquired by FIB irradiation to the region. A computer program for a control unit of a FIB processing apparatus, comprising: a processing position detecting procedure of detecting a processing position according to the superimposed image by superimposing the mark image as a reference. 8. An integrated circuit device mounted on a stage is irradiated with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
In the IB processing method, a step of forming a plurality of alignment patterns with a predetermined size at predetermined intervals on the surface of the integrated circuit device, and an optical microscope image of a region of a processing position where the alignment marks are formed, FIB to the area
Scanning ion microscope image (SIM
Image) and the alignment mark image as a reference, and a processing position detecting step of detecting a processing position according to the superimposed image; and the FIB at the position detected by the processing position detecting step. FIB processing step of irradiating to perform the etching or pattern formation. 9. An integrated circuit device mounted on a stage is irradiated with a focused ion beam (FIB) to perform etching or pattern formation at the irradiation position.
In the IB processing method, a step of forming the alignment pattern on the surface of the integrated circuit device according to CAD data having a plurality of alignment patterns of a predetermined size at predetermined intervals, and processing in which the alignment marks are formed. A CAD data image based on the CAD data of the area of the position and a scanning ion microscope image (SIM image) acquired by FIB irradiation to the area are overlapped with each other with the alignment mark image as a reference, and A machining position detecting step of detecting a machining position according to the superimposed image, and a position detected by the machining position detecting step,
FIB processing step of irradiating the FIB to perform the etching or pattern formation.
IB processing method. 10. The size and spacing of the alignment pattern according to claim 8 or 9, in the step of forming the alignment pattern, according to a design rule for miniaturization of the integrated circuit device. F characterized by
IB processing method.