JP2003008619A - Packet communication device - Google Patents

Abstract

(57) [Problem] To provide a packet communication device capable of efficiently accommodating different speed line interfaces. The packet communication according to the present invention comprises a first line interface, a second line interface accommodating a line slower than the line accommodated by the first line interface, a crossbar switch, and the first line interface. And periodically receives a packet output request from the second line interface and the second line interface.
A scheduler for transmitting a packet transmission permission to the crossbar switch to the first line interface and the second line interface;
The capacity of the link between the second line interface and the crossbar switch is made larger than the capacity of the link between the second line interface and the crossbar switch.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the Internet.
The present invention relates to a packet data communication device for switching variable length packets such as Protocol (IP) and fixed length packets (generally called cells) in an asynchronous transfer mode (hereinafter referred to as ATM).

[0002]

2. Description of the Related Art In recent years, data traffic including the Internet has been rapidly increasing. In addition, there is also a movement to try to provide high-quality and highly reliable services on the Internet, such as transaction processing that was conventionally performed using dedicated lines. To accommodate this,
Not only transmission lines but also packet data communication devices need to have large capacity, high speed, and high reliability.

It is known that an input / output buffer type switch is suitable as a switching system for a packet data communication device from the viewpoint of increasing the capacity. "The Tiny Tera: A PacketSwitch Core", Nick McK, discloses a packet switch that uses an I / O buffer type switch.
eown, Martin Izzard, Adisak Mekkittikul, WilliamEl
lersick, and Mark Horowitz, IEEE MICRO, January / Fe
There is bruary 1997 (hereinafter referred to as "reference 1"). The switch disclosed in Document 1 is considered to be a switch as shown in FIG. N port cards 701 are provided in front of the crossbar switch 706 having n input / output ports, and an input buffer 703 is arranged for each port card 701. The variable length packet input from the input line 700 is divided into fixed length packets (cells). The cells buffered in the input buffer 703 are subjected to connection scheduling between input / output ports by the scheduler 705, and then the port cards 7
01 is output and is switched by the crossbar switch 706. The connection between the input and output ports is changed on a cell-by-cell basis. In particular, in this configuration, each input buffer 703 has a queue buffer (Virtual) for each output route.
l Output Queue (VOQ), which enables reading from an arbitrary queue buffer whose output is instructed by the scheduler 705.
Head Of Line Blocking (HO
Throughput is prevented from decreasing due to L). The crossbar switch 706 slices the cell 704 in units of, for example, a plurality of bits, and performs parallel processing on a plurality of switch surfaces.

In addition, various types of line speeds can be supported in the conventional packet data communication device. FIG. 3 shows the main signal system configuration of a general packet data communication device that supports a plurality of types of lines. In FIG. 3, the crossbar switch 750 has a plurality of input ports and a plurality of output ports in the unit of 2.4 Gbps,
N × n switching is performed between the input / output ports. The physical connection between the crossbar switch 750 and the line interface is the 2.4 Gbps driver (transmission unit) 730,
This is performed by the 2.4 Gbps receiver (reception unit) 731. In this example, not only the 2.4 Gbps line interface 721 but also various types of low-speed lines are supported. In order to improve the line accommodation efficiency of packet data communication devices, it is common for line interfaces to support low-speed lines for multiple ports. In FIG. 3, the line interface 722 is 600 Mbps.
× 4 ports, 150 Mb for line interface 723
In this example, ps × 16 ports and the line interface 724 accommodate gigabit Ethernet (1 Gbps) × 2 ports. In this way, as for the low speed line, a configuration is adopted in which as many ports as possible are accommodated in one line interface so that switchable resources are not wasted.

[0005]

It is assumed that a large-capacity switch that supports a higher speed line will be required in the future as traffic increases, but connection with the access part of the network and connection with conventional equipment will be required. If you think about it,
It is also necessary to support conventional low speed lines.

FIG. 4 shows an example of a switch configuration. The crossbar switch 850 has a plurality of 40 Gbps unit input ports and a plurality of output ports, and performs n × n switching between input / output ports. Crossbar switch 8
The physical connection between 50 and the line interface is 40G
This is performed by a bps driver (transmission unit) 830 and a 40 Gbps receiver (reception unit) 831. In particular, several hundred
In a large capacity switch of Gbps to several Tbps class, the crossbar switch 850 and the line interface may be physically connected by an optical component such as an optical interconnect. 40Gbp based on the same idea as in FIG.
Not only the s line interface 821 but also various types of low speed lines are supported. The switching unit of the crossbar switch 850 is 40 Gbps, but for example, supporting 16 2.4 Gbps lines and 40 gigabit Ethernet lines causes division loss due to the number of mounted components and the mounting area of the line interface. There is a possibility that the capacity density of the line interface will become low due to the limitation of 8 2.4 Gbps lines (823) and 8 Gigabit Ethernet lines (824). In this case, for the line interface with low density, 40 lines are required for connection with the crossbar switch 850.
Since it is redundant to mount the driver 830, the receiver 831 or the optical interconnect module for Gbps, it is not desirable in terms of mounting area and component cost. This problem does not depend on the speeds of the drivers and receivers illustrated in FIG. 4 and the line speed to be accommodated, but is a problem that generally occurs when a high speed line and a low speed line are mixed and accommodated in a switch.

Further, the conventional input / output buffer type crossbar switch as shown in Document 1 is basically based on a one-to-one connection between an input port and an output port. That is,
Considering connecting multiple low-speed line interfaces and high-speed line interfaces with a crossbar switch, the traffic input to a certain high-speed line is output simultaneously to multiple low-speed lines, and multiple low-speed lines are also output. Since it is not possible to connect the traffic input to the line together and output it to one high-speed line at the same time, the switch usage efficiency may drop significantly.
In other words, the conventional crossbar switch does not support one-to-many connection or multiple-to-one connection between input / output ports, so that the desired output port is vacant when the low-speed line interface and the high-speed line interface are mixed. "Blocking" phenomenon occurs that data cannot be sent even though it exists.

[0008]

According to one aspect of the present invention, the number of connection ports between each line interface and a crossbar switch is set according to the speed of the line accommodated in each line interface. In one embodiment of the present invention, the input / output connection between the low speed line interface section and the crossbar switch is connected using 1 port, and the input / output connection between the high speed line interface section and the crossbar switch is n port. And connect. The scheduler that determines the connection between the input and output ports of the crossbar switch receives one transmission request request from the low-speed line interface and one transmission request request from the high-speed line interface for each port, that is, n transmission request requests. The scheduler determines the input / output connection relationship based on the requests received from all ports, and notifies whether it can be sent or not on a port-by-port basis. In the low-speed line interface, if transmission is permitted, the packet corresponding to the notified destination output is transmitted. With regard to the high-speed line interface, the packet corresponding to the destination output permitted to be transmitted is transmitted to each of the n ports. In a high-speed line interface, when a plurality of transmission permits are recognized for one destination output, a plurality of packets are continuously read from the queue buffer corresponding to the destination output. Further, when a plurality of transmission permits are recognized for a plurality of destination outputs, the packets are sequentially read from the queue buffer corresponding to the destination output.

According to another aspect of the present invention, in the scheduler, the input side of the low speed line interface unit is connected to the output side of one low speed line interface unit or the output side of one high speed line interface unit, The crossbar switch is controlled so that the input side of the interface section is connected to the output side of at most n first line interfaces or the output side of one second line interface.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a packet communication device according to the present invention will be described.

FIG. 2 shows an embodiment of the packet communication device of the present invention. This packet communication device has a crossbar switch 10 for performing n × n switching, line interfaces 20-1 to 20-n connected to the crossbar switch 10, and a scheduler 40. In addition, the crossbar switch 10, the line interface 20, and the scheduler 4
In the case of 0, the control unit 50 performs control such as initial setting, statistical information collection, and failure information collection through the control bus 51.

The line interface 20 will be described. The input side of the line interface 20 is the input processing unit 2
1, VOQ (Virtual Output Queue)
e) 23 and the VOQ control unit 22. The output side of the line interface 20 has a VIQ (Virtual)
It has an Input Queue 33, a VIQ controller 31, and an output processor 32.

FIG. 14 shows an embodiment of the input processing section 21. When the packet data is input to the device through the input line 40, it is converted into an electric signal by the optical / electrical signal converter (O / E) 21-1. After that, at PHY 21-2, SONET (synchronous optical)
physical layer processing such as an (1 network) frame is performed. Next, the L2 processing unit 21-3 performs layer 2 processing such as packet extraction and error checking. Then, the search engine 21-4 performs layer 3 processing such as output port search and quality class search based on the destination IP address. Specifically, the search process is performed by the L3 TABLE connected to the search engine 21-4.
21-5 is used. The L3 TABLE 21-5 stores in advance a correspondence relationship between the destination IP address, the output port, the quality class, and the next hop IP address which is the IP address of the next transfer destination. The search result is added to the header part of the packet. The output side function of the line interface 20 will be described later.

In the following, for the crossbar switch, 4
Two line interface cards that accommodate one 0 Gbps line (input / output 40 Gbps: hereinafter referred to as 40 Gbps line interface) and two line interfaces that accommodate 10 Gbps × 2 lines (input / output 20 Gbps: hereinafter referred to as 20 Gbps line interface) are mixed. The description will be made by taking as an example the case of being installed. The crossbar switch connects input / output ports to the four line interfaces installed and switches input 4 × output 4. The line slot of this packet communication device is premised to be slot-free, and both the 40 Gbps line interface and the 20 Gbps line interface can be mounted.

FIG. 1 shows an embodiment of a packet communication device for 4 × 4 switching. This packet communication device includes a crossbar switch 10 for 4 × 4 switching and a line interface 20-connected to the crossbar switch 10.
1 to 20-4 and a scheduler 40. In this embodiment, the line interfaces 20-1, 20-3 and 10 Gbps accommodating 40 Gbps × 1 port are provided.
a line interface 20-2 accommodating s × 2 ports,
20-4 is mounted. Line interface 20-
Two 20G transmission drivers 15 are mounted on each of the input sides of 1 and 20-3, and two 20G reception drivers 16 are mounted on each of the output sides of the line interfaces 20-1 and 20-3. Has been done. Further, one 20G transmission driver 15 is mounted on each input side of the line interfaces 20-2 and 20-4, and 20G is provided on each output side of the line interfaces 20-2 and 20-4.
One reception driver 16 of each is mounted. Regarding the crossbar switch 10, two reception drivers 16 and transmission drivers 15 are provided for the line interface slot on the reception side and the transmission side of the slot, respectively. Further, the crossbar switch corresponds to each input / output driver and has two physical input / output ports per line interface slot (for example, the input ports corresponding to the line interface 20-1 are IP11, IP12,
The output port has OP11, OP12). 40 Gbp
The s line interfaces 20-1 and 20-3 and the crossbar switch 10 are connected by two 20 Gbps links, and the 20 Gbps line interfaces 20-2 and 20-2,
20-4 and the crossbar switch 10 are one 20 Gbps
Connected by a link. The scheduler 40 controls all the line interfaces 2 through the control line 41 at regular intervals.
Collect the packet output request information of 0-1 to 20-4,
Based on these, the connection relationship between the line interfaces is determined, and the packet transmission permission is issued to the line interfaces 20-1 to 20-4.

An embodiment of the scheduler 40 for determining the connection relationship between the line interfaces will be described. When multiple packet output requests collide with each output line interface, the schedule 40
The input line interface to be connected is selected by the cyclic selection method (round robin). If the output requests are prioritized, the connection relationship between the I / O line interfaces is determined so that the output requests with higher priorities are prioritized, and if the priorities overlap, the same priority is given. The cyclic selection may be performed for the output request. By sequentially performing the above selection for each output line interface,
The connection relationship between the input interface and the output interface can be determined.

Although not shown in FIG. 1, the input side of each line interface has an input processing section 21, a VOQ control section 22 and a VOQ 23, as shown in FIG. , VIQ control unit 31, output processing unit 3
2, and VIQ33.

The details of the VOQ control unit 22 and the transmission / reception format between the VOQ control unit and the scheduler 40 are shown in FIG. The VOQ control unit 22 includes a header analysis unit 221, a buffer management unit 222, and a transmission request creation unit 2
23 and. The header analysis unit 221 analyzes the header of the input packet, and uses this to analyze the header.
22 is notified. In the buffer analysis unit, the header analysis unit 22
WA (Write Address) so that the packet is written to the desired queue buffer (corresponding to the output line interface) of the VOQ based on the information received from 1.
To the VOQ 23. In addition, the buffer management unit 222
Then, the packet storage information of the VOQ 23 is sent to the sending request creation unit 2
23, and sends a sending request to the scheduler 40. The scheduler 40 has a configuration capable of receiving two transmission requests 401 and 402 for each line interface slot. For each of the transmission requests 401 and 402,
Transmission request valid bits (V) 411 and 412 are added, and the validity / invalidity of the request is determined by this bit. Specifically, as shown in FIG. 16, for the 40 Gbps line interface, the transmission request valid bit (V) 411,
Both 412 are enabled (“1”), and 20 Gbp
As for the s line interface, as shown in FIG. 17, only one of the transmission request valid bits (V) 411 and 412 (411 in this example) is set to valid (“1”). That is, the scheduler 40 can receive two transmission requests from the 40 Gbps line interface. Note that the transmission request creation unit of the 40 Gbps line interface displays "1" for both the transmission requests 401 and 402 for the queue buffer of the output route where two or more packets that can be transmitted within the VOQ 23 are accumulated. (Output # 1 in this example) For the queue buffer of the output route where only one packet that can be sent is stored,
“1” is displayed only in the transmission request 401 (output # 4 in this example). In the example of FIG. 1, the scheduler 40 receives a maximum of 6 transmission requests corresponding to the physical ports of the crossbar switch 40. The scheduler 40 schedules the six transmission requests among the corresponding six input / output ports of the crossbar switch 10 to determine the connection relationship. When the connection relationship is determined, the scheduler 40
Returns the transmission permission to the VOQ control unit 22 of each line interface 20. The scheduler 40 has two transmission permits 501 for each line interface slot.
502 can be transmitted. Send permission 501,
502 includes a transmission permission valid bit (V) 51
1, 512 are added, and the validity / invalidity of the transmission permission is determined by this bit. Specifically, as shown in FIG. 18, for the 40 Gbps line interface, both of the transmission permission valid bits (V) 511 and 512 are validated,
As for the 20 Gbps line interface, as shown in FIG. 19, transmission permission valid bits (V) 511, 5
Only one of the 12 (511 in this example) is set to be valid. That is, the scheduler 40 transmits a maximum of two transmission permission (one transmission permission 501 and one transmission permission 502) to the 40 Gbps line interface, and transmits 20 Gbps.
Only one send permission can be sent to the ps line interface. When the buffer management unit 222 in the VOQ control unit 22 receives one or two transmission permits, one or two packets are read from the VOQ 23 corresponding to the RA.
(Read Address) is sent to the VOQ 23.

In the above configuration, as a connection method between the 20 Gbps line interface and the 40 Gbps line interface, (1) one 40 Gbps line interface input is connected to one 40 Gbps line interface output (2) two 20 Gbps line interface inputs Connect to one 40Gbps line interface output (3) Connect one 40Gbps line interface input to two 20Gbps line interface output,
The three examples will be described in order.

First, the 40 Gbps line interface 2
Input of 0-1 is 40 Gbps line interface 20-
3 when connected to the output of the line interface 20-
The operation of No. 1 will be described with reference to FIG. When two output permits for the output side line interface 20-3 are received from the scheduler 40 through the control line 41, VO
The Q control unit 22 gives two RAs to the VOQ 23, and the queue buffer 233 corresponding to the line interface 20-3.
Sequentially read out two packets (A1, A2). Logically, the output line interfaces 20-1 to 20-1
20-4 respectively corresponding to the queue buffers 231-2
This is equivalent to selecting the queue buffer 233 from 34 with the selector 230 and reading a packet. The two packets (A1, A2) read out are separated by the separation unit (DMX) 1
20G drivers (2
It is output to the corresponding input ports IP11 and IP12 of the crossbar switch through the 0G-DRV) 15.
These two packets (A1, A2) are output to the line interface 20-3 via desired output ports OP31, OP32 in the crossbar switch 10.
Operation on the output side of the line interface 20-3 Fig. 7
Shown in. Two packets (A1, A2) are each 2
It is input to the line interface 20-3 through the 0G receiver (20G-DRV) 16. After that, the multiplex part (M
UX) 160, and time-multiplexed and stored in the queue buffer corresponding to the corresponding input interface in the VIQ (in this case, since the packet is input from the line interface 20-1, the corresponding queue buffer 331). Are controlled by the VIQ control unit 33. After being assembled into the original variable length packet by the VIQ 33, the packet is read and sent to the output processing unit 32.

Here, the structure of the output processing unit 32 will be described with reference to FIG. The input variable length packet is subjected to layer 2 processing by the L2 processing section 32-3. For example,
If the output line is Ethernet, the next transfer destination I
The layer 2 address (MAC address) of the connection-destination router is searched for from the next hop IP address which is the P address, and is added. The correspondence between the next hop IP address and the layer 2 address of the connection destination router is L
It is stored in 2TABLE32-5. After the layer 2 processing is completed, the variable-length packet is subjected to mapping processing in the PHY 32-2, for example, a SONET frame, and then converted into an optical signal in the electric / optical signal conversion unit (E / O) 32-1. After that, it is sent to the output line 50.

Next, the inputs of the two 20 Gbps line interfaces 20-2 and 20-4 are one 40 Gbps.
The operation of the line interface 20-2 when connected to the output of the line interface 20-1 will be described with reference to FIG. When one output permission for the output side line interface 20-1 is received from the scheduler 40 through the control line 41, the VOQ control unit 22 receives the VOQ 23.
To the line interface 20-1 by giving one RA to the packet buffer (B1) from the queue buffer 231.
Read one. Logically, the queue buffers 231 to 234
Corresponds to reading the packet (B1) by selecting the queue buffer 231 with the selector 230. The read packet (B1) is sent to the 20G driver (20G-D
RV) 15 is output to the corresponding input port IP21 of the crossbar switch 10. Here, nothing is connected to the input port IP22 of the crossbar switch 10. The packet (B1) is output to the line interface 20-1 through the desired output port OP11 at the crossbar switch 10. Further, the operation of the line interface 20-4 is shown in FIG. 9, but since this performs the same operation as described in FIG. 8, detailed description thereof will be omitted. The packet (C1) read from the queue buffer 231 of the line interface 20-4 is output to the line interface 20-1 through the desired output port OP12 in the crossbar switch 10.
Operation on the output side of the line interface 20-1 Fig. 1
It shows in 0. The two packets (B1, C1) are input to the line interface 20-1 via the 20G receiver (20G-DRV) 16, respectively. Then, the VIQ control is performed so that the signals are time-multiplexed by the multiplexer (MUX) 160 and stored in the queue buffer (the packet B1 is the queue buffer 332 and the packet C1 is the queue buffer 334) corresponding to the corresponding input interface in the VIQ. It is controlled by the unit 33. Finally, the operation of the line interface 20-3 when the input of the 40 Gbps line interface 20-3 is simultaneously connected to the outputs of the 20 Gbps line interfaces 20-2 and 20-4 is shown in FIG.
This will be described using 1. Control line 41 from scheduler 40
Through the output side line interfaces 20-2 and 2
When the output permission for 0-4 is received, the VOQ control unit 22 gives two RAs to the VOQ 23 to send the packet (D1) from the queue buffer 232 corresponding to the line interface 20-2, and the line interface 20-. Packets (E1) are sequentially read out from the queue buffer 234 corresponding to No. 4. The two packets (D1, E1) read out are time-separated by the separation unit (DMX) 150, and the 20G driver (20G-DRV) 1
Corresponding input port IP of crossbar switch through 5
31, output to IP32. Packet (D1)
Is the desired output port OP21 at the crossbar switch 10.
Through the line interface 20-2. Also, the packet (E1) is sent to the crossbar switch 10
Is output to the line interface 20-4 through the desired output port OP41. Nothing is connected to the output ports OP22 and OP42 of the crossbar switch 10. The operation of the output side of the line interface 20-2 is shown in FIG. The packet (D1) is input to the line interface 20-2 through the 20G receiver (20G-DRV) 16 and stored in the queue buffer (the queue buffer 333 in this case) corresponding to the corresponding input interface in the VIQ. To
It is controlled by the VIQ control unit 33. After being assembled into the original variable length packet by the VIQ 33, the packet is read and sent to the output processing unit 32. FIG. 13 shows the processing on the output side of the line interface 20-4, but since this is the same as in FIG. 12, its explanation is omitted.

A mounting image of the line interface to which the present invention is applied is shown below. FIG. 24 shows the case of the 40 Gbps line interface 70. 20G driver LSIs 91 and 20G for connecting to the crossbar switch 10
Two receiver LSIs 92 are mounted, and these input / output signals are connected to the back panel 95 through the connector 93. FIG. 25 shows the case of the 20 Gbps line interface 80. Crossbar switch 10
20G driver LSIs 91 and 20 for connecting to
One G receiver LSI 92 is mounted, and these input / output signals are connected to the back panel 95 through the connector 93. In this example, the back panel is used to connect the line interface and the crossbar switch. However, especially in a large-capacity packet switching system, it may be possible to connect the line interface and the crossbar switch by using optical components instead of electricity. It

As described above, according to this embodiment,
When configuring a high-capacity packet communication device, if a high-density line interface that accommodates high-speed lines and a low-density line interface that accommodates multiple low-speed lines coexist, the low-speed line interface has few drivers and receivers (optical In the case of connection, it is sufficient to mount optical components).
It becomes possible to realize a line interface having cost linearity such that a receiver (optical component in the case of optical connection) can be mounted.

Also, a plurality of low speed line interfaces and 1
It is possible to provide a packet communication device that enables one-to-many connection or multiple-to-one connection between input / output ports of a switch between two high-speed line interfaces.

In the embodiment described above, two links are provided between the high speed line interface and the crossbar switch, and one link is provided between the low speed line interface and the crossbar switch. / Depending on the speed of the line accommodated in the low speed line interface, n _H links are set up between the high speed line interface and the crossbar switch, and n _L links are set up between the low speed line interface and the crossbar switch. It is also possible to extend the configuration.

As another embodiment, a method of changing the physical speed of the connection link according to the type of the line interface in the connection between the crossbar switch and the line interface will be described. First, FIG. 20 shows the flow of packets from the line interface to the crossbar switch.
Will be explained. 40Gbps line interface 2
00-1 is equipped with one 40 Gbps driver 150, and 20 Gbps line interface 200-2
Is equipped with one 20 Gbps driver 15.
Further, one 40 Gbps receiver 160 is mounted on the receiving side of the crossbar switch 100 for each slot. 40 mounted on the receiving side of the crossbar switch 100
The Gbps receiver 160 is configured to be able to receive data regardless of whether 40 Gbps data or 20 Gbps data arrives. Specifically, at the time of receiving 20 Gbps data, 40 Gbps
Data extraction processing may be performed at a rate that is half that of data reception. 40 Gbps line interface 20 for the interface slot of the crossbar switch 100
When 0-1 is installed, when the 40 Gbps data (A1, A2) is received, the separation circuit (DMX) 11
At 0, this is separated by time, and A1 and A2 are input to the input ports IP11 and IP12 in the crossbar switch 100, respectively. On the other hand, when the 20 Gbps line interface 200-2 is installed, 20
When the Gbps data (C1) is received, the delay circuit (D
LY) 120 delays this by the processing time of DMX 110 and inputs C1 to the input port IP21 in the crossbar switch 100. Nothing is input to the input port IP22. Mode switching for these line interface speeds is realized by the configuration shown in FIG. DMX 110 and DL for each slot of the crossbar switch 100
Y120 switching selectors SEL1 (101) and SEL2
(102) is prepared. Specifically, when 40 Gbps data is input, the data is time-separated by the DMX 110 and input to the input ports IP11 and IP12. When 20 Gbps data is input, it is delayed by the DLY 140 and is input only to the input port IP11. When the line interface is installed, the level line signal 105 (for example, 40
“1” is output for Gbps, and “0” is output for 20 Gbps, whereby SEL1 (101) and SEL2 (10) are output.
2) is set. In addition, SEL1 (101), SEL
The setting of 2 (102) may be performed by software. The exchange of the data transmission request / transmission permission signal between the line interfaces 200 and the scheduling method are the same as those in the above-described embodiment, and therefore the description thereof is omitted.

Next, the flow of packets from the crossbar switch to the line interface will be described with reference to FIG. The transmission side of the crossbar switch 100 has a 40 Gbps driver 15 for each line interface slot unit.
One 0 is installed. Also connected to this 40
40 Gbps for the Gbps line interface 200-1
One s receiver 160 is installed, 20 Gbps
One 20 Gbps receiver 16 is mounted on the line interface 200-2. In the 40 Gbps driver 150 installed on the transmission side of the crossbar switch 100, 4
It is possible to transmit data at either speed of 0 Gbps data and 20 Gbps data. Specifically, when the opposing receiver 16 is compatible with 20 Gbps, data may be transmitted at a rate half that of 40 Gbps. When the 40 Gbps line interface 200-1 is mounted on the crossbar switch 100, the output ports OP11 and OP of the crossbar switch 100 are installed.
The data (A1, A2) output from 12 is time-multiplexed by a multiplexing circuit (MUX) 130 and sent to the line side as a 40 Gbps multiplexed signal. Further, when the 20 Gbps line interface 200-2 is installed, when the data (C1) from the output port OP21 is received, the delay circuit (DLY) 140 delays this by the processing time of the MUX 130, and C1 is output. Is sent to the line interface as a 20 Gbps signal. Output port O
Nothing is output from P21. Mode switching for these line interface speeds is realized by the configuration shown in FIG. For each slot of the crossbar switch 100,
Switching selector SEL3 for MUX 130 and DLY 140
(103) is prepared. Specifically, when 40 Gbps data is output, output ports OP11 and O
It is output from P12 and time-multiplexed in the MUX 130. When 20 Gbps data is output, this is output from the input port OP11, and this is D
It is configured to be delayed by LY140. Regarding the switching selector SEL3 (103), when the line interface is installed, the level line signal 105 (for example, 40 Gbps) which differs depending on the capacity of the line interface board is installed.
"1" and 20 Gbps output "0", and the setting is realized by this. In addition, SEL3 (1
The setting of 03) may be performed by software.

As described above, according to the present embodiment, when a large-capacity packet communication device is constructed, a high-density line interface accommodating a high-speed line and a low-density line interface accommodating a plurality of low-speed lines coexist. In this case, a driver / receiver (optical component in the case of optical connection) according to the line interface speed may be mounted, and a line interface with cost linearity can be realized. Further, it is possible to provide a packet communication device capable of making a one-to-many connection or a plurality-to-one connection between input / output ports of a switch between a plurality of low speed line interfaces and one high speed line interface.

According to the embodiment described above, the following effects can be expected. (1) When configuring a high-capacity packet communication device, a high-density line interface accommodating a high-speed line and a low-density line interface accommodating a plurality of low-speed lines can be mixed, and the physical interface is proportional to the line interface capacity. A packet communication device having an inter-switch link can be configured. (2) It is possible to provide a packet communication device capable of transferring data between a plurality of low speed line interfaces and one high speed line interface. Specifically, a one-to-many connection or a plurality-to-one connection between the input / output line interfaces is possible, and a packet communication device in which traffic blocking does not occur can be configured.

[0031]

EFFECTS OF THE INVENTION In a packet communication device in which a line interface accommodating a high speed line and a line interface accommodating a low speed line are mixed, efficient packet switching can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing functional blocks of a packet communication device of the present invention.

FIG. 2 is a block diagram showing a configuration of a packet communication device of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional packet communication device.

FIG. 4 is a block diagram showing a configuration of a conventional packet communication device.

FIG. 5 is a block diagram showing configurations of a line interface and a scheduler of the packet communication device of the present invention.

FIG. 6 is a block diagram showing a configuration of a line interface card (input side) of the packet communication device of the present invention.

FIG. 7 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 8 is a block diagram showing a configuration of a line interface card (input side) of the packet communication device of the present invention.

FIG. 9 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 10 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 11 is a block diagram showing a configuration of a line interface card (input side) of the packet communication device of the present invention.

FIG. 12 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 13 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 14 is a block diagram showing a configuration of a line interface card (input side) of the packet communication device of the present invention.

FIG. 15 is a block diagram showing a configuration of a line interface card (output side) of the packet communication device of the present invention.

FIG. 16 is an example of a data format used in scheduling of the packet communication device of the present invention.

FIG. 17 is an example of a data format used in scheduling of the packet communication device of the present invention.

FIG. 18 is an example of a data format used in scheduling of the packet communication device of the present invention.

FIG. 19 is an example of a data format used in scheduling of the packet communication device of the present invention.

FIG. 20 is a block diagram showing another configuration of the line interface card and the crossbar switch of the packet communication device of the present invention.

FIG. 21 is a block diagram showing another configuration of the line interface card and the crossbar switch of the packet communication device of the present invention.

FIG. 22 is a block diagram showing another configuration of the crossbar switch of the packet communication device of the present invention.

FIG. 23 is a block diagram showing another configuration of the crossbar switch of the packet communication device of the present invention.

FIG. 24 is a block diagram showing a configuration of a line interface card of the packet communication device of the present invention.

FIG. 25 is a block diagram showing a configuration of a line interface card of the packet communication device of the present invention.

FIG. 26 is a block diagram of a conventional large capacity packet switch.

[Explanation of symbols]

10 ... Crossbar switch, 20 ... Line interface, 21 ... Input processing unit, 22 ... VOQ control unit, 23 ...
・ VOQ, 31 ... VIQ control unit, 32 ... Output processing unit,
33 ... VIQ, 40 ... Scheduler, 50 ... Control unit

Claims (13)

[Claims] 1. A packet communication device comprising: a first line interface; a second line interface that accommodates a line that is slower than the line accommodated by the second line interface; a crossbar switch; A packet output request is periodically received from the first line interface and the second line interface, and based on the request, the first line interface and the second line interface receive a packet for the crossbar switch. A scheduler for transmitting a transmission permission, and a capacity of a link between the first line interface and the crossbar switch is larger than a capacity of a link between the second line interface and the crossbar switch. Packet communication device. 2. The packet communication device according to claim 1, wherein the number of links between the first line interface and the crossbar switch is between the second line interface and the crossbar switch. Packet communication device with more links. 3. The packet communication device according to claim 1 or 2, wherein the scheduler has more than the first line interface to the second line interface in the same cycle. A packet communication device that receives a packet output request. 4. The packet communication device according to claim 1, wherein the scheduler sets a maximum value of the number of packet output requests received from the first line interface in the same cycle. , The ratio between the number of packet output requests received from the second line interface and the maximum value is determined by the capacity of the link between the first line interface and the crossbar switch, and the ratio between the second line interface and the crossbar switch. A packet communication device equal to the ratio of the capacity of the link to the switch. 5. The packet communication device according to claim 2, wherein the scheduler is configured to transmit the first packet in the same cycle.
From the second line interface, the maximum number of packet transmission requests equal to the number of links between the first line interface and the crossbar switch is received from the second line interface. A packet communication device for receiving the same number of packet transmission requests as the number of links between the line interface and the crossbar switch. 6. The packet communication device according to claim 1, wherein the scheduler permits the first line interface to send out more packets than the second line interface. A packet communication device for transmitting. 7. The packet communication device according to claim 2, wherein the scheduler includes a maximum number of links between the first line interface and the crossbar switch in the first line interface. The transmission permission of an equal number of packets is transmitted to the second line interface,
A packet communication device that transmits a transmission permission of a maximum number of packets equal to the number of links between the second line interface and the crossbar switch. 8. A packet communication device comprising a plurality of first line interfaces, a plurality of second line interfaces each having a speed n times that of the first line interface, and a plurality of the first line interfaces. A packet output request is periodically received from one line interface and a crossbar switch connected to the plurality of second line interfaces, and from the plurality of first line interfaces and the plurality of second line interfaces. , Based on the request, while controlling the crossbar switch, periodically,
A scheduler for transmitting packet transmission permission to the crossbar switch to the plurality of first line interfaces and the plurality of second line interfaces, and each line interface of the plurality of second line interfaces, The scheduler is connected to the crossbar switch by n times as many links as the number of links connecting the first line interface and the crossbar switch, and the scheduler has a first line having one input side of the first line interface. Connected to the output side of the interface or the output side of the one second line interface, and the input side of the second line interface has a maximum of n output sides of the first line interface or one second line A packet communication device that controls the crossbar switch so that it is connected to the output side of the interface. 9. The packet communication device according to claim 8, wherein the scheduler is maximum in the same cycle.
A packet communication device for permitting the second line interface to transmit n times as many packets as the maximum number of packets permitted to be transmitted to the crossbar switch to the first line interface. 10. The packet communication device according to claim 8, wherein an input side and an output side of each line interface of the plurality of first line interfaces respectively include the crossbar switch. A packet communication device connected by one link, and the input side and output side of each line interface of the plurality of second line interfaces are respectively connected to the crossbar switch by n links. 11. The packet communication device according to claim 10, wherein each line interface input side of said plurality of first line interfaces has one transmission driver connected to said one link. However, each line interface output side of the plurality of first line interfaces is
A receiver connected to the two links, each line interface input side of the plurality of second line interfaces has n transmission drivers connected to the n links, and A packet communication device in which each line interface output side of the plurality of second line interfaces has n receivers connected to the n links. 12. A packet communication device comprising a plurality of first devices.
Line interfaces, each of which is connected to the plurality of second line interfaces having a speed n times that of the first line interface, the plurality of first line interfaces and the plurality of second line interfaces. A packet output request periodically from the crossbar switch, the plurality of first line interfaces, and the plurality of second line interfaces, and based on the requests,
A scheduler for controlling the crossbar switch and periodically transmitting a packet transmission permission to the crossbar switch to the plurality of first line interfaces and the plurality of second line interfaces; Each line interface of the plurality of first line interfaces is connected to the crossbar switch at a link speed of speed V, and each line interface of the plurality of second line interfaces is connected to the crossbar switch at a speed of n × V. The scheduler is connected to a switch, and the scheduler has a first line interface having one input side of the first line interface.
Connected to the output side of the line interface or one output side of the second line interface, and the input side of the second line interface has a maximum of n output sides of the first line interface or one second side Packet communication device that controls the crossbar switch so that it is connected to the output side of the line interface. 13. The packet communication device according to claim 12, wherein the scheduler is a maximum of n times the maximum number of packets permitted to be transmitted to the crossbar switch by the first line interface in the same cycle. A packet communication device that permits the second line interface to send the number of packets.