JP2003007604A - Semiconductor device manufacturing method and semiconductor device inspection method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the reticle on which a plurality of identical semiconductor devices are arranged on the entire surface, without reducing the use efficiency of a stepper, and without lowering the yield of peripheral semiconductor devices. Then, an inspection reference chip is formed. SOLUTION: A step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on a surface of a silicon wafer 103 includes a reference chip forming process. In the reference chip forming process, the first region corresponding to most of the wafer 103 is exposed in a first exposure range for exposing the entire plurality of semiconductor device patterns formed on the reticle 102, Exposure to the predetermined second region is performed in a second exposure range in which a part of the plurality of semiconductor device patterns formed on the reticle is not exposed. Thus, a chip in which a part of the semiconductor device pattern is not exposed is formed as the reference chip 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a method of inspecting the same, and more particularly to a probe on a semiconductor substrate when the same semiconductor device is formed two-dimensionally continuously at a predetermined repetition interval. The present invention relates to a method for producing a chip that serves as an inspection reference, and an inspection method for a probe inspection and a visual inspection of a semiconductor device using the formed reference chip.

[0002]

2. Description of the Related Art In recent years, with the spread of portable equipment, energy saving, and reduction of waste, there is an increasing demand for a semiconductor device having a non-volatile memory that can rewrite data and retain the data even when the power is turned off. ing. The nonvolatile memory includes an EEPROM, a flash memory, and a ferroelectric memory. In the inspection, a test (retention test) for checking whether or not data is lost after being left at a predetermined temperature is usually performed. Therefore, the same semiconductor device is inspected a plurality of times discontinuously. This inspection may be carried out after the process of sealing in a plastic package or the like and the assembly process, but it is usually carried out in a wafer state because it can be carried out at a higher temperature in a shorter time and at a lower cost.

First, a conventional method of exposing a semiconductor device onto a semiconductor substrate will be described with reference to the drawings.

FIG. 13 is a schematic diagram of a step of step-and-repeat reduction exposure of a pattern of etching or impurity implantation for manufacturing a semiconductor device on a photoresist film formed on a semiconductor substrate by a stepper. 1
01 is a stepper shutter, 102 is a reticle, and 103
Is a semiconductor substrate, and 104 is a plurality of semiconductor chips.

FIG. 14 shows an example of a reticle used for manufacturing a semiconductor device. Reference numeral 105 denotes a semiconductor device pattern in each step of manufacturing a semiconductor device, and the semiconductor device patterns 105 are arranged at equal intervals over the entire exposure area of the reticle.
The process inspection pattern for checking the quality of the manufacturing process is a portion other than the necessary pattern in the semiconductor device, or the marginal portion 1 between the semiconductor devices.
It is formed in 06.

FIG. 15 shows another example of a reticle used for manufacturing a semiconductor device. The semiconductor device patterns 105 are arranged in a part of the exposure area of the reticle so that the intervals are even, and the process inspection pattern 107 for checking the quality of the manufacturing process is formed in the remaining part of the exposure area.

FIG. 16 is a diagram showing a state in which a pattern is formed on the semiconductor substrate 103 using the reticle shown in FIG. A portion 108 indicates a range in which the pattern of the semiconductor device can be obtained by one exposure. The exposure of the reticle is performed by setting the exposure range of the stepper to a predetermined position. In the case of FIG. 16, almost all of the pattern formed on the reticle is repeatedly exposed over the entire surface of the semiconductor substrate.

FIG. 17 shows the structure of FIG.
It is a figure which shows the state which formed the pattern using this reticle. In this case, the normal stepper exposure is performed in the range where a plurality of semiconductor device patterns are formed, and the region where the semiconductor device pattern is obtained by one exposure is 109. In the case of forming the other pattern, that is, the process inspection pattern 107, the pattern is formed over almost the entire surface of the reticle, and the region where the semiconductor device and other patterns are obtained by one exposure is 110.

Which of the reticle pattern methods in FIGS. 14 and 15 is selected depends on which type the process inspection pattern corresponds to, or the chip size of the semiconductor device. When the semiconductor substrate is repeatedly exposed using almost the entire surface of the pattern formed on the reticle, the number of times of the exposure is reduced, the stepper occupying time is reduced, and the manufacturing cost can be reduced.

Next, a wafer inspection including a retention test, which is carried out in an inspection of a non-volatile memory such as a flash memory or a ferroelectric memory, will be described with reference to the drawings.

FIG. 18 is a flowchart showing an example of a wafer inspection procedure for a non-volatile memory. If the steps are roughly divided, the first probe inspection (step P102) and the second probe inspection (step P104) are performed with the wafer bake (step U108) interposed.

In the first probe inspection (step P102), first, the wafer cassette is set (step U10).
2) After adjusting the inspection device (step U104), in the wafer inspection of steps W102 to W106, data writing for the data retention test is performed on all the good chips on the wafer in the first probe inspection. Step W102
In each step from W106 to W106, after the edge chip recognition is performed, inspection and data writing are sequentially performed for each chip. After step W106 is completed, the wafer cassette is released (step U106), and in step U108, the wafer is baked at a predetermined temperature for a predetermined time.

Next, a second probe inspection (step P10)
In 4), first, the wafer cassette is set (step U110), the inspection device is adjusted (step U112), and then the wafer inspection in steps W108 to W112 is performed.
By carrying out a read test of the written data, it is inspected whether or not it has a data holding capacity higher than a predetermined value. In each of steps W108 to W112,
After the edge chip recognition is performed, a read test is sequentially performed for each chip, and then the results of the first probe inspection and the second probe inspection are collated. Needless to say, in this case, the non-defective chip for the second probe inspection needs to be a semiconductor device that has definitely obtained the non-defective product for the first probe inspection.

Next, the method of detecting the presence or absence of the measuring chip and the method of detecting the connection between the probe and the bonding pad in the probe inspection will be described.

FIG. 19 is an equivalent circuit showing the connection between the input circuit of the semiconductor device and the probe for probe inspection.
111 is a bonding pad, 112 is an inspection probe, 113 is an input circuit to the circuit section, 114 is a diode for protecting an input transistor, 115 is a current source, and 116 is a voltmeter. 117 is a thick insulating film, 118 is a silicon substrate, 119 is a surface protective film, and 120 is a chip coating agent. Inspection probe 112 and bonding pad 11
The connection inspection of No. 1 is performed by measuring the voltage generated between both terminals of the protection diode 114 by applying the current source 115 as shown in FIG.

FIG. 20 is a view showing a conventional reference chip position for collating the inspection results of the first probe inspection and the second probe inspection. In the portion 121 on the semiconductor substrate where the exposure range of the stepper is not entered, the bonding pad window forming reticle and the like are not exposed, so that the semiconductor device pattern such as the bonding pad is not formed. The reference chip in the case of this figure is the chip 1 arranged at the left end of the chip patterned as a semiconductor device.
22. The detection is carried out by arranging four adjacent chip positions 1
Of the 23, 124, 125 and 126, two chip positions 123 and 124 have a defective connection of the inspection probe,
This is done because the chip positions 125 and 126 have a good connection of the inspection probe.

Next, a conventional semiconductor device appearance inspection method will be described with reference to the drawings. FIG. 21 is a diagram showing an example of designated chips for appearance inspection on the wafer of FIG. Normally, the number of wafers and the number of appearance inspection chips are set in accordance with the appearance inspection standard, and the appearance inspection is performed on the designated chips arranged in a cross shape as shown by 127 in this figure.

[0018]

However, the conventional method of manufacturing a semiconductor device as described above has the following problems.

When the process evaluation pattern is arranged in the marginal area between the semiconductor devices, the same semiconductor device is repeatedly arranged on almost the entire surface of the semiconductor substrate. Therefore, there is no reference or mark chip on the wafer, such as a chip that is different in appearance from the semiconductor device. In particular, in the case of a small chip size in which the number of semiconductor devices to be formed reaches several thousand, the number of chips interposed from the peripheral chips to the target chip increases, and this problem becomes more prominent.

When a process evaluation pattern is formed at a predetermined position on the semiconductor substrate instead of the semiconductor device,
This chip serves as a mark. However, since the reticle of the type shown in FIG. 15 is used, the number of semiconductor devices subjected to reduction exposure at one time is reduced, and the time required to complete the step and repeat on the entire surface of the wafer becomes longer. This means that the occupied time of the stepper increases,
This causes an increase in process cost for manufacturing a semiconductor device.

Alternatively, a method may be considered in which a stepper does not perform exposure at a predetermined position on the semiconductor substrate and no pattern is formed instead of the semiconductor device pattern. In this case, the etching pattern and the film thickness are not changed. Since a region different from that of the peripheral semiconductor device is formed, there is a problem in that the peripheral semiconductor device has a processing problem and the yield is reduced.

Further, when the same semiconductor devices are arranged on the semiconductor substrate at uniform intervals, the semiconductor device formed on the peripheral portion of the wafer is subjected to the reference chip for the probe inspection by the conventional semiconductor device probe inspection method. When used as, there are the following problems. In the peripheral portion of the silicon wafer, the state of etching and film formation of the semiconductor device is not always uniform, and the inspection probe and the semiconductor substrate may have electrical continuity even in the portion where the pattern is not formed. On the contrary, in some cases, even in the pattern formation portion, the inspection probe and the semiconductor substrate may not have electrical continuity. Further, there are cases where the inspection probe and the semiconductor substrate at the outermost peripheral chip do not have electrical continuity due to problems in the measurement environment such as wafer warpage and inspection stage inclination.
Therefore, the outermost peripheral chip on which the pattern is formed cannot always be recognized as a fixed position for all silicon wafers. Therefore, even if an attempt is made to collate the results of a large number of probe tests using the outermost peripheral reference chip, a deviation will occur for each probe test, causing a serious quality problem such as outflow of defective chips.

Further, when the same semiconductor devices are arranged on the semiconductor substrate at uniform intervals, the number of chips from the semiconductor device formed on the peripheral portion of the wafer is counted by the conventional appearance inspection method of the semiconductor device. When deciding the location of the visual inspection, there are the following problems. That is, an error may occur in the counting, and the location of the visual inspection target chip may be mistaken.

According to the present invention, the manufacturing cost of a semiconductor wafer is increased without changing the reticle in which a plurality of identical semiconductor devices are arranged on the entire surface, or the peripheral semiconductor devices are determined to be defective and the yield is reduced. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can form a reference chip for inspection on a wafer without performing the above.

Further, by using the reference chip on the wafer manufactured by using the method for manufacturing a semiconductor device of the present invention, even when a probe test is performed a large number of times, it is possible to prevent an error in collating the test results. An object of the present invention is to provide a semiconductor device inspection method capable of ensuring high quality.

Further, by using the mark chips on the wafer manufactured by the method for manufacturing a semiconductor device of the present invention, the chips to be visually inspected can be easily grasped, high work efficiency can be obtained, and the objects to be visually inspected can be obtained. An object of the present invention is to provide a semiconductor device appearance inspection method capable of ensuring high quality by preventing chip extraction errors.

[0027]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention reduces a semiconductor device pattern for etching or implanting impurities into a photoresist layer formed on a surface of a silicon wafer. The step of exposing includes a reference chip forming process. In the reference chip forming process, the first area corresponding to most of the wafer is exposed in the first exposure range in which the entire plurality of semiconductor device patterns formed on the reticle are exposed, The exposure to the predetermined second region is performed in the second exposure range where a part of the plurality of semiconductor device patterns formed on the reticle is not exposed. As a result, a chip in which a part of the semiconductor device pattern is not exposed is formed as a reference chip.

According to this manufacturing method, in the process of manufacturing the semiconductor devices arranged on the semiconductor substrate, it is possible to perform inspection on the semiconductor substrate without creating a new reticle and increasing the occupied time of the stepper. It is possible to form the reference chip.

In the above manufacturing method, the reference chip forming process can be included in the step of forming a bonding pad window on the surface protective film. Further, the reference chip forming process may be included in the step of forming a contact window on the metal wiring layer. Alternatively, the reference chip forming process may be included in the step of forming a bonding pad window on the chip coating agent.

In the method of inspecting a semiconductor device according to the present invention, the step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on the surface of a silicon wafer includes a reference chip forming process. In the reference chip forming process, the first area corresponding to most of the wafer is exposed in the first exposure range for exposing the entire plurality of semiconductor device patterns formed on the reticle, and the predetermined area on the wafer is set. Of a plurality of semiconductor device patterns formed on the reticle in a second exposure range that does not expose a part of the semiconductor device pattern, and a part of the semiconductor device pattern is exposed. It is characterized in that the semiconductor device is probe-tested using a reference chip which is not provided.

Further, according to another method of inspecting a semiconductor device of the present invention, a step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on a surface of a silicon wafer is a reference chip forming process. In the reference chip forming process, the first region corresponding to most of the wafer is exposed in a first exposure range in which the entire plurality of semiconductor device patterns formed on the reticle are exposed, A semiconductor device is manufactured by a manufacturing method in which a predetermined second region on a wafer is exposed in a second exposure range in which a part of the plurality of semiconductor device patterns formed on the reticle is not exposed, and the semiconductor device pattern It is characterized in that a reference chip that is not partially exposed is used as a mark chip in a visual inspection.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. This figure shows a part of a step of step-and-repeat reduction exposure of an etching or impurity implantation pattern for manufacturing a semiconductor device on a photoresist film formed on a semiconductor substrate by a stepper. Reference numeral 103 is a semiconductor substrate, 104 is a plurality of semiconductor chips, 102 is a reticle, 001 is a stepper shutter, and 005 is a plurality of reference semiconductor chips on a wafer.

FIG. 2 shows an exposure method in a step of performing exposure with a reticle in a normal state. Most areas on the semiconductor substrate are exposed by this method. 105
Is a semiconductor device pattern in each manufacturing process, and is arranged so as to be evenly spaced over the entire exposure area of the reticle. Reference numeral 006 denotes the exposure range, and reduction exposure is performed on the photoresist on the semiconductor substrate including the entire region of the semiconductor device pattern 105 in the reticle.

FIG. 3 shows an exposure method for forming a reference chip in a step of exposing a plurality of reference semiconductor chips on a predetermined portion of a semiconductor substrate. 0
07 indicates the exposure range. In FIG. 3, a part of the semiconductor device pattern 105 arranged on the reticle (the lower end portion of the four chips at the lower end in this figure) is blocked by the shutter or the like and is not exposed.

4 to 6 each show an example in which a reference semiconductor chip is formed by setting the exposure range as shown in FIG.

FIG. 4 is an equivalent circuit showing a connection state between the input circuit of the semiconductor device and the probe for probe inspection when a part of the reticle for forming the bonding pad window is not exposed. 111 is a bonding pad, 112 is an inspection probe, 113 is an input circuit to the circuit section, 114 is a diode for protecting an input transistor, 115 is a current source, 1
16 is a voltmeter. Since the protective film 008 remains on the bonding pad 111, the inspection probe 112 and the bonding pad 111 cannot be connected.

FIG. 5 is an equivalent circuit showing a connection state between the input circuit of the semiconductor device and the probe inspection probe when a part of the reticle for forming the contact window for metal wiring is not exposed. In this case, the inspection probe 112 and the bonding pad 111 can be connected, but the inspection probe 112 is in the open state because the wiring between the bonding pad 111 and the input protection diode 114 is cut.

FIG. 6 is an equivalent circuit showing the connection state of the input circuit of the semiconductor device and the probe inspection probe when a part of the reticle for forming the bonding pad window of the chip coating agent is not exposed. Since the chip coating agent 009 remains on the bonding pad 111, the inspection probe 112 and the bonding pad 111 cannot be connected.

By using one of the above methods, the reference semiconductor chip can be detected based on the difference in resistance value (voltage value difference) between the corresponding semiconductor device and the peripheral semiconductor devices. Exposure to most of the semiconductor substrate is shown in FIG.
The reticle exposure is performed within the range shown in FIG. 3 only when a plurality of reference chips are formed on the semiconductor substrate.

FIG. 7 shows a state in which a reference chip 010 is formed on the semiconductor substrate 103. Note that in the manufacturing method of the present embodiment, the difference in shape from the surrounding chips does not exist at all in the transistor forming process and hardly exists in the metal wiring process, so that the yield in the chips around this reference chip decreases. Can be prevented. Further, regarding the place where the reference chip is formed, the yield decrease due to the reference chip itself can be minimized by partially utilizing the part where etching and film formation are unstable near the peripheral portion of the wafer.

(Second Embodiment) FIG. 8 is a flow chart showing a method for inspecting a semiconductor device according to a second embodiment of the present invention. The steps are roughly divided into a first probe inspection (step P02) and a second probe inspection (step P0).
4) is performed with a wafer bake (step U08) interposed.

In the first probe inspection (step P02), first, the wafer cassette is set (step U0
2) After adjusting the inspection device (step U04), in the wafer inspection of steps W02 to W06, data writing for the data retention test is performed on all the good chips on the wafer in the first probe inspection. Steps W02 to W0
In each step of 6, inspection and data writing are sequentially performed for each chip. After completion of step W06, the wafer cassette is released (step U06), and step U08
Then, the wafer is baked at a predetermined temperature for a predetermined time.

Next, a second probe inspection (step P0
In 4), first, the wafer cassette is set (step U10), the inspection device is adjusted (step U12), and then the read test of the written data is performed in the wafer inspection of steps W08 to W12 to obtain data of a predetermined value or more. Inspect whether or not it has retention ability. In each of steps W108 to W112, a read test is sequentially performed for each chip, and then the results of the first probe test and the second probe test are compared. In the second probe inspection at this time, the reference chip coordinates are recognized and the collation with the first probe inspection result is surely performed.

The reference chip coordinates are recognized based on the fact that the plurality of reference chips prepared by the manufacturing method shown in the first embodiment cannot be electrically connected to the inspection probe and the semiconductor substrate or the power supply wiring. This reference chip can be used to collate the wafer inspection results obtained by performing the probe inspection a number of times.

FIG. 9 shows the inspection result obtained by the first probe inspection. For simplification of the illustration, the illustration is omitted except for the upper left part of the wafer, but the other parts are also the same.
C in the drawing shows a chip in which the inspection probe is not electrically connected to the semiconductor substrate or the power supply wiring. F
Shows a chip which has an electrical connection but is determined to be defective by inspection of other items. P indicates a chip that passed the inspection. FIG. 10 shows the inspection results obtained by the second probe inspection, and similarly, only a part is shown. The same applies when there are three or more inspections, so the case of two inspections will be described here.

The inspection results are collated by matching the positions of the plurality of reference chips 011 and 012 in the inspection results of the first and second inspections. As a result, the chip 013 in which only one of the peripheral chips has been tested,
The chip 014, which has a connection failure in one of the inspections, is not judged as a non-defective product. This gives the final non-defective product map shown in FIG.
In addition, it is possible to easily obtain high-quality semiconductor devices and prevent defective products from being mixed or leaked. Here, P indicates a chip that has passed all inspections, and F indicates a chip that has been determined to be defective in any inspection. In this example, the case where each inspection result is collated after the probe inspection has been described, but by determining the reference chip at the beginning of each probe inspection, the probe inspection can be performed while referring to the previous probe inspection result during the inspection. You can do it.

(Third Embodiment) FIG. 12 shows a semiconductor device inspection method according to a third embodiment of the present invention.

Reference numeral 015 is a plurality of mark chips produced by the manufacturing method shown in the first embodiment. Due to the difference that the inspection probe is not electrically connected to the semiconductor substrate or the power supply wiring, there is formed a state in which a plurality of defective chips are continuously present in the group of good chips. Since there are a plurality of chips having a plurality of continuous defect marks at specific locations 015, 016, 017, and 018 on the wafer, this can be used as a mark chip.

Further, when the reticle for forming the bonding pad window of the chip coat film is used for forming the mark chip, it is easy to determine whether or not the bonding pad window is formed in the chip, so that a defective mark is formed. It can be used as a landmark chip even if it is not dripping. By setting a chip existing in a predetermined area 019 near this mark chip as a visual inspection target, the visual inspection target chip can be easily selected.

[0051]

According to the method of manufacturing a semiconductor memory device of the present invention, a standard reticle can be formed on a semiconductor substrate without making a new reticle and without increasing the process cost by reducing the use efficiency of the stepper. Chips or landmark chips can be created.

According to the semiconductor device inspection method of the present invention,
It is possible to prevent misalignment even in the case of a large number of inspections and provide a high quality semiconductor device. In addition, since the inspection can be performed while referring to the result of the previous inspection at the time of the probe inspection, the chip judged to be defective in the previous inspection can be skipped, which is effective in shortening the inspection time and reducing the inspection cost.

According to the semiconductor device inspection method of the present invention,
A chip subject to visual inspection can be easily detected, and a high-quality semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an exposure range of a reticle for explaining the manufacturing method according to the first embodiment.

FIG. 3 is a plan view showing an exposure range of a reticle for explaining the manufacturing method according to the first embodiment.

FIG. 4 is an equivalent circuit diagram for explaining the operation of an example in which the manufacturing method of the first embodiment is carried out.

FIG. 5 is an equivalent circuit diagram for explaining the operation of another example in which the manufacturing method of the first embodiment is carried out.

FIG. 6 is an equivalent circuit diagram for explaining the operation of another example in which the manufacturing method of the first embodiment is carried out.

FIG. 7 is a plan view of a semiconductor device wafer for carrying out a semiconductor device inspection method according to a second embodiment of the present invention.

FIG. 8 is a flowchart of an inspection method according to the second embodiment of the present invention.

FIG. 9 is a wafer map showing a first inspection result for explaining the inspection method according to the second embodiment.

FIG. 10 is a wafer map showing a second inspection result for explaining the inspection method according to the second embodiment.

FIG. 11 is a wafer map showing the result after collation for explaining the inspection method in the second embodiment.

FIG. 12 is a plan view of a semiconductor device wafer for implementing a semiconductor device inspection method according to a third embodiment of the present invention.

FIG. 13 is a schematic view showing a method of manufacturing a semiconductor device of a conventional example.

FIG. 14 is a plan view of a reticle used in a conventional method for manufacturing a semiconductor device.

FIG. 15 is a plan view of a reticle used in a conventional method for manufacturing a semiconductor device.

FIG. 16 is a plan view showing a conventional semiconductor device wafer.

FIG. 17 is a plan view showing a semiconductor device wafer of a conventional example.

FIG. 18 is a flowchart of a conventional semiconductor memory device inspection method.

FIG. 19 is an equivalent circuit diagram showing a connection inspection between the probe and the semiconductor substrate in the probe inspection.

FIG. 20 is a plan view showing a reference chip in a probe inspection of a conventional example.

FIG. 21 is a plan view showing a conventional semiconductor device wafer.

[Explanation of symbols]

001 shutter 005 Reference semiconductor chips 006 exposure range 007 exposure range 008 protective film 009 Chip coating agent 102 reticle 103 semiconductor substrate 104 semiconductor chip 105 Semiconductor device pattern 111 Bonding pad 112 Inspection probe 113 Input circuit 114 Protective diode 115 current source 116 Voltmeter

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Claims (6)

[Claims] 1. A step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on a surface of a silicon wafer includes a reference chip forming process, and in the reference chip forming process,
Exposure to a first region corresponding to most of the wafer is performed in a first exposure range for exposing the entire plurality of semiconductor device patterns formed on the reticle, and a predetermined second region on the wafer is exposed. A chip in which a part of the semiconductor device pattern is not exposed is formed as a reference chip by performing the exposure in a second exposure range in which a part of the plurality of semiconductor device patterns formed on the reticle is not exposed. Manufacturing method of semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the reference chip forming process is included in a step of forming a bonding pad window on the surface protective film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the reference chip forming process is included in a step of forming a contact window in a metal wiring layer. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the reference chip forming process is included in a step of forming a bonding pad window on a chip coating agent. 5. The step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on a surface of a silicon wafer includes a reference chip forming process, and in the reference chip forming process,
Exposure to a first region corresponding to most of the wafer is performed in a first exposure range for exposing the entire plurality of semiconductor device patterns formed on the reticle, and a predetermined second region on the wafer is exposed. A semiconductor device is manufactured by a manufacturing method in which a part of the plurality of semiconductor device patterns formed on the reticle is not exposed, and a semiconductor device is manufactured by using a reference chip in which part of the semiconductor device pattern is not exposed. A method of inspecting a semiconductor device, which comprises inspecting a semiconductor device with a probe. 6. The step of reducing and exposing a semiconductor device pattern for performing etching or impurity implantation on a photoresist layer formed on a surface of a silicon wafer includes a reference chip forming process, and in the reference chip forming process,
Exposure to a first region corresponding to most of the wafer is performed in a first exposure range for exposing the entire plurality of semiconductor device patterns formed on the reticle, and a predetermined second region on the wafer is exposed. A semiconductor device is manufactured by a manufacturing method in which a part of a plurality of semiconductor device patterns formed on the reticle is not exposed in a second exposure range, and a reference chip whose part of the semiconductor device pattern is not exposed is subjected to an appearance inspection. A method for inspecting a semiconductor device, which is used as a marking chip in a case.