JP2003092270A - Compound semiconductor processing method - Google Patents

Abstract

(57) Abstract: When valence electrons of a first compound semiconductor are controlled by irradiation of particles containing impurity atoms and activation annealing, defects that remain / generate in an injection layer are irradiated with the particles. And a processing method for compensating / suppressing generation by adding a step of laminating a second compound semiconductor layer on the first compound semiconductor layer. SOLUTION: An impurity element for controlling valence electrons in a first compound semiconductor layer composed of a compound semiconductor composed of a group II and group VI element, a group III and group V element, or a mixed crystal thereof is provided. A step of irradiating the particles containing particles with acceleration, a step of laminating a second compound semiconductor layer on the first compound semiconductor layer irradiated with the particles, and a step of heat-treating after laminating the second compound semiconductor layer And

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing method for controlling valence electrons of a compound semiconductor and forming a good metal electrode.

[0002]

2. Description of the Related Art In recent years, new semiconductor materials have been actively developed in order to realize semiconductor devices having particularly excellent specific characteristics such as high frequency characteristics, light emission characteristics, and breakdown voltage characteristics. Among semiconductor materials, compound semiconductors represented by indium phosphide (InP) and gallium arsenide (GaAs) are silicon.
Since it has higher electron mobility and saturated electron velocity than (Si), it is a material expected to be applied to next-generation high-frequency devices and the like.

Generally, when an active element is formed of a semiconductor material, doping with an impurity element is performed in order to control its function and characteristics. For example, chemical vapor deposition (CVD
Method, a p- and n-type doping layer having desired characteristics can be formed by adding a doping gas to the reaction gas. On the other hand, in a device manufacturing process that actually uses a semiconductor material, not only the formation of a doping layer by thin film deposition as described above, but also methods such as ion implantation are useful.

Ion implantation is a method of accelerating particles to be introduced and irradiating the semiconductor material with impurity doping, and by determining the substrate material (target material), implanted ion species, implantation energy, and implantation amount. ,
Highly precise doping layer with desired concentration / depth (thickness)
And it can be formed with good reproducibility. Further, by laminating the patterned implantation mask layer on the substrate material, it is possible to selectively select a region to be doped. Also in compound semiconductor materials, GaAs field effect transistors
(FET) and an integrated circuit (IC) are used for forming a doping layer.

[0005]

The technique of ion implantation into silicon (Si) is an established technique and is indispensable for the device manufacturing process. However, in the case of compound semiconductors, multiple elements are used. As such, there are several challenges in ion implantation and activation annealing processes. For example, various phenomena related to crystal stoichiometry, out-diffusion of implanted atoms during activation annealing, dissociation of constituent elements, and the like can be very complicated compared to Si. For example, generally, an annealing treatment at a relatively high temperature is required to activate the ion-implanted element, but in this activation annealing treatment, the dissociation vapor pressure of the constituent elements is different in the compound semiconductor. Only the specific element is easily released. As a result, there has been a problem that structures such as defects and dislocations remain / generate in the ion-implanted region. Therefore, in the compound semiconductor, the semiconductor device using the ion implantation layer as a doping layer has been limited.

As described above, the conventional methods for controlling the valence electrons of the compound semiconductor material have problems that they do not sufficiently satisfy the required characteristics or they are difficult.

Therefore, in order to solve the above-mentioned problems in the prior art, the present invention accelerates and irradiates particles containing an impurity element for controlling valence electrons to a first compound semiconductor layer composed of a single layer or multiple layers. By including a step, a step of stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer, and a step of heat-treating after stacking the second compound semiconductor layer Another object of the present invention is to provide a doping layer having a low contact resistance with respect to a metal electrode while suppressing generation of defects in the injection layer.

In order to solve the above problems in the prior art, the present invention accelerates and irradiates particles containing an impurity element for controlling valence electrons to the first compound semiconductor layer composed of a single layer or multiple layers. A step of stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer, a step of heat-treating after stacking the second compound semiconductor layer, and a step of heat-treating after the heat treatment. By including a step of removing a predetermined part of the second compound semiconductor layer, it is an object to suppress the generation of defects in the injection layer and to easily provide a semiconductor device having high reproducibility.

[0009]

In order to achieve the above object, a method for treating a compound semiconductor according to the present invention is an impurity element for controlling valence electrons of a first compound semiconductor layer composed of a single layer or multiple layers. Of accelerating and irradiating the particles containing the compound, a step of stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer, and a heat treatment after the second compound semiconductor layer is stacked. And a process.

In order to achieve the above object, the method for treating a compound semiconductor according to the present invention accelerates particles containing an impurity element for controlling valence electrons in a first compound semiconductor layer having a single layer or multiple layers. And irradiating, a step of stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer, a step of heat treatment after stacking the second compound semiconductor layer, and a step of heating. After the treatment, a step of removing a predetermined part of the second compound semiconductor layer is included.

Further, in the method for treating a compound semiconductor according to the present invention, it is preferable that the group III element constituting the compound semiconductor contains at least one selected from aluminum (Al), gallium (Ga) and indium (In).

In the method for treating a compound semiconductor according to the present invention, the group V element constituting the compound semiconductor is nitrogen (N),
It is preferable to contain at least one selected from phosphorus (P) and arsenic (As).

Generally, defects are introduced into the impurity atom injection layer formed by the ion injection method or the like immediately after the injection. Activation annealing treatment at high temperature is effective for the recovery, but in the case of compound semiconductors, the constituent elements with high dissociation vapor pressure tend to escape, so even if the implanted impurity element is activated, Defects and dislocations are likely to remain inside, and new ones are easily generated. Further, the activation annealing treatment causes impurity atoms near the surface of the implantation layer to diffuse / segregate, and in some cases, desired semiconductor characteristics may not be obtained due to the influence of the surface high-concentration doping layer.

Therefore, the inventors of the present invention, in order to obtain the desired doping layer while suppressing the influence of the above-mentioned phenomenon occurring during the activation annealing treatment as much as possible, after irradiating the first compound semiconductor layer with the impurity particles, By stacking two compound semiconductor layers and performing heat treatment, generation of defects and dislocations in the doping layer is suppressed, and the metal electrode (ohmic electrode) formed on the second compound semiconductor layer has low contact. I found it to be a resistance.

Further, the inventors of the present invention, in order to obtain the desired doping layer while suppressing the influence of the above phenomenon occurring during the activation annealing treatment as much as possible, a predetermined part of the second compound semiconductor layer after the heat treatment. It was found that by removing the region, a semiconductor device in which the first compound semiconductor layer has a desired doping profile can be easily manufactured.

Further, in the constitution of the present invention, the group III element constituting the compound semiconductor contains aluminum (Al), gallium (Ga), indium (In), or the group V element constituting the compound semiconductor material is nitrogen. (N), Rin
It has been found that when applied to a compound semiconductor of a system containing (P) and arsenic (As), it works very effectively.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
A description will be given with reference to the drawings.

In FIG. 1, the first compound semiconductor layer 11 is irradiated with particles 12 containing accelerated impurity atoms, and a second compound semiconductor layer 14 is further laminated thereon, followed by heat treatment to form a good doping layer 15. It is a flowchart showing the procedure to do.

First, a first process for forming a doping layer is performed.
The compound semiconductor layer 11 is prepared (step). Further normal washing
After purification treatment, the first compound semiconductor layer for controlling valence electrons
Irradiate the particles 12 containing the accelerated impurity element 11
(Process). Particle acceleration energy and irradiation dose
Is appropriately determined by the thickness and concentration of the desired doping layer
However, each is approximately 100 eV to 10 MeV, 1 × 10^Ten
~ 1 x 10¹⁷Pieces / cm ²Is. Above all, 50
~ 200 keV, 1 x 10¹²~ 1 x 10¹⁴Pieces / cm²of
The range is often used. In some cases, during injection
Substrate heating to expose particles or several different irradiations
It is also effective to irradiate the particles multiple times under the conditions. That conclusion
As a result, impurity atoms are injected into the surface of the first compound semiconductor layer 11
The implanted region 13 is formed,
Contains many defects due to the effect of particle irradiation (process).

Then, in order to obtain a good doping layer, the second compound semiconductor layer 14 is laminated on the implantation region 13 (step). The second compound semiconductor layer material to be laminated is
The film has the same composition as that of the first compound semiconductor layer, or substantially matches the lattice constant of the first compound semiconductor layer material,
A film structure having a composition that is smaller than the energy gap value is suitable. The thickness is preferably about 10 to 20 nm in consideration of the surface diffusion region of impurity atoms. The formation method is also the chemical vapor deposition method (CV
D method), MBE method or the like may be selected as appropriate and is not particularly limited.

Finally, heat treatment (annealing treatment) is performed to activate the implanted impurity atoms, and a doping layer 15 having a low defect is formed (step). The method of this activation annealing treatment is not particularly limited, and can be applied to any method such as heat treatment generally performed in a tubular furnace or heating by infrared rays or laser irradiation. Looking at the formed doping layer 15 in detail, the inside of the first compound semiconductor layer has an impurity distribution substantially in accordance with the profile designed in advance under the implantation conditions, and the inside of the second compound semiconductor layer is surface-treated by heat treatment. Due to the diffused part of the impurity atoms, a high-concentration doping layer 15a suitable for forming an ohmic electrode is formed. Therefore, the second
The ohmic electrode layer 16 having a low contact resistance can be formed by vapor-depositing an appropriately selected metal on the compound semiconductor layer (1) (step).

A concrete example carried out by this procedure is shown in the following first and second embodiments.

2A and 2B, after the doping layer is formed in the steps (steps to) shown in FIG. 1, a predetermined part of the second compound semiconductor layer 14 (15a) is further removed to remove the first compound semiconductor. It is a process drawing showing the procedure of forming an electrode on the surface of layer 11 (15b).

The steps up to are the same as above.
In the example shown in FIG. 1, the heavily doped layer 15a
Although the procedure is suitable for forming the ohmic electrode layer 16 due to the effect of, the high-concentration doping layer 1 is used for forming a Schottky junction on the compound semiconductor layer.
On the contrary, 5a may be unsuitable. Therefore, in this case, by removing a desired region of the highly doped second compound semiconductor layer, the impurity atom implantation step (steps
) With a distribution according to the injection conditions appropriately determined by
Exposing the compound semiconductor layer is effective means.
Therefore, a part of the second compound semiconductor layer region formed after the heat treatment is removed by a method such as etching (step). As the removing method, only the second compound semiconductor layer may be removed according to the etching rate calculated in advance,
In a certain etching method, when the composition of the first compound semiconductor layer and the second compound semiconductor layer has an etching selection ratio (when the etching rate of the second compound semiconductor layer is higher than that of the first compound semiconductor layer) Alternatively, only the second compound semiconductor layer may be selectively etched. Particularly in the latter case, it is easy to remove only the second compound semiconductor layer and expose the surface of the first compound semiconductor layer designed in advance. As a result, the exposed first compound semiconductor layer becomes the implantation doping layer 15b suitable for forming the Schottky electrode. Therefore, the Schottky electrode layer 17 having good characteristics can be formed by vapor-depositing an appropriately selected metal on the first compound semiconductor layer (step).

A concrete example of this procedure is shown in the following third and fourth embodiments.

<First Embodiment> A case in which indium phosphide (InP) is adopted as the first compound semiconductor according to the present invention and an n-type doping layer is formed by introducing silicon (Si) will be described below. To do.

First, Si was ion-implanted as an n-type impurity into a semi-insulating single crystal InP substrate having a plane orientation of (100). The implantation conditions were implantation energy: 100 keV and implantation dose: 8 × 10 ¹² pieces / cm ² . FIG. 3A shows the result of measurement of the Si depth profile in the InP layer immediately after Si ion implantation by secondary ion mass spectrometry (SIMS). From this, the InP surface layer is about 300 nm
It can be seen that Si atoms are distributed in the region. In addition, this distribution almost agrees with the simulation result of the ion implantation distribution based on the LSS theory, and it is possible to obtain a desired impurity concentration profile in the first compound semiconductor layer by properly setting the implantation conditions. all right. However, in this state, the implanted Si is not activated and does not function as a doping layer.

Therefore, prior to the annealing treatment for activating the implanted Si, an InP layer having the same composition as the first compound semiconductor layer was epitaxially grown by the MBE method to a thickness of about 20 nm as the second compound semiconductor layer. Then, the ion-implanted InP substrate on which the InP layer has been additionally grown is irradiated with infrared rays in a nitrogen atmosphere and heated at 700 to 750 ° C. for 15
A minute activation annealing process was performed. For comparison,
A sample subjected to activation annealing treatment without depositing the InP layer which is the second compound semiconductor layer under the same conditions was also prepared.

The doping characteristics of the prepared sample are determined by Hall.
As a result of evaluation by measurement and the like, it was found that Si ion-implanted InP exhibits n-type conduction regardless of the presence or absence of the second compound semiconductor layer deposition step, and that Si is activated in all cases, but the sample without InP deposition In addition, unnecessary carrier generation, which is considered to be caused by defects remaining / generated inside the injection layer, was found, and its mobility was lower than that of the InP deposited sample. In addition, the existence of a relatively deep donor level (-200 meV) due to the above defects was confirmed.

On the other hand, in the InP deposited sample produced by the method of the present invention, the sheet resistance value R _s : 300 to 500 Ω / □ and the sheet carrier concentration n _s : 7.0 to 7.5 × 10 ¹² at room temperature (300 K). cm ^-2 , mobility μ: 14
0 to 1600 cm ² / Vs was obtained, and from the temperature characteristic measurement of the sheet carrier concentration, only the shallow donor level (up to 5 meV) due to the Si donor was observed. That is, the present inventors have confirmed that the InP deposition process has an effect of compensating / suppressing defects that may remain / create inside the implantation layer in the conventional ion implantation / activation annealing process.

Further, the Si depth profile in the sample after the heat treatment was measured by SIMS. The result is shown in FIG. As a result, the Si distribution in the InP substrate, which is the first compound semiconductor layer, hardly changed as compared with FIG. 3A, and the initial profile was maintained, but additional growth was performed. It was found that a high-concentration doping layer was formed in the InP layer, which is the second compound semiconductor layer, due to slight surface diffusion of Si accompanying the heat treatment. Therefore, Ni / Au is formed on the heavily doped layer.
As a result of forming an ohmic electrode made of Ge / Ni / Au and evaluating the contact resistance of the electrode, it was found that good ohmic characteristics were exhibited.

This effect was also confirmed in other compound semiconductor materials such as GaAs deposition on GaAs.

<Second Embodiment> In the first embodiment, the case where the second compound semiconductor layer is made of a material different from that of the first compound semiconductor layer will be described below.

In the present embodiment, the first compound semiconductor layer (semi-insulating single crystal InP substrate) and ion implantation conditions (Si implantation energy: 100 keV, Si implantation dose: 8 × 10 ¹² pieces / cm ² ) are used. This is exactly the same as the first embodiment. In this embodiment then, indium gallium arsenide _{(In x Ga 1-x As} : x = 0.52) were InP lattice-matched as the second compound semiconductor layer layer a MBE
The film was epitaxially grown to a thickness of about 20 nm. Then, the ion-implanted InP substrate was irradiated with infrared rays in a nitrogen atmosphere, and an activation annealing treatment was performed at a heating temperature of 700 to 750 ° C. for 15 minutes. As a result, the inventor of the present invention has the effect of compensating / suppressing defects that may remain / generated inside the implantation layer in the conventional ion implantation / activation annealing process as in the first embodiment. Confirmed.

Further, as a result of forming an ohmic electrode on the high-concentration doping layer made of the InGaAs layer and evaluating the contact resistance of the electrode, it was confirmed that good ohmic characteristics were exhibited.

<Third Embodiment> A case where indium phosphide (InP) is adopted as the first compound semiconductor according to the present invention and a Schottky electrode is formed in an n-type doping layer by introducing silicon (Si) will be described below. Explained.

First, Si is ion-implanted into a semi-insulating single crystal InP substrate under the same implantation conditions as in the above embodiment, and an InP layer (thickness: up to 20 nm) is epitaxially formed as a second compound semiconductor layer. After growing, 700-750 ℃
The activation annealing treatment was performed at the heating temperature of 15 minutes.
The obtained sample has a second surface on the surface, as in the first embodiment.
A good n-type layer consisting of a high-concentration doping layer made of the compound semiconductor layer and an injection doping layer formed in the first compound semiconductor layer was formed. S in the sample after heat treatment
The i-depth direction profile is the same as that shown in FIG. When forming an electrode having ohmic characteristics as in the first embodiment, high-concentration doping formed in the second compound semiconductor layer is effective, but a high doping level is required to obtain Schottky characteristics. However, it was difficult to form a good Schottky junction with any metal material.

Then, the second compound semiconductor layer portion in the region where the Schottky electrode is formed is removed by wet etching to the original surface of the first compound semiconductor layer, and the exposed surface of the Schottky made of Pt / Au. The electrode was formed. In this embodiment, a mixed solution of sulfuric acid / hydrogen peroxide diluted with pure water is used as an etching solution, and the second compound semiconductor layer I is formed by controlling the etching time.
The nP layer (high concentration doping layer) was removed. as a result,
It was found that the Schottky characteristic was excellent according to the Si impurity distribution in the first compound semiconductor layer.

This effect was also confirmed in other compound semiconductor materials such as GaAs deposition on GaAs.

<Fourth Embodiment> In the third embodiment, the case where the second compound semiconductor layer is made of a material different from that of the first compound semiconductor layer will be described below.

In this embodiment, an InGaAs layer lattice-matched with the InP layer (thickness:
(.About.20 nm) after epitaxial growth, activation annealing treatment was performed at a heating temperature of 700 to 750.degree. Similar to the second embodiment, the obtained sample has a good n-type including a high-concentration doping layer formed of the second compound semiconductor layer on the surface and an implantation doping layer formed in the first compound semiconductor layer. A layer was formed.

Then, the second compound semiconductor layer (InGaAs layer) forming the Schottky electrode is removed by etching, and Pt / A is formed on the surface of the first compound semiconductor layer (InP layer).
A Schottky electrode made of u was formed. In the present embodiment, by using a citric acid / hydrogen peroxide water mixed solution diluted with pure water as an etching solution, InGaA
Only the s layer can be selectively etched, and the InP doping layer that is the first compound semiconductor layer can be easily exposed. As a result, it was found that good Schottky characteristics were exhibited according to the Si impurity distribution in the first compound semiconductor layer.

<Fifth Embodiment> An InP MES-FET having a Si ion implantation layer as a channel layer was manufactured by using the method shown in each of the above embodiments. That is, after the source / drain electrodes (ohmic electrodes) of the FET are formed by the procedure shown in the second embodiment, the second compound of the portion to be the gate is formed by the method shown in the fourth embodiment. The semiconductor layer (InGaAs layer) was selectively removed, and a gate electrode (Schottky electrode) was formed on the surface of the ion-implanted n-InP layer. As a result, the MES-FET showing high reproducibility and good characteristics by this method.
The present inventors have confirmed that the above can be easily produced.

[0044]

As described above, according to the method for treating a compound semiconductor of the present invention, a first layer having a single layer or multiple layers is used.
Accelerating and irradiating the compound semiconductor layer with particles containing an impurity element for controlling valence electrons, and stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer. And a step of performing heat treatment after stacking the second compound semiconductor layer, a low defect doping layer can be formed and an ohmic electrode with low contact resistance can be formed. .

According to the compound semiconductor processing method of the present invention, a step of accelerating and irradiating particles containing an impurity element for controlling valence electrons is applied to the first compound semiconductor layer composed of a single layer or multiple layers. And the first particle irradiated
Laminating a second compound semiconductor layer on the compound semiconductor layer, a step of heat treatment after the second compound semiconductor layer is laminated, and a predetermined part of the second compound semiconductor layer after the heat treatment. It becomes possible to easily form a Schottky junction or the like using the first compound semiconductor layer having a desired doping profile by including the step of removing.

[Brief description of drawings]

FIG. 1 is a conceptual process chart showing an example of a treatment procedure in a treatment method for a compound semiconductor according to the present invention.

FIG. 2 is a conceptual process diagram showing an example of a processing procedure in a method for processing another compound semiconductor according to the present invention.

FIG. 3 (a) Si in the InP layer immediately after Si ion implantation
The figure which shows the SIMS measurement result of a depth direction profile (b) The figure which shows the SIMS measurement result of the Si depth direction profile in the sample after heat processing

[Explanation of symbols]

11 First Compound Semiconductor Layer 12 Particles Containing Impurity Atoms 13 Impurity Atom Injected Region (Injection Layer) 14 Second Compound Semiconductor Layer 15 Doping Layer (15a High Concentration Doping Layer, 1
5b Implanted doping layer) 16 Ohmic electrode layer 17 Schottky electrode layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shigeo Yoshii             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Asami Yoshi Suzuki             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Hiroyuki Furuya             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5F102 FA03 GB01 GC01 GD01 GJ06                       GL04 GM04 GN04 GR04 GR07                       GR10 HC07 HC21

Claims (4)

[Claims] 1. A method for treating a compound semiconductor composed of a group II element and a group VI element, a group III element and a group V element, or a mixed crystal thereof, with respect to a first compound semiconductor layer composed of a single layer or multiple layers. Accelerating and irradiating particles containing an impurity element for controlling valence electrons; stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer; A method of treating a compound semiconductor, comprising a step of performing heat treatment after stacking the compound semiconductor layers. 2. A method for treating a compound semiconductor comprising a group II element and a group VI element, a group III element and a group V element, or a mixed crystal thereof, with respect to a first compound semiconductor layer composed of a single layer or multiple layers. Accelerating and irradiating particles containing an impurity element for controlling valence electrons; stacking a second compound semiconductor layer on the particle-irradiated first compound semiconductor layer; A method for treating a compound semiconductor, comprising: a step of performing heat treatment after stacking the compound semiconductor layers; and a step of removing a predetermined part of the second compound semiconductor layer after the heat treatment. 3. The group III element forming the compound semiconductor contains at least one selected from aluminum (Al), gallium (Ga), and indium (In). Method of treating compound semiconductor of. 4. The group V element constituting the compound semiconductor contains at least one selected from nitrogen (N), phosphorus (P), and arsenic (As). Method of treating compound semiconductor of.