JP2003078400A - Oscillation stop detector - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce power consumption by suppressing current consumption due to charging and discharging in an oscillation stop detection operation. SOLUTION: A charging transistor 20, a reverse discharging transistor 21, a reverse discharging reference transistor 22, a discharging reference transistor 23, a charging capacitance 27, and a discharging capacitance 2
8 and a discharge resistor 29, the discharge currents from the charge capacitors 27 and 47 are received by the discharge capacitors 28 and 48, respectively.
In the period synchronized with the clock signal 1, the charging capacitors 27 and 4
7, the current is basically prevented from flowing by charging the charging capacitors 27 and 47 in reverse.
As a result, current consumption due to charging and discharging in the oscillation stop detection operation is suppressed, and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation stop detection device for detecting an oscillation stop.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a configuration of a conventional oscillation stop detecting device for detecting oscillation stop, that is, stop of an input clock (fixed at H level or fixed at L level). In FIG. 3, reference numeral 1 is a clock signal (CLK) of a constant cycle supplied by oscillation. Reference numeral 2 is an inverter which receives the clock signal 1. Reference numeral 3 denotes a reverse phase signal (NCLK) of the clock signal 1, which is an output of the inverter 2. Reference numeral 4 is a charging N-channel transistor which is turned on / off by the reverse phase signal 3 of the clock signal. Reference numeral 5 is a discharge N-channel transistor which is turned on / off by the clock signal 1. Reference numeral 6 is a charging side node formed of the drain of the charging N-channel transistor 4. Reference numeral 7 is a discharge-side node formed of a channel on the side other than the charge-side node 6 of the discharging N-channel transistor 5. Reference numeral 8 is a charging capacitor provided between the charging side node 6 and the ground potential VSS. Reference numeral 9 is a discharge capacitor provided between the discharge side node 7 and the ground potential VSS. Reference numeral 10 is a discharge resistor provided between the discharge side node 7 and the ground potential VSS. Reference numeral 11 is an inverter having the discharge side node 7 as an input. Reference numeral 12 is an oscillation stop detection signal (Fstop) output from the inverter 11.

The operation of the oscillation stop detector of FIG. 3 is as follows. When the clock signal (CLK) 1 is "L" and the negative phase signal (NCLK) 3 of the clock signal is "H", the charging transistor 4 is turned on, the discharging transistor 5 is turned off, and the charging capacitor 8 is at the power supply potential. The discharging capacitor 9 is charged to VDD and discharged to the ground potential VSS through the discharging resistor 10.

Next, when the clock signal 1 is "H" and the negative phase signal 3 of the clock signal is "L", the charging transistor 4 is turned off, the discharging transistor 5 is turned on, and the charging capacitor 8 is discharged. The capacitor 9 is charged and discharged to the ground potential VSS via the discharge resistor 10.

In this series of charging / discharging operations, the discharging capacity 9
And the time constant of the discharge resistor 10 determines the potential of the discharge side node 7. If the time constants of the discharge capacitor 9 and the discharge resistor 10 are set such that the time until the potential of the discharge side node 7 becomes lower than the switching level of the inverter 11 becomes longer than the cycle of the clock signal 1, oscillation will occur. If the clock signal 1 continues to be supplied, the oscillation stop detection signal (F
Stop) 12 remains “L”.

Next, when the oscillation is stopped and the supply of the clock signal 1 is stopped, the discharge capacitor 9 is no longer charged, and the discharge side node 7 is discharged to a level lower than the switching level of the inverter 11. The oscillation stop detection signal (Fstop) 12 becomes "H", and it can be detected that the oscillation has stopped.

[0007]

However, in the above-mentioned conventional structure, since the time constants of the discharging capacitor 9 and the discharging resistor 10 are used, it is necessary to constantly discharge through the discharging resistor 10. Therefore, it is in the same state as the current is constantly flowing, and power consumption always occurs.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an oscillation stop detecting device capable of achieving low power consumption by suppressing current consumption due to charge / discharge in the oscillation stop detecting operation.

[0009]

In order to solve the above problems, the present invention uses the time constants of the discharge capacity and the discharge resistance,
A discharge current from the charging capacity is received by the discharging capacity, and by reversely discharging the charging capacity and charging the charging capacity in a cycle synchronized with the clock signal, a configuration in which no current basically flows is realized, A circuit capable of reducing current consumption is provided.

Specifically, the oscillation stoppage detection device according to claim 1 of the present invention is such that an inverter for receiving a clock signal as an input and for generating a reverse phase signal of the clock signal, and a first charging device for inputting the clock signal. The discharge circuit includes a second charging / discharging circuit that receives an inverted signal of the clock signal, and an oscillation stop determination circuit that detects the oscillation stop based on the output potentials of the first and second charging / discharging circuits.

The first charging / discharging circuit has one end connected to a power source and one end connected to a first one-conductivity-type charging transistor that is operated by a clock signal and the other end of the first one-conductivity-type charging transistor. A first charging capacitor having the other end connected to the ground terminal, and a first one conductivity type reverse discharging transistor having one end connected to the other end of the first one conductivity type charging transistor and operated by a clock signal A first discharge resistor connected between one end and the other end of the first reverse discharge transistor, and a first discharge whose one end is connected to the other end of the first one conductivity type reverse discharge transistor. Of the first discharging capacitance, a first one-conductivity-type reverse discharging reference transistor that has one end connected to the power supply and the other end connected to the first discharging capacitance, and that operates with a clock signal. One end is connected to the other end and the other end is connected to the ground terminal. It comprises a first opposite conductivity type discharge reference transistor operating in click signal.

The second charging / discharging circuit has a second one-conductivity-type charging transistor which is connected to a power source and which operates at an opposite phase signal of the clock signal, and another second-conductivity-type charging transistor which is connected to the other end. A second charging capacitor having one end connected to the ground terminal and the other end connected to a ground terminal, and a second charging capacitor having one end connected to the other end of the second one-conductivity-type charging transistor and operated by a reverse phase signal of the clock signal. A first conductivity type reverse discharge transistor, and a second
A second discharging resistor connected between one end and the other end of the reverse discharging transistor of, and a second discharging capacitor having one end connected to the other end of the second one-conductivity-type reverse discharging transistor
A second one-conductivity-type reverse discharge reference transistor that has one end connected to a power supply and the other end connected to the other end of the second discharge capacitor and that operates with a reverse-phase signal of the clock signal; It comprises a second reverse conductivity type discharge reference transistor which has one end connected to the other end and the other end connected to the ground terminal and which operates with a reverse phase signal of the clock signal.

The oscillation stop determination circuit receives the first potential appearing at one end of the first charging capacitor and the second potential appearing at one end of the second charging capacitor as inputs, and outputs the first and second potentials. Determine the level.

According to this structure, the discharge currents from the first and second charging capacitors are respectively received by the first and second discharging capacitors, and the first and second discharging capacitors are synchronized with the clock signal. By reversely discharging the charging capacity and charging the first and second charging capacities respectively, basically no current flows. Therefore, the consumption current due to charging / discharging in the oscillation stop detection operation is suppressed. As a result, low consumption can be achieved.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An oscillation stop detecting device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an oscillation stop detection device according to an embodiment of the present invention. In FIG.
Reference numeral 1 is a clock signal (CLK) having a constant cycle supplied by oscillation. Reference numeral 2 is an inverter which receives the clock signal 1. 3 is a reverse phase signal of the clock signal 1 (NC
LK) is the output of the inverter 2.

Reference numeral 20 denotes a charging P-channel (one conductivity type) transistor which is turned on / off by the clock signal 1, the source of which is connected to the power supply potential VDD and the gate of which is the clock signal 1.
Is input, and the drain serves as the charging-side node 24. Reference numeral 27 is a charging capacitor provided between the charging side node 24 and the ground potential VSS.

Reference numeral 21 is a reverse discharge P-channel transistor which is turned on / off by the clock signal 1, and its drain is connected to the drain of the charging P-channel transistor 20,
The clock signal 1 is input to the gate, and the source is the discharge side node 25. Reference numeral 29 is a discharge resistor provided between the charging side node 24 and the discharging side node 25.

Reference numeral 22 is a reverse discharge reference P-channel transistor which is turned on / off by the clock signal 1, the source is connected to the power supply potential VDD, the gate is supplied with the clock signal 1, and the drain is connected to the discharge / reverse discharge reference node 26. Has become.

Reference numeral 23 is a discharge reference N-channel (reverse conductivity type) transistor which is turned on / off by the clock signal 1, the drain serves as the discharge / reverse discharge reference node 26, the clock signal 1 is applied to the gate, and the source is grounded. It is connected to VSS.

Reference numeral 28 denotes a discharge capacity provided between the discharge side node 25 and the discharge / reverse discharge reference node 26.

Reference numeral 30 is a charging P-channel transistor 2
0, reverse discharge P-channel transistor 21, reverse discharge reference P-channel transistor 22, discharge reference N-channel transistor 23, charging capacitor 27, discharging capacitor 28,
And a discharge resistor 29.

Reference numeral 40 denotes a charging P-channel transistor which is turned on / off by the negative phase signal 3 of the clock signal, the source is connected to the power supply potential VDD, the negative phase signal 3 of the clock signal is input to the gate, and the drain is the charging side. It is the node 44. 47 is the charging side node 44 and the ground potential VSS
It is a charging capacity provided between them.

Reference numeral 41 denotes a reverse discharge P-channel transistor which is turned on / off by the clock signal reverse-phase signal 3. The drain is connected to the drain of the charging P-channel transistor 40, and the gate receives the reverse-phase signal 3 of the clock signal. The source is the discharge side node 45. Reference numeral 49 is a discharge resistor provided between the charge side node 44 and the discharge side node 45.

Reference numeral 42 denotes a reverse discharge reference P-channel transistor which is turned on / off by the reverse phase signal 3 of the clock signal,
The source is connected to the power supply potential VDD, the gate is supplied with the reverse phase signal 3 of the clock signal, and the drain is the discharge / reverse discharge reference node 46.

Reference numeral 43 is a discharge reference N-channel transistor which is turned on / off by the negative phase signal 3 of the clock signal. Is connected to the ground potential VSS.

Reference numeral 48 denotes a discharge capacity provided between the discharge side node 45 and the discharge / reverse discharge reference node 46.

Numeral 50 is a charging P-channel transistor 4
0, reverse discharge P-channel transistor 41, reverse discharge reference P-channel transistor 42, discharge reference N-channel transistor 43, charging capacitor 47, discharging capacitor 48,
And a discharge resistor 49.

34 is a charging side node 24 and a charging side node 4
It is a 2-input NAND circuit that receives the potential of 4 as an input, and corresponds to the oscillation stop determination circuit in the claims. 35
Is an output of the 2-input NAND circuit 34 and is an oscillation stop detection signal (Fstop).

Next, the oscillation stop detection operation of the present oscillation stop detection device will be described with reference to FIG.

First, in the charging / discharging circuit 30, when the clock signal 1 is "H", the charging transistor 20, the reverse discharging transistor 21, and the reverse discharging reference transistor 22.
Turns off and the discharge reference transistor 23 turns on. Then, the discharge / reverse discharge reference node 26 becomes the VSS potential, and the discharge side node 25, which had the same potential as the discharge / reverse discharge reference node 26 in the previous stage, also becomes the VSS potential (t1).
In this state, the charging capacitor 27 is discharged to the discharging capacitor 28 through the discharging resistor 29. As a result, the charging node 24
Potential gradually decreases from the VDD potential, and the potential of the discharge side node 25 gradually increases.

Next, when the clock signal 1 becomes "L", the charging transistor 20 and the reverse discharging transistor 2
1. The reverse discharge reference transistor 22 is turned on and the discharge reference transistor 23 is turned off. Then, the discharge / reverse discharge reference node 26 becomes the VDD potential, and the discharge side node 25 becomes the potential obtained by adding the VDD potential to the potential difference of the discharging capacitance 28 (t2). As a result, the charging capacitor 2 is discharged from the discharging capacitor 28 via the reverse discharging transistor 21.
The battery is reversely discharged to 7, and the charging capacity 27 is charged. At this time,
Since the discharging / reverse discharging reference node 26 is at the VDD potential, the discharging side node 25 is discharged to the charging side node 24 until the discharging side node 25 reaches the VDD potential. At this point, the potential difference between the discharge side node 25 and the discharge / reverse discharge reference node 26 disappears. This reverse discharge does not exceed the VDD potential because the reverse discharge of the discharge from the charging capacitor 27 to the discharging capacitor 28 is performed. Further, even when charge loss such as leak current occurs, the charge transistor 20 compensates for the loss. As a result, the potential of the charging side node 24 and the discharging side node 25 become VDD potential.

In this series of charging / discharging operations, the charging capacity 2
The potential of the charge-side node 24 is determined by the capacity ratio of 7 to the discharge capacitance 28 and the time constant of the discharge resistor 29. If the capacitance ratio and the time constant are set to be longer than the switching level of the 2-input NAND circuit 34 longer than the cycle of the clock signal 1, oscillation continues and the clock signal 1 is supplied. Continuing, the oscillation stop detection signal (Fstop) 35 remains "L".

Next, when the oscillation is stopped and the supply of the clock signal 1 is stopped at "H", when the potential of the charging side node 24 is discharged to a level lower than the switching level of the 2-input NAND circuit 34, the oscillation is stopped. Detection signal (Fs
top) 35 becomes "H", and it can be detected that the oscillation has stopped (t3).

However, when the supply of the clock signal 1 is stopped at "L", the charging side node 24 is fixed to the VDD potential. However, with the same configuration as the charging / discharging circuit 30, a negative phase signal (NCLK) of the clock signal 1 is generated. ) 3 charging / discharging circuit 30
When the potential of the charge-side node 44 of the charge / discharge circuit 50 operating in the same manner as in (1) is discharged to a level lower than the switching level of the 2-input NAND circuit 34, the oscillation stop detection signal (Fstop) 35 becomes "H" and oscillation is stopped. You can detect what you have done.

According to the oscillation stoppage detection device of this embodiment, the discharging capacitors 28 and 48 receive the discharging currents from the charging capacitors 27 and 47, respectively, and the charging capacitor 27 is synchronized with the clock signal 1. , 47, and the second charging capacitors 27, 47 are respectively discharged, so that basically no current flows. Therefore, by suppressing the current consumption due to charging / discharging in the oscillation stop detection operation. It is possible to reduce the consumption.

[0037]

According to the oscillation stoppage detection device of the present invention, the discharge currents from the first and second charging capacitors are received by the first and second discharging capacitors, respectively, at a cycle synchronized with the clock signal. , The first and second charging capacities are reversely discharged and the first and second charging capacities are respectively charged, so that basically no current flows, so that the charging in the oscillation stop detection operation is performed. By suppressing the current consumption due to discharge, low power consumption can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an oscillation stop detection device according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the oscillation stop detection device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional oscillation stop detection device.

[Explanation of symbols]

1 clock signal 2 inverter 3 Opposite phase signal of clock signal 4 charging transistor 5 Discharge transistor 6 charging node 7 Discharge side node 8 charging capacity 9 Discharge capacity 10 discharge resistance 11 inverter 12 Oscillation stop detection signal 20 Charging transistor 21 Reverse discharge transistor 22 Reverse discharge reference transistor 23 Discharge reference transistor 24 Charging node 25 Discharge side node 26 discharge / reverse discharge reference node 27 Charging capacity 28 Discharge capacity 29 Discharge resistance 30 charge / discharge circuit 34 2-input NAND circuit 35 Oscillation stop detection signal 40 Charging transistor 41 Reverse discharge transistor 42 Reverse discharge reference transistor 43 Discharge reference transistor 44 Charging node 45 Discharge side node 46 discharge / reverse discharge reference node 47 Charging capacity 48 discharge capacity 49 discharge resistance 50 charge / discharge circuit

Claims (2)

[Claims] 1. An inverter that receives a clock signal and generates a reverse phase signal of the clock signal, and a first end that is connected to a power supply and that operates with the clock signal.
One conductivity type charging transistor, a first charging capacitor having one end connected to the other end of the first one conductivity type charging transistor, and the other end connected to a ground terminal; A first one-conductivity-type reverse discharging transistor, one end of which is connected to the other end of the conductivity-type charging transistor and which operates with the clock signal, and a first one of which is connected between one end and the other end of the first reverse-discharging transistor. 1 discharge resistor, a first discharge capacitor whose one end is connected to the other end of the first one conductivity type reverse discharge transistor, and one of the first discharge capacitor whose one end is connected to the power source. A first one-conductivity-type reverse discharge reference transistor having the other end connected to the other end and operating with the clock signal, and one end connected to the other end of the first discharge capacitor and the other end connected to the ground terminal A first reverse conductivity type that operates with the clock signal A first charging and discharging circuit comprising a conductive reference transistor, a second one conductivity type charging transistor having one end to the power supply is operated in the reverse-phase signal of the connected the clock signal, the second
A second charging capacitor whose one end is connected to the other end of the one conductivity type charging transistor and whose other end is connected to the ground terminal;
A second one-conductivity-type reverse discharging transistor, one end of which is connected to the other end of the second one-conductivity-type charging transistor and which operates with a reverse phase signal of the clock signal, and one end of the second reverse-discharging transistor. And a second discharging resistor connected between the other end, a second discharging capacitor having one end connected to the other end of the second one conductivity type reverse discharging transistor, and one end connected to the power supply. And a second end connected to the other end of the second discharge capacitor and operating with a reverse phase signal of the clock signal.
One-conductivity-type reverse discharge reference transistor and a second reverse conductive transistor, one end of which is connected to the other end of the second discharge capacitor and the other end of which is connected to the ground terminal and which operates with a reverse phase signal of the clock signal. A second charge / discharge circuit including a type discharge reference transistor, a first potential appearing at one end of the first charging capacitor and a second potential appearing at one end of the second charging capacitor are input. An oscillation stop detection device including an oscillation stop determination circuit that determines the levels of the first and second potentials. 2. The oscillation stop detection device according to claim 1, wherein the oscillation stop determination circuit comprises a 2-input NAND circuit.