JP2003069419A - Counter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a counter circuit that can revise a count for carrying with a simple configuration and count a plurality of kinds of cardinal numbers. SOLUTION: A counter 10 comprises carrying circuits 141 to 14j-1 including JKFF circuits 121 to 12k and a 2-input AND circuit. A signal '1' is given to input terminals Jx , Kx of each JKFF circuit 12x and a clock signal CLK is given to a clock input terminal CP1 of the JKFF circuit 121 . An output terminal Qx of the JKFF circuit 12x is connected to a clock input terminal CPx+1 of the JKFF circuit 12x+1 of the next stage. The output value of each output terminal Qx is each bit signal qx of the count. When a control signal is at '1' and the count is '10' in decimal notation, since the counter 10 outputs a clear signal, the signal is carried over and the counter 10 acts like a decimal counter. When the control signal is at '0', no carry over is conducted and the counter 10 acts like a hexadecimal counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit, and more particularly to a counter circuit that counts pulse signals.

[0002]

2. Description of the Related Art Conventionally, a counter circuit that counts the number of pulses of a pulse signal included in an LSI or the like is usually formed by using a plurality of flip-flop (FF) circuits, and is a FF circuit required to represent one digit. It operates as a 2 ^N- ary counter according to the number of stages N (N is an integer). For example, in the case of a 16 (2 ⁴ ) base number counter, it is configured such that four stages of FF circuits are cascaded for each digit, and when counting j (j is an integer) digits, 4 × j FFs are used. The circuit is cascade-connected.

On the other hand, when the radix is not 2 ^N like a decimal number counter, a carry circuit is further provided in the four-stage FF circuit per digit, and a digit is added every time the tenth pulse is input. The carry circuit carried the carry to the leading FF circuit of the counter at the next stage (next digit).

FIG. 8 shows such a decimal counter.
As shown in FIG. 8, the counter circuit 100 has k (= 4 ×
j) JK flip-flop (JKFF) circuits 12 ₁
.About.12 _k and carry circuits 14 _{1 to} 14 _j-1 . The carry circuit 14 is composed of a two-input AND (logical product) circuit.

A predetermined voltage Vcc (high level: "1") is input to the input terminal J _x and the input terminal K _x (x: 1 to k) of each JKFF circuit 12 _x , and the JKFF circuit 12 ₁ receives the clock input. The clock signal CLK is input to the terminal CP ₁ . The output terminal Q _x of the JKFF circuit 12 _x is the JKF of the next stage.
It is connected to a clock input terminal CP _{x + 1} as a pulse input terminal of the F circuit 12 _{x + 1} . Then, the output value of each output terminal Q _x becomes each bit signal q _x of the count value. That is, the count value is q ₁ with the least significant bit LSB (Least
Significant Bit), q _k is the most significant bit MSB (Most
Significant Bit) as a binary number q _k q _k-1 ... q ₂ q ₁
It is represented by.

JKFF circuit 12 _{4m + 1 to} 12 _{4m + 4} (m =
The output terminal of the carry circuit 14 _{m + 1} is connected to the clear terminal C as a clear signal input terminal of 0, 1, 2, ... J-1). Output terminal Q of JKFF circuit 12 _{4m + 2
4m + 2} is connected to one input terminal of the carry circuit 14 m _{+ 1,} the output terminal Q _{4m + 4} of JKFF circuit 12 _{4m + 4} is
It is connected to the other input terminal of the carry circuit 14 _{m + 1} .

The JKFF circuit shown in FIG. 8 has a clock input terminal CP when the input terminals J and K are both "1".
At the falling edge of the clock signal CLK input to the output terminal Q
Is an inverted circuit, and the output of the output terminal W is cleared (becomes "0") at the falling edge of the clear signal input to the clear terminal C.

Therefore, at the falling edge of the clock signal CLK, J
Output signal is inverted from the output terminal to Q ₁ KFF circuit 12 _1, the output at the falling edge of the output signal from the output terminal Q ₁ terminal Q ₂
The output signal from is inverted, and the same operation is repeated thereafter, so that the number of pulses is incremented. Then, when the tenth pulse is input and the count value becomes “10” in decimal, that is, “101” in binary.
If it becomes 0 ", the output signal of the output terminal Q _2, Q ₄ become both" 1 ", the output of the carry circuit 14 ₁ is" 1 "since it from the output terminal Q ₁ to Q ₄ is the output signal reset with becomes "0", the output terminal Q ₅ of JKFF circuit 12 ₅
The output signal of becomes "1" and is carried to the next digit.

[0009]

However, in the above counter circuit, the radix is fixed because the count value for carrying a carry cannot be changed.
If another radix is to be counted, an extra counter has to be provided, which is inflexible. There are also construction of a counter for switching the counter base to provide a power switch circuit is not a 2 ^N counters and radix 2 ^N, but increases the circuit scale further switch the counter each other radix is not 2 ^N circuit configuration Becomes complicated.

The present invention has been made in view of the above facts, and is capable of changing the count value for carrying a carry with a simple structure and capable of counting a plurality of types of radix. The purpose is to provide.

[0011]

In order to achieve the above object, the present invention according to claim 1 provides a pulse input terminal to which a pulse train is input, and an inverted output signal of the current output signal by inputting the pulse. A plurality of sequential circuits including an output end for outputting as a bit signal of the pulse count value and a clear signal input end to which a clear signal for clearing the output signal from the output end is input, A counter in which the output end of the sequential circuit is connected to the pulse input end of the next sequential circuit, and when the count value reaches a predetermined value, the clear signal is output based on the input control signal. And a carry means for carrying out.

The counter includes a plurality of sequential circuits. This sequential circuit includes a pulse input end, an output end, and a clear signal input end. When a pulse is input to the input end, an inverted output signal of the current output signal is output from the output end. This inverted output signal becomes a bit signal of the pulse count value. The output signal from the output end is cleared by inputting the clear signal to the clear signal input end. In such a plurality of sequential circuits, the output terminal of the sequential circuit of the previous stage is connected to the pulse input terminal of the sequential circuit of the next stage. As a result, each time a pulse is input, it is counted up, and the pulse count value can be obtained by the bit signal output from the output terminal of each sequential circuit. For example,
When this counter is composed of N sequential circuits, the counter functions as a 2 ^N base counter having a base of 2 ^N.

The carry means has a function of outputting a clear signal based on the input control signal when the count value reaches a predetermined value. For example, the predetermined value is 2
^A value M other than ^N is set, and a clear signal is output when the count value reaches a predetermined value M. As a result, the output signal of each sequential circuit is cleared, so that it functions as an M-ary counter whose base is M. Then, whether or not the clear signal is output is determined by the input control signal. That is, the 2 ^N- ary counter and the M-ary counter are switched by the control signal. This makes it possible to easily switch counters having different radixes by the control signal.

The sequential circuit has, as described in claim 2,
It can be a JK flip-flop circuit. In this case, a high level is input to the J input terminal and the K input terminal. This causes the output signal from the output end to be inverted every time a pulse is input to the pulse input end.

Further, as described in claim 3, the carry means is an AND circuit having the bit signal and the control signal corresponding to the predetermined value as input signals and the clear signal as an output signal. You can This makes it possible to easily switch counters having different radix with a simple configuration.

According to a fourth aspect of the present invention, the carry means includes a plurality of AND circuits each having a bit signal corresponding to the different predetermined value as an input signal, and the AND circuit based on the control signal. A selection unit that selects any output signal as the clear signal may be included.

This makes it possible to easily switch counters of different radix according to the control signal. Therefore,
Radix and switching of the 2 ^N between counter, radix can be easily performed to switch between the counter counter and radix 2 ^N is not 2 ^N, also possible that more than two groups switch between different counters Becomes

Further, as described in claim 5, a plurality of digits can be counted by providing a plurality of the counters and the carry means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a counter circuit 10 to which the present invention is applied. The same parts as those of the counter circuit 100 shown in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

The counter circuit 10 includes carry circuits 16 ₁ ...
Since the counter circuit 10 is the same as the counter circuit 10 shown in FIG. 8 except that 16 _j-1 is a 3-input AND circuit, description of the circuit configuration will be omitted.

[0021] The first input terminal of the carry circuit 16 ₁ ~ 16 _j-1, the output terminal Q _{4m + 2} JKFF circuit 12 _{4m + 2} is the second input terminal, JKFF circuit 12 _{4m + 4} output terminals Q
_{4m + 4} is connected. Further, the control signal CTL from the outside is input to the third input terminal. Therefore, when the control signal CTL is at high level, that is, "1", the same operation as the counter circuit 100 shown in FIG. 8 is performed, and when the control signal CTL is at low level, that is, "0", 16 (= 2 ⁴ ) Operates as a base counter.

Next, the operation of this embodiment will be described.

FIG. 2 shows a timing chart when the control signal CTL is "1", and FIG. 3 shows a timing chart when the control signal CTL is "0".
First, the case where the control signal is "1" will be described.

The clock signal CLK is the JKFF circuit 12 ₁
2 is input to the clock input terminal CP ₁ of the JKFF circuit 1 at the falling edge of the clock signal CLK, as shown in FIG.
2 ₁ of the output signal from the output terminal Q ₁ is inverted, the output terminal Q
_{At the fall} of the output signal from ₁ , the output signal from the output terminal Q ₂ is inverted, and the same operation is repeated thereafter, so that the number of pulses is sequentially counted up.

For example, t _A when the sixth pulse is input
At the time of, the output terminal Q
_Since the output signal from ₁ , that is, the bit signal q ₁ becomes “0” and falls, the output signal from the output terminal Q ₂ , that is, the bit signal q ₂ becomes “1”. The bit signal q ₃ remains “1” and the bit signal q ₄ remains “0”. Therefore, the count value is "6" in decimal.

When the tenth pulse falls at time t _B , the bit signal q ₁ becomes "0" and
The bit signal q ₂ becomes “1”. At this time, since the bit signal q ₄ is also “1”, the clear signal CLR output from the carry circuit 16 ₁ becomes “1” and the bit signals q ₁ to
The output signal from q ₄ is reset to “0”. As a result, the bit signal q ₄ falls, and the bit signal q ₅ becomes “1”. That is, carry is carried. In addition,
The clear signal CLR instantly falls because the bit signals q ₂ and q ₄ fall.

In this way, when the control signal CTL is "1", the counter circuit 10 functions as a decimal counter.

On the other hand, when the control signal is "0",
As shown in, the clear signal CL from the carry circuit 16 ₁
Since R remains “0”, no carry is carried out even if the 10th pulse is inputted, and the bit signal q ₄ falls at the time point t _C when the 16th pulse is inputted and the bit signal q ₄ falls. q ₅ becomes “1”, that is, carry is carried.

As described above, when the control signal CTL is "0", the counter circuit 10 functions as a hexadecimal counter.

According to the present embodiment, the control signal CTL is set to "1" or "0" to enable or disable the carry, so that the radix is 2 ^N without increasing the circuit scale.
A non-decimal counter or a hexadecimal counter with a radix of 2 ^N can easily be switched.

In the present embodiment, the case where the decimal counter or the hexadecimal counter is switched has been described, but the present invention is not limited to this and the present invention can be applied to the case where the counter of another radix is switched. Further, although the case where the JK flip-flop circuit is used as the flip-flop circuit and the AND circuit is used as the carry circuit has been described in the present embodiment, the present invention is not limited to this.

[Second Embodiment] Next, a second embodiment of the present invention will be described. In the second embodiment, a counter circuit capable of switching counters whose bases are not both 2 ^N base numbers will be described. The same parts as those of the counter circuit 10 described in the first embodiment are designated by the same reference numerals,
Detailed description thereof will be omitted.

FIG. 4 shows a circuit diagram of the counter circuit 20 according to the second embodiment. As shown in FIG. 4, the counter circuit 20 includes a switching carry circuit 22. As shown in FIG. 5, the switch carry circuit 22 is composed of two-input AND circuits 24 and 26 and a selector 28.

One input terminal of the AND circuit 24 has a JK
FF circuit 12 _first output and terminal Q ₁ is connected, the other input terminal, an output terminal Q ₃ of the JKFF circuit 12 ₃ are connected.

One input terminal of the AND circuit 26 has JK
FF circuit 12 and _second output terminal Q ₂ is connected, the other input terminal, the output terminal Q ₄ of the JKFF circuit 12 ₄ is connected.

The output terminal of the AND circuit 24 is the selector 2
8 is connected to the first input terminal of the AND circuit 26, and the output terminal of the AND circuit 26 is connected to the second input terminal of the selector 28. The control signal CTL is input to the third input terminal of the selector 28. The output terminal of the selector 28 is J
It is connected to the clear terminals C of the KFF circuits 12 _{1 to} 12 ₄ and also to the input terminal of the inverter 30. The output terminal of the inverter 30 is connected to the clock input terminal CP ₅ of the JKFF circuit 12 ₅ .

In the selector 28, the control signal CTL is "0".
In the case of, the output of the AND circuit 24 is selected as the output signal, and when the control signal CTL is "1", the output of the AND circuit 26 is selected as the output signal. The output signal from the selector 28 is output as a clear signal CLR to the clear terminals C of the JKFF circuits 12 _{1 to} 12 ₄ . The rest of the configuration is the same as that of the counter circuit 10 shown in FIG. 1, so description of the circuit configuration will be omitted.

Next, the operation of this embodiment will be described.

FIG. 6 shows a timing chart when the control signal CTL is "0", and FIG. 7 shows a timing chart when the control signal CTL is "1".
First, the case where the control signal is “0” will be described.

The clock signal CLK is the JKFF circuit 12 ₁
When input to the clock input terminal CP ₁ of the JKFF circuit 1 at the falling edge of the clock signal CLK, as shown in FIG.
2 ₁ of the output signal from the output terminal Q ₁ is inverted, the output terminal Q
_{At the fall} of the output signal from ₁ , the output signal from the output terminal Q ₂ is inverted, and the same operation is repeated thereafter, so that the number of pulses is sequentially counted up.

For example, t _D when the second pulse is input
At the time of, the output terminal Q
_Since the output signal from ₁ , that is, the bit signal q ₁ becomes “0” and falls, the output signal from the output terminal Q ₂ , that is, the bit signal q ₂ becomes “1”. The bit signal q ₃ remains “0” and the bit signal q ₄ remains “0”. Therefore, the count value is "2" in decimal.

Then, when the fifth pulse falls at time t _E , the bit signal q ₁ becomes "1". At this time, since the bit signal q ₃ is also “1”, the carry circuit 2
The output of the AND circuit 24 of 2 ₁ becomes "1". Further, since the control signal CTL is “0”, the output of the AND circuit 24 is selected as the clear signal CLR, and the JKFF circuit 1
“1” for the clear terminals C of 2 _{1 to} 12 ₄ and the inverter 30
Is output. As a result, the output signals from the bit signals q _{1 to} q ₄ are reset to “0” and the inverter 3
Since the output signal CAR 0 becomes "0" from "1" bit signal q ₅ becomes "1". That is, carry is carried.
The clear signal CLR instantly falls because the bit signals q ₁ and q ₃ fall.

As described above, when the control signal CTL is "0", the counter circuit 10 functions as a quinary counter.

On the other hand, when the control signal is "1", as shown in FIG.
As shown in, when the tenth pulse falls at time t _F , the bit signal q ₁ becomes “0” and the bit signal q ₂ becomes “1”. At this time, since the bit signal q ₄ is also “1”, the AND circuit 26 of the carry circuit 22 ₁
Output becomes "1". Further, the control signal CTL is "1".
Therefore, the output of the AND circuit 26 is the clear signal CLR.
, And “1” is output to the clear terminals C of the JKFF circuits 12 _{1 to} 12 ₄ and the inverter 30. Thus, the output signal from the bit signals q ₁ to q ₄ is reset is "0", the output signal CAR of the inverter 30 becomes "0" from "1" bit signal q ₅ is "1"
become. That is, carry is carried. The clear signal CL
R falls instantly because the bit signals q ₂ and q ₄ fall.

In this way, when the control signal CTL is "1", the counter circuit 10 functions as a decimal counter similar to that described in the first embodiment.

In this embodiment, the output signal of the final stage JKFF circuit of the preceding counter is not input to the clock input terminal CP of the initial stage JKFF circuit of the next stage (next digit) counter. It is configured to receive the inverted output signal of the circuit 22. As a result, as described above, a quinary counter (necessary bit number 3 bits) and a decimal counter (necessary bit number 4 bits) having different required bit numbers are provided.
And can be switched, and a highly flexible counter circuit can be obtained. Therefore, counting of all radix can be realized by one counter circuit.
It is possible to reduce the size and cost of the entire circuit.

In this embodiment, the case of switching the quinary counter or the decimal counter has been described.
The present invention is not limited to this, and the present invention can be applied to the case of switching between counters having a radix other than 2 ^N. In addition, in the present embodiment, a JK is used as the flip-flop circuit.
A flip-flop circuit is used as a switching carry circuit.
Although the case where the ND circuit and the selector are used has been described, the present invention is not limited to this.

[0048]

As described above, according to the present invention,
It is possible to change the count value that carries a carry with a simple configuration, and it is possible to count multiple types of radix.
Has the effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a counter circuit according to a first embodiment.

FIG. 2 is a timing chart showing each signal of the counter circuit according to the first embodiment.

FIG. 3 is a timing chart showing each signal of the counter circuit according to the first embodiment.

FIG. 4 is a circuit diagram of a counter circuit according to a second embodiment.

FIG. 5 is a circuit diagram of a switch carry circuit.

FIG. 6 is a timing chart showing each signal of the counter circuit according to the second embodiment.

FIG. 7 is a timing chart showing each signal of the counter circuit according to the second embodiment.

FIG. 8 is a circuit diagram of a conventional counter circuit.

[Explanation of symbols]

10, 20, 100 Counter circuit 12 _x JKFF circuit (sequential circuit) 14, 16 Carry circuit (carrying means) 22 Switching carry circuit (carrying means) 24, 26 AND circuit 28 Selector (selecting means) 30 Inverter

Claims (5)

[Claims] 1. A pulse input end to which a pulse train is input,
A clear signal to which an inverted output signal of the current output signal is output as a bit signal of the count value of the pulse when a pulse is input, and a clear signal for clearing the output signal from the output end is input. A plurality of sequential circuits including an input end, a counter in which the output end of the sequential circuit of the preceding stage is connected to the pulse input end of the sequential circuit of the next stage, and the count value reaches a predetermined value And a carry means for outputting the clear signal based on the input control signal. 2. The counter circuit according to claim 1, wherein the sequential circuit is a JK flip-flop circuit, and a high level is input to the J input terminal and the K input terminal. 3. The carry circuit is an AND circuit that uses the bit signal and the control signal corresponding to the predetermined value as input signals and the clear signal as an output signal. The described counter circuit. 4. The carry means includes a plurality of ANDs, each of which has a bit signal corresponding to a different predetermined value as an input signal.
3. The counter circuit according to claim 1, further comprising a circuit and a selection unit that selects one of the output signals of the AND circuit as the clear signal based on the control signal. 5. The counter circuit according to claim 1, further comprising a plurality of the counters and the carry means.