JP2003069021A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a highly reliable protection element built-in type semiconductor device in which protection elements made of polycrystalline silicon are integrated. A drift region 2 disposed above a drain region 3; a plurality of base regions 4 and an electric field relaxation region 14 disposed above the drift region 2; a source region 5 formed above the base region; an electric field relaxation Thin field insulating film 18 formed on the upper part of the region; polycrystalline silicon film 13 formed on the upper part of the thin field insulating film 18; interlayer insulating film 12 formed on the upper part of the polycrystalline silicon film 13; interlayer insulating film 12 A plurality of fine via holes C ₃₁ ,..., C ₃₅ through which the polycrystalline silicon film is exposed;
And bonding pads 7 connected to the polycrystalline silicon film 13 through fine via holes C ₃₁ ,..., C ₃₅ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a power semiconductor device in which a protective element made of polycrystalline silicon is integrated on the surface of a main element.

[0002]

2. Description of the Related Art FIG. 7 shows a structure of a MOSFET as an example of an insulated gate field effect transistor (IGFET) in which a conventional protection element is integrated. In the MOSFET as the main element shown in FIG. 7, the n-type drift region 2 is formed on the n ⁺ -type drain region 3, and the drift region 2
A p-type base region (body region) 4 is formed thereon. Then, an n ⁺ type source region 5 is formed on the base region 4. This MOSFET (main element)
Is further provided with a protective diode (protective element) made of polycrystalline silicon (polysilicon) through a thin field insulating film 18 having the same thickness as the gate insulating film 11 on the surface.
Have been integrated. This protection element (protection diode)
Are connected between the source electrode 8 and the gate electrode 6 of the main element (MOSFET). The interlayer insulating film 12 covering the upper surface of the polycrystalline silicon film 13 is provided with two openings, and the bonding pad 7 made of, for example, aluminum is provided through the first opening 28 shown on the right side in FIG. Is electrically connected to one end side of. A source electrode 8 made of, for example, aluminum is connected to the other end side of the polycrystalline silicon film 13 through a second opening (via hole) 21 shown in the center of FIG. P-type and n-type impurities are selectively introduced into the polycrystalline silicon film 13 to form a pn junction diode. The bonding pad 7 is connected to the gate electrode 6 of the MOSFET at the back of the paper.

[0003]

In the IGFET in which the protective element as described above is integrated on the surface, the first interlayer insulating film 12 covering the polycrystalline silicon film 13 is formed by the well-known photolithography technique. An opening 28 and a second opening 21 are formed, and the bonding pad 7 and the source electrode 8 are electrically connected to both ends of the polycrystalline silicon film 13 through the openings 28 and 21, respectively. However, in the first opening 28 having a relatively large opening area, the polycrystalline silicon formed on the lower side of the interlayer insulating film 12 is subjected to an etching process for selectively removing a part of the interlayer insulating film 12. Part of the film 13 is also etched at the same time,
The thickness of the polycrystalline silicon film 13 may be reduced.

A wire (thin lead wire) 23 is bonded to a part of the bonding pad 7. When the polycrystalline silicon film 13 is formed thin as described above, the polycrystalline silicon film 13 cannot absorb the pressure due to the wire bonding well, and a strong pressure is applied to the field insulating film 18 below the polycrystalline silicon film 13. Sometimes. As a result, a crack is generated in the field insulating film 18, and the p-type electric field relaxation region 14 and the bonding pad 7 of the semiconductor substrate.
There is a case where the electric field is electrically short-circuited with the electric field via the polycrystalline silicon film 13.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is a protection element built-in type in which a protection element composed of a highly reliable polycrystalline silicon film is integrated on the surface. To provide the semiconductor device.

[0006]

In order to achieve the above-mentioned object, the first feature of the present invention is to provide a main component having at least a first main electrode region, a second main electrode region and an electric field relaxation region. A semiconductor substrate constituting the element; (b) a field insulating film having a thickness of 30 to 150 nm provided on the electric field relaxation region; and (c) a polycrystal forming a protective element for the main element in contact with the upper portion of the field insulating film. Silicon film; (d) interlayer insulating film in contact with the upper part of the polycrystalline silicon film; (e) through the interlayer insulating film to expose the polycrystalline silicon film through a plurality of fine via holes arranged in a matrix, A gist is a semiconductor device having a bonding pad connected to polycrystalline silicon. The semiconductor substrate according to the first aspect of the present invention is a first main electrode region of a first conductivity type or a second conductivity type, and a first main electrode region disposed above the first main electrode region.
A conductivity type drift region, a second conductivity type electric field relaxation region arranged above the drift region, a plurality of second conductivity type base regions, and a first conductivity type second main electrode arranged above the base region. A region, a gate insulating film formed on a part of each of the plurality of base regions, and a gate electrode formed on the gate insulating film. In the semiconductor device according to the first feature, "first conductivity type" and "second conductivity type"
Have opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. Here, as the semiconductor device according to the first feature of the present invention, MOSFE
T, MOS static induction transistor (SIT), MISF
Insulated gate type semiconductor devices such as ET, MISSIT, insulated gate type bipolar transistor (IGBT) are suitable. Therefore, the "first main electrode region" means the MOSFE
In T, MOSSIT, MISFET, MISIT (hereinafter referred to as “MOSFET”), a semiconductor region having a high impurity density, which is either the source region or the drain region, and in the IGBT, either the emitter region or the collector region. It means a semiconductor region having a high impurity density which is either one of them. On the other hand, the "second main electrode region" means, in MOSFET or the like, either the source region or the drain region which is not the first main electrode region, and in the IGBT, the first main electrode region. It means a semiconductor region which is either an emitter region or a collector region which must not exist. That is, in the MOSFET or the like, if the first main electrode region is the drain region,
The second main electrode region is a source region, and in the IGBT, if the first main electrode region is a collector region, the second main electrode region is an emitter region.

According to the first aspect of the present invention, the protective element made of a polycrystalline silicon film and the bonding pad are electrically connected to each other through a plurality of through holes (fine via holes) formed in the interlayer insulating film. By connecting, the polycrystalline silicon film does not become thin when the through hole is opened. Therefore, even if the wire is bonded to the bonding pad above the polycrystalline silicon film, it is possible to prevent the field insulating film having the same thickness as the gate insulating film of the polycrystalline silicon film from being cracked.

A second feature of the present invention is (a) a step of forming a drift region of the first conductivity type on the first main electrode region of the first conductivity type or the second conductivity type; (b) a drift region Selectively forming a plurality of second-conductivity-type base regions and a second-conductivity-type electric field relaxation region in a part of the base; (c) selecting a first-conductivity-type second main electrode region in the base region. Step (d): forming a gate insulating film on the upper part of the plurality of base regions and on the drift region exposed between the plurality of base regions, and on the upper part of the electric field relaxation region to the same thickness as the gate insulating film; Forming a field insulating film; (e) forming a polycrystalline silicon film on the field insulating film; (f) forming an interlayer insulating film on the polycrystalline silicon film; (g) interlayer insulating Selectively remove part of the membrane,
A plurality of fine via holes exposing a part of the polycrystalline silicon film and a via hole exposing a part of the polycrystalline silicon film with a larger area than the fine via holes are opened in the interlayer insulating film, and the second main electrode region is formed. A step of opening the exposed contact hole; (h) connecting to the second main electrode region through the bonding pad and the contact hole, which are connected to the polycrystalline silicon film through the plurality of fine via holes, and through the via hole. A gist of the method is a method of manufacturing a semiconductor device, the method including the step of forming a main electrode connected to the crystalline silicon film.

According to the second aspect of the present invention, the thickness of the polycrystalline silicon film does not become thin when the fine via hole is opened. Moreover, it can be manufactured by the simple manufacturing process as described above. As a result, it is possible to provide a semiconductor device in which no crack is generated in the gate insulating film formed below the element made of the polycrystalline silicon film. Therefore, a semiconductor device in which the bonding pad and the element made of the polycrystalline silicon film are not electrically short-circuited can be manufactured at a high manufacturing yield at a low cost.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description of the drawings, the same or similar reference numerals are given to the same or similar parts. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following description.
Further, it is needless to say that the drawings include parts in which dimensional relationships and ratios are different from each other.

(First Embodiment) As shown in FIG.
As described above, the semiconductor device according to the first embodiment of the present invention
Is the first main electrode region (drain region) 3 and the second main electrode region
At least the region (source region) 5 and the electric field relaxation region 14
And a semiconductor substrate 1 that constitutes a main element that also includes an electric field relaxation
A film having a thickness of 30 to 150 nm provided on the region 14 is provided.
On the field insulating film 18 and the field insulating film 18
Polycrystalline silicon film forming a protective element for the main element in contact
13 and the insulating layer contacting the upper part of the polycrystalline silicon film 13
Polycrystalline silicon penetrating the edge film 12 and the interlayer insulating film 12
A plurality of microscopic elements arranged in a matrix for exposing the film 13
Via hole C₃₁・ ・ ・ ・ ・ ・ ・ ・, C₃₅Through the multi
Bonding pad 7 connected to crystalline silicon film 13
Is a semiconductor device having. The semiconductor substrate is n⁺Type (No.
Drain region 3 (of one conductivity type)
n-type drift region 2, island-shaped on top of drift region 2
Multiple p-types (second island) exposed
(Conductivity type) base region 4
P-type electric field relaxation region 1 disposed above the shift region 2
4, n formed in a ring shape on the base region 4⁺Type
Is a MOSFET having a source region 5 of. Figure 1
In the cross-sectional view of (a), two are provided inside one base region 4.
Is shown as if there is a source region 5 of
In front of and in the back of the
Is a continuous region having a rectangular ring shape. Furthermore,
Above each of the plurality of base regions 14, a plurality of bases
Between the regions 4 and between the base region 4 and the electric field relaxation region 1
The thickness of the drift region 2 exposed between the
nm-150 nm, preferably 50 nm-100 n thickness
m gate insulating film 11 is arranged. Electric field relaxation region
A thin film having the same thickness as the gate insulating film 11 is formed on the upper portion of the gate insulating film 14.
The field insulating film 18 is formed. This gate insulation film
A gate electrode 6 made of a polycrystalline silicon film is provided on the upper portion of 11.
Are arranged. The polycrystalline silicon film 13 is an electric field relaxation region.
It is also arranged on the field insulating film 18 above the region 14.
Has been. Then, the polycrystalline silicon film 13 and the gate
An interlayer insulating film 12 is disposed on the upper electrode 6.
The polycrystalline silicon film 13 has a plurality of n⁺Type of
Region 2 of doped polysilicon (impurity-doped polysilicon)
5k, 25l, 25m, and 25n are alternately p⁻Type of
The doped polysilicon regions 25a, 25b, 25c are shaped
And a plurality of pn junction diodes connected in series.
It forms an iodo stack. And polycrystalline siri
Of the inter-layer insulating film 12 formed above the control film 13,
Electrode connection area (bonding area) 26 on the plane pattern
The polycrystalline silicon film 13 is formed on the interlayer insulating film 12 located at
Multiple fine via holes C exposing₃₁, C ₃₂，
..., C₃₅Are arranged in a periodic matrix
ing. Furthermore, the gate insulating film 11 and the interlayer insulating film 12 are
A capacitor that penetrates to expose the base region 4 and the source region 5
A tact hole 41 is formed. In addition, the interlayer insulating film 1
N through 2⁺Exposes doped polysilicon region 25k
A via hole 21 is formed so as to emerge. contact
Second main electrode through the hole 41 and the via hole 21
(Source electrode) 8 is the second main electrode region (source region) 5 and
And n⁺Each of the doped polysilicon regions 25k has an
We are in contact with each other. As a result, the second main electrode region 5
n⁺Electrical connection to the doped polysilicon region 25k
Has been done. Fine via hole penetrating the interlayer insulating film 12
N of the polycrystalline silicon film 13⁺Doped policy
The bonding pad 7 is ohmic on the recon region 25n.
Are in contact. The bonding pad 7 is located at the back of the paper.
It is connected to the gate electrode 6. This results in polysilicon
The diode stack composed of the film 13 is connected to the gate electrode 6 and
It is connected to the source electrode 8.

A plurality of base regions 4 are arranged in an island shape on the surface of the drift region 2 so as to allow a desired current capacity,
A drift region 2 serving as a channel region is interposed between adjacent base regions 4 in a mesh shape to realize a multi-channel structure. As shown in FIG. 1, the electric field relaxation region 14 is
A large electric field is applied to the thin field insulating film 18 formed below the polycrystalline silicon film 13 and having the same film thickness as the gate insulating film 11 formed below the polycrystalline silicon film 13, and the field insulating film 18 is destroyed. Prevent that.
The impurity density on the center side of the base region 4 may be increased to form the p ⁺ type base contact region on the center side of the base region 4. As the semiconductor substrate 1, silicon (S) added with an n-type impurity such as phosphorus (P) or antimony (Sb) is used.
i) Single crystals can be used. As shown in FIG. 1B, a fine via hole C opened in the electrode connection region 26.
₁₁ , C ₁₂ , ..., C ₃₁ , C ₃₂ , ...
· _{C 4 5} has a diameter of 1 to 10 [mu] m, preferably 2~5μm
The size is about 10 to 30 μm, and preferably 5 rows and 5 columns are arranged at intervals of about 20 μm. Fine via holes C ₁₁ , C ₁₂ , ..., C ₃₁ ,
C ₃₂ , ..., C _{4 5} can have a diameter of 3 μm, for example. Fine via holes _{C 11, C 1 2,} ·
····, C ₃₁ , C ₃₂ , ···, C ₄₅ may be circular or polygonal.

Semiconductor according to the first embodiment of the present invention
According to the device, n of the polycrystalline silicon film 13⁺Doped Po
A plurality of re-silicon regions 25n and bonding pads 7
Fine via hole C₁₁, C₁₂・ ・ ・ ・ ・ ・ ・ ・, C
₃₁, C₃₂・ ・ ・ ・ ・ ・ ・ ・, C ₄₅Electrically connected through
Has been continued. Therefore, from the explanation of the manufacturing process described later,
As can be understood, the polycrystalline silicon film 13 is formed during the manufacturing process.
It does not become thin. Therefore, the polycrystalline silicon film 13
Via the bonding pad 7 on the upper surface of the electrode connection region 26
Even if the wire 23 is bonded by the
A crack is formed in the thin field insulating film 18 under 13
There is no messing. For this reason, reliable polycrystalline silicon
MOS in which a protection element composed of the insulating film 13 is integrated
A FET can be provided. Bonding pad 7
The polycrystalline silicon film 13 (electrode connection region 26) is on the lower side.
Since it remains with the designed desired film thickness, bonding
Pressure when bonding the wire 23 onto the pad 7
Can be absorbed by the polycrystalline silicon film 13.
At the same time, the inter-layer insulating film 12 is also meshed immediately below the wire 23.
The inter-layer insulating film 12 is also formed at the time of bonding since
Can absorb pressure. Therefore, the pressure during wire bonding
The gate insulating film 1 below the polycrystalline silicon film 13 by force
1 is prevented from cracking, and the semiconductor substrate 1
Between the electric field relaxation region 14 and the bonding pad 7 of
It may be electrically short-circuited through the crystalline silicon film 13.
Absent.

Fine via hole C₁₁, C₁₂・ ・ ・
.., C₃₁, C₃₂・ ・ ・ ・ ・ ・ ・ ・, C₄₅Size of
Is the current capacity of the pn junction diode (protection element)
It can be set appropriately depending on the situation, but if the diameter is too small,
Contact resistance can be increased and sufficient current capacity can be secured.
Without using a fine via hole C₁₁, C
₁₂・ ・ ・ ・ ・ ・ ・ ・, C₃₁, C₃₂・ ・ ・ ・ ・ ・ ・ ・, C
₄₅It becomes difficult to be filled well. On the other hand, the diameter is
If it is too large, it will be
The polycrystalline silicon film 13 remaining under the interlayer insulating film 12
It is etched and its film thickness is reduced.
The stress of the groove is well absorbed by the polycrystalline silicon film 13.
I can't. Therefore, the fine via hole C₁₁，
C₁₂・ ・ ・ ・ ・ ・ ・ ・, C₃₁, C₃₂・ ・ ・ ・ ・ ・ ・ ・, C
₄₅It is preferable to set the diameter of 1 to 10 μm,
More preferably, it is set to 5 μm.

Next, an example of a method of manufacturing the semiconductor device according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. The usage shown in FIGS. 2 to 5 is an example, and it goes without saying that the MOSFET in which the protection element shown in FIG. 1 is integrated can be manufactured by other methods.

(A) First, as shown in FIG. 2 (a), the impurity density obtained by polishing the surface to a mirror surface is 5 × 10 ¹⁷ cm ^{-3 -1.}
A semiconductor substrate 1 made of n ⁺ type silicon single crystal having a size of about 10 ¹⁹ cm ⁻³ is prepared. Then, as shown in FIG. 2B, the impurity density is 5 × 10 ¹³ cm ⁻³ to 1 on the semiconductor substrate 1 using silicon tetrachloride (SiCl ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), or the like. the × ^{10 16} cm ^-3 of about n-type epitaxial layer 9 to 5μm~50μm deposition. To make it n-type, an n-type dopant gas such as phosphine (PH ₃ ) is used. This epitaxial growth layer 9 functions as the drift region 2 of the MOSFET, and the semiconductor substrate 1 has the drain region (first main electrode region).
Functions as 3.

(B) Next, as shown in FIG. 2B, a buffer oxide film (first insulating film) 31 of 30 nm to 100 nm is formed on the surface of the drift region 2 by thermal oxidation. Then, after applying the resist film 51 on the surface of the buffer oxide film 31, as shown in FIG. 2C, the resist film 51 was made to correspond to the base region formation planned region and the electric field relaxation region by using a photolithography technique. Open the window. Using the resist film 51 as a mask, boron ions ( ¹¹ B
P-type impurity ions such as ⁺ ) are selectively implanted into the surface of the epitaxial growth layer 9. As a result, ion-implanted regions 4a and 14a are formed immediately below the protrusion.

(C) After removing the resist film 51, heat treatment (drive-in) is performed to activate the implanted ions, and the impurity concentration is about 5 × 10 ¹⁷ cm ^{−3 to} 7 × 10 ¹⁹ cm ^{−3 in} the base region. 4 and the electric field relaxation region 14 are formed. After removing the buffer oxide film 31, a thickness of 30 nm to 150 nm,
Preferably, a thin oxide film (second insulating film) 32 having a thickness of 50 nm to 100 nm is formed on the entire surface of the epitaxial growth layer 9 by thermal oxidation. Further, as shown in FIG. 2D, a polysilicon film 25 having a thickness of 300 to 800 nm is deposited by the CVD method.

(D) After that, a resist film 52 is applied on the polysilicon film 25, and as shown in FIG. 2E, this resist film 52 is wider than the base region 4 by using the photolithography technique. Patterning is performed so as to have a window portion having an opening width. The polysilicon film 25 is etched by the RIE method using the resist film 52 as an etching mask. Further, as shown in FIG. 2 (e), this RIE
Using the resist film 52 used as a mask for the method, a p-type impurity ion such as boron ion ( ¹¹ B ⁺ ) is ion-implanted so as to overlap the base region 4. Resist film 5 used as a mask for ion implantation
2 is removed and heat-treated to activate the implanted ions,
The central part is deep due to heat diffusion (drive-in),
The base region 4 having a shallow peripheral portion is formed. At this time, the electric field relaxation region 14 is also driven in deeper.
Further, a new pattern of the resist film 53 is formed by using the photolithography technique as shown in FIG. The pattern of the resist film 53 is such that the resist film 53 is arranged in an island shape at the center of the p-type base region 4.
The shape is such that ions are not implanted into the central portion of the mold base region 4. Then, as shown in FIG.
N-type impurity ions such as arsenic ions ( ⁷⁵ As ⁺ ) are selectively implanted into the surface of the p-type base region 4. The ion implantation region shown by the broken line in FIG. 3F has a ring shape in which the outer shape line is defined by the polysilicon film and the inner shape line is defined by the resist film 53. The exposed polysilicon film 25 functions as a mask for ion implantation and, at the same time, the polysilicon film 2
The n-type impurity ions are also implanted in 5. Resist film 5
3 is removed and then heat-treated, as shown in FIG.
The implanted ions are activated and the impurity density is 5 × 10 5.
A source region (second main electrode region) 5 of about ¹⁷ cm ^{−3 to} 7 × 10 ¹⁹ cm ⁻³ is formed. That is, the source region 5 having the defined outline is formed by a self-alignment process using the polysilicon film 25 as a mask.
Are formed, and the polysilicon film 25 becomes an n ⁺ -doped polysilicon film.

(E) Next, a new resist film 54 is applied, and the resist film 54 is patterned by using the photolithography technique. Using the resist film 54 as a mask, the doped polysilicon film 25 is etched by the RIE method as shown in FIG. As a result, the doped polysilicon film 25 has a gate electrode 6 formed in a mesh shape above the surface of the drift region 2 between the p-type base regions 4, and an independent island shape above the electric field relaxation region 14. It is separated into the doped polysilicon film 25 formed as a pattern. Then, the thin oxide film 32 below the gate electrode 6 functions as the gate insulating film 11, and the thin oxide film 32 below the doped polysilicon film 25 functions as the thin field insulating film 18. After removing the resist film 54,
As shown in FIG. 3I, a third insulating film 33 such as an oxide film having a thickness of 0.3 μm to 2 μm or a composite film of an oxide film and a PSG film is deposited by the CVD method. Then, a new resist film 55 is applied on the third insulating film 33, and the resist film 55 is formed by photolithography.
A window portion corresponding to the area where the electrode connection area is to be formed is opened at 5. Then, using this resist film 55 as a mask, as shown in FIG.
As shown in (j), the third insulating film 33 is etched by the RIE method. By using the resist film 55 and the third insulating film 33 as a mask, p-type impurity ions such as boron ions ( ¹¹ B ⁺ ) are selectively implanted. After removing the resist film 55, heat treatment (drive-in) is performed to activate the implanted ions, and the p ⁻ -doped polysilicon film formation region 25 is formed.
a, 25b, 25c are formed. After that, film thickness 600n
A fourth insulating film 34 such as a PSG film or a BPSG film having a thickness of about m to 1.5 μm is deposited on the third insulating film 33 by the CVD method.
Then, as shown in FIG. 4 (l), chemical mechanical polishing (C
MP) or the like is used to flatten the surface of the fourth insulating film 34 until it becomes flat. As a result, the interlayer insulating film 12 including the third insulating film 33 and the fourth insulating film 34 and having a flat surface is formed.

(F) Next, a resist film 56 is applied to the entire surface of the interlayer insulating film 12 and patterned as shown in FIG. 5 (m). This patterned resist film 56
With the mask as a mask, a part of the interlayer insulating film 12 is selectively removed by the RIE method, and the contact hole (source contact hole) 41 and the via hole 2 are removed as shown in FIG.
1, fine via holes C ₃₁ , C ₃₂ , C ₃₃ ,
_C34 and _C35 are formed. At this time, a gate contact hole that exposes a part of the gate electrode 6 is also formed at the back of the paper. Fine via holes C ₃₁ , C ₃₂ ,
After opening C ₃₃ , C ₃₄ , and C ₃₅ , the resist film 56 is removed.

(G) Next, the thickness is 0.5 μm to 10 μm by a sputtering method or an electron beam (EB) vapor deposition method.
Aluminum (Al) or aluminum alloy (A
A metal film 61 such as a (1-Si, Al-Cu-Si) film is deposited. A resist film is applied thereon, and the resist film is patterned by using a photolithography technique to form a metallization mask. Using this metallization mask, the metal film 61 is selectively etched by the RIE method. Then, the photoresist film used for patterning the electrode wiring is removed. As a result, as shown in FIG. 5O, the metal film is patterned to form the bonding pad 7 and the source electrode 8 functioning as the main electrode (second main electrode). The bonding pad 7 covers a gate contact hole (not shown) at the back of the paper. Further, after covering the entire surface on the side where the source electrode 8 and the bonding pad 7 are formed with a resist film, the entire oxide film on the other main surface of the semiconductor substrate 1 is etched to expose the exposed semiconductor substrate 1 (n). A drain electrode 15 that functions as another main electrode (first main electrode) is formed in the ⁺ drain region 3).

(H) After removing the resist film used for the entire etching of the back surface (the other main surface) and sintering at 400 ° C. to 450 ° C., as shown in FIG. By connecting 23, the semiconductor device according to the embodiment of the present invention is completed.

According to the method of manufacturing the semiconductor device of the first embodiment of the present invention, the thickness of the polycrystalline silicon film 13 is 30 as designed by the simple manufacturing process as described above.
Since the thickness (as-deposit thickness) of 0 to 800 nm is maintained, cracks do not occur in the thin field insulating film 18 formed under the bonding pad 7 due to the bonding pressure during wire bonding. For this reason, a semiconductor device (a MOSFET with a built-in protection element) in which a defect in which the bonding pad 7 and the electric field relaxation region 14 are electrically short-circuited does not occur can be manufactured at a high manufacturing yield at a low cost.

(Second Embodiment) As shown in FIG.
The semiconductor device according to the second embodiment of the present invention is the first
A semiconductor substrate 1 forming a main element including at least a main electrode region (collector region) 43, a second main electrode region (emitter region) 45, and an electric field relaxation region 14, and a thickness provided above the electric field relaxation region 14. Field insulating film 18 having a thickness of 30 to 150 nm, and a polycrystalline silicon film 1 which is in contact with the upper part of the field insulating film 18 and constitutes a protective element for the main element
3, the interlayer insulating film 12 in contact with the upper portion of the polycrystalline silicon film 13, and a plurality of fine via holes C ₃₁ , arranged in a matrix that penetrate the interlayer insulating film 12 to expose the polycrystalline silicon film 13. The semiconductor device has a bonding pad 7 connected to the polycrystalline silicon film 13 via C ₃₅ . The semiconductor substrate is a p ⁺ type (second
Conductivity type) collector region 43, n type drift region 2 on the collector region 43, and a plurality of p type (second conductivity type) base regions (body regions) arranged in an island shape on the drift region 2. 4, an IGBT having a p-type electric field relaxation region 14 arranged above the drift region 2 in the peripheral portion of the chip, and an n ⁺ type emitter region 45 formed on the ring above the base region 4.

A gate insulating film 11 is disposed on the drift region 2 exposed between the base regions 4 and between the base region 4 and the electric field relaxation region 14, and the upper portion of the gate insulating film 11 is disposed. Is provided with a polycrystalline silicon film 13. The polycrystalline silicon film 13 has an electric field relaxation region 14
Is also disposed on the upper portion of the field insulating film 18 having the same film thickness as the gate insulating film 11 on the upper part of. An interlayer insulating film 12 is arranged on the polycrystalline silicon film 13 and the gate electrode 6. Then, the polycrystalline silicon film 13, a plurality of ^{n +} -type doped polysilicon film region 25k, 25l, 25 m, the plurality alternating with 25n p ^- -type doped polysilicon film region 25a (second conductivity type) ，
25b and 25c are formed to form a diode forming region 25 in which a plurality of pn junction diodes are connected in series. Then, the interlayer insulating film 12 located in the electrode connection region 26 on the planar pattern has the fine via holes C ₃₁ ,
With C _32, ·····, the _{C 35.} Further, a contact hole 41 is formed penetrating the gate insulating film 11 and the interlayer insulating film 12 to expose the base region 4 and the emitter region 45. Further, a via hole 21 penetrating the interlayer insulating film 12 and exposing the n ⁺ -doped polysilicon film region 25k is formed. Via the contact hole (emitter contact hole) 41 and the via hole 21,
The emitter electrode 46 electrically connects the emitter region 45 and the n ⁺ -doped polysilicon film region 25k. Then, as in the first embodiment, the fine via hole C is formed.
_The bonding pad 7 connected to the polycrystalline silicon film via ₃₁ , C ₃₂ , ..., C ₃₅ is connected to the gate electrode 6 via the gate contact hole at the back of the drawing.

As shown in FIG. 6, the electric field relaxation region 14 is
A large electric field is applied to the thin field insulating film 18 formed below the polycrystalline silicon film 13 and having the same film thickness as the gate insulating film 11 formed below the polycrystalline silicon film 13, and the field insulating film 18 is destroyed. Prevent that.

According to the semiconductor device according to the second embodiment of the present invention, the doped polysilicon film region 25n of the polycrystalline silicon film 13 and the bonding pad 7 have a plurality of fine via holes C ₁₁ , C ₁₂ , ...
C _{31, C} 32, · · · · _·, because they are electrically connected through _{C 4 5,} the first in the same manner as in the embodiment polycrystalline silicon film 13 can be maintained the thickness as designed. Therefore, at the time of bonding, cracks are prevented from being generated in the gate insulating film 11 below the polycrystalline silicon film 13 due to the bonding pressure, and polycrystalline silicon is provided between the electric field relaxation region 14 of the semiconductor substrate 1 and the bonding pad 7. There is no electrical short circuit through the membrane 13.

Semiconductor according to the second embodiment of the present invention
A method for manufacturing a device relates to the first embodiment of the present invention.
In a method of manufacturing a semiconductor device, n⁺Type (first conductivity type)
The semiconductor substrate 1 made of the silicon single crystal is prepared.
Of the semiconductor device according to the second embodiment of the present invention.
In the manufacturing method, 5 × 10¹⁸cm^-3~ 1 x 10²¹cm
^-3p⁺Type (second conductivity type) silicon substrate (semiconductor substrate
A plate) 43 may be prepared. The subsequent manufacturing method is
And a method for manufacturing a semiconductor device according to the first embodiment
The drain electrode 15 is the same as the collector electrode 44.
The rain region 3 is the collector region 43, and the source electrode 8 is the emitter region.
And the source region 5 is read as the emitter region 45.
It suffices to replace them, and duplicate explanations are omitted.

According to the method of manufacturing the semiconductor device according to the second embodiment of the present invention, the gate insulating film 11 formed under the protective element made of the polycrystalline silicon film 13 is formed by a simple manufacturing process. Thin field insulating film 1 of the same thickness
No cracks occur in No. 8. Therefore, a semiconductor device (protection element built-in type IGBT) in which the bonding pad 7 and the electric field relaxation region 14 are not electrically short-circuited can be manufactured at a high manufacturing yield and at a low cost.

(Other Embodiments) Although the present invention has been described by the first and second embodiments, it is understood that the description and drawings forming a part of this disclosure limit the present invention. should not do. From this disclosure, various alternative embodiments, examples, and manufacturing process technologies will be apparent to those skilled in the art.

For example, in the above description of the first and second embodiments, the first conductivity type is n-type and the second conductivity type is p-type.
Although described as a type, it goes without saying that the first conductivity type may be p-type and the second conductivity type may be n-type.

Furthermore, in the description of the first and second embodiments, the case where the Si substrate is used as the semiconductor substrate has been described, but silicon carbide (SiC), diamond, gallium arsenide (GaAs), indium phosphide (InP). Of course, other semiconductor materials such as) may be used.

As described above, needless to say, the present invention includes various embodiments and the like not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the scope of claims reasonable from the above description.

[0035]

According to the present invention, since the thickness of the polycrystalline silicon film maintains the designed film thickness, the polycrystalline silicon film absorbs the bonding pressure at the time of wire bonding on the bonding pad. You can
It is possible to prevent cracks from occurring in the thin field insulating film below the polycrystalline silicon film.

Therefore, according to the present invention, the electric field relaxation region of the semiconductor substrate and the bonding pad are not electrically short-circuited via the crack of the field insulating film.

Therefore, according to the present invention, it is possible to improve the reliability and improve the manufacturing yield of a semiconductor device having a built-in protective element in which a protective element made of polycrystalline silicon is integrated on the surface of the main element. .

[Brief description of drawings]

FIG. 1 is a sectional view showing a part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention (No. 1).

FIG. 3 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention (No. 2).

FIG. 4 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention (No. 3).

FIG. 5 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention (No. 4).

FIG. 6 is a sectional view showing a part of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device having a conventional MOSFET.

[Explanation of symbols]

1 semiconductor substrate 2 drift region 3 drain region (first main electrode region) 4 base region 4a base region formation planned region 5 source region (second main electrode region) 6 gate electrode 7 bonding pad 8 source electrode (second main electrode) 9 epitaxial growth layer 11 gate insulating film 12 interlayer insulating film 13 polycrystalline silicon film 14 electric field relaxation region 14a electric field relaxation region formation region 15 drain electrode (first main electrode) 18 thin field insulating film 21 via hole 23 wire 25 doped poly Silicon film 25a, 25b, 25cp p ^- doped polysilicon region 25d, 25k, 25m, 25n n ⁺ doped polysilicon region 26 electrode connection region 26a electrode connection region formation scheduled region 28 first opening 29 second opening 31 Buffer oxide film (first insulating film) 32 Thin oxide film (second insulating film) Edge film) 35 Oxide film 33 Third insulating film 34 Fourth insulating film 41 Contact hole 43 Collector region (first main electrode region) 44 Collector electrode (first main electrode) 45 Emitter region (second main electrode region) 46 Emitter Electrodes (second main electrode) 51, 52, 53, 54, 55, 56 Resist films C ₁₁ , C ₁₂ , ..., C ₃₁ , C ₃₂ ,.
.., C ₃₅ , ..., C ₄₅ fine via holes

Claims (7)

[Claims] 1. A semiconductor substrate forming a main element having at least a first main electrode region, a second main electrode region and an electric field relaxation region, and a thickness of 30 to 150 provided on the electric field relaxation region.
nm field insulating film, a polycrystalline silicon film which is in contact with the upper portion of the field insulating film and constitutes a protection element of the main element, an interlayer insulating film which is in contact with the upper portion of the polycrystalline silicon film, and the interlayer insulating film And a bonding pad connected to the polycrystalline silicon through a plurality of fine via holes arranged in a matrix that expose the polycrystalline silicon film through the substrate. 2. The semiconductor substrate, a first conductivity type or a second conductivity type first main electrode region, the first conductivity type drift region disposed on the first main electrode region, The electric field relaxation region of the second conductivity type and a plurality of base regions of the second conductivity type arranged on the drift region, and the second main electrode region of the first conductivity type arranged on the base region. The semiconductor device according to claim 1, further comprising: a gate insulating film formed on an upper portion of each of the plurality of base regions; and a gate electrode formed on an upper portion of the gate insulating film. apparatus. 3. The semiconductor device according to claim 2, wherein the field insulating film has substantially the same thickness as the gate insulating film. 4. The polycrystalline silicon film has a plurality of the first-conductivity-type doped polysilicon regions and a plurality of the second-conductivity-type doped polysilicon regions, which are alternately formed. The semiconductor device according to any one of claims 1 to 3. 5. The diameter of the fine via hole is 1 μm in diameter.
It is m-10 micrometers, The semiconductor device of any one of Claims 1-4 characterized by the above-mentioned. 6. The fine via hole is 10 to 30 μm.
The semiconductor device according to claim 1, wherein the semiconductor devices are arranged in a matrix at intervals of m. 7. A step of forming a drift region of the first conductivity type above a first main electrode region of the first conductivity type or a second conductivity type, and a step of forming the drift region of the second conductivity type in a part of the drift region. Selectively forming a plurality of base regions and the second conductivity type electric field relaxation region, and selectively forming the first conductivity type second main electrode region in the base region, A gate insulating film is formed on the plurality of base regions and on the drift region exposed between the plurality of base regions, and a field insulating film having the same thickness as the gate insulating film is formed on the electric field relaxation region. A step of forming a polycrystalline silicon film on the field insulating film, a step of forming an interlayer insulating film on the polycrystalline silicon film, and a part of the interlayer insulating film being selectively removed. And the interlayer insulation A plurality of fine via holes exposing a part of the polycrystalline silicon film and a via hole exposing a part of the polycrystalline silicon film with an area larger than the fine via holes are opened in the film, and the second main electrode is formed. A step of opening a contact hole exposing the region; a bonding pad connecting to the polycrystalline silicon film via the plurality of fine via holes; and connecting to the second main electrode region via the contact hole, And a step of forming a main electrode connected to the polycrystalline silicon film via a hole.