JP2003069040A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a silicon carbide semiconductor device and a method of manufacturing the same, which can increase design flexibility. On the SiC substrate 1 An N-type, N ^- together with the drift layer 2 and the P ⁺ -type first gate layer 3 and the N ⁺ source layer 4 are laminated in this order, a source layer 4 first Gate layer 3
Are formed to reach the drift layer 2, and an N ⁻ type channel layer 6 and a P ⁺ type second gate layer 7 are formed on the inner wall of the trench 5. P-type impurity regions 30 for forming a super junction structure are provided in the drift layer 2 side by side, and have different concentrations in the depth direction and different widths in the horizontal direction in the depth direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 2001-144292 discloses a silicon carbide semiconductor device having a super junction. Specifically, as shown in FIG. 14, an N-type layer 101 is formed on an N ⁺ -type SiC substrate 100, and P-type base regions 102a and 102b and an N-type source region are formed on the surface layer of the N-type layer 101. 103 and an N-type channel layer 104 are formed, and a gate electrode 106 is arranged on the upper surface of the substrate with a gate oxide film 105 interposed. On the other hand, the P-type region 107 is formed inside the N-type layer 101.
Are juxtaposed, and N-type regions 101a and P-type regions 107 are alternately buried in the lateral direction to form a super junction. A high breakdown voltage can be obtained by this super junction. However, there is a demand for flexible design of super junctions.

[0003]

The present invention has been made based on such a background, and an object thereof is to provide a silicon carbide semiconductor device capable of further increasing the degree of freedom in design and a manufacturing method thereof. To do.

[0004]

The invention according to claim 1 is characterized in that the impurity regions at the super junction have different concentrations in the depth direction.
As described above, since the concentration gradient in the depth direction can be desired, the degree of freedom in design is increased.

The invention according to claim 2 is characterized in that the impurity regions at the super junction have different lateral widths in the depth direction. In this way, the width can be changed as desired in the depth direction, so that the degree of freedom in design is increased.

The invention according to claim 3 is characterized in that the impurity regions at the super junction have different concentrations in the depth direction and different lateral widths in the depth direction. In this way, the concentration gradient in the depth direction can be made desired, and the width can be changed as desired in the depth direction, thereby increasing the degree of freedom in design.

As a manufacturing method, as described in claim 5, a drift layer of the first conductivity type is formed on the SiC substrate of the first conductivity type by epitaxial growth. Then, the first ion implantation is performed on the drift layer using a mask to bury the second conductivity type impurity region at a predetermined depth in the drift layer below the mask opening. further,
The second ion implantation is performed on the drift layer using another mask, and the second conductivity type impurity region is formed at a predetermined depth in the drift layer below the mask opening by the second ion implantation. It is buried so as to be connected to the conductivity type impurity region.

As a result, the silicon carbide semiconductor device according to the first, second, and third aspects can be manufactured.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a vertical sectional view of a silicon carbide semiconductor device according to the present embodiment.

[0010] In FIG. 1, on the SiC substrate 1 as a drain region N ⁺ -type (first conductivity type), N consisting epitaxial layer ^- -type drift layer 2 (low concentration first conductivity type a), P ⁺ type (second conductivity type) consisting of an epitaxial layer
Of the first gate layer 3 and the epitaxial layer of N ⁺
Type (first conductivity type) source layer 4 is sequentially stacked. A trench 5 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed. further,
The inner wall of the trench 5 is made of N ^{− made of an} epitaxial layer.
Type (first conductivity type) channel layer 6 is formed, and a P ⁺ type (second
A second gate layer 7 of conductivity type is formed.

An insulating film (LTO film) 8 is formed on the upper surface of the substrate.
Is formed, and the first gate electrodes 11 and 12 pass through the contact holes formed in the insulating film 8 to form the first gate layer 3
, The second gate electrodes 9 and 10 are connected to the second gate layer 7, and the source electrode 13 is connected to the N ⁺ source layer 4. Aluminum is used for the electrode materials 9 and 11, and electrode materials 10 and 12 are used.
Nickel is used for. Note that the metal materials 9 and 11 are not necessary when contacting the N-type SiC layer. A drain electrode 14 is formed on the entire back surface (lower surface) of the substrate 1.

As the transistor operation, the channel width is changed by adjusting the width of the depletion layer in the channel layer 6 sandwiched between the two gate layers 3 and 7 by the voltage to the first and second gate terminals to change the drain current. Adjust.

Further, the source layer 4 and the first gate layer 3 are provided on the outer peripheral portion (outer peripheral portion of the chip) of the transistor cell formation region.
A trench 20 penetrating through and reaching the drift layer 2 is formed. The inner wall of the trench 20 is formed of P ⁺ type Si.
The C layer 21 is formed, and the P ⁺ type SiC layer 21 functions as a guard ring. The upper surface of the P ⁺ type SiC layer 21 (outer peripheral portion of the chip) is covered with an insulating film (LTO film) 8.

On the other hand, in the drift layer 2 in the transistor cell formation region, a P-type (second conductivity type) impurity region 30 is provided inside the drift layer 2 in parallel.
Further, N-type (first conductivity type) impurity regions and P-type impurity regions 30 are alternately buried in the lateral direction to form a super junction.

Here, in the present embodiment, the buried P-type impurity region 30 has a different concentration in the depth direction and a different width in the lateral direction. Specifically, the concentration has three levels in the depth direction, the deepest region 31 has the lowest concentration (P ⁻ ), and the intermediate depth region 32 has an intermediate concentration (P), In the shallowest region 32, it is the deepest (P ⁺ ). On the other hand, regarding the width in the horizontal direction,
The deepest region 31 has the widest width, the intermediate depth region 32 has the middle width, and the shallowest region 32 has the narrowest width.

Regarding the concentration of each of the regions 31, 32 and 33, when aluminum is used as an impurity, for example, P ⁻ region 3
1 is 5 × 10 ¹⁶ to 1 × 10 ¹⁸ atms / cm ³ and the P region 32 is 5 × 10 ¹⁷ to 1 × 10 ¹⁹ atms / cm ³ ,
The P ⁺ region 33 is 5 × 10 ^{18 to} 5 × 10 ²⁰ atms / cm ³
Is.

As described above, with respect to the impurity region 30 at the super junction, the concentration gradient in the depth direction can be made desired, and the width can be changed as desired in the depth direction. Increase.

Even if the potential of the P-type impurity region 30 forming the super junction is floating,
It may be ground potential together with the source. FIG. 1 shows a case of floating, and FIG. 2 shows a case of ground potential.

On the other hand, a P-type impurity region 3 is formed in the guard ring portion in the outer peripheral portion (chip outer peripheral portion) of the transistor cell.
No super junction by 0 is formed.
That is, the super junction structure is adopted only in the transistor cell formation region, and the super junction structure is not adopted in the outer peripheral portion of the transistor cell formation region. This makes it possible to prevent the breakdown voltage from decreasing.

Next, the manufacturing method will be described. As shown in FIG. 3A, the N ⁻ drift layer 2 is formed on the N ⁺ type SiC substrate 1 by epitaxial growth. And
A patterned mask 40 is arranged on the N ⁻ drift layer 2. That is, the mask 40 having the opening 41 is formed. In this state, aluminum ion implantation is performed. This ion implantation has a high implantation energy (for example, 400 keV).
And, the injection amount is low. As a result, the deepest P-type region (P ⁻ region) 31 of the super junction is formed.

Subsequently, as shown in FIG. 3 (b), a patterned mask 42 is placed on the mask 40. At this time, the opening 41 of the mask 40 is closed by the mask 42, and an opening 43 having an area smaller than that of the opening 41 is formed in the region. Center of opening 41 and opening 4
The centers of 2 coincide. In this state, aluminum ion implantation is performed. This ion implantation is performed with a medium implantation energy (for example, 200 keV) and a medium implantation amount. As a result, the P-type region 32 is formed at a middle depth of the super junction and at a medium concentration.

Subsequently, as shown in FIG. 4A, a patterned mask 44 is placed on the mask 42. At this time, the opening 43 of the mask 42 is closed by the mask 44, and an opening 45 having an area smaller than that of the opening 43 is formed in the region. Center of opening 43 and opening 4
The centers of 5 coincide. In this state, aluminum ion implantation is performed. This ion implantation is performed with a low implantation energy (for example, 100 keV) and a high implantation amount. As a result, the shallowest superjunction and high concentration P-type region (P ⁺ region) 33 is formed.

After that, as shown in FIG. 4B, a first gate layer (P ⁺ layer) 3 and an N ⁺ source layer 4 are formed on the N ⁻ drift layer 2 by continuous epitaxial growth.
Then, as shown in FIG. 5A, trenches 5 and 20 penetrating the source layer 4 and the first gate layer 3 and reaching the drift layer 2 are formed.

Thereafter, as shown in FIG. 5B, an N ^-- type epitaxial layer 6 is formed on the substrate including the trenches 5 and 20 by epitaxial growth. Then, as shown in FIG. 6A, the N ⁻ type epi layer 6 in the outer peripheral portion of the transistor cell formation region is subjected to a predetermined amount t1 by RIE.
Only etch to thin. Further, as shown in FIG. 6B, a P ⁺ layer 7 is formed on the surface layer portion of the N ⁻ type epi layer 6 by thermal diffusion. As a result, the P ⁺ layer 7 is entirely formed in the guard ring formation region in the outer periphery of the transistor cell formation region. Although the P ⁺ layer 7 was formed by thermal diffusion,
The P ⁺ layer 7 may be formed by epitaxial growth or ion implantation.

Subsequently, as shown in FIG. 7A, the source contact region A in the transistor cell formation region is formed.
The N ⁻ type epi layer 6 and the P ⁺ layer 7 of 1 are removed by RIE. Further, as shown in FIG. 7B, the source layer 4 of the first gate contact region A2 in the transistor cell formation region is removed by RIE.

Thereafter, as shown in FIG. 1, after depositing the insulating film 8 and forming contact holes, gate electrodes 9 and 10, gate electrodes 11 and 12, and source electrode 13 are formed. Further, the drain electrode 14 is formed on the back surface of the substrate.

In this manner, the first ion implantation is performed on the drift layer 2 of FIG. 3A using the mask 40 to a predetermined depth in the drift layer 2 below the mask opening 41. A step of burying the P ⁻ type impurity region 31 and a second ion implantation for the drift layer 2 of FIG.
And a step of burying a P-type impurity region 32 in a predetermined depth in the drift layer 2 in a state of being connected to the P-type impurity region 31 by the first ion implantation (the third time for the second ion implantation). The same applies to the ion implantation in step 1), the mask opening 41 in the first ion implantation and the mask opening 43 in the second ion implantation have the same center, and the area and the implantation in the first ion implantation are the same. The energy, the implantation energy in the second ion implantation, and the ion implantation amount were made different. As a result, the impurity regions 30 can have different concentrations in the depth direction and different lateral widths in the depth direction.

As another example replacing FIG. 1, as shown in FIG. 8, the lateral width is the narrowest in the deepest P ⁻ region 51, and the intermediate width in the intermediate depth P region 52. , May be the widest in the shallowest P ⁺ region 52.

At the time of manufacturing, as shown in FIGS.
As shown in (c), the openings 6 of the masks 60, 62, 64
When implanting ions while narrowing the widths of 1, 63 and 65,
The injection energy and injection amount may be adjusted.

Further, although it is applied to the JFET in FIG. 1, the present invention is not limited to this, and as shown in FIG.
It may be applied to ET. That is, the N ⁺ type SiC substrate 70
An N-type epi layer 71 is formed on the N type epi layer 71, and P type base regions 72 and 73, an N ⁺ type source region 74, and an N ⁻ type channel layer 75 are formed in the surface layer portion of the N type epi layer 71. A gate electrode 77 is arranged on the upper surface of the substrate via a gate oxide film 76. The source electrode 78 is in contact with the N ⁺ source region 74 and the P ⁺ base region 73. Board 70
A drain electrode 79 is formed on the back surface of the. This M
In the OSFET, P is provided inside the N-type drift layer 71.
^- embedded between region 31 and P region 32 and P ⁺ region 33 by arranging the P-type region 30 formed by laminating. As a manufacturing method, FIG.
As shown in FIG. 3, after growing the N-type epi layer 71 by a predetermined thickness on the N ⁺ -type SiC substrate 70, the P-type region 30 is formed by ion implantation, and then the N-type epi layer 71 is formed. You can continue to grow.

Further, in FIG. 1, the impurity region 30 is used.
Have different concentrations in the depth direction and different widths in the horizontal direction in the depth direction. However, the present invention is not limited to this. As shown in FIG. 12, the impurity regions 30 have the same horizontal width in the depth direction. The concentration may be different in the depth direction, or as shown in FIG. 13, the impurity regions 30 may have the same concentration in the depth direction and the lateral widths different in the depth direction. .

Further, although the side surface of the trench 5 is inclined in FIG. 1, it may be vertical. In FIG. 3, the mask opening 41 in the first ion implantation and the mask opening 43 in the second ion implantation have the same center, and the area and the implantation energy in the first ion implantation are the same. Although the implantation energy in the second ion implantation and the ion implantation amount are all different, the present invention is not limited to this, and at least one of them may be made different (third implantation of the third ion implantation). The same applies to ion implantation).

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a silicon carbide semiconductor device according to an embodiment.

FIG. 2 is a vertical cross-sectional view of a silicon carbide semiconductor device.

FIG. 3 is a vertical cross-sectional view for explaining the manufacturing process of the silicon carbide semiconductor device.

FIG. 4 is a vertical cross-sectional view for explaining the manufacturing process of the silicon carbide semiconductor device.

FIG. 5 is a vertical cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device.

FIG. 6 is a vertical cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device.

FIG. 7 is a vertical cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device.

FIG. 8 is a vertical sectional view of another example of a silicon carbide semiconductor device.

FIG. 9 is a vertical cross sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device.

FIG. 10 is a vertical cross-sectional view of another example of a silicon carbide semiconductor device.

FIG. 11 is a vertical cross-sectional view for explaining the manufacturing process for the silicon carbide semiconductor device of another example.

FIG. 12 is a vertical cross-sectional view of another example of a silicon carbide semiconductor device.

FIG. 13 is a vertical sectional view of another example of a silicon carbide semiconductor device.

FIG. 14 is a vertical cross-sectional view of a silicon carbide semiconductor device for explaining a conventional technique.

[Explanation of symbols]

1 ... N⁺Type SiC substrate, 2 ... N^-Drift layer, 3 ... First
Gate layer (P⁺Layer), 4 ... N⁺Source layer, 5 ... Trench,
6 ... N^-Channel layer, 7 ... Second gate layer (P ⁺Layers), 3
0 ... P-type impurity region, 31 ... P^-Area, 32 ... P area,
33 ... P⁺region.

Continued front page    (72) Inventor Jun Kojima             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO F-term (reference) 5F102 GB04 GB05 GC05 GC07 GC09                       GD04 GJ02 GL02 GR07 GS01                       GT02 HC07

Claims (6)

[Claims] 1. A first conductivity type SiC which becomes a drain region.
A low-concentration first-conductivity-type drift layer (2) made of SiC is formed on the substrate (1), and SiC is formed on the drift layer (2) or on the surface layer portion of the drift layer (2).
A first conductivity type source layer (4) of
Inside the drift layer (2), a second conductivity type impurity region (3
0) in parallel, the first conductivity type impurity region and the second conductivity type impurity region are alternately buried in the drift layer (2) in the lateral direction to form a super junction, wherein Impurity region (30) has a different concentration in the depth direction. A silicon carbide semiconductor device. 2. A first conductivity type SiC which becomes a drain region.
A low-concentration first-conductivity-type drift layer (2) made of SiC is formed on the substrate (1), and SiC is formed on the drift layer (2) or on the surface layer portion of the drift layer (2).
A first conductivity type source layer (4) of
Inside the drift layer (2), a second conductivity type impurity region (3
0) in parallel, the first conductivity type impurity regions and the second conductivity type impurity regions are alternately buried in the drift layer (2) in the lateral direction to form a superjunction. Impurity region (30) has a lateral width that differs in the depth direction. A silicon carbide semiconductor device. 3. A first conductivity type SiC which becomes a drain region.
A low-concentration first-conductivity-type drift layer (2) made of SiC is formed on the substrate (1), and SiC is formed on the drift layer (2) or on the surface layer portion of the drift layer (2).
A first conductivity type source layer (4) of
Inside the drift layer (2), a second conductivity type impurity region (3
0) in parallel, the first conductivity type impurity regions and the second conductivity type impurity regions are alternately buried in the drift layer (2) in the lateral direction to form a superjunction. Impurity region (30) has a different concentration in the depth direction and a width in the lateral direction that differs in the depth direction. 4. The super junction structure is adopted only in the transistor cell formation region, and the super junction structure is not adopted in the outer peripheral portion of the transistor cell formation region. 2. A silicon carbide semiconductor device according to item 1. 5. A first conductivity type SiC which becomes a drain region.
A low-concentration first-conductivity-type drift layer (2) made of SiC is formed on the substrate (1), and SiC is formed on the drift layer (2) or on the surface layer portion of the drift layer (2).
A first conductivity type source layer (4) of
Inside the drift layer (2), a second conductivity type impurity region (3
0) in parallel to each other to embed the first conductivity type impurity regions and the second conductivity type impurity regions in the drift layer (2) alternately in the lateral direction to form a superjunction silicon carbide semiconductor device. And a step of forming a low-concentration first-conductivity-type drift layer (2) on the first-conductivity-type SiC substrate (1) by epitaxial growth, and a mask (40) for the drift layer (2). Using the first ion implantation to bury the second conductivity type impurity region (31) at a predetermined depth in the drift layer (2) below the mask opening (41); The second ion implantation is performed on (2) using another mask (42), and impurities of the second conductivity type are formed at a predetermined depth in the drift layer (2) below the mask opening (43). Region (32) is the first ion Preparation of a silicon carbide semiconductor device which comprises a step, the embedding state connected with the impurity region of the second conductivity type (31) according to input. 6. A mask opening (41) for the first ion implantation and a mask opening (4) for the second ion implantation.
3) has the same center, and at least one of the area, the implantation energy in the first ion implantation, the implantation energy in the second ion implantation, and the implantation amount of ions is different. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein.