JP2003068991A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FeRAM which improves the crystallinity of PZT and contributes to miniaturization of a ferroelectric capacitor, and a method of manufacturing the same. SOLUTION: Ferroelectric capacitors in FeRAM are:
Ir constituting a part of lower electrode layer of ferroelectric capacitor
A first PZT film and a second PZT film provided on the IrOx film;
And an upper electrode 25 provided on the first and second PZT films 23 and 24. By forming the Ir film 21 and the IrOx film 22 under specific film forming conditions, the crystals of the first and second PZT films 23 and 24 are mainly <111>.
Strongly oriented in the direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it can contribute to miniaturization of devices including a ferroelectric capacitor while improving the crystallinity of the ferroelectric material. Ferroelectric memory (FeRAM: Ferro)
-Electric RAM) and its manufacturing method.

[0002]

2. Description of the Related Art Ferroelectric memories are low power, high speed processing,
Also, it is attracting attention as a non-volatile memory. This memory uses the remanent polarization of a ferroelectric material, and is a conventional EEPROM (Electrically Erasable Program).
Rewriting is faster than mmable ROM) and the number of rewriting can be increased by 3 to 7 digits. Therefore, FeRAM can be used as both a storage memory and a working memory in practical application.
It is very advantageous for system design.

With the miniaturization of semiconductor devices, in FeRAM devices, in order to achieve miniaturization including capacitors, an element in which a ferroelectric capacitor is provided on a plug connected to the source / drain of a transistor has been proposed. There is. In such a stack structure, a structure in which an antioxidant film is provided on the plug is becoming established so that the plug is not oxidized by the crystallization annealing of the ferroelectric film.

[0004]

A ferroelectric capacitor is processed by photolithography and etching. As the size of the capacitor becomes finer, it becomes difficult to reduce the size of the capacitor by etching each layer of the capacitor to form a so-called platform structure.

If it is possible to use batch etching for etching from the upper electrode of the capacitor to the lower electrode including the adhesion layer or the diffusion prevention layer at once, it is possible to form a fine capacitor. In this batch etching, the photolithography process in the middle can be omitted, so that the manufacturing process is shortened. However, when the thickness of the entire capacitor is large, it is difficult to etch a fine shape when batch etching is used.

FIG. 1 is a diagram showing the structure of a conventional ferroelectric capacitor.

The lower electrode of the capacitor shown in FIG. 1A is a titanium (Ti) layer 101 and a platinum (Pt) layer 103.
Are formed from. The lower electrode of the capacitor shown in FIG. 1B has a Pt layer 103 and iridium oxide (Ir).
It is formed of an Ox) layer 109 and an iridium (Ir) layer 111.

In the structure shown in FIGS. 1A and 1B, crystallinity is improved by matching the crystal orientation of the lead zircorate titanate (PZT) layer 105, which is a ferroelectric material, with the crystal orientation of the lower electrode. While it can be improved, it causes a problem that the film thickness of the entire capacitor is significantly increased. Further, in the case of the stack type capacitance, the oxidation prevention film of the plug is required, so that the film thickness of the entire capacitor tends to be further increased.

In the conventional ferroelectric capacitor, P
It has been considered that Pt is necessary for the lower electrode in order to orient the crystals in the ZT layer 105 to (111). P
Since the crystal orientation of ZT has a strong correlation with the electrical characteristics of capacitance, it is important to control the crystal orientation in consideration of the coupling with Pt. On the other hand, the formed Pt film inevitably increases the film thickness of the ferroelectric capacitor.

An object of the present invention is to provide a semiconductor device which can contribute to miniaturization of a ferroelectric capacitor while improving the crystallinity of the ferroelectric material, and a manufacturing method thereof.

[0011]

In order to achieve the above object, in a semiconductor device of the present invention, a ferroelectric capacitor includes a lower electrode composed of an iridium layer and an iridium oxide layer,
It is composed of a lead zircorate titanate (PZT) layer and an upper electrode layer. In this structure, the PZT layer is mainly oriented in the <111> direction. The iridium layer is mainly oriented in the <111> direction, and the iridium oxide layer is mainly oriented in the <200> direction. At that time, the lattice spacing between the iridium (111) plane and the iridium oxide (200) plane is 2.22 angstroms or less.

In another aspect, the present invention provides a method for manufacturing a semiconductor device having a ferroelectric capacitor. The method comprises a step of depositing an iridium layer forming a part of a lower electrode of the ferroelectric capacitor at a temperature higher than 450 ° C., and a step of depositing an iridium layer on the iridium layer at a temperature higher than 300 ° C. and lower than a deposition temperature of the layer. Depositing an iridium oxide layer at a temperature, heating the deposited iridium oxide layer at a temperature equal to or higher than a deposition temperature of the layer, and depositing lead zircolate titanate (PZT) on the heated iridium oxide layer. A) depositing and heating the layers.

Particularly, the step of depositing and heating the PZT layer includes a step of forming a first PZT layer by sputtering and performing crystallization annealing, and a step of forming a film on the first PZT layer with a film thickness larger than that of the first PZT layer. It is preferable to include a step of forming a thick second PZT layer by sputtering and performing crystallization annealing.

According to the present invention, it is possible to orient the PZT crystal in (111) without using platinum, which was conventionally considered to be essential, for the lower electrode. As a result, the film thickness of the entire capacitor can be reduced while maintaining the conventional characteristics. As a result, batch etching of the capacitors is facilitated, and fine capacitors can be formed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 2 shows a FeRAM according to an embodiment of the present invention.
3 is a cross-sectional view illustrating the device structure of FIG. This FeRAM
Includes a memory cell transistor formed on a p-type or n-type silicon substrate 11.

FIG. 2 shows a cross section of such a cell structure, which can be formed by a process similar to a conventional CMOS process. That is, the p-type well 11A is formed on the silicon substrate 11, and the active region defined by the shallow trench isolation (STI) structure 12 is formed in the p-type well 11A. Further, on the silicon substrate 11, a gate electrode 13 is provided corresponding to the above active region, and constitutes a word line of FeRAM.

Further, the silicon substrate 11 and the gate electrode 1
A gate oxide film is provided between the gate electrodes 3 and 3. In the p-type well 11A, n ⁺ -type diffusion regions 11B and 11C are formed on both sides of the gate electrode 13 as a source region and a drain region of the memory cell. Therefore, the channel region is formed in the p-type well 11A between the diffusion region 11B and the diffusion region 11C.

The gate electrode 13 is covered with a CVD oxide film 14 provided so as to cover the surface of the silicon substrate 11, corresponding to the active region. CVD oxide film 1
The lower electrode 15 of the FeRAM is formed on the 4 and the flattening insulating film 14A. As will be described later, in the present embodiment, the lower electrode 15 is formed of the Ir film 21 (see FIG. 5B) and the IrOx film 22 (see FIG. 5C).

On the lower electrode 15, PZT (Pb (Zr,
A ferroelectric film 16 made of Ti) O ₃ ) is formed. As will be described later, in the present embodiment, the ferroelectric film 16
Is the first PZT film 23 having a different film thickness (see FIG. 5D).
And the second PZT film 24 (see FIG. 6E).

An upper electrode 17 made of Pt or the like is formed on the ferroelectric film 16. The lower electrode 15, the ferroelectric film 16 and the upper electrode 17 form a ferroelectric capacitor, and the entire ferroelectric capacitor is formed by another interlayer insulating film 1.
Covered by 8.

A contact hole 18A exposing the upper electrode 17 is formed on the interlayer insulating film 18. Also,
A contact hole 18C exposing the diffusion region 11C is formed, and a via plug 20 is provided so as to electrically contact the diffusion region 11C and a bit line pattern 19B described later through the contact hole 18C.

Further, a via plug 21 is provided in the flattening insulating film 14A so as to electrically contact the diffusion region 11B and the lower electrode 15. Furthermore, the diffusion region 1 is formed on the interlayer insulating film 18 via the via plug 20.
A bit line pattern 19B made of an Al alloy is formed so as to make electrical contact with 1C.

Next, before explaining the method for manufacturing FeRAM according to the present embodiment, the concept of the present invention will be briefly explained through some experimental results included in the present invention.

FIG. 3 is a diagram for explaining the relationship between the film formation temperature of the Ir film forming a part of the lower electrode 15 of the FeRAM according to this embodiment and the (111) diffraction intensity of the Ir film.

This figure shows that in the deposition of the Ir film, the (11)
1) It shows that the diffraction intensity becomes strong. Specifically, a change in strength can be seen at the film formation temperature exceeding 450 ° C. Further, it is shown that the intensity change becomes larger at the film forming temperature of 500 ° C. as a boundary, and at the film forming temperature of 550 ° C., the diffraction intensity substantially rises to the intensity change. That is, it can be seen that the (111) diffraction intensity of the Ir film is increased by increasing the Ir film formation temperature.

FIG. 4 is a diagram for explaining the relationship between the film formation temperature of the Ir film forming a part of the lower electrode 15 of the FeRAM according to this embodiment and the (111) diffraction intensity of the PZT film 16.

In this figure, two types of experimental results are shown. One is an IrOx film provided on the Ir film.
There is a relation between the film forming temperature of the Ir film when formed at 00 ° C. and the (111) diffraction intensity (illustrated by ▪) of the PZT film. It is the relationship between the film formation temperature of the film and the (111) diffraction intensity of the PZT film (illustrated by ●).

Referring to FIG. 4, when the film forming temperature of the IrOx film is 300 ° C., the (111) diffraction intensity of the PZT film finally formed is increased even if the film forming temperature of the Ir film thereunder is increased. It does not change so much and only slightly increases at a film forming temperature of more than 500 ° C. On the other hand, when the film formation temperature of the IrOx film is 400 ° C., the (111) diffraction intensity of the PZT film finally formed increases as the film formation temperature of the Ir film below it increases as in FIG. I understand.

Specifically, the Ir film formation temperature is 450 ° C.
The PZT (111) diffraction intensity starts to increase when the temperature exceeds 1.0 ° C., and when the film forming temperature exceeds 500 ° C., a very remarkable increase in the diffraction intensity occurs. It can be seen that when the film forming temperature of the Ir film is 550 ° C., the intensity reaches more than 4 times the diffraction intensity when the film forming temperature is 400 ° C.

It is known that it is necessary to realize the (111) crystal orientation of the PZT film in order to improve the electrical characteristics of the ferroelectric capacitor. From the experimental results shown in FIGS. 3 and 4, the Ir film was formed at a film forming temperature of higher than 450 ° C., and the IrOx film was formed at a film forming temperature of at least 300 ° C. and not exceeding the above-mentioned film forming temperature of the Ir film. It can be seen that the (111) crystal orientation of the PZT film can be strengthened by forming the film. Paying attention to this point, in the present embodiment, Pt, which has been concerned about the thickness of the film until now,
The device design of the ferroelectric capacitor is performed without using as a lower electrode.

5 and 6 show FeRA according to the present embodiment.
FIG. 6 is a diagram illustrating a manufacturing process of M.

FIG. 5A shows a SiON film 45 and a Si film formed by a normal CMOS transistor forming process and a CVD method.
Step of sequentially providing an interlayer film such as an O ₂ film 46, W plug 47
A step of providing A to 47E, and the antioxidant film 48 and Si
The figure shows a state in which the steps of sequentially providing the O ₂ film 49 have been completed, so to speak, a structure which is a prerequisite for the manufacturing process according to the present embodiment.

First, the CMOS process will be briefly described. A p-type well 41A and an n-type well 41B are formed on a p-type or n-type Si substrate 41. Further, the Si substrate 41 is covered with the field oxide film 42 that defines the active region of each well 41A and 41B. A gate oxide film 43 is formed on each active region of the p-type well 41A and the n-type well 41B. In the p-type well 41A, the p-type polysilicon gate electrode 44A is formed on the gate oxide film 43, and the n-type well 4 is formed.
In 1B, an n-type polysilicon gate electrode 44B is formed on the gate oxide film 43. Like the polysilicon gate electrode 44A or 44B, the field oxide film 4
Polysilicon wiring patterns 44C and 44D extend on the upper surface 2. Further, n-type diffusion regions 41a and 41b are formed by ion-implanting n-type impurities into the active region of the p-type well 41A, and the n-type well 41B is formed.
P-type diffusion regions 41c and 41d are formed in the active region.

Next, the SiON film 45 and the SiO ₂ film 4
The process of sequentially providing 6 will be described. A SiON film 45 is deposited on the structure after the CMOS process by the CVD method, and a SiO ₂ film 46 is further deposited thereon by the CVD method. Here, the SiO ₂ film 46 is polished and flattened by the CMP method using the SiON film 45 as a stopper. Then, in the flattened SiO ₂ film 46, contact holes (not shown) are formed in the diffusion regions 41a, 41b, respectively.
It is formed so that 41c and 41d are exposed.

Next, a W layer (not shown) is deposited on the structure after the above step so as to fill the contact hole, and the W layer is polished by the CMP method using the SiO ₂ film 46 as a stopper. Flatten. As a result, the W plugs 47A to 4A corresponding to the contact holes are formed.
7E is formed. Next, on the structure after the above steps, S
An antioxidant film 48 made of iON and a SiO ₂ film 49 (corresponding to the CVD oxide film 14 in FIG. 2) are formed, and heat treatment is further performed in an N ₂ atmosphere to sufficiently degas.

The manufacturing process of the ferroelectric capacitor portion will be described with reference to FIG. First, in the process of FIG. 5B, CVD in the structure of FIG.
An Ir film 21 forming a part of the lower electrode on the oxide film 14.
Deposit. In this embodiment mode, a film is formed by a DC magnetron sputtering method. The film forming conditions are preferably a film forming temperature of 500 ° C. or higher (see FIG. 3) and a film thickness of about 200.
nm, sputtering power 1.0 kW and Ar flow rate =
It is 100 sccm. Further, it should be noted that the crystal orientation of Ir can be strengthened by lowering the sputtering rate. Here, the film forming rate is set to 200 nm / 144 sec (about 1.39 nm / se).
It is set to c).

Further, since the Ir film 21 is used as an antioxidant film for preventing the W plug 47A and the like from being oxidized, the film thickness is set to 150 nm or more. The thicker the Ir film 21 is, the more the oxidation of the W plug can be prevented against higher-temperature oxygen annealing (various kinds of annealing required in the FeRAM formation process).

Next, in the step of FIG.
The IrOx film 22 is formed on the Ir film 21 in the structure (B).
Deposit. In this embodiment mode, a film is formed by reactive sputtering by a DC magnetron sputtering method. The film forming conditions are preferably a film forming temperature of 400 ° C. or higher (see FIG. 4), a film thickness of about 50 nm, a sputtering power of 1.0 kW, and an Ar / O ₂ flow rate of 25 sccm / 25 s.
It is ccm.

Next, after the IrOx film 22 is formed by the above reactive sputtering, annealing is performed in an oxygen atmosphere. The annealing conditions are 400 ° C. and 30 minutes, and the temperature needs to be the above film formation temperature or higher. Here, not only the crystallinity control of the IrOx film 22 but also the stress control of the multilayer film forming the lower electrode is performed.

Next, in the step of FIG.
The first PZT is formed on the IrOx film 22 in the structure of FIG.
The film 23 is formed. In this embodiment mode, a film is formed by an RF sputtering method. The film forming conditions are room temperature film forming, a film thickness of about 10 nm, a sputtering power of 1.0 kW, and an Ar flow rate of 35 sccm.

Next, after forming the first PZT film 23 by the RF sputtering, crystallization annealing is performed in an oxygen atmosphere. Annealing conditions are 550 ° C and 3
It is 0 minutes, and the temperature needs to be the film formation temperature or higher.

Next, in the step of FIG.
The second PZ is formed on the first PZT film 23 in the structure (D).
The T film 24 is formed. In this embodiment mode, a film is formed by an RF sputtering method. The film forming conditions are room temperature film forming, film thickness of about 90 nm, sputtering power of 1.0 kW and Ar.
Flow rate = 35 sccm.

Next, after the second PZT film 24 is formed by the RF sputtering, RTA in an oxygen atmosphere is performed.
Crystallization annealing is performed by (rapid heat treatment). Regarding the annealing conditions, first, annealing is performed in an atmosphere of 600 ° C. for 90 seconds, a heating rate of 100 ° C./sec, and an oxygen concentration of 2.5%. Then, annealing is performed in an atmosphere of 750 ° C. for 60 seconds, a temperature rising rate of 100 ° C./sec, and an oxygen concentration of 100%.

Next, in the step of FIG.
After forming the second PZT film 24 in the structure of (E), for example, a Pt film or the like is formed as the upper electrode 25. Next, in the step of FIG. 6G, the capacitor shown in FIG. 6F is processed. In this embodiment mode, processing is performed by collective etching. As a result, a ferroelectric capacitor including the Ir pattern 21A and IrOx pattern 22A, the first PZT pattern 23A, the second PZT pattern 24A, and the upper electrode pattern 25A, which form the lower electrode, is formed.

FIG. 7 is a diagram showing diffraction patterns of the ferroelectric capacitors according to some embodiments including the ferroelectric capacitors in the FeRAM according to the present embodiment.

FIG. 7 (A) corresponds to the characteristics according to the present embodiment, and the Ir film is 500 ° C. and the IrOx film is 40 ° C.
X of PZT film when each film is formed at 0 ° C.
The line diffraction pattern is shown. Here, compared with other lattice planes (100), (101), (110), etc., (1
It is shown that the diffraction intensity of 11) is high. This time,
The crystal orientation of the Ir film is mainly the (111) plane,
The crystal orientation of the Ox film is mainly the (200) plane.

FIG. 7B shows the Ir film at 550 ° C. and Ir.
The X-ray diffraction characteristics of the PZT film when the Ox film is formed at a film forming temperature of 400 ° C. are shown. Compared to FIG. 7A, it is shown that the diffraction intensity of (111) becomes higher by fixing the film forming temperature of the IrOx film and raising the film forming temperature of the Ir film by 50 ° C. There is.

FIG. 7C shows the Ir film at 550 ° C. and Ir.
The X-ray diffraction pattern of the PZT film when the Ox film is formed at a film forming temperature of 300 ° C. is shown. FIG. 7 (A)
In comparison with (11), the film formation temperature of the IrOx film is lowered by 100 ° C. and the film formation temperature of the Ir film is fixed.
Almost no diffraction intensity of 1) is observed. This is because, as described above, the film formation temperature of the IrOx film formed on the Ir film has not reached the temperature necessary to improve the (111) diffraction intensity of the PZT film (see FIG. 4).
In this case, the crystals of the PZT film are mainly oriented in the <100> or <001> direction instead of the <111> direction.

FIG. 8 shows the film formation temperature T and the lattice spacing d of the Ir film and the IrOx film which form the FeRAM according to the present embodiment.
It is a figure explaining the relationship with.

Referring to FIG. 8, on the (111) plane of the Ir film, the lattice spacing d is 2.22 at a film forming temperature of 500 ° C. or higher.
It can be seen that it is less than Angstrom. Also, IrO
On the (200) plane of the x film, it can be seen that the lattice spacing d is 2.22 angstroms or less at the film formation temperature of 400 ° C. or higher.

As described above, the FeRAM according to the present embodiment
Then, the lower electrode is formed by the Ir film 21 and the IrOx film 22. Further, in the present embodiment, the ferroelectric film 16 is formed in two steps as the first PZT layer 23 and the second PZT layer 24 having different film thicknesses. PZT film formation 2
By performing the process in a divided manner, it is possible to prevent the metal forming the lower electrode from diffusing into PZT in the first PZT film 23. Further, by growing the second PZT film 24 using the first PZT film 23 as a seed layer,
Even with PZT having a thin film thickness of 100 nm, the leak current can be suppressed low.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and structural changes such as a device size and / or setting parameters in a manufacturing process, etc. There may be changes in method. Hereinafter, these points will be described.

For example, in the above embodiment, attention is paid to the crystal orientation and miniaturization of the so-called lower interface between the lower electrode and the PZT film. Therefore, the material of the upper electrode does not limit the present invention.

In the above embodiment, the PZT film is formed by the sputtering method, but it may be formed by the sol-gel method or the CVD method. Further, PZT can be doped with various impurities (Ca, Sr, La, etc.) according to the characteristics of the capacitor.

[0056]

According to the present invention, it is possible to improve the crystallinity of PZT and realize a device design that does not use Pt for which the film thickness is a concern for the lower electrode.
This can also contribute to miniaturization of the ferroelectric capacitor.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a conventional ferroelectric capacitor.

FIG. 2 is a sectional view illustrating a device structure of FeRAM according to an embodiment of the present invention.

FIG. 3 is a view showing a film formation temperature of an Ir film forming a part of a lower electrode of FeRAM according to an embodiment of the present invention- (111) of an Ir film.
It is a figure explaining a diffraction intensity.

FIG. 4 is a diagram showing a deposition temperature of an Ir film forming a part of a lower electrode of FeRAM according to an embodiment of the present invention- (11) of a PZT film.
1) It is a figure explaining diffraction intensity.

FIG. 5 is a diagram illustrating a manufacturing process (No. 1) of the FeRAM according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process (No. 2) of the FeRAM according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating diffraction characteristics of various capacitors including a ferroelectric capacitor in FeRAM according to the embodiment of the present invention.

FIG. 8 is a view showing I configuring a FeRAM according to an embodiment of the present invention.
It is a figure explaining the relationship of the film-forming temperature T of the r film | membrane and IrOx film-lattice plane space | interval d.

[Explanation of symbols]

11 silicon substrate 11A p-type wells 11B and 11C n ⁺ type diffusion region 12 STI structure 13 gate electrode 14 CVD oxide film 14A flattening insulating film 15 lower electrode 16 ferroelectric film 17 upper electrode 18 interlayer insulating film 18A, 18C contact Hole 19B Bit wiring pattern 20, 21 Via plug 21 Ir film 21A Ir pattern 22 IrOx film 22A IrOx pattern 23 First PZT film 23A First PZT pattern 24 Second PZT film 24A Second PZT pattern 25 Upper electrode 25A Upper electrode pattern 41 Si substrate 41A p-type Well 41B n-type wells 41a and 41b n-type diffusion regions 41c and 41d p-type diffusion region 42 field oxide film 43 gate oxide film 44A p-type polysilicon gate electrode 44B n-type polysilicon gate electrodes 44C and 44D poly Reconfigurable interconnect pattern 45 SiON film 46 SiO ₂ film 47A～47E W plug 48 antioxidant film 49 SiO ₂ film

Claims (5)

[Claims] 1. A semiconductor device having a ferroelectric capacitor, comprising: an iridium layer forming a part of a lower electrode layer of the ferroelectric capacitor; and an iridium oxide layer provided on the iridium layer. Further comprising: a lead zirconate titanate layer provided on the iridium oxide layer; and an upper electrode layer provided on the lead zircolate titanate layer, the lead zirconate titanate layer Are mainly oriented in the <111> direction. 2. The semiconductor device according to claim 1, wherein the (111) lattice spacing of the iridium layer is 2.22 angstroms or less. 3. The semiconductor device according to claim 1, wherein the (200) lattice spacing of the iridium oxide layer is 2.22 angstroms or less. 4. A method of manufacturing a semiconductor device having a ferroelectric capacitor, comprising: depositing an iridium layer forming a part of a lower electrode of the ferroelectric capacitor at a temperature higher than 450 ° C .; Depositing an iridium oxide layer above the layer at a temperature above 300 ° C. and below the deposition temperature of the layer; heating the deposited iridium oxide layer at a temperature above the deposition temperature of the layer; And a step of depositing a lead zircolate titanate (PZT) layer on the heated iridium oxide layer and heating the same. 5. The step of depositing and heating the PZT layer comprises: forming a first PZT layer by sputtering and performing crystallization annealing; and forming a film on the first PZT layer more than the first PZT layer. The method for manufacturing a semiconductor device according to claim 4, further comprising: a step of forming a thick second PZT layer by sputtering and performing crystallization annealing.