JP2003068861A - Semiconductor switch apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor switch apparatus that can widen the bandwidth of high-frequency continuity loss characteristics. SOLUTION: Each of LDMOSFETs Q1 and Q2 has a base electrode 112 separated from a source electrode 111, a terminal for drive is connected to the base electrode 112 and the semiconductor support substrate of a semiconductor chip, and at the same time is connected to the common ground of a drive circuit 414 and a high frequency, the number of LC series resonance elements for connecting a high-frequency signal line to the high-frequency ground is decreased to one, the occurrence of dips is reduced, flatness in continuity loss characteristics is improved, and at the same time the bandwidth of the high-frequency continuity loss characteristics is widened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switch device that passes / blocks a high frequency signal by turning on / off a semiconductor switch element.

[0002]

2. Description of the Related Art In FIG. 7, a gate electrode 503 of one MOSFET Q10 and a gate electrode 504 of another MOFET Q20 have a common potential, and one MOSFET Q10 has a common potential.
10 shows an example of a conventional semiconductor switching device using two MOSFETs Q10 and Q20 connected in anti-series so that the source electrode 505 of the MOSFET 10 and the source electrode 506 of the other MOSFET Q20 have a common potential. In the device, the drain electrode 507 of the MOSFET Q10 is connected to one switch terminal 509 for passing a high frequency signal, and the drain electrode 508 of the other MOSFET Q20 is connected to the other switch terminal 510 for passing a high frequency signal, A drive circuit 514 is connected to the source electrode side terminal 520 and the gate electrode side terminal 521 for applying drive power.

The drive circuit 514 is composed of a drive power supply 519, and the drive power supply 519 is coupled to a high frequency ground 530 via a parasitic capacitance 529 generated between the ground.

The semiconductor switch device having the above-mentioned structure is constructed such that the source electrodes 50 of both MOSFETs Q10 and Q20 are provided.
The gate electrode 50 based on the common potential 511 of 5, 506
The common potential 512 of 3,504 is directly voltage-driven, and the
When the gate-source voltage exceeds the operation threshold voltage of the FETs Q10 and Q20, two MOSFETs Q1
0 and Q20 are in conduction with Okamochi, and switch terminal 50
The conduction path of the high frequency signal formed between 9, 510 is closed.

When the gate-source voltage becomes lower than the threshold voltage, the two MOSFETs Q10 and Q20 are simultaneously cut off, and the conduction path for high frequency signals is opened.

FIG. 8 shows the structure of a MOSFET used in a conventional example. This MOSFET is a semiconductor support substrate 60.
1. A semiconductor substrate on which a semiconductor layer 603 is formed with a buried oxide film 602 as an insulating film interposed therebetween is used, and an n + type drain region 6 is formed on the surface of the semiconductor layer 603 of the semiconductor substrate.
04 and the p-type well region 605 are formed separately from each other, and n as a source region is included in the well region 605.
A + type source region 606 is formed.

On the surface of the semiconductor layer 603, a thin gate oxide film 608 is provided on the channel region 607 existing between the drain region 604 and the source region 606 and in the well region 605. A conductive polysilicon film 609 is formed to form an insulated gate structure.

A drain electrode 610 made of aluminum (Al) or the like is formed so as to be electrically connected to the drain region 604, and Al or the like is formed so as to electrically connect the source region 606 and the well region 606. A source electrode 611 also made of Al is formed, and a gate electrode 613 made of Al or the like is formed so as to be electrically formed with the polysilicon film 609.

In this conventional MOSFET, the base electrode and the source electrode have a common potential and are in a floating state with respect to the ground, so that the parasitic capacitance between the ground exists as described above.

FIG. 9 shows an equivalent LCR network circuit diagram in a semiconductor chip constituting a conventional semiconductor switch device. In the conventional example, as shown in FIG.
For ET, LC series resonant element of shunt arm,
It is composed of one series resonance element 802 and another series resonance element (803) which is hierarchically compounded inside the series resonance element 802. Here, the breakdown of the larger series resonance element 802 is that the capacitor C805 is the drive power source 5
19, the parasitic capacitance to ground (corresponding to the parasitic capacitance 529 in FIG. 7) with respect to the high frequency ground, the inductor 806 starts from the source pad of the semiconductor chip, and the drive power source 519
It is the inductance due to the wire wiring up to.

The breakdown of the built-in series resonance element 803 is that the capacitor 807 is a gate oxide film capacitor and the inductor 80 is a capacitor.
Reference numeral 8 is the inductance due to the wire wiring from the gate pad of the semiconductor chip to the drive power source 519.

[0012]

In the semiconductor switch device having the above-mentioned conventional structure, the conduction path of the high frequency signal is composed of the two MOSFETs Q10 and Q20, and the capacitance component is inserted in series in the conduction path. However, it has the advantage that a frequency that can be passed is from DC and that a relatively wideband signal can be handled, but the switch terminals 509 and 510 through which a high-frequency signal passes.
There is a problem that the pass band becomes narrow (up to several hundred MHz band at most) in the high frequency conduction characteristic between them.

That is, when the LC series resonance elements are hierarchically constructed as shown by the above equivalent circuit, the notch filter operates at each resonance frequency and the dip occurs at the resonance frequency in the frequency-dependent waveform of the conduction loss. As they occur, a new secondary dip appears at a frequency approximately equal to the difference between the two resonance frequencies, and this secondary dip dominates the frequency band of the conduction characteristics of the semiconductor switch device (upper limit frequency of flat characteristics). This is because

There is a drive circuit of a semiconductor switch device which has a wide band by what is called an optical insulation type drive. Instead of directly connecting the semiconductor switch device and the drive circuit, the drive circuit side is provided with a light emitting element such as a light emitting diode, and the semiconductor switch device is provided with a light receiving element such as a solar cell.
The semiconductor switch device is controlled by the electromotive force of the light receiving element that receives the light of the light emitting element and is wired so as to be optically coupled to each other. In this case, it is electrically isolated in the middle of the drive circuit. That is, minute (about 500 fF)
There is only capacitive coupling of about several GHz in conduction characteristics
The pass band of is obtained. However, in terms of switching characteristics, the high speed of the original semiconductor switch (approximately 10 nsec)
There is a problem that you can't make the most of it. This is because the charging / discharging time of the solar cell of the light receiving element is slow and the switching time of the entire device is delayed (about 100 μsec).

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor switch device capable of widening the band of high frequency conduction loss characteristics.

[0016]

In order to achieve the above object, in the invention of a semiconductor switch device according to claim 1, a series circuit of two semiconductor switch elements consisting of transistors for turning on / off a conduction path of a high frequency signal is provided. , A drive circuit for driving both semiconductor switch elements, wherein the both semiconductor switch elements are formed on one semiconductor chip, and the first main electrodes and control electrodes of both semiconductor switches are inside the semiconductor chip. The second main electrode side terminal of the one semiconductor switch element is connected to the one side switch terminal through which the high frequency signal passes, and the second main electrode side terminal of the other semiconductor switch element passes through the high frequency signal. The other switch terminals are respectively configured to drive one of the two drive terminals for applying drive power to the two semiconductor switch elements. In the semiconductor switch device in which the control terminal is connected to the control electrodes of both semiconductor switches inside the semiconductor chip and is connected to the signal line of the drive circuit, a base electrode separate from the first main electrode is provided in both of the semiconductor switch elements. A drive terminal on the other side of the two drive terminals is connected to the base electrode and the semiconductor support substrate of the semiconductor chip inside the package in which the semiconductor chip is mounted, and the high frequency and the drive circuit are common. It is connected to the ground of.

According to a second aspect of the present invention, there is provided the semiconductor switch device according to the first aspect, wherein the semiconductor chip substrate is a silicon-on-insulator substrate having an insulating layer sandwiched between a semiconductor layer and a semiconductor support substrate. In the semiconductor switch element, the high-concentration first-conductivity-type drain region and the second-conductivity-type well region formed separately in the semiconductor layer and the high-concentration first-concentration region formed in the well region are used. A conductive type source region, a gate electrode forming the control electrode formed on the well region interposed between the drain region and the source region via a gate insulating film, the well region and the drain A drift region formed between the drain region and the region, and a drain electrode forming the second main electrode formed on the drain region. A double diffusion lateral MOSFET having a source electrode forming the first main electrode formed on the source region and the base electrode formed on a region apart from the gate insulating film on the well region. It is characterized by being formed.

According to the invention of a semiconductor switch device of claim 3, in the invention of claim 2, the double diffusion lateral type M
Each semiconductor switching element composed of an OSFET is provided with a channel region in a well region corresponding to the gate electrode, and a gate oxide film forming the gate insulating film so as to be sandwiched between the channel region and the gate electrode, The sum of the length of wiring from the gate electrode to the high frequency ground plane via the drive circuit and the length of wiring from the base electrode to the high frequency ground plane is L (mm), and the gate oxide film thickness is tox. (Μm), the length of the channel region is Lg (μm), and the total width of the channel region is W.
g (μm), L × Lg × Wg / tox <6.
It is characterized by satisfying 7 × 10 ⁵ .

According to a fourth aspect of the present invention, there is provided the semiconductor switch device according to the second or third aspect, wherein the inside of the package is connected to a metal frame for fixing the semiconductor chip, a metal frame through which a high frequency signal passes, and a drive circuit. The length of the wire connecting the metal frame through which the high-frequency signal passes and the semiconductor switch element is Lw (mm), and the thickness of the buried oxide film forming the insulating layer of the semiconductor substrate is tbox. (Μm) and the bottom area S of the drift region surrounding the drain region in contact with the buried oxide film is (μm ² ),
It is characterized by satisfying S × Lw / tbox <7.2 × 10 ⁵ .

According to the invention of a semiconductor switch device of claim 5, in the invention of any one of claims 1 to 4, an operational amplifier having an output terminal connected to an output signal terminal and an inverting input terminal, and the operational amplifier A sample-hold circuit is composed of a hold capacitor connected between the non-inverting input terminal and the ground, and a series circuit of the two semiconductor switch elements inserted between the input signal terminal and the input terminal of the operational amplifier. It is characterized by

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to embodiments.

The SOI (Silicon) according to the present embodiment
On Insulator) structure type double diffusion lateral type M
The OSFET (hereinafter referred to as LDMOSFET) uses an SOI substrate in which a semiconductor layer 103 is formed on a semiconductor supporting substrate 101 via a buried oxide film 102 which is an insulating film as shown in FIG. An n + type drain region 104, which is a high-concentration first conductivity type drain region, and a p type well region 105, which is a second conductivity type well region, are formed separately from each other on the surface of the well region 1.
An n + type source region 106, which is a high-concentration first conductivity type source region, is formed so as to be included in 05.

On the surface of the semiconductor layer 103, a thin gate oxide film 108 is formed on the channel region 107 existing between the drain region 104 and the source region 106 and in the well region 105. A conductive polysilicon film 109 is formed to form an insulated gate structure. In addition, the well region 105 and the drain region 10
A drift region is formed between the drift regions.

A drain electrode 110 made of aluminum (Al) or the like is formed so as to be electrically connected to the drain region 104, and a source electrode made of Al or the like is formed so as to be electrically connected to the source region 106. 111
So as to be electrically connected to the well region 105.
And the like, and a gate electrode 113 made of Al or the like is further formed so as to be electrically formed with the polysilicon film 109.

Here, the length Lg of the gate electrode 113 is set to 1.
2 μm, the thickness tox of the gate oxide film 108 is 0.05 μm
m, the length of the channel region 107 in the direction perpendicular to the paper surface of FIG. 2 (total width of the channel region 107) Wg is 4000 μm
I am trying. In addition, the film thickness tbo of the buried oxide film 102
x is set to 2 μm. Furthermore, L0 in the figure indicates the length of the bottom surface where the drain region 104 and the drift region are in contact with the buried oxide film 102, and the bottom area S considering this two-dimensional spread is set to 80,000 μm ² .

FIG. 3 shows two LDMs of the above SOI structure type.
Form OSFETs Q1 and Q2 on the chip
The schematic surface view of the semiconductor chip 302 which has Q2 electrically connected in series is shown.

Here, in the SOI structure type device, a capacitor structure is formed between the semiconductor supporting substrate 101 and the diffusion region formed in the semiconductor layer 103 via the buried oxide film 102, and a high frequency is generated as a capacitance between substrates (Cdsub). Affect the characteristics. Designing the surface layout of the diffusion region in the semiconductor substrate 103 that minimizes the inter-substrate capacitance realizes a semiconductor switch device with improved high frequency pass characteristics by using an SOI structure type LDMOSFET in the contact portion of the switch. Important above.

Therefore, in the present embodiment, in addition to the above-described structure, the drain region 104 is arranged in the approximate center as shown in FIG. 2, and the channel region 10 is surrounded so as to surround the outer periphery thereof.
7 and RACETRACK with well region 105 formed
The surface layout of the shape is used.

Here, two LDMOSFETs Q1 and Q
2 drain electrodes 115 and 116 for electrically connecting to the respective drain electrodes 110, and a source electrode 111
Common source pad 11 for electrical connection with
7, a common base pad 118 for making an electrical connection with the base electrode 112, and a common gate pad 119 for making an electrical connection with the gate electrode 113.

FIG. 4 shows an example of mounting the semiconductor chip 302 shown in FIG. 3 in the package X. In this mounting example,
The semiconductor support substrate 101 of the semiconductor chip 302 is die-bonded on a conductive lead frame (metal frame) 301 using a conductive base, and the drain pads 115 and 116 are switch terminals 303 and 304 made of a metal frame. Drain wires 311, 31 respectively
Wire-bonded by 2 and gate pad 119
Is wire-bonded to the driving signal input terminal 305 made of a metal frame by the gate wire 313, the source pad 117 is wire-bonded to the terminal 306 made of a metal frame by the source wire 314, and the base pad 118 is the lead frame 301 and the base wire. Wire bonding is performed by 315, and the lead terminals 301 are further connected to the base terminals 307, 30.
8, 309 and 310 are integrally formed.

Here, the switch terminals 303 and 304 through which a high-frequency signal opened and closed by the series circuit of the LDMOSFETs Q1 and Q2 passes, and the input terminal 305 and the terminal 306 to which the driving power of the semiconductor switch device is applied are separated by the base frame 301. Arranged to do so.

Here, of the high-frequency signal wiring length starting from the drain electrode 110 on one side and ending at the next component via the pattern of the electronic circuit board on which the semiconductor switching device is arranged, the inductance in the semiconductor switching device SW. The sum of the lengths Lw (the sum of the lengths of the wires in the package X and the lead frame) that contributes to the above is set to 18 mm in the mounting example of FIG. The contribution of the inductance due to this is 18 nH (converted to 1 nH / 1 mm).

Next, FIG. 1 shows a circuit diagram of a semiconductor switch device using the semiconductor chip 302 mounted on the package X as shown in FIG.

Here, the gate electrode 113 of one LDMOSFET Q1 and the gate electrode 113 of the other LDMOSFET Q2 are common gate pad 1 as described above.
19 is commonly connected in the semiconductor chip 302, so that the potentials a of both gate electrodes 113, 113 are the same.

The source electrode 111 of the one LDMOSFET Q1 and the source electrode 111 of the other LDMOSFET Q2 are connected to the semiconductor chip 302 on the source pad 117.
Both LDMOSFETQ are connected in common in
1 and Q2 are connected in anti-series.

Further, the base electrode 112 of the one LDMOSFET Q1 and the base electrode 112 of the other LDMOSFET Q2 are commonly connected to the common base pad 118 in the semiconductor chip 302.
The potentials b of 2,112 are the same potential.

Furthermore, both LDMOSFETs Q1 and Q2 are formed on a common semiconductor supporting substrate 101, and the semiconductor supporting substrate 101 is electrically connected to the lead frame 301, so that the potential c of both semiconductor supporting substrates 101 becomes the above base. The potential of the base pad 118 electrically connected to the lead frame 301 by the wire 315, that is, both L
Base electrodes 112, 112 of the DMOSFETs Q1, Q2
It has the same potential as the potential b.

The switch terminal 303 on the drain electrode 110 side of one LDMOSFETQ1 becomes one switch terminal through which a high frequency signal passes, and the other LDM.
The switch terminal 304 on the drain electrode 110 side of the OSFET Q2 serves as the other switch terminal for the high frequency signal.

The common potential b on the side of the base electrode 112 is connected to the high frequency ground 430, the common potential a on the side of the gate electrode 113 is connected to the drive circuit 414, and the drive circuit 41.
The other end of 4 is connected to the high frequency ground 430.

Here, the wiring 431a starting from each gate electrode 113 of each LDMOSFET Q1, Q2 to the high frequency ground 430 via the drive circuit 414, and each LD.
Of the wiring 431b starting from the base electrodes 112 of the MOSFETs Q1 and Q2 and reaching the high frequency ground 430, the total wiring length of the wire and the lead frame that contribute to the inductance in the semiconductor chip 302 is 7 m in the mounting example.
It is as m.

The contribution of the inductance by this is 7 nH
(Converted to 1 nH / 1 mm). The drive power source 419 that constitutes the drive circuit 414 is a high-level voltage that makes the LDMOSFETs Q1 and Q2 conductive, and the LDMOSFETQ.
1 and Q2 are both low-level voltage to shut off LDM
A pulse waveform signal that is alternately applied to the gate electrodes 113 of the OSFETs Q1 and Q2 is output.

Here, the high level voltage refers to the common potential a on the gate electrode 113 side with respect to the potential of the high frequency ground 430.
Is a voltage value higher than the thresholds of the LDMOSFETs Q1 and Q2 (preferably about 3V or more), and the low-level voltage is the threshold of the LDMOSFETs Q1 and Q2 with respect to the potential of the high frequency ground 430. It is a voltage value (preferably about 0 V) below the value.

With the time ratio (duty ratio) of the high and low level voltages being approximately 50%, the signal frequency range is several k.
It is possible to take from Hz to several tens of MHz.

FIG. 5 shows an equivalent LCR network circuit diagram in the semiconductor switch device of this embodiment shown in FIG. First, in order to improve the frequency band of conduction loss in this network circuit, a design for increasing the resonance frequency of two internal circuit elements is derived as a problem.

Circuit element (1) LC series resonance element → acts as a band rejection filter (notch filter) with a shunt arm applied between the high frequency signal path and the high frequency ground.

Circuit element (2) LC resonance element due to the inductance on the high frequency signal path (series arm) and the capacitance of the shunt arm → acts as a low pass filter (low pass filter).

In the case of either filter, the resonance frequency fo
The form of is given by the formula.

However, L of the inductance and C of the capacitance in the equation change depending on each resonance element.

Fo = 1 / (2π√ (LC)) The equivalent circuit of the above-described conventional semiconductor switch device is configured as shown in FIG. 8, and the notch filter operates at each resonance frequency and the conduction loss depends on the frequency. In the characteristic waveform, a dip occurs at the above resonance frequency, and a new secondary dip appears at a frequency approximately equal to the difference between the two resonance frequencies, and this secondary dip is the frequency band of the conduction characteristic of the semiconductor switch device. There is a problem that it governs (upper limit frequency of flatness characteristics).

On the other hand, in the mounting example of the semiconductor chip 302 used in this embodiment, the LC series resonance element of the circuit element (1) (LC series resonance element of shunt arm) is provided for one transistor, that is, LDMOSFET. It is one. Here, the breakdown of the series resonance element 804 includes wiring starting from the gate electrode 113 and reaching the surface of the high frequency ground 430 via the drive circuit 414 and wiring starting from the base electrode 112 and reaching the surface of the high frequency ground 430. , An inductor 809, which is the sum L of the wiring length using wires that contribute to the inductance, and a gate oxide film capacitance 810.

Since the LC series resonance element is one of the LC series resonance elements 804 for one LDMOSFET, a dip occurs at the resonance frequency, but there is no secondary dip other than that, so that the band of the high frequency conduction characteristic is reduced. (Frequency upper limit frequency) is not reduced.

Here, in the present embodiment, the drive circuit 41
The sum of the lengths of wiring extending to the surface of high-frequency ground 430 via 4 and the length of wiring starting from the base electrode 112 and reaching the surface of high-frequency ground 430 is L (mm).
The gate oxide film thickness of T is tox (μm), the length of the channel region is Lg (μm), and the total width of the channel region is Wg.
(Μm), L × Lg × Wg / tox <6.7 × 10 ⁵ is satisfied to reduce L × C of the circuit element (1) and increase the notch frequency at which a dip appears. The resonance frequency is 1.0 GHz or higher when applied to the equation.

Further, in FIG. 5, the inductor 812 is an LD
A wiring inductor starting from the drain electrode 110 of the MOSFET and ending at the pattern of the electronic circuit board on which the semiconductor switch device is mounted. The wiring inductor mainly corresponds to the wire frame length Lw inside the package, and the capacitor 813 is the semiconductor chip. This is the inter-substrate capacitance between the drain electrode 110 of 312 and the semiconductor support substrate 101 on the back surface side of the SOI substrate.

These LC correspond to the circuit element 2 (LC resonance element of the low-pass filter), and have the wire frame length Lw (mm) and the thickness tbox (μm) of the buried oxide film 102. And the drain region 104
And the bottom area S (μm ² ) of the drift region surrounding the embedded oxide film 102 in contact with the buried oxide film 102 satisfy S × Lw / tbox <7.2 × 10 ⁵ ... ,
The band frequency (cutoff frequency) of the low-pass filter 811 can be increased. Numerically,
When applied to the equation, the resonance frequency is 1.0 GHz or higher.

In this embodiment, an example of an n-channel type MOSFET (metal / oxide film / semiconductor LDMOSFET) is shown as a semiconductor switch, but a p-channel type M is used.
It may be OSFET. Furthermore, MOSFET is JF
ET (junction field effect transistor), MESFET
(Field Effect Transistor with Metal / Oxide Semiconductor Structure), B
Even if it is replaced with JT (junction type bipolar transistor) or the like, the same effect can be obtained.

FIG. 6 shows an example of use in which a voltage follower type sample and hold circuit is constructed by using the semiconductor switch device of this embodiment.

Here, in the semiconductor switch device SW, one switch terminal 303 is connected to the analog signal input terminal IN and the other switch terminal 304 is connected to the non-inverting input terminal of the operational amplifier OP to be inserted in the signal path.

The operational amplifier OP has an output end connected to the conversion signal output terminal OUT and an inverting input end. Further, the hold capacitor C1 is connected between the non-inverting input terminal of the operational amplifier OP and the ground.

A drive circuit 41 for the semiconductor switch device SW.
Although not shown in the figure, it is assumed that 4 is included in the semiconductor switch device SW.

Next, the basic operation of the sample hold circuit of FIG. 6 will be described. First, when the semiconductor switch device SW is driven on, the hold capacitor C1 is charged to a voltage equal to the input signal voltage input to the analog signal input terminal IN. Here, when the semiconductor switch device SW is used, if the input impedance of the operational amplifier OP is close to infinity, the electric charge of the hold capacitor C1 is not discharged anywhere, and the voltage is held as it is. Therefore, when the semiconductor switch device SW is repeatedly turned on and off at regular intervals, an output voltage waveform obtained by sampling the instantaneous value of the input voltage at regular time intervals is obtained from the conversion signal output terminal OUT.

Thus, the wide band property of the conduction characteristic of the semiconductor switch device SW of the present invention can be utilized, and the waveform quality of the input high frequency analog signal is impaired over a wide band in combination with the low capacitance and low on resistance performance. Without drive circuit 4
It is possible to provide a sampling and holding circuit capable of suppressing noise from 14 and capable of high-speed sampling.

[0062]

According to the invention of the semiconductor switch device of claim 1, a series circuit of two semiconductor switch elements composed of transistors for turning on / off a conduction path of a high frequency signal, and a drive circuit for driving both semiconductor switch elements are provided. The two semiconductor switching elements are formed on one semiconductor chip, the first main electrodes of the two semiconductor switches and the control electrodes of the two semiconductor switches are connected to each other inside the semiconductor chip, and the second semiconductor switching element of the one semiconductor switching element is formed. A terminal on the main electrode side of the switch terminal on one side through which a high-frequency signal passes, and a terminal on the second main electrode side of the other semiconductor switch element on the other side through which a high-frequency signal passes. One of the two drive terminals for applying drive power to both semiconductor switch elements has a drive terminal on one side and a semiconductor electrode that is a semiconductor electrode. In a semiconductor switch device connected inside a chip and connected to a signal line of a drive circuit, each of the semiconductor switch elements includes a base electrode separated from a first main electrode, and the two drive terminals are connected to each other. Since the drive terminal on the other side of the inside is connected to the base electrode and the semiconductor support substrate of the semiconductor chip inside the package in which the semiconductor chip is mounted and is connected to the high frequency and the ground common to the drive circuit, the high frequency signal The number of LC series resonant elements that connect the line and the high frequency ground can be reduced to one, and as a result, the appearance of dips can be reduced, the flatness can be improved, and the band of the high frequency conduction loss characteristics can be widened. is there.

According to the invention of a semiconductor switch device of claim 2, in the invention of claim 1, the substrate of the semiconductor chip is a semiconductor substrate comprising a silicon-on-insulator substrate in which an insulating layer sandwiches a semiconductor layer and a semiconductor support substrate. In the semiconductor switch element, the high-concentration first-conductivity-type drain region and the second-conductivity-type well region formed separately in the semiconductor layer and the high-concentration first-concentration region formed in the well region are used. A conductive type source region, a gate electrode forming the control electrode formed on the well region interposed between the drain region and the source region via a gate insulating film, the well region and the drain A drift region formed between the drain region and the region, and a drain electrode forming the second main electrode formed on the drain region. A double diffusion lateral MOSFET having a source electrode forming the first main electrode formed on the source region and the base electrode formed on a region apart from the gate insulating film on the well region. Therefore, it is possible to provide a semiconductor switch device in which two double-diffused lateral MOSFETs are integrated on one chip.

The invention of a semiconductor switch device according to a third aspect of the invention is the invention of the second aspect, wherein the double diffusion lateral MO is provided.
Each semiconductor switch element composed of SFET is provided with a channel region in a well region corresponding to the gate electrode, and a gate oxide film forming the gate insulating film so as to be sandwiched between the channel region and the gate electrode, The sum of the length of wiring from the gate electrode to the high frequency ground plane via the drive circuit and the length of wiring from the base electrode to the high frequency ground plane is L (mm), and the gate oxide film thickness is tox. (Μm), the length of the channel region is Lg (μm), and the total width of the channel region is Wg.
(Μm), L × Lg × Wg / tox <6.7
Since × 10 ⁵ is satisfied, it is possible to reduce the inductor and the gate oxide film capacitance of the semiconductor switch element due to the total extension of the wiring length from the gate electrode of the semiconductor switch element to the high frequency ground via the drive circuit. This has the effect of reducing the product of L and C of the LC series resonance element that connects the high-frequency signal line and the high-frequency ground, and increasing the frequency at which the dip appears to 1 GHz or higher.

According to a fourth aspect of the present invention, there is provided the semiconductor switch device according to the second or third aspect, wherein the inside of the package is connected to a metal frame for fixing the semiconductor chip, a metal frame through which a high frequency signal passes, and a drive circuit. The length of the wire connecting the metal frame through which the high-frequency signal passes and the semiconductor switch element is Lw (mm), and the thickness of the buried oxide film forming the insulating layer of the semiconductor substrate is tbox. (Μm) and the bottom area S of the drift region surrounding the drain region in contact with the buried oxide film is (μm ² ),
Since S × Lw / tbox <7.2 × 10 ⁵ is satisfied, the product of the inductor between the metal frame through which the high-frequency signal passes and the semiconductor switch element and the capacitance between the drain electrode of the semiconductor switch element and the semiconductor substrate There is an effect that the cut-off frequency of the low-pass filter composed of the inductor and the capacitance can be increased to 1 GHz or higher by reducing the above.

According to the invention of a semiconductor switch device of claim 5, in the invention of any one of claims 1 to 4, an operational amplifier having an output terminal connected to an output signal terminal and an inverting input terminal, and the operational amplifier A sample-hold circuit is composed of a hold capacitor connected between the non-inverting input terminal and the ground, and a series circuit of the two semiconductor switch elements inserted between the input signal terminal and the input terminal of the operational amplifier. Therefore, the CR time constant formed by the on-resistance of the semiconductor switch element and the capacitance of the hold capacitor is small, sampling can be performed at a high distance, and the primary switch of the semiconductor switch element with respect to the capacitance of the hold capacitor can be increased.
By reducing the ratio of the capacitances between the secondary circuits, it is possible to reduce noise mixing from the drive circuit and improve the signal accuracy.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a sectional view of an LDMOSFET used in the above.

FIG. 3 is a schematic surface view of a semiconductor chip used in the above.

FIG. 4 is an explanatory diagram of a mounting example of a semiconductor chip used in the above in a package.

FIG. 5 is an equivalent LCR network circuit diagram of the above.

FIG. 6 is a circuit diagram of a sampling hole circuit using the same as above.

FIG. 7 is a circuit diagram of a conventional semiconductor switch device.

FIG. 8 is a cross-sectional view of a semiconductor switch used in the above.

FIG. 9 is an equivalent LCR network circuit diagram of a conventional semiconductor circuit.

[Explanation of symbols]

Q1, Q2 LDMOSFET 303, 304 switch terminals 110 drain electrode 111 Source electrode 112 base electrode 113 gate electrode 414 drive circuit 419 Drive power supply 430 High frequency ground

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Claims (5)

[Claims] 1. A series circuit of two semiconductor switch elements, each of which comprises a transistor for turning on / off a conduction path of a high-frequency signal, and a drive circuit for driving both semiconductor switch elements. Formed on a semiconductor chip, the first main electrodes and control electrodes of both semiconductor switches are connected to each other inside the semiconductor chip, and the terminal on the second main electrode side of the one semiconductor switch element passes a high-frequency signal. In order to apply drive power to both of the semiconductor switch elements, the switch terminal on one side and the terminal on the second main electrode side of the other semiconductor switch element respectively constitute the switch terminals on the other side through which a high-frequency signal passes. One of the two driving terminals is connected to the control electrodes of both semiconductor switches inside the semiconductor chip, and the driving circuit is connected. In the semiconductor switching device connected to the signal line, both of the semiconductor switching elements are provided with a base electrode separate from the first main electrode, and the driving terminal on the other side of the two driving terminals is the base. A semiconductor switch device, comprising: an electrode and a semiconductor supporting substrate of the semiconductor chip, which are connected to each other inside a package in which the semiconductor chip is mounted and to a ground common to a high frequency and a driving circuit. 2. A semiconductor substrate made of a silicon-on-insulator substrate having an insulating layer sandwiched between a semiconductor layer and a semiconductor supporting substrate is used as a substrate of the semiconductor chip, and the semiconductor switch element is separated from the semiconductor layer. A high-concentration first-conductivity-type drain region and a second-conductivity-type well region, a high-concentration first-conductivity-type source region formed in the well region, the drain region, and the source region. A gate electrode forming the control electrode formed on the well region interposed therebetween via a gate insulating film, a drift region formed between the well region and the drain region, and a drain region on the drain region. A drain electrode forming the second main electrode formed on the source region and forming the first main electrode formed on the source region. 2. The semiconductor switch device according to claim 1, comprising a double-diffused lateral MOSFET having an electrode and the base electrode formed on a region of the well region away from the gate insulating film. 3. A semiconductor switch element comprising the double-diffused lateral MOSFET is provided with a channel region in a well region corresponding to the gate electrode, and the gate insulating film is sandwiched between the channel region and the gate electrode. And a gate oxide film forming the gate oxide film, the wiring extending from the gate electrode as a starting point to the high frequency ground plane via the drive circuit and the wiring length from the base electrode to the high frequency ground plane as L ( mm), and the gate oxide film thickness is t
ox (μm), and the length of the channel region is Lg (μ
3. The semiconductor switch device according to claim 2, wherein L × Lg × Wg / tox <6.7 × 10 ⁵ is satisfied when the sum of the widths of the channel regions is Wg (μm). 4. The inside of the package comprises a metal frame for fixing the semiconductor chip, a metal frame through which a high frequency signal passes, and a metal frame connected to a driving circuit, and the metal frame through which the high frequency signal passes and a semiconductor switch. The length of the wire connecting the elements is Lw (mm), the thickness of the buried oxide film forming the insulating layer of the semiconductor substrate is tbox (μm), and the drift region surrounding the drain region is the buried oxide film. 4. The semiconductor switch device according to claim 2, wherein S × Lw / tbox <7.2 × 10 ⁵ is satisfied when the bottom area S in contact with is set to (μm ² ). 5. An operational amplifier having an output terminal connected to an output signal terminal and an inverting input terminal, a hold capacitor connected between a non-inverting input terminal of the operational amplifier and ground, and an input signal terminal. 5. The semiconductor switch device according to claim 1, wherein a sample hold circuit is configured by a series circuit of the two semiconductor switch elements inserted between the operational amplifier and the input terminal.