JP2003068757A - Active matrix substrate and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide an active matrix substrate capable of improving the performance of a thin film transistor. SOLUTION: A thin film transistor (n-TFT, in which a semiconductor thin film 600 is formed in a predetermined pattern on an insulating substrate 1).
An active matrix substrate 23 on which a p-TFT is formed. The thin-film transistor (n-TFT, p-TFT) is formed of a bottom-gate thin-film transistor in which the gate electrode 4 is located below the semiconductor thin film 600.
At least one insulating film 4 among the insulating films constituting the thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used in, for example, a liquid crystal display device, an organic electroluminescence (hereinafter referred to as organic EL) display device and a method for manufacturing the same, and in particular, a thin film transistor used for the substrate and the same It relates to a manufacturing method.

[0002]

2. Description of the Related Art A thin film transistor (T) developed as a driving element for a liquid crystal display device or an organic EL display.
Among FT), a thin film transistor using polycrystalline silicon has been attracting attention because it can form a driving circuit and can be formed into a so-called system-on-panel by incorporating a highly functional circuit in the panel. ing. A substrate having a low melting point is essential in the manufacturing process of the polycrystalline silicon TFT, and so-called low temperature polycrystalline silicon TFTs having a process temperature of 700 ° C. or lower have been developed.

[0003]

By the way, as the functions of the circuits incorporated in the display are advanced, the improvement of the performance of the low temperature polycrystalline silicon TFT alone is strongly demanded.
Conventionally, as a means for improving the performance of the polycrystalline silicon TFT,
Techniques such as increasing the crystal grain size, reducing the defect level in the film by hydrogenation, and densifying the gate insulating film have been adopted.
However, it is becoming difficult to further improve the driving current and reduce the leakage current by extending the conventional method.

Further, in the future, as the built-in circuits become more complicated, the demands for multilayer wiring and miniaturization of elements will increase, and the development of an element structure that meets these requirements is required. In the multi-layer wiring of the element, it is required that the step coverage of the interlayer insulating film is good, but as the element becomes finer, the conventional CVD method is used.
There is a problem in that sufficient step coverage cannot be obtained by a method such as (chemical vapor deposition).

Further, as an example of improving the step coverage in the pixel electrode portion of a liquid crystal display, as shown in JP-A-11-249168, for example, a coating film of perhydropolysilazane is used to flatten the pixel electrode portion. It is known how to realize. However, such TF
The T structure was intended to improve the orientation of the liquid crystal molecules of the liquid crystal display, and did not improve the TFT device characteristics.

In view of the above points, the present invention has an active thin film transistor structure capable of driving a large amount of current, a dense and high quality gate insulating film, and a thin film transistor having a good step coverage even when miniaturized. It is an object of the present invention to provide a matrix substrate and a method for manufacturing the same, and to realize a significant improvement in performance of a thin film transistor element.

[0007]

An active matrix substrate according to the present invention is an active matrix substrate in which a thin film transistor in which a semiconductor thin film is formed in a predetermined pattern is formed on an insulating substrate, and the thin film transistor has a gate electrode. A bottom gate type thin film transistor located under the semiconductor thin film, and at least one of insulating films constituting the thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same. To do.

In the active matrix substrate of the present invention,
At least one of the insulating films forming the bottom-gate thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same,
The insulating film can be formed while flattening the steps. In particular, when the bottom gate type gate insulating film is formed of a film obtained by baking a coating film of perhydropolysilazane or a composition containing the same, the gate insulating film can be formed while flattening the steps of the gate electrode of the bottom gate. . Therefore, when a semiconductor thin film to be a channel layer of a thin film transistor is formed on the flattened gate insulating film, the semiconductor thin film also becomes flat. Incidentally, when a large amount of current is applied when a semiconductor thin film is formed on a stepped gate insulating film, heat is generated in the curved portion of polycrystalline silicon, and the so-called ON breakdown voltage of the thin film transistor is lowered. However, according to the present invention, since a flattened semiconductor thin film is formed, this problem is avoided and a larger current drive becomes possible.

An active matrix substrate according to the present invention is an active matrix substrate in which a thin film transistor in which a semiconductor thin film is formed in a predetermined pattern is formed on an insulating substrate, and the thin film transistor has a gate electrode in the upper and lower portions of the semiconductor thin film. Of the sandwich gate type thin film transistor located at, and at least one of the insulating films constituting the thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same.

In the active matrix substrate of the present invention,
Since at least one of insulating films constituting a sandwich gate type (or also called a double-sided gate structure) thin film transistor having upper and lower gates is formed by baking a coating film of perhydropolysilazane or a composition containing the same, The insulating film can be formed while flattening the steps.
In particular, a lower gate insulating film is formed by flattening a coating film of perhydropolysilazane or a composition containing the same on the lower electrode, and the lower gate insulating film is formed on the lower gate insulating film to be a flattened channel layer. Further, when forming the upper gate insulating film and the upper gate electrode, a sandwich gate type thin film transistor is manufactured while realizing a flat channel layer. Compared with the single gate structure, this sandwich gate structure improves the steepness of the sub-threshold characteristics, can obtain a larger current at the same gate voltage even in the saturation current region, and can reduce the wiring above and below the multilayer structure. It is characterized by being less susceptible to electrical interference from the device, and is particularly promising for low-voltage drive circuit elements. By the way, if an attempt is made to form a sandwich gate structure by a conventional manufacturing method, the problem of the step of the semiconductor thin film described above appears, and the original performance cannot be exhibited. The present invention improves this point.

A method of manufacturing an active matrix substrate according to the present invention is a method of manufacturing an active matrix substrate in which a thin film transistor in which a semiconductor thin film is formed in a predetermined pattern is formed on an insulating substrate. At least one of the insulating films,
A coating film of perhydropolysilazane or a composition containing the perhydropolysilazane is formed of a baked film, and the baking process of the coating film is a process of high-pressure annealing in an atmosphere containing a gas having an oxidizing ability.

In the method for manufacturing an active matrix substrate of the present invention, at least one of the insulating films constituting the thin film transistor is spin-coated by dropping a solution of perhydropolysilazane or a composition containing the same onto the substrate surface. Since it is formed by the coating film applied by the above method, a flattened insulating film without steps can be formed easily and uniformly.
By high-pressure annealing the coating film thus formed in an atmosphere containing a gas having an oxidizing ability, the obtained silicon oxide film becomes a high-quality film close to thermal oxidation, enabling high performance of thin film transistors. To do.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the active matrix substrate and the method for manufacturing the same according to the present embodiment, in particular, at least one of the insulating films forming the thin film transistor is coated with perhydropolysilazane or a composition containing the same (for example, xylene). Is used as a solvent) to form a coating film, and the coating film is baked to form the coating film. That is,
A solution of perhydropolysilazane or a composition containing the same is dropped onto the surface of a substrate and spin-coated to flatten the steps, while forming a simple and uniform insulating film. In the past, it was general to convert the coating film thus formed into silicon oxide by subjecting it to steam annealing at about 400 ° C. under normal pressure. On the other hand, in the present embodiment, the coating film is annealed and steam-annealed under high pressure. The atmospheric pressure of this atmosphere can be a high pressure exceeding 1 atmospheric pressure, and the higher the pressure is, the more preferable. However, the actual pressure of the apparatus determines the upper limit of the high pressure. In the present embodiment, from the pressure exceeding 0.1 MPa to 5MP
It can be about a and is several atmospheres or more, preferably 1M
It can be Pa or more. As an example of baking the coating film, steam annealing is performed at 2 MPa at 300 ° C. to 600 ° C. for about 2 hours. The silicon oxide film obtained by this annealing process becomes a high-quality film close to a thermal oxide film, and greatly contributes to high performance of thin film transistors.

Perhydropolysilazane is converted to silicon oxide by the reaction formula shown below when steam annealing is performed. (SH ₂ 2NH) _n + H ₂ O → SiO ₂ + NH
₃ (+ SiN + SiOH) However, SiN + SiOH is an unconverted compound.

Conventionally, this steam annealing has often been performed at a relatively low temperature under normal pressure, so that the obtained oxide film also contains silicon nitride and silicon hydride as unreacted residues (so-called unconverted compounds). It was Further, silicon oxide also contains defects due to dangling bonds of silicon, and these unreacted substances, defects, etc. have been a cause of deteriorating the performance of thin film transistor elements. In the present embodiment, steam annealing is performed under high pressure (for example, 2 MPa, 300 ° C.
By performing the treatment under the condition of 600 ° C.), it is possible to form high-quality silicon oxide in which the unreacted substance, defects in the film, and the like are significantly reduced.

FIG. 11 is a conceptual diagram of a high pressure steam oxidation treatment apparatus. This high-pressure steam oxidation treatment device 51 includes a pressure vessel 52 hermetically sealed, a treatment chamber 53 hermetically sealed in the pressure vessel 52, heaters 54, 55 for heating the treatment chamber 53, and a pressure vessel 52. The pressure rising line 56 and the pressure reducing line 57 are connected, and the process gas supply line 58 and the process gas exhaust line 59 are connected to the process chamber 53.

The processing gas is a gas that produces an atmosphere containing steam as a main component or an atmosphere of an inert gas.
The processing chamber 53 is a quartz tube whose inner wall is made of quartz,
Prevents metal from entering the semiconductor. The heater 54 is used in the processing chamber 53.
Is provided so as to surround the outer periphery of the processing chamber 53, for example, 30
It can be maintained at 0 ° C to 700 ° C. The pressure rising line 56 has an air source, a pressure reducing valve 62, a flow meter 63, and a valve 64, and supplies the air 61 into the pressure vessel 52 by opening and closing the valve 64.
The pressure can be raised to 1 to 5 MPa. The decompression line 57 is configured to exhaust the air in the pressure vessel 52 by opening and closing the valve 65 to decompress the pressure vessel 52.

The processing gas supply line 58 supplies the processing gas to the processing chamber 53 at a downstream portion where the processing gas is released into the processing chamber 53.
It has a heater 55 that heats to a temperature equivalent to the above, and is branched into a nitrogen supply line 67 and a water supply line 68 in the upstream portion. The nitrogen supply line 67 includes a supply source and the pressure reducing valve 6.
9, a flow meter 70 and a valve 71, and a valve 7
The processing gas is supplied into the processing chamber 53 by opening and closing the chamber 1 to make the processing chamber 53 into a predetermined processing gas atmosphere, and the processing chamber 53 can be pressurized to, for example, 0.1 to 5 MPa. The water supply line 68 has a pump 72 and a valve 73, and pumps water from a water source to open and close the valve 73 to supply water to the heater 55. The heater 55 evaporates water and supplies it to the processing chamber 53. There is. An object mounting stage 74 is provided at the center of the processing chamber 53, and a glass substrate, a silicon substrate, or the like is placed on the stage 74.

1 to 4 show an embodiment of the active matrix substrate of the present invention together with its manufacturing method. This example is a case where it is applied to an active matrix substrate on which a bottom gate type thin film transistor is formed.

First, as shown in FIG. 1A, for example, Ta, Mo, W, or the like is formed on one main surface of an insulating substrate 1 such as glass.
A plurality of gate electrodes 2 are formed by forming Cr, Cu, or the like, or an alloy thereof with a required film thickness, in this example, a film thickness of 20 nm to 250 nm, and patterning the film.

Next, as shown in FIG. 1B, plasma CV
By the D method, the atmospheric pressure CVD method, the low pressure CVD method or the like, a required insulating film, in this example, a silicon nitride film (SiN _x film) 3 is formed on the entire surface of the substrate including each gate electrode 2 to a required film thickness (for example, 30
The thickness is about 50 nm to 50 nm). Then, a solution of perhydropolysilazane is spin-coated on the entire surface of the substrate to form a desired film thickness on the gate electrode 2, which is about 50 nm to 200 in this example.
The coating film is formed to have a film thickness of about nm. After that, the coating film is baked to form the silicon oxide gate insulating film 4. In this example, the gate insulating film 4 is formed by annealing in water vapor at 1 MPa and 400 ° C. for about 30 minutes. At this stage, the spaces between the gate insulating films 2 are also filled with the silicon oxide film 4a obtained by baking the coating film of perhydropolysilazane, and the gate insulating film 4 can be planarized. In this annealing step, the gate insulating film 4 can be densified and defects can be reduced by performing high-pressure steam annealing at a temperature equal to or lower than the softening temperature of glass, for example, about 2 MPa and 600 ° C. under a high pressure exceeding 0.1 MPa.

Further, on the flattened gate insulating film 4,
Amorphous silicon thin film 6a is formed into a desired film thickness, for example, about 60n.
The film is formed with a film thickness of about m to 160 nm. Here, when the plasma CVD method is used to form the amorphous silicon thin film 6a, 400 ° C. to 450 ° C. for 1 to 2 hours in a nitrogen (N ₂ ) atmosphere in order to desorb hydrogen in the film. Perform a degree of annealing. After this, laser annealing, for example, a wavelength of 200 nm
The amorphous silicon thin film 6a is converted into a polycrystalline silicon thin film 6 by annealing with an excimer laser L of 400 nm.
If necessary here, the threshold voltage Vth of the thin film transistor
For the purpose of controlling the temperature, the required conductivity type impurities are ion-implanted into the polycrystalline silicon thin film 6. Dose 0.1 × 10, boron ions (B ⁺⁾ in this example ¹² cm ^{- 2 ~4} × 10
¹⁴ cm ^{- 2} degree by ion implantation. Accelerating voltage is 10 ke
It is about V to 100 keV.

Next, as shown in FIG. 2C, a required insulating film, that is, a silicon oxide film 7 in this example, is formed on the polycrystalline silicon thin film 6.
Is formed into a required film thickness (for example, about 20 nm to 200 nm) by a method such as a plasma CVD method. This silicon oxide film 7 may also be formed by applying the above-mentioned perhydropolysilazane and baking it. Next, a photoresist film is applied and formed on the entire surface, and the photoresist film is selectively exposed by so-called back surface exposure from the side of the substrate 1 using the gate electrode 2 as a mask, and development processing is applied to only the corresponding portion on the gate electrode 2. A photoresist mask 8 is formed on. Then, the underlying silicon oxide film 7 is selectively removed by etching through the photoresist mask 8 to leave the silicon oxide film 7 only on the portion corresponding to the gate electrode 2 (substantially the channel region).

Next, the mass-separated impurity ions, which are phosphorus ions (P ⁺ ) 9 in this example, are ion-implanted into the entire surface of the polycrystalline silicon thin film 2 on the substrate so that all the polycrystalline silicon thin films 2 have a low concentration n-type. The region 41a is formed. The low-concentration n-type region 41a becomes a low-concentration region (that is, an LDD region) of the source region and the drain region of the LDD structure thereafter. The dose in this example 4 × 10 ¹² cm ^{- 2} ~5
× 10 ¹³ cm ^{- 2} mm, the accelerating voltage 10keV~100
It is about keV.

After ion implantation for LDD, as shown in FIG. 2D, a photoresist mask 10 covering the p-channel thin film transistor side and also covering the gate electrode 2 and the LDD region 41a on the n-channel thin film transistor side.
To form. Through this photoresist mask 10,
N-type impurity 11 is ion-implanted into the polycrystalline silicon thin film to form a high concentration n-type source region 42S and drain region 42D.
To form. In this example, PH ₃ gas diluted with hydrogen (H ₂ ) is used, phosphorus ions (P ⁺ ) 11 are doped by ion shower doping using a non-mass separation type ion beam, and the source region 42S and the drain of the n-channel thin film transistor are drained. The region 42D is formed. Dose amount is 1 × 10
^{14 cm - 2 ~1 × 10 15} cm - 2 mm, the accelerating voltage is 10
It can be set to about keV to 100 keV. Thus, the LDD structure n-channel thin film transistor (n
-TFT) is formed.

Next, as shown in FIG. 3E, a photoresist mask 12 covering the n-channel thin film transistor (n-TFT) side is formed, and this photoresist mask 1 is formed.
P-type impurity 13 is ion-implanted into the polycrystalline silicon thin film on the side of the p-channel thin film transistor via 2 to obtain a high concentration of p
A mold source region 43S and a drain region 43D are formed. In this example, B ₂ H ₆ gas diluted with hydrogen (H ₂ ) is used, and boron ions (B ⁺ ) 13 are doped by ion shower doping using the same non-mass separation type ion beam, and the source region 43S and drain are A region 43D is formed. Dose amount is 1 × 10 ¹⁵ cm ^{-2 to} 3 × 10 ¹⁵ cm
^{- 2} mm, the accelerating voltage may be about 10KeV～100keV. As a result, a p-channel thin film transistor (p-TFT) is formed.

Next, after the photoresist mask 12 is peeled off, an activation process is performed. The activation treatment may be laser annealing, lamp annealing, or furnace annealing. After the activation process, the silicon oxide film 7 on the polycrystalline silicon thin film 6 and the polycrystalline silicon thin film 6 are simultaneously patterned into an island shape to form each island-shaped active layer 600 and each thin film transistor (n-TFT, p-TFT). To form. In this way, the thin film transistor 45 and the pixel thin film transistor 46 are formed for the drive circuit (see FIG. 3F).

Next, as shown in FIG. 3F, n channels,
p-channel thin film transistor (n-TFT, p-TF)
The first interlayer insulating film 14 and the second interlayer insulating film 14 are formed on the entire surface of the substrate including T).
The interlayer insulating film 15 is sequentially formed. In this example, plasma C
A silicon oxide (SiO _x ) film 14 having a film thickness of 100 nm to 400 nm is formed by the VD method, and a film thickness of 100
A silicon nitride film 15 having a thickness of nm to 400 nm is formed, and hydrogenation annealing is performed at 350 ° C. to 400 ° C. for 1 hour in a nitrogen (N ₂ ) atmosphere. This silicon oxide film 14 can also be formed by applying perhydropolysilazane and baking it.

Next, as shown in FIG. 4, contact holes 17 are formed in the silicon oxide film 14 and the silicon nitride film 15 which are interlayer insulating films, and a wiring electrode material such as Al--Si is sputtered and patterned. Thus, the wiring electrode 18 is formed. That is, through the contact hole 17, the required source regions 42S, 43 of the thin film transistor are formed.
The wiring electrode 18 connected to the S and drain regions 42D is formed. Next, the flattening film 19 is formed on the upper surface. In this example, an acrylic organic resin is applied to a thickness of about 1 μm to form the flattening film 19. Further, a contact hole 20 is formed in the flattening film 19, is connected to one wiring electrode 18 of the pixel thin film transistor 46 through the contact hole 20, and a pixel electrode 21 extending on the surface of the flattening film 20 is formed. To do. In this example, the pixel electrode 21 is formed of a transparent electrode. For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or the like is deposited and patterned. The ITO film is annealed at 220 ° C. for 30 minutes in a nitrogen (N ₂ ) atmosphere. Thus, the active matrix substrate 23 according to the first embodiment of the present invention is obtained.

According to the first embodiment, when the coating film is formed using the solution of perhydropolysilazane in forming the bottom gate type gate insulating film 4, the bottom gate electrode 2 is formed due to the nature of the coating liquid. The gate insulating film 4 can be formed while flattening the steps. Since the polycrystalline silicon thin film 6 to be the channel layer is formed on the flattened gate insulating film 4, the polycrystalline silicon thin film 6 also becomes flat. By flattening the polycrystalline silicon thin film 6, heat generation in the polycrystalline silicon thin film 6 is suppressed even when a large current is passed, a decrease in ON breakdown voltage of the thin film transistor is avoided, and a bottom gate type thin film transistor capable of driving a larger current is obtained. To be In the annealing process for the coating film of perhydropolysilazane, for example, high-pressure steam annealing at 2 MPa and 600 ° C. is performed to achieve the densification of the planarized gate insulating film 4 and the reduction of the Si / SiO ₂ interface state. it can. As the gate insulation film 4 is densified, the gate insulation breakdown voltage is improved, so that the gate insulation film 4 can be thinned. Therefore, the active matrix substrate 223 in which the high performance thin film transistors are integrated can be obtained. The active matrix substrate 23 of this embodiment is
Integrating high-performance circuits with high-performance thin film transistors,
It enables the realization of so-called system displays.

5 to 9 show another embodiment showing the active matrix substrate of the present invention together with its manufacturing method.
This example is a case where it is applied to an active matrix substrate on which a sandwich gate type thin film transistor is formed.

The steps of FIGS. 5A to 5B are the same as those of FIGS.
It is similar to the process up to B. That is, as shown in FIG. 5A, for example, Ta, Mo, W, Cr, Cu, or the like, or an alloy thereof is formed on a main surface of the insulating substrate 1 such as glass to have a required film thickness of 20 nm to 20 nm in this example. It is formed to a film thickness of 250 nm and patterned to form a plurality of lower gate electrodes 2A.

Next, as shown in FIG. 5B, plasma CV
By the D method, the atmospheric pressure CVD method, the low pressure CVD method or the like, a required insulating film, in this example, a silicon nitride film (SiN _x film) 3 having a required film thickness (for example, 30 nm) is formed on the entire surface of the substrate including each lower gate electrode 2A. To about 50 nm). Then, a solution of perhydropolysilazane is spin-coated on the entire surface of the substrate, and a required film thickness on the lower gate electrode 2A, about 5 in this example.
The coating film is formed to have a film thickness of about 0 nm to 200 nm. Then, this coating film is baked to form a lower gate insulating film 4A of silicon oxide. In this example, the lower gate insulating film 4A is formed by annealing in water vapor at 1 MPa and 400 ° C. for about 30 minutes. At this stage, the spaces between the lower gate electrodes 2A are also filled with the silicon oxide film 4a obtained by baking the coating film of perhydropolysilazane, and the lower gate insulating film 4A can be planarized. In this annealing step, 0.1
A temperature equal to or lower than the softening temperature of glass under high pressure exceeding MPa,
For example, by performing high-pressure steam annealing at about 600 ° C. at 2 MPa, the gate insulating film 4 can be densified and defects can be reduced.

Further, the flattened lower gate insulating film 4A
An amorphous silicon film 6a is formed on the upper surface of the substrate to a desired film thickness, for example, about 6
A film having a thickness of about 0 nm to 160 nm is formed. Here, when the plasma CVD method is used for forming the amorphous silicon film 6a, 400 ° C. to 450 ° C. for 1 to 2 hours in a nitrogen (N ₂ ) atmosphere in order to desorb hydrogen in the film. Perform a degree of annealing. After this, laser annealing, for example, a wavelength of 200 nm
The amorphous silicon film 6a is converted into the polycrystalline silicon thin film 6 by annealing with a 400 nm excimer laser 7. If necessary, the necessary conductivity type impurities are ion-implanted into the polycrystalline silicon thin film 6 for the purpose of controlling the threshold voltage Vth of the thin film transistor. In this example, boron ion (B
⁺⁾ The dose of ^{0.1 × 10 12 cm - 2 ~4} × 10 14 c
m ^{- 2} about by ion implantation. Accelerating voltage is 10 keV ~
It is about 100 keV.

Next, as shown in FIG. 6C, the polycrystalline silicon thin film 6 is patterned into an island shape by selective etching to form an active layer 600 of each thin film transistor. An upper gate insulating film 4B is formed on the surface of each active layer 600. In this example, a silicon oxide film 4B having a film thickness of 20 nm to 200 nm to be an upper gate insulating film is formed by a method such as a plasma CVD method. This silicon oxide film 4B can also be formed by applying perhydropolysilazane and firing as described above.

Next, as shown in FIG. 6D, the upper gate electrode 2B is formed on each upper gate insulating film 4B. In this example, Ta, Mo, Cr, Cu or their alloys are formed to a film thickness of 20.
Then, the upper gate electrode 2B is formed by patterning it to a thickness of about 250 nm to 250 nm.

Next, as shown in FIG. 7E, the upper gate electrode is
With the pole 2B as a mask, LDD regions are formed in all active layers 600.
The low concentration region 41a is formed. In this example, mass separation
Phosphorus ion (P⁺) 25 on the board
Ions are implanted into all active layers 600 to form low concentration n-type regions.
Form. Dose amount is 4 × 10¹²cm^-2~ 5 x 10 ¹³
cm^-2About 10 keV to 100 keV
It can be degree.

Next, as shown in FIG. 7F, one thin film transistor
Transistor side, p-channel thin film transistor side in this example
And the other thin film transistor,
Upper gate electrodes 2B and L on the side of the channel thin film transistor
The photoresist mask 10 covering the DD region 41a
Form. Selection is made through this photoresist mask 10.
N-type impurity 11 is ion-implanted into the selected active layer 600.
And high concentration n-type source region 42S and drain region 42
Form D. In this example, hydrogen (H₂) PH diluted with₃
Using gas, phosphorus ion (P⁺) 11 for non-mass separation type
Ion shower doping using an ion beam
The source region 42S of the n-channel thin film transistor.
And a drain region 42D is formed. Dose amount is 1 × 1
0¹⁴cm ^-2~ 1 x 10¹⁵cm^-2Degree, acceleration voltage is 1
It can be set to about 0 keV to 100 keV. this
Thus LDD structure n-channel thin film transistor
(N-TFT) is formed.

Next, as shown in FIG.
Photoresist that covers the membrane transistor (n-TFT) side
Forming a mask 12 and forming a p-channel thin film transistor
P-type on the side active layer 600 using the upper gate electrode 2B as a mask
High-concentration p-type source region 4 by ion-implanting impurities 13
3S and the drain region 43D are formed. In this example hydrogen
(H₂) Diluted B₂H₆Boron ion using gas
(B⁺) 13 also uses a non-mass separation type ion beam
The source region was doped by ion shower doping.
43S and the drain region 43D are formed. The dose is
1 x 10¹⁵cm ^-2~ 3 x 10¹⁵cm^-2Degree, acceleration power
The pressure can be about 10 keV to 100 keV
It As a result, a p-channel thin film transistor (p-T
FT) is formed. In this way, the thin film for the drive circuit
The transistor 45 and the pixel thin film transistor 46
Form.

Next, the activation process is started. The activation may be performed by laser annealing, lamp annealing, or furnace annealing, but when perhydropolysilazane is applied, the firing step and the activation step can be combined. In this sense
The activation process is 400 ℃, 1MPa steam annealing 2
It may be annealed for about the time.

Next, as shown in FIG. 8H, after this activation treatment, the first interlayer insulating film 14 is formed by the plasma CVD method.
And the second interlayer insulating film 15 is formed. In this example, the film thickness is 1
00 nm to 400 nm silicon oxide (SiO _x ) film 1
4 is formed, a silicon nitride film 15 having a film thickness of 100 nm to 400 nm is continuously formed, and the film is formed in a nitrogen (N ₂ ) atmosphere for 3
Hydrogenation annealing is performed at 50 ° C. to 400 ° C. for 1 hour. This silicon oxide film 14 can also be formed by applying perhydropolysilazane and baking it.

Next, as shown in FIG. 9, contact holes 17 are formed in the silicon oxide film 14 and the silicon nitride film 15 which are interlayer insulating films, and a wiring electrode material such as Al-Si is sputtered and patterned. Thus, the wiring electrode 18 is formed. That is, through the contact hole 17, the required source regions 42S, 43 of the thin film transistor are formed.
The wiring electrode 18 connected to the S and drain regions 42D and 43D is formed. Next, the flattening film 19 is formed on the upper surface. In this example, an acrylic organic resin is applied to a thickness of about 1 μm to form the flattening film 19. Furthermore, the flattening film 19
A contact hole 20 is formed in the
One wiring electrode 1 of the pixel thin film transistor via 0
A pixel electrode 21 is formed that extends to the surface of the flattening film 20 while being connected to the pixel electrode 21. In this example, the pixel electrode 21 is formed of a transparent electrode. For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide) or the like is deposited and patterned. The ITO film is annealed at 220 ° C. for 30 minutes in a nitrogen (N ₂ ) atmosphere. Thus, the active matrix substrate 24 according to the second embodiment of the present invention is obtained.

According to the second embodiment, the flattened lower gate insulating film 4A formed by the coating film of perhydropolysilazane and the flattened polycrystalline silicon thin film 600 to be the active layer thereon are formed. And by forming a sandwich gate type thin film transistor,
Even if a large current is applied, the heat generated in the polycrystalline silicon thin film and the on-breakdown voltage of the thin film transistor are prevented from decreasing, and a sandwich gate type thin film transistor capable of driving a larger current can be obtained. In the annealing process for the perhydropolysilazane coating film, high-pressure steam annealing is performed in the same manner as described above, so that the gate insulating film 4 [4A, 4B] can be densified and the interface state can be reduced. It is possible to reduce the thickness of the gate insulating film 4 [4A, 4B]. Therefore, the active matrix substrate 24 in which the high performance thin film transistors are integrated can be obtained. The active matrix substrate 24 of the present embodiment also makes it possible to realize a system display in which high-performance circuits formed by high-performance thin film transistors are integrated.

FIG. 10 shows another embodiment of the active matrix substrate of the present invention. In this example, many steps are common to the first and second embodiments described above, and therefore FIG. 10 shows a final completed drawing. In the present embodiment, as a manufacturing process, first, a silicon nitride (SiN _x ) film 31 and a silicon oxide (SiO ₂ ) film 32, which will be a buffer layer, are formed on an insulating substrate 1 made of glass or the like to have a required film thickness. Then, an amorphous silicon thin film is required to have a required film thickness, in this example, about 60 n.
It is formed with a film thickness of about m to 160 nm. The silicon nitride film 31, the silicon oxide film 32, and the amorphous silicon thin film are formed by a method such as plasma CVD or low pressure CVD.
As the insulating substrate 1, for example, trade name A manufactured by Asahi Glass Co., Ltd.
N635, AN100, product name Cod manufactured by Corning
e1737 and the like are suitable. When the plasma CVD method is used, the SiO ₂ film 32 of the buffer layer is preferably formed by decomposing inorganic silane gas (eg SiH, Si ₂ H ₆ etc.). Or as SiO ₂ film 32, a sputtering method, it may be SiO ₂ by vapor deposition or the like. Here, when the plasma CVD method is used for forming the amorphous silicon thin film, annealing is performed at 400 ° C. to 450 ° C. for about 1 hour in a nitrogen (N ₂ ) atmosphere to release hydrogen in the film. To do. After that, laser annealing is performed to convert into polycrystalline silicon. In this example, the amorphous silicon thin film is converted into a polycrystalline silicon thin film by annealing with an excimer laser having a wavelength of 200 nm to 400 nm. Next, the polycrystalline silicon thin film is selectively etched to form an island-shaped polycrystalline silicon thin film, that is, the active layer 600.

Next, the gate insulating film 33 is formed. In this example, perhydropolysilazane is applied by spin coating,
The gate insulating film 33 is formed of a silicon oxide thin film having a film thickness of 20 nm to 200 nm by firing. Here, the active layer 600 made of a polycrystalline silicon thin film and the silicon oxide thin film 33 as a gate insulating film are annealed by high-pressure steam to densify the silicon oxide thin film 33. This annealing is performed, for example, at an annealing temperature of 200 ° C to 600 ° C and a pressure of 1 to 2MP.
a It can be performed in 2 hours. Here, if necessary,
In order to control the threshold voltage Vth of the thin film transistor,
Boron ion (B ⁺ ) dose 0.1 × 10 ¹² cm
^{- 2 ~4 × 10 12 cm -} 2 degree ion implantation. The acceleration voltage is about 20 to 200 keV.

After that, the so-called top gate type active matrix substrate 3 shown in FIG. 10 is performed through the same steps as the steps after FIG. 6D in the above-described second embodiment.
Get 5.

In the third embodiment as well, similar to the above-described embodiments, a flat gate insulating film 3 having no step is formed.
3 is obtained, and the subsequent coverage of the interlayer insulating films 14 and 15 is improved. Since the active layer 600 is also formed flat, a thin film transistor that can be driven with a large current can be obtained. Further, the gate insulating film 33 can be densified, the interface state can be reduced, the gate withstand voltage can be improved, and the gate insulating film 33 can be thinned. Therefore, the active matrix substrate 35 in which the high performance thin film transistors are integrated can be obtained. The active matrix substrate 35 of the present embodiment also makes it possible to realize a system display in which a high-performance thin film transistor-based high-function circuit is integrated.

[0049]

According to the active matrix substrate of the present invention, at least one of the insulating films forming the thin film transistor, particularly, for example, the lower gate insulating film in the thin film transistor having the bottom gate structure or the sandwich structure, or the top gate structure is used. An ideal thin film transistor having a flat channel layer can be prepared by forming a gate insulating film in a thin film transistor by using a film obtained by baking a coating film of perhydropolysilazane or a composition containing the perhydropolysilazane and planarizing the film. Therefore, a large drive current can be easily obtained. According to the method for manufacturing an active matrix substrate of the present invention, at least one of insulating films forming a thin film transistor, particularly a thin film coated with perhydropolysilazane and water vapor of relatively low temperature and high pressure when forming a gate insulating film. By combining with annealing, it is possible to achieve densification of the planarized gate insulating film and reduction of the semiconductor / insulating film interface state level. Further, since the gate insulation breakdown voltage can be improved as the insulation film becomes denser, the gate insulation film can be made thinner. That is, according to the present invention, a high-performance thin film transistor can be formed on a large-area substrate, for example, a glass substrate, which can greatly contribute to the realization of a so-called system display in which a high-performance circuit is integrated on a display panel.

[Brief description of drawings]

1A to 1B are manufacturing process diagrams (No. 1) showing a first embodiment of an active matrix substrate according to the present invention.

2A to 2D are manufacturing process diagrams (No. 2) showing the first embodiment of the active matrix substrate according to the present invention.

3A to 3F are manufacturing process diagrams (No. 3) showing the first embodiment of the active matrix substrate according to the present invention.

FIG. 4 is a first active matrix substrate according to the present invention.
It is a manufacturing-process figure (4) which shows embodiment.

5A to 5D are manufacturing process diagrams (1) showing the second embodiment of the active matrix substrate according to the present invention.

6A to 6D are manufacturing process diagrams (No. 2) showing the second embodiment of the active matrix substrate according to the present invention.

7A to 7F are manufacturing process diagrams (No. 3) showing the second embodiment of the active matrix substrate according to the present invention.

FIG. 8 is a manufacturing process diagram (4) showing the second embodiment of the active matrix substrate according to the present invention.

FIG. 9 is a second active matrix substrate according to the present invention.
It is a manufacturing-process figure (5) which shows embodiment.

FIG. 10 is a configuration diagram showing a third embodiment of an active matrix substrate according to the present invention.

FIG. 11 is a conceptual diagram of a high-pressure steam oxidation treatment apparatus applied to the present invention.

[Explanation of symbols]

1 ... Insulating substrate, 2 2A, 2B, ... Gate electrode, 3 ... Insulating film, 4, 4A, 4B ... Gate insulating film, 6a ... Amorphous silicon thin film, 6 ... ..Polycrystalline silicon thin film, 7 ... Insulating film, 8, 10, 12 ... Photoresist mask, 11 ... Phosphorus ion (P ⁺ ),
13 ... Boron ion (B ⁺ ), 41a ... Low concentration region (LDD region), 42S, 43S ... Source region, 42D, 43D ... Drain region, 600 ...
Active layer, n-TFT ... n-channel thin film transistor, p-TFT ... p-channel thin film transistor, 4
5 ... Drive circuit thin film transistor, 46 ... Pixel thin film transistor, 23, 24, 35 ... Active matrix substrate

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/316 H05B 33/14 A 5F110 29/786 H01L 29/78 617V H05B 33/14 617N 619A 627A F term (Reference) 2H090 HA02 HB12X HC05 HC15 LA01 LA04 2H092 GA59 JA26 JA36 JA40 KB25 MA10 MA30 NA21 PA06 3K007 AB05 AB07 EB00 FA01 5C094 AA23 AA25 BA03 BA29 BA43 CA19 DA14 DA15 DB01 DB04 BF10 BC04 BA06 BF46 BB10 BF46 BB10 BF10 BB10 BF10 BF10 AA07 AA30 BB02 BB04 CC08 DD02 DD13 DD14 DD17 EE02 EE04 EE06 EE30 FF02 FF03 FF09 FF12 FF21 FF29 FF30 FF32. PP35 QQ09 QQ11 QQ12 QQ19 QQ24

Claims (6)

[Claims] 1. An active matrix substrate comprising a thin film transistor in which a semiconductor thin film is formed in a predetermined pattern on an insulating substrate, wherein the thin film transistor has a bottom gate type thin film transistor in which a gate electrode is located under the semiconductor thin film. The active matrix substrate is characterized in that at least one of the insulating films constituting the thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same. 2. The active matrix substrate according to claim 1, wherein the at least one insulating film is a gate insulating film. 3. An active matrix substrate comprising a thin film transistor formed by forming a semiconductor thin film in a predetermined pattern on an insulating substrate, wherein the thin film transistor has a sandwich gate in which a gate electrode is located above and below the semiconductor thin film. An active matrix substrate comprising a thin film transistor, wherein at least one of insulating films constituting the thin film transistor is formed by baking a coating film of perhydropolysilazane or a composition containing the same. 4. The active matrix substrate according to claim 3, wherein the at least one insulating film is a gate insulating film. 5. A method of manufacturing an active matrix substrate, comprising a thin film transistor in which a semiconductor thin film is formed in a predetermined pattern on an insulating substrate, wherein at least one of the insulating films constituting the thin film transistor is formed by: An active matrix, characterized in that a coating film of perhydropolysilazane or a composition containing the same is formed by firing, and the step of firing the coating film is a step of high-pressure annealing in an atmosphere containing a gas having an oxidizing ability. Substrate manufacturing method. 6. The method of manufacturing an active matrix substrate according to claim 5, wherein the at least one insulating film is a gate insulating film.