JP2003060174A - Semiconductor integrated circuit manufacturing method and reticle, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit manufacturing method, a reticle, and a semiconductor integrated circuit device capable of further reducing the number of manufacturing masks at the time of manufacturing a new mask set when applying IC design / manufacturing by a master slice method. I do. For example, in a master process for a CMOS gate array, a master chip is prepared in advance. In the slicing process for realizing the circuit specifications required by the user by the multi-layer wiring, one dedicated mask for element contact formation, and a fixed mask pattern 1 in which all via hole arrangements between the wiring layers of the multi-layer wiring layer are shared thereafter First, a dedicated mask for the wiring layer of each multilayer wiring and a dedicated mask for the protective film are prepared. With these, a fixed via hole is selectively used to construct a multilayer wiring according to a circuit specification required by a user.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to manufacturing of a semiconductor integrated circuit, and more particularly, to a master slice type semiconductor integrated circuit manufacturing method, reticle and semiconductor in which a standard chip such as a gate array is prepared in advance and completed by a wiring process. The present invention relates to an integrated circuit device.

[0002]

2. Description of the Related Art A master slice is known as a design / manufacturing method applied to a semi-custom IC such as a gate array. By preparing in advance a chip called a master (standard chip) in which transistors are standardly arranged according to the desired integration scale, and achieving electrical connection and change between the transistors in accordance with the user's required function in the slicing process. Realize a dedicated integrated circuit.

That is, the master chip consists of a basic cell consisting of several elements such as transistors or a portion in which a CMOS gate array is regularly arranged and an input / output portion.
In terms of the manufacturing process, formation of transistors is completed. In the slicing step, a contact connecting the metal wiring and the transistor and a metal wiring are formed.

To use the built-in transistor as effectively as possible and to perform automatic placement and wiring using CAD, multi-layer metal wiring is used. The larger the number of wiring layers, the higher the transistor use efficiency and the shorter the time for automatic placement and wiring tends to be. However, since the manufacturing period of the slicing process increases and the cost also increases, it is usually 2
It is said that a structure formed by three to three wiring layers is desirable.

[0005]

Regarding a master slice type semiconductor integrated circuit, as is well known, in a slicing step, a via contact (via hole) to a diffusion layer such as a transistor element, a first layer wiring, and a via hole to a first layer wiring. , Various second-layer wirings are required.

In recent years, the required integrated circuits have become more complicated, and the number of integrated transistor elements in the master chip has been increasing. In addition, there is a strong tendency that the number of wiring layers in the slicing process becomes more (4-5, 6 layers) because the technique of automatic placement and routing has improved. This allows
An integrated circuit device in which the usage rate of elements is further increased is realized.

As described above, as the number of wiring layers increases, the above-described various dedicated masks for via holes, wiring layers, etc. are required. Therefore, if there is an unexpected design change, all masks must be manufactured again from the reticle. The total cost of changes for each mask is enormous and is economically unfavorable.

The present invention has been made in consideration of the above circumstances, and when applying the IC design / manufacturing by the master slice method, it is possible to further reduce the number of manufacturing masks when manufacturing a new mask set. An object of the present invention is to provide a manufacturing method, a reticle, and a semiconductor integrated circuit device.

[0009]

In the method for manufacturing a semiconductor integrated circuit according to the present invention, a group of basic elements which are regularly arranged in advance on a silicon wafer are laid, and a circuit specification required by a user is realized by multilayer wiring. Regarding the application of the master slice method, at least a part or all of the multilayer wiring uses a fixed mask pattern in which the via hole arrangement is made common, and the formed fixed via holes are selectively utilized to meet the circuit specifications. It is characterized by constructing a multi-layered wiring corresponding to it.

A semiconductor integrated circuit device according to the present invention relates to a master slice product in which a group of basic elements regularly arranged in advance on a silicon wafer is laid and a circuit specification required by a user is realized by multilayer wiring. It is characterized in that a fixed via hole is arranged between the respective wiring layers regardless of the circuit specifications during the construction of the wiring to construct a multilayer wiring according to the circuit specifications.

According to the method for manufacturing a semiconductor integrated circuit and the semiconductor integrated circuit device of the present invention, a fixed mask pattern is used to form a fixed via hole having a common via hole arrangement. New designs and changes can be made by simply changing the wiring layer mask. As a result, the fixed via holes are selectively used to construct the multilayer wiring according to the circuit specifications.

Further, in the method for manufacturing a semiconductor integrated circuit according to the present invention, a fixed mask pattern is used to uniformly dispose via holes by lithography in at least the entire region where the basic element group is laid. It is characterized by doing. Further, in the semiconductor integrated circuit device according to the present invention, the fixed via holes are uniformly and regularly arranged in at least the entire region where the basic element group is laid. As a result, it is possible to suppress the deviation of each via hole processing within the via hole formation surface and improve the processing accuracy and processing stability.

Further, regarding the improvement of processing accuracy and processing stability, in the method of manufacturing a semiconductor integrated circuit according to the present invention, the formation of the multilayer wiring layer is performed by embedding the wiring metal in the via hole and flattening the wiring layers. It is characterized by including a chemical conversion step. In the semiconductor integrated circuit device according to the present invention, due to the fixed via hole, the plugs related to the wiring and the isolated plug-shaped result not related to the wiring are mixed between the wiring layers of the multilayer wiring. Characterize. In other words, in addition to forming the plugs necessary for wiring, by forming the plug shape uniformly within the wafer surface, the in-wafer processing is uniformized including the formation of via holes and the planarization process.

The reticle according to the present invention relates to the application of the master slice method in which basic element groups regularly arranged in advance on a silicon wafer are laid and the circuit specifications required by the user are realized by multilayer wiring. Between the wiring layers, a mask pattern of via hole arrangement common to the circuit specifications is provided.

According to the reticle of the present invention, it is possible to provide a mask pattern of via hole arrangement which is made common to circuit specifications. If the required via connection between the wiring layers of the multilayer wiring is realized with at least one reticle specification, it contributes to the reduction of the number of reticle used. It is sufficient to respond to a new design or change only by changing the mask of the wiring layer. In addition, preferably, the mask pattern has a via hole arrangement having a uniform regularity over the entire region where the basic element group is laid. The versatility will be increased and the accuracy and stability of the lithography technology will be improved.

[0016]

1 is a flow chart showing a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and is a process flow taking a master slice type CMOS gate array as an example.

In the master process, a basic device group and a CMOS gate array which are regularly arranged on a silicon wafer are laid in advance. That is, well formation on a silicon substrate, element isolation pattern (element isolation insulating film) formation, threshold control impurity introduction, gate electrode formation, and source / drain region formation (including low-concentration extension regions) are usually common. It consists of a mask. This is a master chip prepared in advance.

Next, a slicing process for realizing the circuit specifications required by the user by the multilayer wiring is started. In the method of this embodiment, one dedicated mask for forming gates and source / drain contacts for the CMOS gate array and a mask pattern for commonizing all via hole arrangements between wiring layers of the subsequent multilayer wiring layer are fixed. One common dedicated mask, each multilayer wiring, each wiring layer dedicated mask up to the uppermost metal wiring, and the dedicated mask for the protective film are prepared. As a result, the fixed via holes are selectively used to construct the multilayer wiring according to the circuit specifications required by the user.

That is, a new design or change can be made only by changing the mask for the wiring layer. In other words, the via hole contact between each layer has a fixed mask pattern, and the mask is composed of one common reticle. If it can be adapted to the transistor of the basic element without any trouble, there is a possibility that the dedicated mask in the contact portion with the diffusion layer may be shared by the fixed mask pattern between the multilayer wiring layers.

According to the method of the above embodiment, a via hole contact does not require a reticle for each wiring layer, which is economical. As a result, it becomes possible to construct a multi-layer wiring according to the circuit specification by selectively using the fixed via hole. Since the technique of automatic placement and wiring has also improved, it is suitable for a master slice product having a larger number of wiring layers in the slicing process (4 to 5, 6 layers).

When using a fixed mask pattern, it is desirable that the via holes are arranged uniformly over the entire area where the basic element group is laid in order to widely correspond to new designs and changes.

Further, since the via hole is formed by the lithography technique, the basic element group is uniformly arranged in the entire region to be laid, so that the deviation of the shape of the via hole pattern is reduced and the uniform via hole pattern is highly accurate. Contributes to shape formation.

Further, in the multi-layer wiring layer, if the damascene technology including the step of burying the wiring metal in the via hole and the flattening step between the wiring layers is used, the basic element group is uniformly arranged in the entire area. Has a positive effect on flattening. That is, the planarization error in the wafer surface is reduced by the uniform via hole and the remaining metal for wiring in the wafer surface that also includes the dummy.

FIG. 2 is a pattern plan view of a reticle for forming a fixed mask pattern between wiring layers of a multilayer wiring layer according to an embodiment of the present invention. All via hole arrangements in the wiring layers of the multi-layered wiring layers are shared by the pattern 21 with this regularity, and are uniformly provided in the entire area where the basic element group is laid. The wiring grid 22 related to automatic placement and wiring is shown by a broken line and referred to.

In this embodiment, the via hole arranging pattern 21 has a matrix shape, and the via hole arranging pitch is at least larger than the arranging interval of the wiring grid 22. At a minimum, one wiring grid is required between the via hole arrangements (two here). Also, the via hole arrangement and one of the grids are overlapped (23) or they are passed between the grids (24), that is, the wiring is passed. In the case of design changes, various other common common via hole arrangements and positional relationships between grids are conceivable. A part of the wiring example is shown by a chain line.

FIG. 3 is a pattern plan view showing another example of a reticle for forming a fixed mask pattern between wiring layers of a multilayer wiring layer similar to FIG. All via hole arrangements in the wiring layers of the multilayer wiring layers are shared by the pattern 31 having this regularity, and are uniformly provided in the entire region where the basic element group is laid. The wiring grid 32 related to automatic placement and wiring is shown by a broken line and referred to.

In this embodiment, the via hole arrangement pattern 31 has a zigzag pattern, and the via hole arrangement pitch is at least larger than the arrangement interval of the wiring grid 32. Further, the layout of via holes and one of the grids are made to overlap (33) or pass between the grids (34), that is, the wiring is made to pass. In the case of design changes, various other common common via hole arrangements and positional relationships between grids are conceivable. A part of the wiring example is shown by a chain line.

According to the pattern example of each reticle described above, a mask pattern of via hole arrangement that is common to circuit specifications is provided. If the required via connection between the wiring layers of the multi-layer wiring is realized with at least one reticle specification, it will contribute to the reduction of the number of reticle used. In addition,
Since the via holes having a uniform regularity are provided in the entire region where the basic element group is laid, the versatility is increased and the accuracy and stability of the lithography technique are improved.

In the pattern example of each reticle,
Of course, a common via hole arrangement is provided for each wiring layer to the input / output section and the pad section (not shown), but it is not always necessary to lay the via hole arrangement at the same pitch as the entire area where the basic element group is laid. . It is sufficient to provide a via hole arrangement that is easy to use in each area of the input / output section and the pad section.

FIG. 4 is a semiconductor integrated circuit device according to one embodiment of the present invention and is a sectional view showing a characteristic portion of a master slice product. An interlayer insulating film 41 is formed on the element region where a part of the CMOS gate array (standard chip) is laid through the master process. Gate electrode and source
A predetermined contact part CON to the drain diffusion layer is formed. The first layer metal wiring ML1 is formed on the contact portion CON.
Are formed. On the interlayer insulating film 42 on the first-layer metal wiring ML1, there is provided a via hole arrangement that is common to all subsequent wiring layers.

That is, fixed via holes FVIA are arranged regardless of the circuit specifications, and the first layer metal wiring ML is formed.
The plug PG related to the connection with 1 and the result of the isolated plug shape NPG not related to the wiring are mixed. When the first-layer metal wiring ML1 is placed and routed on the resultant product of the plug-shaped NPG that is unrelated to the circuit connection, it is possible to intentionally avoid the placement and routing.

Next, the second layer metal wiring ML2 is selectively formed on the fixed via hole FVIA, and passes through between the arrangement of the via holes FVIA. Electrical connection is made. Also regarding the second-layer metal wiring ML2, when the wiring is arranged and routed over the result of the plug-shaped NPG that is not related to the circuit connection, it is possible to intentionally avoid and detour.

Further, an interlayer insulating film 43 is formed on the second layer metal wiring ML2, and the above-mentioned common via hole arrangement is provided on the interlayer insulating film 43. That is, fixed via holes FVIA are arranged regardless of the circuit specifications, and the plug PG related to the connection with the second layer metal wiring ML2 and the result of the isolated plug shape NPG not related to the wiring are mixed. There is.

Next, the third-layer metal wiring ML3 is selectively formed on the fixed via hole FVIA, and passes through between the via holes FVIA. Electrical connection is made. The arrangement and wiring of the third-layer metal wiring ML3 also have the same relationship with the result of the plug-shaped NPG that is not related to circuit connection.

The next fourth layer metal wiring ML4 and an upper wiring layer (not shown) are the same as those described above. That is, it is selectively formed on the fixed via hole FVIA, and a predetermined electrical connection with the lower wiring layer is made by passing between the arrangement of the via holes FVIA.

In this way, the metal wiring ML having a predetermined number of layers is formed.
1, ML2, ML3, ... Use common fixed via holes FVIA, and realize a desired integrated circuit by multilayer wiring by connecting with a selective plug PG according to required circuit specifications.

In the via hole FVIA, the one on the wiring layer related to the connection (plug PG) and the one not related to the wiring (isolated plug shape NPG) are simultaneously formed by anisotropic etching. At this time,
The height of (ML1, ML2, ML3, ...) Of each wiring layer is 5
Since the thickness is from 00 to 800 nm, if the holes that will be the plugs PG reach the wiring layer when they are detected and etching is stopped, even if the holes are to form the plug-shaped NPG, there is no danger such as a short circuit.

According to the above-described embodiment, the via hole contact is common to each wiring layer and is used without change even when the circuit design is changed or when a new circuit is designed, which is economical. Is. As a result, the fixed via holes are selectively used on the wiring layer side to form a multilayer wiring according to the circuit specifications. Since the technique of automatic placement and wiring has also improved, it can be applied to a structure having a high transistor usage rate as a master slice product having a larger number of wiring layers in the slicing process (4 to 5, 6 layers).

The via hole arrangement is uniformly arranged as a standard plug pattern over the entire area where the basic element group is laid in order to widely support new designs and changes. It is desirable to arrange the wiring regularly so as not to hinder the wiring. With such a via hole arrangement, the deflection of the via hole pattern shape and the plug shape is reduced, which contributes to the formation of a highly accurate and uniform via hole pattern shape and plug shape.

In the above-mentioned multilayer wiring layer, a damascene technique is used for forming a plug metal in a via hole, for example. That is, the metal embedded in the via hole is flattened by CMP (chemical mechanical polishing) and left as a plug shape in the interlayer insulating film. By uniformly disposing the plug shape in the entire area where the basic element group is laid, including the dummy plug shape, there is also an advantage of reducing the planarization error in the wafer surface.

[0041]

As described above, according to the present invention,
In the slicing process, a fixed mask pattern for connection between wiring layers is used to form a fixed via hole with a common via hole arrangement. New designs and changes can be made by simply changing the wiring layer mask. As a result, the fixed via holes are selectively used to construct the multilayer wiring according to the circuit specifications. By arranging the via holes uniformly over the entire area where the basic element group is laid, it is advantageous to change, and it suppresses the deviation of each via hole processing in the via hole formation surface, thereby improving the processing accuracy and processing stability. Can be increased. As a result, it is possible to provide a semiconductor integrated circuit manufacturing method, a reticle, and a semiconductor integrated circuit device that can further reduce the number of manufacturing masks when manufacturing a new mask set when applying IC design / manufacturing by the master slice method.

[Brief description of drawings]

FIG. 1 is a flow chart showing a method of manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, which is a CM of a master slice system.
It is a process flow taking the OS gate array as an example.

FIG. 2 is a pattern plan view of a reticle that forms a fixed mask pattern between wiring layers of a multilayer wiring layer according to an embodiment of the present invention.

3 is a pattern plan view showing another example of a reticle that forms a fixed mask pattern between wiring layers of a multilayer wiring layer similar to FIG.

FIG. 4 is a sectional view showing a characteristic portion of a master slice product, which is a semiconductor integrated circuit device according to an embodiment of the present invention.

[Explanation of symbols]

21, 31 ... Reticle via hole arrangement pattern 22, 32 ... Wiring grid 41, 42, 43 ... Interlayer insulating film CON ... contact part FVIA ... Fixed via hole ML1, ML2, ML3 ... Metal wiring PG ... plug NPG: isolated plug shape

Claims (8)

[Claims] 1. An application of a master slice system in which basic element groups regularly arranged in advance on a silicon wafer are laid and circuit specifications required by a user are realized by multilayer wiring, and at least a part or all of the multilayer wiring is applied. Regarding a semiconductor integrated circuit characterized by using a fixed mask pattern in which the via hole arrangement is made common, and using the formed fixed via holes selectively to construct a multilayer wiring according to the circuit specifications. Production method. 2. The fixed mask pattern is used to uniformly dispose the via holes at least in the entire region where the basic element group is laid by a lithography technique. Manufacturing method of semiconductor integrated circuit. 3. The manufacturing of a semiconductor integrated circuit according to claim 1, wherein the formation of the multi-layer wiring layer includes a step of burying a wiring metal in the via hole and a planarization step between wiring layers. Method. 4. An application of a master slice method in which basic element groups regularly arranged in advance on a silicon wafer are laid, and a circuit specification required by a user is realized by multilayer wiring, and at least between wiring layers of the multilayer wiring. A reticle that provides a mask pattern of via hole arrangement common to the circuit specifications. 5. The reticle according to claim 4, wherein the mask pattern has a via hole arrangement having a uniform regularity over the entire region where the basic element group is laid. 6. A master slice product in which basic element groups regularly arranged in advance on a silicon wafer are laid and a circuit specification required by a user is realized by multi-layer wiring. In the semiconductor integrated circuit device, fixed via holes are arranged regardless of the circuit specifications, and multilayer wiring is constructed according to the circuit specifications. 7. The semiconductor integrated circuit device according to claim 6, wherein the fixed via hole is arranged with regularity in at least the entire region where the basic element group is laid. 8. The fixed via hole allows a plug related to wiring and an isolated plug-shaped resultant not related to wiring to be mixed between wiring layers of the multilayer wiring. 6. The semiconductor integrated circuit device according to 6 or 7.