JP2003059936A - Manufacturing method of bipolar transistor - Google Patents

Abstract

(57) [Problem] To provide a bipolar transistor that simplifies manufacturing, reduces cost, and improves high-speed operation. SOLUTION: A base electrode 107 is formed of polycrystalline silicon, and an intrinsic base layer 112a and an extraction base electrode 1 are provided.
12b are connected to form a base electrode 112, and an ALD (Atomi) is formed on the surface of the intrinsic base region 112a.
c Layer Doping) to form emitter region 1
Then, an emitter electrode 114 is formed of metal on the emitter region 115. With such a manufacturing method, the emitter region 115 can be formed thin, and high-speed operation can be improved. Further, the emitter electrode 114 is
Since it can be formed together with the source electrode and the drain electrode of the MOS, the manufacturing process can be simplified and the cost can be reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a bipolar transistor, and more particularly to a bipolar transistor used in a high frequency circuit.

[0002]

2. Description of the Related Art A bipolar transistor used in a high frequency circuit is manufactured, for example, by the method disclosed in Japanese Patent Application No. 2-98116. This manufacturing method is
As shown in FIG. 6, n ^{+ is} formed on the surface of the p-type silicon substrate 201.
N consisting of a type subcollector 202 and an epitaxial layer
^The n-type subcollector 2 is formed by forming the ⁺ -type subcollector 203.
A field oxide film 204 is formed in 03. Also, n
By ion-implanting phosphorus into a predetermined region of the type subcollector 203 and thermally diffusing it, an n ⁺ type subcollector 202a is formed so as to be connected to the n ⁺ type subcollector 202. Further, a double insulating film of a silicon oxide film 205 and a silicon nitride film 206 is sequentially formed on the n-type sub-collector 203, a base electrode 207 made of p ⁺ -type polycrystalline silicon is formed thereon, and a silicon oxide film 208 is formed. Form. Next, the silicon oxide film 208 and the base electrode 207.
Is dry-etched to form the opening 210, and the opening 21 is formed.
A first sidewall 209 made of a silicon oxide film is formed on the inner wall of 0.

Next, as shown in FIG. 7, the silicon oxide film 205 and the silicon nitride film 206 are etched by etching to form a wider opening 211 under the opening 210. At this time, the base electrode 207
Forms an eaves portion 207a protruding toward the opening 211 on the side of the opening 211, and the lower surface of the eaves portion 207a is exposed in the opening 211.

Thereafter, as shown in FIG. 8, a base layer 212 is grown by the CVD method. In this growth, the intrinsic base layer 212a of single crystal silicon grows on the single crystal n-type subcollector 203, and the drawn base layer 212b of polycrystalline silicon grows from the lower surface of the eaves portion 207a of the base electrode 212. Thus, the intrinsic base layer 212
The a and the extraction base layer 212b grow from below and above, respectively, and are connected and integrated. On the other hand, in the central portion of the intrinsic base layer 212a, only single crystal silicon grows from bottom to top to form the recess 212c. Here, the film thickness of the intrinsic base layer 212a is about 40 to 120 nm.

Next, as shown in FIG. 9, a second sidewall 213 is formed of a silicon oxide film, and the silicon oxide film 205 and the silicon nitride film 206 are removed by etching to expose the n ⁺ type subcollector 203a. rear,
The emitter electrode 214 and the collector electrode 216 are formed of polycrystalline silicon. Then, as shown in FIG.
As for the emitter electrode 214, 70 keV, 5 × 10 ¹⁵ c
Ion implantation at m ^-2 , 900-10 in nitrogen atmosphere
A heat treatment is performed at 00 ° C. for 1 hour to diffuse n-type impurities from the emitter electrode 214 to the intrinsic base layer 212a. As a result, the intrinsic base layer 2 below the emitter electrode 214
An emitter region 215 is formed on 12a. The emitter region 215 thus formed has a depth of 35 nm and a surface concentration of 6 × 10 ²⁰ cm ⁻³ .

[0006]

In the conventional manufacturing method as described above, the step of forming the base electrode 207 and the step of forming the emitter electrode 214 are both made of polycrystalline silicon. On the other hand, in the CMOS manufacturing process, the gate electrode is made of polycrystalline silicon, but the source and drain electrodes are made of metal. Therefore, it is difficult for the above-described bipolar transistor manufacturing method to match the CMOS manufacturing process, and cost reduction is hindered.

Further, since polycrystalline silicon is used for the emitter electrode 214, it is difficult to reduce the parasitic resistance due to the emitter electrode 214, which hinders high speed operation. An object of the present invention is to simplify manufacturing and reduce cost in a bipolar transistor.

Another object of the present invention is to improve high speed operation in a bipolar transistor.

[0009]

A method of manufacturing a bipolar transistor according to a first aspect of the present invention is a method of manufacturing a bipolar transistor on a semiconductor substrate, wherein a first region of a first conductivity type is formed on the semiconductor substrate. 1 region forming step,
A first electrode forming step of forming a first electrode so as to be electrically connected to the first region, and a second conductivity type second electrode on the first region.
A second region forming step of forming a region; a second electrode forming step of forming a second electrode so as to be electrically connected to the second region; and a first electrode forming so as to be electrically connected to the second region. The third region of the conductivity type is set to ALD (Atomic Layer Do
ping) method for forming a third region, and
And a third electrode forming step of forming a third electrode on the region.

In this manufacturing method, ALD (Atomic)
By forming the third region by the Layer Doping method, the third region can be thinly formed. As a result, the speed of the bipolar transistor can be increased. A method for manufacturing a bipolar transistor according to a second aspect of the present invention is the method for manufacturing a bipolar transistor according to the first aspect, wherein the second electrode forming step includes a step of forming the second electrode from polycrystalline silicon, and the third electrode forming step comprises It includes a step of forming the third electrode with a metal.

In this manufacturing method, the third electrode is formed of metal on the third region formed by the ALD method. Therefore, as compared with the case where both the second electrode and the third electrode are made of polycrystalline silicon, the step of forming polycrystalline silicon can be reduced. Further, the third electrode forming step is a step of forming electrodes with a metal, and thus can be performed together with the step of forming the source and drain electrodes of the CMOS. This can reduce the manufacturing cost of the bipolar transistor. Furthermore, since the third electrode is formed of metal, the parasitic resistance value can be reduced and high-speed operation can be improved as compared with the case where the third electrode is formed of polycrystalline silicon.

A bipolar transistor according to a third aspect of the invention is
A bipolar transistor formed on a semiconductor substrate, comprising: a first region of a first conductivity type formed on a semiconductor substrate; a first electrode electrically connected to the first region; and a first electrode formed on the first region. The formed second region of the second conductivity type and the second region electrically connected to the second region and formed of polycrystalline silicon.
The ALD (Atom) is electrically connected to the electrode and the second region.
The third region of the first conductivity type is formed by the ic layer doping method, and the third electrode is formed of metal on the third region.

This bipolar transistor is manufactured by the method for manufacturing a bipolar transistor according to the second aspect of the invention. Therefore, as described above, compared with the case where both the second electrode and the third electrode are made of polycrystalline silicon, it is possible to reduce the step of forming polycrystalline silicon. Further, since the third electrode step is a step of forming an electrode with a metal,
This can be performed together with the step of forming the source and drain electrodes of the CMOS. This can reduce the manufacturing cost of the bipolar transistor. Furthermore, since the third electrode is formed of metal, the parasitic resistance value can be reduced and high-speed operation can be improved as compared with the case where the third electrode is formed of polycrystalline silicon.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION [Structure] FIGS. 1 to 4 are sectional views for explaining a manufacturing process of a bipolar transistor according to an embodiment of the present invention, and FIG. It is a completed sectional view of a transistor.

Bipolar transistor according to the present embodiment
Is n on the p-type silicon substrate 101. ⁺Type sub-collector 1
02 and n-type sub-collector 103 are formed, and n
A mold made of a silicon oxide film is formed in the mold subcollector 103.
A field oxide film 104 is formed. Also, n⁺Type
N as connected to the sub-collector 102⁺Type sub-collection
The tractor 102a is formed. Furthermore, n-type sub-collection
Silicon oxide film 105 and silicon nitride
The double insulating film of the chemical conversion film 106 is formed.
A base electrode 107 made of polycrystalline silicon is formed on top
Silicon oxide on the base electrode 107.
The chemical film 108 is formed.

An opening 110 is formed in the base electrode 107 and the silicon oxide film 108, and the opening 110 is formed.
A first sidewall 109 made of a silicon oxide film is formed on the inner wall of the. A base layer 112 is formed below the opening 110 so as to be connected to the base electrode 107. The base layer 112 is composed of an intrinsic base layer 112a made of single crystal silicon and a lead base layer 112b made of polycrystalline silicon. Further, the base layer 112 is formed with a recess 112c continuous with the opening 110.

A second sidewall 113 is formed on the inner wall of the recess 112c and the inner wall of the first sidewall 109. Inside the second sidewall 113, ALD (Ato (Ato) is formed on the surface of the intrinsic base layer 112a.
The emitter region 115 is formed by the mic layer doping method. An emitter electrode 114 made of a metal such as aluminum or copper is formed on the emitter region 115. Furthermore, the emitter electrode 1
The side surface of 14 is covered with a silicon oxide film 116. In addition, the collector electrode 117 is an n ⁺ type sub-collector 1
Connected to 02a.

[Manufacturing Flow] The manufacturing process of the bipolar transistor of this embodiment will be described below with reference to FIGS. As shown in FIG. 1, the resistivity is 50 Ωcm,
On the surface of the p-type silicon substrate 101 having the plane orientation (100),
N ⁺ subcollector 102 with an As concentration of about 10 ²¹ cm ^-3
And an n-type subcollector 103 formed of an epitaxial layer having an As concentration of about 10 ¹⁸ cm ⁻³ . Further, a field oxide film 104 of a silicon oxide film exposed on the surface of the n-type subcollector 103 is formed. Further, a silicon oxide film 105 and a silicon nitride film 106 are formed on the n-type subcollector 103 by CVD, and then,
A base electrode 107 made of p ⁺ polycrystalline silicon is formed, and a silicon oxide film 10 is formed so as to cover the base electrode 107.
8 is formed. Further, phosphorus is ion-implanted into a predetermined region of the n-type subcollector 103 and thermally diffused to form the n ⁺ -type subcollector 102 a so as to be connected to the n ⁺ -type subcollector 102. Then, the base electrode 107 and the silicon oxide film 108 are dry-etched to form the opening 1
10 is formed, and the first sidewall 109 is formed on the inner wall of the opening 110 with a silicon oxide film.

Next, as shown in FIG. 2, the silicon oxide film 105 and the silicon nitride film 106 are removed by wet etching to form a wider opening 111 continuously below the opening 110. At this time, a part of the n-type subcollector 103 is exposed on the bottom surface of the opening 111. Also,
The lower surface of the base electrode 107 is exposed to the opening 111 at the end portion on the side of the opening 111, and constitutes the eaves portion 107a.

Thereafter, as shown in FIG. 3, a base layer 112 is heteroepitaxially grown on the n-type sub-collector 103 with p-type silicon germanium. On the surface of the n-type sub-collector 103, since the n-type sub-collector 103 is single crystal silicon, the intrinsic base layer 11 of single-crystal silicon extends upward from the surface of the n-type sub-collector 103.
2a grows. On the other hand, on the lower surface of the base electrode 107,
Since the base electrode 107 is polycrystalline silicon, the polycrystalline silicon extraction base layer 112b grows downward from the lower surface of the base electrode 107. In this way, the intrinsic base layer 112a and the extraction base layer 11 that grow vertically are formed.
2b is continuous under the eaves portion 107a and integrally forms the base layer 112. Eaves part 107a
In the central portion of the intrinsic base layer 112a which is not located below the base layer 112, only the intrinsic base layer 112a grows.
2c is formed.

The film formation method of silicon germanium is AP
Although there are a CVD method, an LPCVD method, a UHV-CVD method and the like, it is preferable to use the UHV-CVD method which can obtain a high quality silicon germanium film at a low temperature. In this embodiment, the UHV-CVD method is used, and the film formation temperature is 550 ° C.
Si was used as a film forming gas under the film forming pressure of 10 ⁻³ Torr.
H ₄ , GeH _4, and B ₂ H ₆ were used. The boron concentration was set to about 10 ¹⁸ cm ⁻³ , and the germanium concentration was set to a gradient distribution with a peak value of 15%. As a result of film formation under these conditions,
A 100 nm intrinsic base layer 107 was obtained.

Next, as shown in FIG. 4, after the second sidewall 113 is formed on the first sidewall 109, an ALD (Atomic La) is formed on the bottom surface of the recess 112c.
The emitter region 115 is formed by the yer doping method. The formation of the emitter region 115 by the ALD method is
First, using AsH ₃ gas, arsenic is adsorbed on the surface of the intrinsic base region 112a by the UHV-CVD method under the processing temperature of 550 ° C. and the pressure of 3 × 10 ⁻¹⁰ Torr. Next, a silicon oxide film is grown at 450 ° C. to form a cap layer. Then, RTA (R
arsenic is diffused inward from the surface of the intrinsic base region 112a and activated by rapid thermal annealing. Then, the cap layer is removed by etching.

Intrinsic base region 1 formed in this embodiment
The arsenic atoms adsorbed on the surface of 12a are arranged most densely in one layer. Since the diameter of the arsenic atom is 0.23 nm, the surface density of the adsorbed arsenic atom is 1 / (0.23 × 10 ^-7 ) ² cm ²
= 2 × 10 ¹⁵ cm ⁻² , and RTA (Rapid Th
This is equivalent to ion implantation of 2 × 10 ¹⁵ cm ⁻² since all arsenic atoms are doped by the optical annealing. The depth of the emitter region 115 formed by the ALD method is 20 nm, and the surface concentration is 2 × 10 ¹⁵ cm ⁻² / 20 × 10 ⁻⁷ cm = 1 × 10 ²⁰ c.
m ^-3 . The surface concentration and depth of the emitter region are changed by adjusting the temperature and time of the RTA according to the demand for withstand voltage or high speed.

After forming the emitter region 115 as described above, as shown in FIG. 5, a silicon oxide film 116 is formed as an interlayer film, and a contact hole is formed so as to expose the emitter region 115 and the n + type subcollector 102a. After being formed, the emitter electrode 11 is made of aluminum or copper.
4 and the collector electrode 117 are formed. The formation of the emitter electrode 114 and the collector electrode 117 can be performed simultaneously with the step of forming the source and drain electrodes of the CMOS.

[Summary] In the bipolar transistor of this embodiment, since the emitter region 115 is formed by the ALD method, it is not necessary to form the polycrystalline silicon emitter electrode 114 and perform ion implantation through the emitter electrode 114. Therefore, in the present embodiment, the emitter electrode 11
4 can be formed of a metal, and the step of stacking polycrystalline silicon can be reduced. In addition, the emitter electrode 114
Since the collector electrode 117 and the collector electrode 117 are made of metal, the process of forming the emitter electrode 114 and the collector electrode 117 is
It can be performed simultaneously with the step of forming the source and drain electrodes of the MOS. As a result, the manufacturing process is simplified,
The manufacturing cost of the bipolar transistor can be reduced.

In the present embodiment, the emitter electrode 11
Since 4 is made of metal, the parasitic resistance can be reduced as compared with the case of being made of polycrystalline silicon. As a result, the high speed operation of the bipolar transistor can be improved.

[0027]

According to the present invention, the manufacturing of the bipolar transistor can be simplified and the cost can be reduced. Further, according to the present invention, the high speed operation of the bipolar transistor can be improved.

[Brief description of drawings]

FIG. 1 is a manufacturing flow (1) of a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a manufacturing flow (part 2) of the bipolar transistor according to the embodiment of the present invention.

FIG. 3 is a manufacturing flow (No. 3) of the bipolar transistor according to the embodiment of the present invention.

FIG. 4 is a manufacturing flow (4) of the bipolar transistor according to the embodiment of the present invention.

FIG. 5 is a completed cross-sectional view of a bipolar transistor according to an exemplary embodiment of the present invention.

FIG. 6 is a manufacturing flow (1) of a conventional bipolar transistor.

FIG. 7 is a manufacturing flow (2) of a conventional bipolar transistor.

FIG. 8 is a manufacturing flow (3) of a conventional bipolar transistor.

FIG. 9 is a manufacturing flow (4) of a conventional bipolar transistor.

FIG. 10 is a completed sectional view of a conventional bipolar transistor.

[Explanation of symbols]

101 p-type silicon substrate 102, 102a n ⁺ subcollector 103 n-type subcollector 104 field oxide film 105 silicon oxide film 106 silicon nitride film 107 base electrode 107a eaves portion 108 silicon oxide film 109 first sidewalls 110, 111 opening 112 Base layer 112a Intrinsic base layer 112b Lead-out base layer 112c Recess 114 Emitter electrode 115 Emitter region 116 Silicon oxide film 117 Collector electrode

Claims (3)

[Claims] 1. A method of manufacturing a bipolar transistor on a semiconductor substrate, the method comprising: forming a first region of a first conductivity type on the semiconductor substrate; forming a first region electrically; A first electrode forming step of forming a first electrode so as to be connected, and a second step of forming a second region of a second conductivity type on the first region
A region forming step, a second electrode forming step of forming a second electrode so as to be electrically connected to the second region, and a first conductivity type first electrode so as to be electrically connected to the second region. ALD (Atomic Layer Dop)
ing) method for forming a third region, and a third electrode forming process for forming a third electrode on the third region. 2. The second electrode forming step includes a step of forming the second electrode with polycrystalline silicon, and the third electrode forming step includes a step of forming the third electrode with a metal. 1. The method for manufacturing the bipolar transistor according to 1. 3. A bipolar transistor formed on a semiconductor substrate, wherein a first region of a first conductivity type formed on the semiconductor substrate and a first electrode electrically connected to the first region. A second region of the second conductivity type formed on the first region, a second electrode electrically connected to the second region and formed of polycrystalline silicon, and an electrical connection to the second region. ALD (Atomi)
A bipolar transistor including a third region of the first conductivity type formed by the c Layer Doping method, and a third electrode formed of a metal on the third region.