JP2003059279A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce cell area of a semiconductor memory in which rewriting and erasure can be performed with a small data unit such as a bit unit or a byte unit. SOLUTION: A first secondary word line SWL1, a second secondary word line SWL2, and a third secondary word line SWL3 intersecting with first and second word lines WL1, WL2, that is, extending in parallel to each bit line BL1-BL3 are arranged. The first secondary word line SWL1 is electrically connected to secondary control gates 29 of first and second memory cells 11, 12, the second secondary word line SWL2 is electrically connected to secondary control gates 29 of third and fourth memory cells 13, 14, and the third secondary word line SWL3 is electrically connected to secondary control gates 29 of fifth and sixth memory cells 15, 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, in a nonvolatile semiconductor memory device having a floating gate and a control gate capacitively coupled to the floating gate, a floating gate and a control gate are stacked in this order, instead of a stack type gate. There has been proposed a non-volatile semiconductor memory device having a split type gate that is capacitively coupled directly to a semiconductor substrate.

(First Conventional Example) FIG. 14 shows a sectional structure of a memory cell in a split type nonvolatile semiconductor memory device according to the first conventional example. As shown in FIG.
The conventional semiconductor memory device includes a floating gate 103 formed on a semiconductor substrate 101 via a tunnel insulating film 102, a capacitance insulating film 104 on the side of the floating gate 103, and a semiconductor substrate 101 and a gate insulating film 105. Control gate 10 formed through
6 and 6.

A source region 107 is formed on the semiconductor substrate 101 on the side of the control gate 106.
A drain region 108 is formed in a region lateral to the floating gate 103.

As described above, since the control gate 106 is provided on the channel of the semiconductor substrate 101,
Floating gate 103 and control gate 1
It is possible to directly control the off operation of the transistor including 06 by the control potential applied to the control gate 106 without passing through the capacitive coupling of the floating gate unlike the stack type. As a result, it is possible to avoid an over-erase phenomenon that occurs in the stack type memory cell, that is, a phenomenon in which the floating gate is charged to a positive potential and the transistor is not turned off even when the ground potential (0 V) is applied to the control gate.

15A and 15B show a split type nonvolatile semiconductor memory device according to a first conventional example, and FIG. 15A shows a portion in which a plurality of memory cells are arranged in an array. FIG. 15B shows a planar configuration thereof.

As shown in FIGS. 15 (a) and 15 (b), the first memory cell 201 and the second memory cell 202, the third memory cell 203 and the fourth memory cell 203 which share their drains, respectively. Memory cell 204, and fifth memory cell 205 and sixth memory cell 206.

First, third and fifth memory cells 201,
Each control gate of 203, 205 is connected to the first word line WL1, and each control gate of the second, fourth and sixth memory cells 202, 204, 206 is
It is connected to a second word line WL2 extending in parallel with the first word line WL1.

First word line WL1 and second word line W
The source line SL extending between the memory cell 201 and each of the memory cells 201
~ 206 drain.

First and second memory cells 201, 202
Of the source of each word line WL1, WL2 and source line S
Connected to a first bit line BL1 that intersects L, respectively, and sources of the third and fourth memory cells 203 and 204 are connected to a second bit line BL2 extending in parallel with the first bit line BL1; Fifth and sixth memory cells 20
The sources of 5, 206 are connected to a third bit line BL3 extending in parallel with the second bit line BL2.

16 (a) to 16 (c) are bias voltages for the respective memory cells 201 to 206 in respective operations, and FIG. 16 (a) shows a write operation, and FIG.
16B shows the read operation, and FIG. 16C shows the erase operation.

In a normal memory cell array, a large number of memory cells are formed so as to share a word line WL, a bit line BL and a source line SL, so that a plurality of memory cells simultaneously perform a write operation, an erase operation or a read operation. Take action.

As shown in FIG. 16A, if a control voltage of 5 V is applied to the first word line WL1 during the write operation, for example, the first word line WL1 shown in FIG. The first, third and fifth memory cells 201, 203 and 205 which share the source line SL are simultaneously written. On the other hand, each bit line BL1 to BL3
Since the control voltage applied to each bit line can be controlled independently, for example, the potential of the first bit line BL1 connected to the first memory cell 201 for writing is set to 5V and the other bit lines BL2 and BL3 are set. By setting the same potential as the source line SL, the first memory cell 201 can be selected and written.

Next, as shown in FIG. 16B, during the read operation, for example, 2.5 V is applied to the first word line WL1.
Control voltage is applied to the first memory cell 201 and the third memory cell 20 sharing the first word line WL1.
The bit lines B from the third and fifth memory cells 205 at the same time
A read current flows through L1 to BL3. At this time, usually, a circuit configuration is adopted in which only the potential of the first bit line BL1 connected to the first memory cell 201 to be read is selected by a column switch or the like and sensed.
It becomes possible to select and read the memory cell 201.

Next, as shown in FIG. 16C, during the erase operation, for example, a negative control voltage of -6V is applied to the first word line WL1 and a positive control of 6V is applied to the source line SL. Apply voltage. In this way, the source line S
The first and the third sharing the L and the first word line WL1
And the fifth memory cells 201, 203 and 205 are erased at the same time, and it is not possible to select any one of the memory cells.

Normally, one word line WL and one source line S
Since a memory cell in units of kilobits is connected to L, the data is erased collectively in large data units of kilobits. Such an EEPROM device that erases all at once is generally called a flash memory device, while a nonvolatile semiconductor memory device that can be erased in small units of about 1 bit or 1 byte is simply an EEPROM.
The device is called, and these distinctions are used in the present application.

The fact that the erasing operation of the flash memory device is collectively performed in a relatively large unit means that the rewriting cannot be arbitrarily performed in a small data unit of about 1 bit or 1 byte. . This feature of being able to be erased in a batch does not cause any particular problem in applications such as storing instruction programs or mass storage.

However, when it is used for temporary storage of data at the time of executing a program, rewriting is performed in bit units or byte units, so that FIG.
It is not possible to use a flash memory device having such an array configuration.

(Second Conventional Example) Now, a second conventional example in which an EEPROM device is realized by using a split type memory cell will be described.

FIGS. 17A and 17B show a split type EEPROM device according to a second conventional example, and FIG. 17A shows a partial circuit in which a plurality of memory cells are arranged in an array. The configuration is shown, and FIG. 17B shows the planar configuration.

The difference from the first conventional example is that the source line SL is provided in parallel with the bit line BL, that is, so as to cross the word line WL.

For example, as shown in FIG. 16 (a), the first
The source line SL1 of the first to fourth memory cells 201 to 2 is
Connected to the drain of 04, the second source line SL2 is
Here, it is connected to the fifth and sixth memory cells 205 and 206.

In the EEPROM device having such a structure, it is assumed that a negative control voltage is applied to the first word line WL1 and a positive control voltage is applied to the first source line SL1 during the erase operation. Only the first memory cell 201 and the third memory cell 203 which are accessed by the first word line WL1 and the first source line SL1 are erased,
Fifth memory cell 2 connected to first word line WL
05 is not erased.

As for the write operation and the read operation, like the first conventional example, only the desired memory cell can be accessed. Therefore, an EEPROM device capable of rewriting in units of 2 bits is realized.

[0025]

However, in the EEPROM device according to the second conventional example, as shown in FIG. 16B, a plurality of source lines SL1 and SL2 are arranged in parallel with the bit lines BL1 to BL3. A cell area is increased because a space for arranging is required. As a rough estimate,
This is about 1.5 times that of the memory cell shown in (b). This is an EEPROM constructed by adding an access MOS transistor to a conventional stack type memory cell.
As in the case of the device, there is a problem that the cell area cannot be easily reduced.

An object of the present invention is to solve the above-mentioned conventional problems and to realize a reduction in the cell area of an EEPROM device capable of rewriting and erasing in small data units such as bit units or byte units. To do.

[0027]

In order to achieve the above object, the present invention provides a semiconductor memory device in addition to a normal first control gate and a first word line, and a second control circuit for controlling the potential of a floating gate. The control gate and the second word line are provided so as to intersect with the first word line.

Specifically, the semiconductor memory device according to the present invention includes a floating gate formed on a semiconductor substrate via a first insulating film, and a capacitance via a floating gate and a second insulating film. A plurality of memory cells each including a first control gate coupled to each other, a floating gate, and a second control gate capacitively coupled to the first control gate and a third insulating film; A first control (word) line electrically connected to the second control gate, and a second control (word) line electrically connected to the second control gate,
The first control line and the second control line are provided so as to intersect with each other.

According to the semiconductor memory device of the present invention, each memory cell has a second control gate, which is capacitively coupled to the floating gate and the first control gate through the third insulating film, and the second control gate. And a second control line electrically connected to the second control line, and the second control line is provided so as to intersect with the first control line,
Since the memory cell to be accessed can be specified by the first control line and the second control line, the memory cell erase operation can be performed in a data unit as small as a bit / byte unit. Further, since the second control line intersects with the first control line, it is inevitably in the same direction as the bit line extends, so that the cell area does not increase much compared to the flash memory device.

In the semiconductor memory device of the present invention, a plurality of memory cells are arranged in an array, a first control gate is formed on a semiconductor substrate via an insulating film, and a floating gate is the first control gate. Is preferably formed on the side surface of the floating gate via the second insulating film, and the second control gate is formed on the upper surface and the side surface of the floating gate via the third insulating film.

In the semiconductor memory device of the present invention, it is preferable that a step portion straddling the floating gate is provided below the floating gate on the semiconductor substrate.

The semiconductor memory device of the present invention has a plurality of second control lines, and further includes a plurality of driver circuits for applying a predetermined control voltage to each second control line. Is preferred.

In this case, it is preferable to perform the read operation by applying a positive control voltage to the second control line.

In this case, it is preferable that the write operation be performed by applying a positive control voltage to the second control line.

Further, it is preferable that the positive control voltage is higher than the control voltage applied to the first control line.

The semiconductor memory device of the present invention comprises a first driver circuit for applying a positive control voltage to the first control line and a second driver circuit for applying a negative control voltage to the second control line.
It is preferable to further include the driver circuit of.

In this case, it is preferable that the second driver circuit also generate a positive control voltage higher than the positive control voltage and apply it to the second control line.

In the semiconductor memory device of the present invention, a plurality of first control lines are provided, and during the erase operation of the memory cell connected to one first control line of the plurality of first control lines. It is preferable that the control voltage applied to the one first control line and the control voltage applied to another first control line adjacent to the one first control line are set to different voltage values.

[0039]

(First Embodiment) First Embodiment of the Present Invention
Embodiments will be described with reference to the drawings.

FIG. 1 shows a split type EEPROM device according to the first embodiment of the present invention, and shows a partial circuit configuration in which a plurality of memory cells are arranged in an array.

As shown in FIG. 1, the memory cell array of the semiconductor memory device according to the first embodiment has a first memory cell 11 and a second memory cell 12 which share a drain between adjacent memory cells. The third memory cell 13 and the fourth memory cell 14 and the fifth memory cell 15 and the sixth memory cell 16 are included.

First, third and fifth memory cells 11, 1
The control gates 3 and 15 are connected to the first word line W
Second, fourth and sixth memory cells 1 connected to L1
Each of the control gates 2, 14 and 16 is connected to a second word line WL2 extending in parallel with the first word line WL1.

The source line SL extending between the first word line WL1 and the second word line WL2 is composed of the memory cells 11 to 11.
It is connected to each of the 16 shared drains.

The sources of the first and second memory cells 11 and 12 are connected to the first bit line BL1 intersecting with the word lines WL1 and WL2 and the source line SL, respectively, and the third and fourth memory cells are connected. The sources of 13 and 14 are connected to the second bit line BL2 extending parallel to the first bit line BL1, and the sources of the fifth and sixth memory cells 15 and 16 are parallel to the second bit line BL2. Is connected to a third bit line BL3 extending to.

A feature of the first embodiment is that the first and second secondary word lines SWL1 and SWL1 intersect the first and second word lines WL1 and WL2, that is, extend in parallel with the bit lines BL1 to BL3. Word line SWL2
And a third secondary word line SWL3.

The first secondary word line SWL1 is electrically connected to the secondary control gate (SCG) 29 of the first and second memory cells 11 and 12, and the second
Of the secondary word line SWL2 of the third and fourth memory cells 13 and 14
Electrically connected to the third secondary word line SWL
3 is electrically connected to the secondary control gates 29 of the fifth and sixth memory cells 15 and 16.

Although not shown, each word line W
L1, WL2, secondary word lines SWL1 to SWL
A word line driver circuit capable of setting these potentials to desired values is connected to the end portions of 3 and the source line SL, respectively.

Similarly, although not shown, a bit line driver circuit capable of setting these potentials to desired values and an end portion of each bit line BL1 to BL3, and each bit line BL1.
To a BL3 potential, the sense amplifier is connected to detect and further amplify.

FIG. 2A shows an E corresponding to the partial circuit of FIG.
FIG. 2 (b) is a plan view of the EPROM device.
The cross-sectional structure in the IIb-IIb line of (a) is shown.
2A and 2B, the same components as those shown in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2 (a) or FIG. 2 (b),
The first memory cell 11 is, for example, a floating gate 22 formed on a semiconductor substrate 20 made of p-type silicon via a tunnel insulating film 21 made of silicon oxide.
And the capacitance insulating film 2 on the side of the floating gate 22.
3 and a control gate 25 formed via a semiconductor substrate 20 and a gate insulating film 24 made of silicon oxide. Here, the capacitive insulating film 23 may be formed of the same insulating film as the tunnel insulating film 21, or may have a laminated structure of, for example, silicon oxide and silicon nitride. In addition, the gate insulating film 24 and the tunnel insulating film 2
1 and 1 may be formed of the same insulating film.

An n ⁺ type source region 26 is formed on the side of each control gate 25 on the semiconductor substrate 20, and an n ⁺ type drain region 27 is formed in a region between the floating gates 22. Has been done.

Each floating gate 22 and each control gate 25 in the first memory cell 11 and the second memory cell 12 is covered with a secondary control gate 29 via an inter-cell insulating film 28 made of, for example, silicon oxide. .

In FIG. 2A, word lines WL1 and W
The L2 and the secondary word lines SWL1 to SWL3 are both made of polysilicon, and the source line SL is the semiconductor substrate 20.
Is formed by impurity diffusion on the upper part of the.

The bit lines BL1 to BL3 are made of aluminum and are electrically connected to the sources of the memory cells 11 to 16 by contact plugs.

As described above, since the secondary control gate 29 has the coupling capacitance with both the floating gate 21 and the control gate 24, the potential of each floating gate 22 is influenced by the potential of each control gate 25 and the potential of the secondary control gate 29. Affected by.

The floating gate 21 and the control gate 24 of this secondary control gate 29
A bias voltage for each operation is applied to each node by using capacitive coupling with respect to each of the memory cells 11 to control the potential of the floating gate 22 which is in an electrically insulating (floating) state. To operate.

The bias conditions at each operation in the EEPROM device having the secondary control gate in addition to the normal control gate as described above will be described below with reference to FIGS. 3 (a) to 3 (c).

First, as shown in FIG. 3A, in the write operation, a positive control of about 5 V is applied to the control gate 25 and the drain 27 so that electrons are injected into the floating gate 22 of the memory cell to be written. A voltage (bias voltage) is applied, and the secondary control gate 29 is set to 0V. The control gate bias value in this case is adjusted so that the potential of the floating gate 22 can be sufficiently increased only by the coupling capacitance with the control gate 25.

Next, as shown in FIG. 3B, during the read operation, a positive control voltage of about 2.5 V is applied to the control gate 25 connected to the memory cell to be read, and the source 26 ( = Control voltage of about 1 V is applied to the bit line BL), and the drain 27 (= source line SL) is set to 0 V
Raises the potential of the adjacent floating gate 22. Also in this case, as in the write operation, the control voltage of the secondary control gate 29 is set to 0 V, so that the control gate bias value is only the coupling capacitance with the control gate 25.
The potential of is adjusted to be as high as necessary.

Next, as shown in FIG. 3C, a negative control voltage of about -6 V is applied to the secondary control gate 29 connected to the memory cell to be erased, and a positive voltage of about 5 V is applied to the drain 27. Is applied to lower the potential of the floating gate 22. At this time, the potential of the floating gate 22 that is capacitively coupled to the secondary control gate 29 is lowered to generate a predetermined potential difference with respect to the drain 27.

As described above, in the first embodiment,
As a bias application method during the erase operation, a positive voltage is applied to the source line SL as in the conventional case, but a negative voltage is not applied to the control gate 25 (= word line WL), and instead, a secondary control gate 29 ( A negative voltage is applied to the secondary word line SWL).

Therefore, if a positive voltage is applied to each drain 27 of the memory cells 11 to 16 connected to the source line SL, for example, a negative voltage of about -6 V is applied only to the first secondary word line SWL1. Then, the first and second
Only in the memory cells 11 and 12, the potential of the floating gate 22 can be lowered by capacitive coupling with the secondary control gate 29. This allows
It is possible to select and erase a 2-bit memory cell from a memory cell array in which a plurality of memory cells are integrated.

Although the first embodiment has been described using the split type memory cell, the present invention is not limited to this, and the present invention can be applied to other EEPROM devices such as a stack type memory cell.

(First Modification of First Embodiment) A first modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 shows a sectional structure of an EEPROM device according to a first modification of the first embodiment. In FIG. 4, the same components as those shown in FIG. 2B are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 4, in this modification, the area between the secondary control gate 29 and the floating gate 22 is reduced by digging the region between the floating gate 22 and the inter-cell insulating film 28A into a recess. Is increasing. As described above, by increasing the coupling capacitance between the secondary control gate 29 and the floating gate 22, the influence of the potential of the secondary control gate 29 on the floating gate 22 can be more strongly exerted.

In this modification, the secondary control gate 29 and the drain 27 are erased during the erase operation.
Since a high potential difference is generated between the
It is necessary to set the film thickness of A to a value that ensures a sufficient breakdown voltage.

(Second Modification of First Embodiment) A second modification of the first embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a sectional structure of an EEPROM device according to a second modification of the first embodiment. In FIG. 5, the same components as those shown in FIG. 2B are designated by the same reference numerals and the description thereof will be omitted. In FIG. 5, the same components as those shown in FIG. 2B are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 5, in the present modification, the step portion 20a in which the control gate 25 is located in the upper stage and the drain region 27 is located in the lower stage is provided on the semiconductor substrate 20.
Is provided. With this configuration, the height dimension of the floating gate 22 on the semiconductor substrate 20 is increased, and the area facing the secondary control gate 29 is further increased. Therefore, the coupling capacitance between the secondary control gate 29 and the floating gate 22 is increased. Will increase even more.

Moreover, since the floating gate 22 is formed so as to straddle the step portion 20a, the floating of hot electrons generated in the channel region formed in the lower portion of the control gate 25 in the semiconductor substrate 20 during the writing operation. The injection efficiency into the gate 22 is improved.

In this modification, the secondary control gate 29 and the drain 27 are also erased during the erase operation.
Since a high potential difference is generated between the
It is necessary to set the film thickness of A to a value that ensures a sufficient breakdown voltage.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows an EE according to the second embodiment of the present invention.
3 shows the configuration of each driver circuit for a word line and a secondary word line in a PROM device.

In the second embodiment, each driver circuit of the word line and the secondary word line for driving the EEPROM device according to the first embodiment and its modification will be described.

FIG. 6 shows only one memory cell 10 in the memory cell array and a word line WL, a source line SL, a secondary word line SWL and a bit line BL connected to the memory cell 10.

The word line WL is a positive voltage source 31 capable of driving the memory cell 10 at a voltage of the input port 30 which receives an input signal from a decoder circuit (not shown), that is, a ground voltage (0V) to a power supply voltage (Vdd). It is connected to the word line driver circuit 40 which is composed of a level shifter for boosting the voltage up to.

The word line driver circuit 40 has a source connected to the positive voltage source 31, a drain connected to the word line WL, a first PMOS transistor 41, a source connected to the ground voltage source 32, and a drain connected to the first voltage source 32. The first NMOS transistor 42 connected to the word line WL in common with the first PMOS transistor, the gate connected to the inverter 43, the source connected to the positive voltage source 31, and the drain connected to the first PMOS transistor 41. Second PMOS transistor 4 connected to the gate and grounded
4 and a second NMOS transistor 45 whose drain is connected to the gate of the first PMOS transistor 41, whose source is grounded, and whose gate is connected to the input port 30.

Each secondary word line SWL is connected to a negative voltage driver circuit 52 which is a secondary word line driver and controlled independently. Therefore, although not shown, a plurality of negative voltage driver circuits 50 are provided corresponding to the secondary word lines SWL.

As described in the first embodiment, the EEPROM device according to the present invention, during the erase operation shown in FIG.
No negative voltage is applied to the control gate 25.
Instead, the negative level shifter function is transferred to the negative voltage driver circuit 35 connected to the secondary word line SWL.

As described above, since the portion for generating the negative voltage from the word line driver circuit 40 is unnecessary, the first PM
The breakdown voltage of the OS transistor 41 and the first NMOS transistor 42 can be reduced, and the area of the driver circuit can be reduced.

On the other hand, in the conventional memory cell array, since it is necessary to generate and apply a negative voltage to each word line, the driver portion is provided with a level shifter for generating a negative voltage and a driver. As a result, the potential difference between the source, drain, and gate of each transistor corresponding to the first PMOS transistor 41 and the first NMOS transistor 42 becomes large, so that the transistor size is increased so that each transistor can have a sufficient breakdown voltage. There is a need to. As a result, the area of the driver circuit is increased, which causes an increase in the memory core area.

(First Modification of Second Embodiment) A first modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 8 shows bias conditions during the erase operation of the EEPROM device according to the first modification of the second embodiment.

In FIG. 8, the control gate 25A
Selectively erase only the memory cells including. That is,
A negative voltage of about -6V is applied to the control gate 25A, and a positive voltage of about 3V is applied to the control gate 25B. As a result, due to the capacitive coupling between the control gate 25A and the secondary control gate 29, the potential of the floating gate 22 adjacent to the control gate 25A is lowered, and the erase operation is strengthened.

At this time, at the same time, the control gate 25
Control gate 25B for applying a positive voltage to B
By capacitive coupling with the control gate 25B, the potential of the floating gate 22 adjacent to the control gate 25B is increased, and the potential reduction due to the capacitive coupling with the secondary control gate 29 in the floating gate 22 is offset to make it difficult to erase. As a result, the erase unit can be 1 bit.

Since the erase speed changes exponentially with respect to the potential difference between the floating gate 22 and the drain 27, a sufficient erase time difference can be secured between the adjacent floating gates 22.

In this way, the control gate 25A,
By optimizing the control voltage applied to each of 25B and the secondary control gate 29, 1-bit erasing is possible.

(Second Modification of Second Embodiment) A second modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 9 shows bias conditions during the read operation of the EEPROM device according to the second modification of the second embodiment. In the second modification, the secondary control gate 29 is also used during the read operation.

In FIG. 9, the control gate 25A
Read operation is performed from the memory cell including. That is, a positive voltage of about 2.5 V is applied to both the control gate 25A and the secondary control gate 29,
The other node applies the ground voltage. This way,
The potential of the floating gate 22 rises due to capacitive coupling of the control gate 25A and the secondary control gate 29 to the floating gate 22, and the amount of read current increases. As a result, the width dimension of the memory cell transistor can be reduced, so that the cell area can be reduced.

The secondary control gate 29
When the potential of the voltage is raised to 2.5V, the control gate 2
The potential of the floating gate 22 adjacent to 5B also rises, but since the ground potential is applied to the control gate 25B, the cut-off state of the memory cell is held, so that there is no problem in operation.

Further, in the second modification, it is necessary to provide a positive / negative voltage driver circuit capable of generating a positive voltage instead of the negative voltage driver circuit 50 shown in FIG.

(Third Modification of Second Embodiment) A third modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 10 shows bias conditions during the write operation of the EEPROM device according to the third modification of the second embodiment. In the third modification, the secondary control gate 29 is also used during the write operation.

In FIG. 10, the control gate 25
A write operation is performed on a memory cell including A. That is, a positive control voltage of about 4V is applied to the control gate 25A, and the secondary control gate 29 receives 7V.
A positive control voltage of about V is applied, a positive control voltage of about 5V is applied to the drain 27, and the ground voltage is applied to the other nodes.

In this way, the control gate 2
Capacitance coupling between 5A and the secondary control gate 29 with respect to the floating gate 22 raises the potential of the floating gate 22 to improve the writing efficiency. This makes it easy to secure the potential of the floating gate 22 necessary for the write operation, so that the potential applied to the control gate 25A can be reduced.

Also in the third modification, it is necessary to provide a positive / negative voltage driver circuit capable of generating a positive voltage instead of the negative voltage driver circuit 50 shown in FIG.

(Fourth Modification of Second Embodiment) A fourth modification of the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 shows an overwriting bias condition during screening of the EEPROM device according to the fourth modification of the second embodiment. In the fourth modification, the secondary control gate 29 is used in the screening process for ensuring reliability.

As shown in FIG. 9, to the secondary control gate 29, a positive voltage of about 9 V, which cannot be applied by a normal word line driver circuit, is applied to inject excess electrons into the floating gate 22. To do. After that, by examining the change in the threshold voltage Vt of the memory cell due to being left unattended, it is possible to efficiently screen the memory cells having poor retention characteristics.

Also in the fourth modification, it is necessary to replace the negative voltage driver circuit 50 shown in FIG. 6 with a positive / negative voltage driver circuit capable of generating a positive voltage of about 9V.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 12 shows the configuration of each driver circuit for the word line and the secondary word line in the flash memory device according to the third embodiment of the present invention. 12, the same components as those shown in FIG. 6 are designated by the same reference numerals.

The third embodiment is different from the EEPROM device according to the second embodiment in that the random erase for each bit is not performed, but the word line driver circuit and the second word line driver circuit are smaller in circuit area than the EEPROM device according to the second embodiment. Has been realized.

As shown in FIG. 12, the difference from the second embodiment is that the positive / negative high-voltage driver circuit 51 as the second word line driver circuit has each secondary word line SW.
The point is that the positive voltage can be generated and output while being connected to L to SWL3 all together.

Further, the word line driver 40A omits the structure of the level shifter.

The bias conditions in the write operation of the flash memory device having the above-mentioned structure will be described below.

As shown in FIG. 13, a positive control voltage of about 1.8V is applied to the control gate 25A, and a positive control voltage of about 5V is applied to the secondary control gate 29 and the drain 27. Is applied.

By doing so, the secondary word lines SWL1 to SWL having the floating gates 22 at a high potential are set.
A positive voltage of about 5V is collectively supplied to the WL3 from the positive / negative high voltage driver circuit 51.

A positive voltage of about 1.8 V for applying a write current to the memory cell 10 is applied to the word line WL selected by the decoder circuit, while a write current is applied to the unselected word line WL. 0V is applied so that it does not exist. Therefore, the write operation can be performed in bit units simply by applying a relatively low control voltage to the selected word line WL.

[0112]

According to the semiconductor memory device of the present invention,
Since the memory cell accessed by the first control line and the second control line can be specified, the erase operation of the memory cell can be performed in a data unit as small as a bit / byte unit. Further, since the second control line intersects with the first control line, it is inevitably in the same direction as the bit line extends, so that the cell area does not increase much compared to the flash memory device.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram showing a memory cell array in a semiconductor memory device according to a first embodiment of the present invention.

2A is a semiconductor memory device according to the first embodiment of the present invention, FIG. 2A is a plan view of a portion corresponding to the partial circuit of FIG. 1, and FIG. IIb-IIb is a sectional view taken along the line.

3A to 3C show operating bias conditions of the semiconductor memory device according to the first embodiment of the present invention, FIG. 3A is a circuit diagram of an element during a write operation, and FIG. Is a circuit diagram of an element during a read operation, and FIG. 7C is a circuit diagram of an element during an erase operation.

FIG. 4 is a configuration cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment of the present invention.

FIG. 5 is a configuration cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing each driver circuit for a word line and a secondary word line in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an element showing an erase operation bias condition of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram of an element showing a bias condition during an erase operation of a semiconductor memory device according to a first modification of the second embodiment of the present invention.

FIG. 9 is a circuit diagram of an element showing a bias condition during a read operation of a semiconductor memory device according to a second modification of the second embodiment of the present invention.

FIG. 10 is a circuit diagram of an element showing a bias condition during a write operation of a semiconductor memory device according to a third modification of the second embodiment of the present invention.

FIG. 11 is a circuit diagram of an element showing an overwriting operation bias condition during screening of a semiconductor memory device according to a fourth modification of the second embodiment of the present invention.

FIG. 12 is a circuit diagram showing each driver circuit for a word line and a secondary word line in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 13 is a circuit diagram of an element showing a bias condition during a write operation of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a configuration of a memory cell of a split type flash memory device according to a first conventional example.

15A and 15B show a split flash memory device according to a first conventional example, FIG. 15A is a partial circuit diagram showing a memory cell array, and FIG. 15B is a memory cell array. It is a partial top view shown.

16A to 16C are circuit diagrams of elements showing operation bias conditions of the flash memory device according to the first conventional example.

17A and 17B show a split type EEPROM device according to a second conventional example, FIG. 17A is a partial circuit diagram showing a memory cell array, and FIG. 17B shows a memory cell array. It is a partial top view.

[Explanation of symbols]

10 memory cell 11 first memory cell 12 second memory cell 13 third memory cell 14 fourth memory cell 15 fifth memory cell 16 sixth memory cell 20 semiconductor substrate 20a stepped portion 21 tunnel insulating film ( First insulating film) 22 Floating gate 23 Capacitance insulating film (second insulating film) 24 Gate insulating film 25 Control gate (first control gate) 25A Control gate 25B Control gate 26 Source (region) 27 Drain (region) 28 inter-cell insulating film (third insulating film) 28A inter-cell insulating film (third insulating film) 29 secondary control gate (second control gate) 30 input port 31 positive voltage source 32 ground voltage source 40 word line driver Circuit (first driver circuit) 40A Word line driver circuit (first Driver circuit) 41 first PMOS transistor 42 first NMOS transistor 43 inverter 44 second PMOS transistor 45 second NMOS transistor 50 negative voltage driver circuit (second driver circuit) 51 positive and negative voltage driver circuit (second) Driver circuit) WL1 first word line (first control line) WL2 second word line (first control line) SWL1 first secondary word line (second control line) SWL2 second secondary word Line (second control line) SWL3 Third secondary word line (second control line)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 29/792 G11C 17/00 612F 611Z (72) Inventor Toshio Kuroki 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Sangyo Co., Ltd. (72) Inventor Masaaki Ogura 12590, New York, United States, Wappinger's Falls, Old Hopewell Road 140, Halo LSI Design and Device Technology Incorporated F-term (reference) 5B025 AA01 AC04 AD01 AD03 5F083 EP03 EP24 EP26 EP27 EP28 EP32 EP34 EP35 EP54 EP56 ER03 ER05 ER19 ER30 GA03 JA04 JA36 LA12 LA16 MA06 MA19 5F101 BA04 BA29 BB03 BB04 BC11 BC13 BD10 BD22 BE05 BE07

Claims (10)

[Claims] 1. A floating gate formed on a semiconductor substrate via a first insulating film, a first control gate capacitively coupled to the floating gate via a second insulating film, and A plurality of memory cells each including a floating gate, a first control gate, and a second control gate that is capacitively coupled via a third insulating film; and a first memory cell electrically connected to the first control gate. A control line and a second control line electrically connected to the second control gate are provided, and the first control line and the second control line are provided so as to intersect with each other. A semiconductor memory device characterized by being present. 2. The plurality of memory cells are arranged in an array, the first control gate is formed on the semiconductor substrate through an insulating film, and the floating gate is formed of the first control gate. The second control gate is formed on the side surface through the second insulating film, and the second control gate is formed on the upper surface and the side surface of the floating gate.
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed via the insulating film. 3. The semiconductor memory device according to claim 2, wherein a step portion straddling the floating gate is provided below the floating gate in the semiconductor substrate. 4. A plurality of the second control lines are provided, and a plurality of driver circuits for applying a predetermined control voltage to each of the second control lines are further provided. The semiconductor memory device according to claim 1. 5. The semiconductor memory device according to claim 4, wherein a read operation is performed by applying a positive control voltage to the second control line. 6. The semiconductor memory device according to claim 4, wherein a write operation is performed by applying a positive control voltage to the second control line. 7. The semiconductor memory device according to claim 6, wherein the positive control voltage is higher than a control voltage applied to the first control line. 8. A first driver circuit for applying a positive control voltage to the first control line, and a second driver circuit for applying a negative control voltage to the second control line. The semiconductor memory device according to claim 1, further comprising: 9. The method according to claim 8, wherein the second driver circuit also generates a positive control voltage higher than the positive control voltage and applies the positive control voltage to the second control line. Semiconductor memory device. 10. A plurality of the first control lines are included, and the one of the plurality of first control lines is connected to one of the first control lines during an erase operation of the memory cell. The control voltage applied to the first control line and the control voltage applied to the other first control line adjacent to the one first control line are set to different voltage values. The semiconductor memory device according to claim 1.