JP2003058420A - Method of reading data from NAND flash memory - Google Patents

Abstract

(57) [Problem] In a conventional method of reading data from a NAND flash memory, every time data of one word is read, the involvement of a CPU is required and ancillary processing occurs. There is a problem that it takes time to read the data. In a method of reading data from a NAND flash memory, a NAND to be read is used.
Identifying a sector on the flash memory;
Setting a cache line in which an address within the address range associated with the NAND type flash memory is registered as an address tag so as to invalidate an address hit; and sequentially setting addresses within the address range as access targets. Outputting a read command.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reading data from a NAND flash memory provided in various electronic devices such as a memory card, and more particularly to a NAND flash memory for a cache memory built in or attached to a CPU. The present invention relates to a method of reading data from the.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing an example of the configuration of an information processing apparatus using a NAND flash memory as a storage means. In FIG. 3, 1 is a CPU (central processing unit) that executes programs and processes data, and 2 is a cache line that is connected to the CPU 1 and has a predetermined storage capacity in order to speed up data access. The cache memory 3 for storing data as a storage unit, for each cache line of the cache memory 2, the information for specifying the address on the other storage means where the data stored in the cache line was originally stored (for example, The address array is provided as a head address, and hereinafter, the specific information will be referred to as an address tag).
1, a processor configured to include a cache memory 2 and the like for executing processing relating to control of the entire electronic device, and the like, 5 is an NA
ND type flash memory, 6 is an input / output port of the NAND type flash memory 5, 7 is an input / output controller, 8 is a memory cell array, and 9 is connected between the input / output controller 7 and the memory cell array 8 and is composed of various registers. It is a group of registers that are In the register group 9,
A data register 10 for temporarily storing data read from the memory cell array 8 or data to be written to the memory cell array 8 having a capacity of 1 word (1 byte), and a command register for storing commands output from the CPU 1. 11, an address register 12 that stores the start address of a sector to be processed in the memory cell array 8 that is output from the CPU 1, the start address of the sector to be processed is initially set, and one word of data from the memory cell array 8 Data register 10
It includes at least an address counter 13 that increments the set address value each time it is read out or when one word of data is written from the data register 10 to the memory cell array 8. The address register 12 can also be configured to use the function of the address counter 13 together. Also,
In the information processing apparatus shown in FIG. 3, it is assumed that various other storage means such as a RAM and a ROM (not shown) are connected to the CPU 1 or the processor 4 including the CPU 1.

Further, according to the present invention, the first mode for accessing data through the cache memory to each storage means connected to the processor 4 and the direct mode after removing the cache memory for each storage means It is assumed that the information processing apparatus is configured such that the CPU 1 can appropriately select the second mode for achieving a specific data access. That is, for each storage unit, an address assigned to execute data access via the cache memory (hereinafter referred to as an address in the cache area)
And an address (hereinafter, referred to as an address in the non-cache area) assigned to execute a direct data access without the cache memory.
By the way, regarding data access to the NAND flash memory, normally, no address is assigned to each word data stored in the memory cell array 8 when viewed from the CPU side. Since only a single address or a plurality of addresses forming an address range including a storage area of a predetermined size are assigned to the port 6, data access via the cache memory for the NAND flash memory is performed. In the case of
Address hits also occur in data of different sectors in the ND type flash memory, and the data cannot be transferred to the cache memory. Therefore, NAND
When accessing the data stored in the flash memory, the CPU 1 takes the second mode for direct data access. Specifically, in order to read data from the sector to be read on the memory cell array 8, the address assigned to the input / output port 6 of the NAND flash memory is targeted, and is unique to the NAND flash memory. Rea
While writing the d instruction to the command register 11, N
Data indicating the start address of the sector to be read on the AND type flash memory is written in the address register 12. This makes it possible to specify the address of the sector to be read on the NAND flash memory.

Next, in the above information processing apparatus, NA
The operation of reading data from the ND type flash memory will be described by taking the reading of data for one sector as an example. FIG. 4 is a flowchart showing a conventional data reading method when reading data for one sector from the NAND flash memory. First, a read command specific to the NAND flash memory 5 is output for the address assigned to the input / output port 6 of the NAND flash memory (step S1).
1). Next, the data indicating the start address of the sector to be read is output once or in a plurality of times (step S12). At this time, the head address on the memory cell array 8 is written in the address register 12, and the address value is set in the address counter 13 as an initial value. One word of data corresponding to the address set in the address counter 13 is output to the data register 10.

Next, the CPU 1 determines whether or not the preparation for the reading process has been completed by carrying out the above steps (step S13). If it is confirmed that the read preparation is completed, one word of data is read from the data register 10 and the data is written to, for example, RA.
The data is written in the work area set in M (step S14). At this time, each time one word of data is read from the data register 10, the address value set in the address counter 13 is incremented to 1 corresponding to the address newly set in the address counter 13.
The word data is output to the data register 10.
Next, it is determined whether the reading of the data for one sector from the NAND flash memory is completed (step S15). If the reading of the data for one sector has not been completed, the process returns to step S14 and the reading of the data for one word is continued. If the reading of the data for one sector is completed, the processing is ended.

[0006]

Conventional NAND
Since the method of reading data from the flash memory is as described above, C is read every time one word of data is read.
Since the involvement of the PU is necessary, the CPU performs ancillary processing such as increment processing of the counter in the CPU and comparison processing of the count value set in the counter when executing the reading processing for the data of one word. However, there is a problem that it takes time to read the data because of the occurrence.

The present invention has been made in order to solve the above problems, and it is possible to read data from a NAND flash memory at high speed.
An object of the present invention is to obtain a method of reading data from an ND type flash memory.

[0008]

A NAND according to the present invention
The method of reading data from the flash memory is to specify the sector on the NAND flash memory to be read, and the address associated with the NAND flash memory in the mode for data access via the cache memory. A step of setting one or a plurality of cache lines in the cache memory in which an address within the range is registered as an address tag to invalidate the address hit; and a NAN in the above mode.
A step of sequentially outputting a read command for an access target at an address set at a predetermined address interval corresponding to the capacity of the cache line within the address range associated with the D-type flash memory. It is a thing.

According to the method of reading data from the NAND flash memory according to the present invention, in accordance with the capacity of the cache line within the address range associated with the NAND flash memory in the mode for achieving data access via the cache memory. And a step of writing the data already read in one or a plurality of cache lines into another storage means between the read instructions that are output with the addresses set at predetermined address intervals as access targets. Is.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description, the correspondence between each means and each step of the example described in the embodiment of the present invention and each means and each step of the invention described in the claims will be clarified. In order to do so, each means and each step of the invention described in the claims corresponding to each means and each step of the embodiment are shown in parentheses appropriately in the description according to the embodiment of the present invention. To do.

Embodiment 1. An information processing apparatus to which the method of reading data from the NAND flash memory according to the present invention is applied is a NAND as shown in FIG.
Since a normal information processing apparatus including a flash memory is assumed, the description of the configuration of the information processing apparatus to which the present invention is applied will be omitted. 1 is a flow chart showing a method of reading data from a NAND flash memory according to a first embodiment of the present invention.

Here, in the information processing apparatus shown in FIG. 3, the operation of reading data from the NAND flash memory will be described by taking the reading of one sector of data as an example. In the conventional technology, a method (second mode) is used in which direct access is made to the cache memory by using an address in the non-cache area as an address for specifying the input / output port 6 of the NAND flash memory. However, in the present invention, NA
The difference is that the method (first mode) is used to access data via the cache memory by using the address in the cache area as the address for specifying the input / output port 6 of the ND type flash memory. . Further, as an address in the cache area for specifying the input / output port 6 of the NAND flash memory, an address range including a storage area larger than the size of a sector which is a unit of data reading and writing in the NAND flash memory is allocated. And It should be noted that the address range including the predetermined storage area is NAN
Regarding the correspondence with the input / output port 6 of the D-type flash memory, the address decoder is appropriately configured, that is, the external pin attached to the CPU or the processor and the external pin attached to the NAND type flash memory are appropriately connected according to the circuit specifications. This is realized by hardware.

Next, a specific operation will be described. Here, the storage capacity of each sector, which is a unit of writing and reading in the NAND flash memory, is 51
2 bytes, and the storage capacity for each cache line is 32
Explanation is given assuming that it is a byte. For the input / output port 6 of the NAND flash memory, an address range (“BE000” that includes a storage area of one sector of the NAND flash memory in the cache area is included.
It is assumed that an address range from 0 _h ″ to “BE01FF _h ″) is assigned. First, a read instruction specific to the NAND flash memory 5 is output to the NAND flash memory 5 (step S1). Next, the data indicating the start address of the sector to be read is output once or in a plurality of times (step S2), where the start address on the memory cell array 8 is written in the address register 12. , The address value is set as an initial value in the address counter 13. One word of data corresponding to the address set in the address counter 13 is output to the data register 10. From step 1 and step 2 above , The section on the NAND flash memory to be read It constitutes a processing step of identifying the.

Next, the CPU 1 determines whether or not the above-mentioned steps have been carried out and the preparation for the reading process has been completed (step S3). If it is confirmed that the read preparation is completed, the address tag corresponding to each cache line is searched and the address tag within the address range of the cache area assigned to the input / output port 6 of the NAND flash memory is searched. When the address is registered, an Invalid instruction is output to the cache line having such an address tag, and the cache line is set to invalidate the address hit (step S4). Each cache line is provided with a valid flag (valid when it is "1") so as to correspond to each cache line. By outputting an invalid instruction and setting the valid flag to "0", the cache line Data becomes invalid, and even if the processing target address output from the CPU 1 and the address tag match, the address hit is invalid for the cache line. In other words, since no address hit occurs for a cache line in which "0" indicating invalid data is set in the valid flag, it is possible to store data having the same address tag.
It is possible to read data sequentially from the ND type flash memory.

When the processing for setting the address hit to be invalid for the cache line having the address tag within the address range of the cache area allocated to the input / output port 6 of the NAND flash memory is completed, For each address interval according to the storage capacity of the line, the addresses to be accessed are sequentially set from the top address in the above address range and Read
A command (read command) is output (step S5). As a result, every time the Read instruction is executed, the memory access mechanism of the cache memory is used to sequentially generate, from the address on the memory cell array 8 set in the address counter 13, the data of the capacity of one cache line for each word. Are read out to the cache line. At this time, every time one word of data is read from the data register 10, the address value set in the address counter 13 is incremented.

FIG. 2 is a diagram showing changes in the cache memory when reading data for one sector from the NAND flash memory. When data is read from the NAND flash memory to the cache memory in advance, the cache area allocated to the input / output port 6 of the NAND flash memory as shown in FIG. 2A. Address tags within the address range of are already registered. In step S4,
An invalid instruction is output to a cache line having an address tag within the above address range by detecting an address tag within the above address range, and as shown in FIG. 2B, the valid flag is changed from "1" to " It is rewritten to 0 "and the address hit is invalidated for the cache line. Next, in step S5, “BE0000 _h ”, is sequentially added as addresses to be accessed.
By setting “BE0020 _h ”, “BE0040 _h ” ... And outputting Read commands respectively, new one-sector data is read from the NAND flash memory to the cache memory as shown in FIG. . Note that in FIG. 2C, the data for one sector is overwritten in the storage area where the data has been read in advance from the NAND flash memory, but the reading of the data is not necessarily limited to such a form. However, the data may be read to another cache line position.

When reading data larger than one sector, the reading process shown in FIG. 1 is performed for each sector, whereby the data can be read. However, in such a case, N is read every time data of one sector is read.
Since data having an address tag within the address range of the cache area assigned to the input / output port 6 of the AND type flash memory is invalidated, the data read to the cache memory is stored in, for example, a RAM (other storage means). It is necessary to execute the processing such as writing in the work area in parentheses in parallel. As described above, the data access for one cache line from the NAND flash memory to the cache memory after setting the address to be accessed and outputting the Read instruction is performed independently by the memory access mechanism of the cache memory. Therefore, during that time, it is possible to perform processing so as to write the data already read in another cache line into the work area by using the CPU.

As described above, according to the first embodiment, the Rea peculiar to the NAND flash memory is
The step of outputting the d command and the data related to the start address of the sector to be read to specify the sector to be read, and the address within the address range of the cache area allocated to the NAND flash memory as an address tag. A step of setting a cache line provided to invalidate an address hit;
And a step of outputting a Read instruction with an address sequentially set from within the address range of the cache area allocated to the ND type flash memory as an access target. Since data can be read from the NAND flash memory to the cache memory by using it, it is possible to read data from the NAND flash memory at high speed.

While data is being read to the cache memory by using the memory access function, C
Since data writing to the work area using the PU can be executed in parallel, it is possible to read data from the NAND flash memory to the work area provided in the RAM or the like at high speed. .

The NA explained in the first embodiment
The data read method from the ND type flash memory is
It is intended that the invention be disclosed by way of illustration and not limitation. The technical scope of the present invention is defined by the description of the claims,
Various design modifications are possible within the technical scope described in the claims. For example, in the first embodiment, 1 is set as the address of the cache area assigned to the input / output port 6 of the NAND flash memory.
Although it is configured so that an address range having a size including a storage area for sectors is allocated,
As an address of the cache area assigned to the input / output port 6 of the flash memory, an address range having a size including the storage areas of a plurality of sectors may be assigned. In this case,
It is possible to read the data for the plurality of sectors from the NAND flash memory to the cache memory without invalidating the data on the way.

[0021]

As described above, according to the present invention, the NAND flash memory is selected in the step of specifying the sector on the NAND flash memory to be read and in the mode for data access via the cache memory. Setting the address hit invalidation of one or more cache lines in the cache memory in which the addresses in the associated address range are registered as address tags, and associating with the NAND flash memory in the above mode And a step of sequentially outputting a read command with an address set at a predetermined address interval according to the capacity of the cache line within the specified address range as an access target. Function using NAND type Since it is possible from the flash memory read data to the cache memory, an effect that the reading of data from the NAND-type flash memory makes it possible to implement a high speed.

According to the present invention, the data is accessed through the cache memory in the address range associated with the NAND flash memory, and is set at predetermined address intervals corresponding to the capacity of the cache line. Since there is a step of writing the data already read in one or a plurality of cache lines into another storage unit between the read commands output with the address as the access target, the cache memory of the cache memory is read according to the read command. Since the data writing to the work area using the CPU can be executed in parallel while the data reading by the memory access mechanism is being executed, the NAND flash memory to the RAM
There is an effect that the data can be read out at high speed to the work area provided in the above.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method of reading data from a NAND flash memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a change in a cache memory when reading data for one sector from a NAND flash memory.

FIG. 3 is a diagram showing an example of a configuration of an information processing device using a NAND flash memory as a storage unit.

FIG. 4 is a flowchart showing a conventional data read method when reading data for one sector from a NAND flash memory.

[Explanation of symbols]

1 CPU, 2 cache memory, 3 address array, 4 processors, 5 NAND flash memory,
6 input / output ports, 7 input / output controller, 8 memory cell array, 9 register group, 10 data register, 11 command register, 12 address register, 13 address counter

Claims (2)

[Claims] 1. A first mode for achieving data access to each storage means via a cache memory, and a second mode for performing direct data access to each storage means without the cache memory. For each of the one or more NAND flash memories, at least one of the NAND flash memories is specified as an address viewed from the CPU side that identifies the NAND flash memory in the first mode. Using an information processing device configured to allocate an address range including a storage area for sectors,
In the data read method from the NAND flash memory for reading data from the ND flash memory to the cache memory, the step of identifying the sector on the NAND flash memory to be read, and supporting the NAND flash memory in the first mode Setting the address hit invalidation of one or more cache lines in the cache memory in which the addresses in the attached address range are registered as address tags; and in the NAND flash memory in the first mode. And a step of sequentially outputting a read command with an address set at a predetermined address interval according to the capacity of the cache line within an associated address range as an access target. Method of reading data from Sshumemori. 2. A read instruction that outputs an address set as an access target at an address set in a predetermined address interval according to a capacity of a cache line within an address range associated with a NAND flash memory in the first mode. 2. The NAN according to claim 1, further comprising the step of writing the data, which has already been read into one or a plurality of cache lines, into another storage means during the interval.
A method for reading data from a D-type flash memory.