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JP2003051554A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2003051554A
JP2003051554A JP2001235727A JP2001235727A JP2003051554A JP 2003051554 A JP2003051554 A JP 2003051554A JP 2001235727 A JP2001235727 A JP 2001235727A JP 2001235727 A JP2001235727 A JP 2001235727A JP 2003051554 A JP2003051554 A JP 2003051554A
Authority
JP
Japan
Prior art keywords
trench
oxide film
polysilicon
sacrificial oxide
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001235727A
Other languages
Japanese (ja)
Other versions
JP4670198B2 (en
Inventor
Seishi Noguchi
晴司 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001235727A priority Critical patent/JP4670198B2/en
Publication of JP2003051554A publication Critical patent/JP2003051554A/en
Application granted granted Critical
Publication of JP4670198B2 publication Critical patent/JP4670198B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、トレンチ型のM
OSゲートや、集積回路装置に形成されるトレンチ型の
MOSコンデンサなどを有する半導体装置の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench type M
The present invention relates to a method for manufacturing a semiconductor device having an OS gate and a trench type MOS capacitor formed in an integrated circuit device.

【0002】[0002]

【従来の技術】トレンチ型のMOSゲート構造は、MO
Sトランジスタの低オン抵抗化を実現するために用いら
れる。また、集積回路装置において、MOSトランジス
タやコンデンサや抵抗が、半導体基板に形成される。特
に、半導体メモリーとして多用されるDRAM(Dyn
amic Randam Access Memor
y)などでは、高集積化を図るために、占有面積の大き
いコンデンサをトレンチ型MOSキャパシタで形成して
いる。
2. Description of the Related Art A trench type MOS gate structure is an MO
It is used to realize low on-resistance of the S transistor. Further, in the integrated circuit device, MOS transistors, capacitors and resistors are formed on the semiconductor substrate. In particular, DRAM (Dyn) that is often used as a semiconductor memory
Amic Random Access Memor
In y), etc., a capacitor having a large occupied area is formed by a trench type MOS capacitor in order to achieve high integration.

【0003】図4は、従来のトレンチ型MOSキャパシ
タの製造方法であり、同図(a)から同図(e)は工程
順に示した要部工程断面図である。フォトレジストや絶
縁膜をマスクとして、トレンチエッチング装置によっ
て、シリコン基板51の表面層にトレンチ52を形成す
る。つぎに、図示しないマスク材を除去する(同図
(a))。
FIG. 4 shows a conventional method of manufacturing a trench type MOS capacitor, and FIGS. 4A to 4E are process sectional views showing the main part in the order of processes. A trench 52 is formed in the surface layer of the silicon substrate 51 by a trench etching apparatus using the photoresist and the insulating film as a mask. Next, the mask material not shown is removed ((a) in the same figure).

【0004】つぎに、熱酸化によって、トレンチ52の
内壁に犠牲酸化膜54を形成する(同図(b))。つぎ
に、第1犠牲酸化膜54をフッ酸等で除去することで、
トレンチエッチングの際にトレンチ51内の表層にでき
たダメージ層53を除去する(同図(c))。
Next, a sacrificial oxide film 54 is formed on the inner wall of the trench 52 by thermal oxidation (FIG. 2 (b)). Next, by removing the first sacrificial oxide film 54 with hydrofluoric acid or the like,
The damage layer 53 formed on the surface layer in the trench 51 during the trench etching is removed (FIG. 7C).

【0005】つぎに、改めて熱酸化を行い、トレンチ5
2の内壁にキャパシタ用酸化膜55を形成する(同図
(d))。つぎに、CVD(Chemical Vap
or Deposition)法などでポリシリコン5
6をトレンチ52の内部に堆積させる(同図(e))。
このポリシリコン56とキャパシタ用酸化膜55とシリ
コン基板51で、トレンチ型MOSキャパシタが形成さ
れる。
Next, thermal oxidation is performed again to form trench 5
An oxide film 55 for capacitors is formed on the inner wall of 2 ((d) of the same figure). Next, CVD (Chemical Vap)
or Deposition) method, etc.
6 is deposited inside the trench 52 ((e) in the same figure).
A trench type MOS capacitor is formed by the polysilicon 56, the capacitor oxide film 55 and the silicon substrate 51.

【0006】前記の方法でトレンチ52を形成した場合
のトレンチ52の底部近傍の拡大図をつぎに示す。図5
は、図4(c)のB部拡大図であり、同図(a)は側壁
面と底面が直角に交差した場合、同図(b)は側壁面と
底面が鈍角に交差した場合である。図5において、トレ
ンチエッチング後のトレンチ52の側壁面57と底面4
8の交差箇所付近のトレンチの底端部59(同図
(a))、60(同図(b))は、通常、図のように、
直角か、もしくは角ばった形状(鈍角)になっており、
その形状は犠牲酸化を経て、キャパシタ用酸化膜55を
形成する際においても残存している。
An enlarged view of the vicinity of the bottom of the trench 52 when the trench 52 is formed by the above method is shown below. Figure 5
4B is an enlarged view of a portion B of FIG. 4C, where FIG. 4A shows a case where the side wall surface and the bottom surface intersect at a right angle, and FIG. 4B shows a case where the side wall surface and the bottom surface intersect at an obtuse angle. . In FIG. 5, side wall surface 57 and bottom surface 4 of trench 52 after trench etching
The bottom end portions 59 (FIG. (A)) and 60 (FIG. (B)) of the trench near the intersection of 8 are usually
It has a right angle or an angular shape (obtuse angle),
The shape remains even when the oxide film 55 for capacitors is formed through sacrificial oxidation.

【0007】[0007]

【発明が解決しようとする課題】このように、直角もし
くは鋭角の形状をしたトレンチ底端部に形成されたキャ
パシタ用酸化膜は、一般にトレンチの側壁や底部に形成
されたキャパシタ用酸化膜に比べて電界ストレスに対し
て弱く、絶縁破壊し易い。その主な原因は、構造的に底
端部に電界が集中し易いことや、また、底端部は、シリ
コン基板の異なる配向面の接合箇所であり、シリコンを
熱酸化した際に形成される酸化膜の膜厚は配向面毎に異
なるため、底端部では酸化膜に歪みや応力が加わり、そ
の結果、酸化膜が十分成長できず、底端部では酸化膜の
膜厚が薄くなることが考えられる。
As described above, the oxide film for a capacitor formed on the bottom end of the trench having a right angle or an acute angle is generally compared to the oxide film for a capacitor formed on the side wall or the bottom of the trench. It is weak against electric field stress and easily causes dielectric breakdown. The main cause is that the electric field is apt to concentrate on the bottom end part structurally, and the bottom end part is a joint part of different orientation planes of the silicon substrate, which is formed when silicon is thermally oxidized. Since the thickness of the oxide film differs depending on the orientation plane, strain and stress are applied to the oxide film at the bottom edge, and as a result, the oxide film cannot grow sufficiently and the oxide film becomes thin at the bottom edge. Can be considered.

【0008】この発明の目的は、前記の課題を解決し
て、トレンチの底端部での電界集中と絶縁膜の薄膜化が
起きにくい半導体装置の製造方法を提供することにあ
る。
An object of the present invention is to solve the above problems and provide a method of manufacturing a semiconductor device in which concentration of an electric field at the bottom end of a trench and thinning of an insulating film are less likely to occur.

【0009】[0009]

【課題を解決するための手段】前記の目的を達成するた
めに、半導体基板の表面層にトレンチを形成する工程
と、該トレンチ内壁に第1犠牲酸化膜を形成する工程
と、該第1犠牲酸化膜上にポリシリコンを形成する工程
と、前記トレンチの底面と側壁面の交差箇所を含みその
近傍に前記ポリシリコンを残し、それ以外の前記ポリシ
リコンを除去する工程と、露出した前記第1犠牲酸化膜
を除去する工程と、前記トレンチの底面と側壁面と、前
記残渣ポリシリコンとを、酸化して第2犠牲酸化膜を形
成する工程と、該第2犠牲酸化膜を除去し、前記交差箇
所に、凹状の丸みを形成する工程と、前記トレンチ内壁
に絶縁膜を形成する工程と、を含む製造方法とする。
In order to achieve the above object, a step of forming a trench in a surface layer of a semiconductor substrate, a step of forming a first sacrificial oxide film on an inner wall of the trench, and a step of forming the first sacrificial oxide film. A step of forming polysilicon on the oxide film, a step of leaving the polysilicon in the vicinity including the intersection of the bottom surface of the trench and the side wall surface, and removing the other polysilicon, and the exposed first Removing the sacrificial oxide film; oxidizing the bottom and sidewall surfaces of the trench and the residual polysilicon to form a second sacrificial oxide film; removing the second sacrificial oxide film; The manufacturing method includes a step of forming a concave roundness at the intersection, and a step of forming an insulating film on the inner wall of the trench.

【0010】また、半導体基板の表面層にトレンチを形
成する工程と、該トレンチ内壁に第1犠牲酸化膜を形成
する工程と、該第1犠牲酸化膜上にポリシリコンを形成
する工程と、前記トレンチの底面と側壁面の交差箇所を
含みその近傍に前記ポリシリコンを残し、それ以外の前
記ポリシリコンを除去する工程と、前記第1犠牲酸化膜
が形成されたトレンチの底面と側壁面と、前記残渣ポリ
シリコンとを、酸化して第2犠牲酸化膜を形成する工程
と、該第2犠牲酸化膜を除去し、前記交差箇所に、凹状
の丸みを形成する工程と、前記トレンチ内壁に絶縁膜を
形成する工程と、を含む製造方法とする。
Further, a step of forming a trench in the surface layer of the semiconductor substrate, a step of forming a first sacrificial oxide film on the inner wall of the trench, a step of forming polysilicon on the first sacrificial oxide film, A step of leaving the polysilicon in the vicinity thereof including the intersection of the bottom surface and the side wall surface of the trench and removing the other polysilicon, and a bottom surface and a side wall surface of the trench in which the first sacrificial oxide film is formed; Oxidizing the residual polysilicon to form a second sacrificial oxide film, removing the second sacrificial oxide film, and forming a concave roundness at the intersection, and insulating the inner wall of the trench. And a step of forming a film.

【0011】また、前記絶縁膜が、MOS型デバイスの
ゲート絶縁膜もしくは集積回路装置に形成されるコンデ
ンサの絶縁膜のいずれかであるとよい。
Further, the insulating film may be either a gate insulating film of a MOS type device or an insulating film of a capacitor formed in an integrated circuit device.

【0012】[0012]

【発明の実施の形態】図1は、この発明の第1実施例の
半導体装置の製造方法であり、同図(a)から同図
(h)は工程順に示した要部工程断面図である。この工
程図はトレンチ型MOSキャパシタの要部工程断面図で
あり、図4(a)のA部に相当する拡大図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a method of manufacturing a semiconductor device according to a first embodiment of the present invention. FIGS. 1A to 1H are sectional views showing the main process steps in the order of steps. . This process drawing is a process cross-sectional view of the main part of the trench type MOS capacitor, and is an enlarged view corresponding to the portion A in FIG.

【0013】フォトレジストや絶縁膜をマスクとして、
トレンチエッチング装置によって、シリコン基板1の表
面層にトレンチ2を形成する。トレンチの表面は、側壁
面3と底面4と、側壁面と底面の交差箇所5の近傍であ
る底端部から構成される。トレンチ2を形成した後で、
図示しないマスク材を除去する(同図(a))。つぎ
に、800℃から1000℃程度の熱酸化によって、ト
レンチ2の内壁に、数十から100nm程度の膜厚の第
1犠牲酸化膜7を形成する。この第1犠牲酸化膜7は、
トレンチの表面層に形成されたダメージ(多結晶部)を
取り込む(同図(b))。
Using the photoresist and the insulating film as a mask,
The trench 2 is formed in the surface layer of the silicon substrate 1 by the trench etching apparatus. The surface of the trench is composed of a side wall surface 3 and a bottom surface 4, and a bottom end portion near the intersection 5 of the side wall surface and the bottom surface. After forming the trench 2,
The mask material not shown is removed ((a) in the same figure). Next, the first sacrificial oxide film 7 having a film thickness of about several tens to 100 nm is formed on the inner wall of the trench 2 by thermal oxidation at about 800 ° C. to 1000 ° C. This first sacrificial oxide film 7 is
Damage (polycrystalline part) formed in the surface layer of the trench is taken in (FIG. 2B).

【0014】つぎに、減圧CVD法などにより、ポリシ
リコン8を図示しないウェハ全面およびトレンチ2の内
部に、例えば、100から300nm程度堆積させる
(同図(c))。つぎに、例えば、等方性のポリシリコ
ンエッチング装置で堆積したポリシリコン8を除去す
る。このとき、30秒から90秒程度のエッチング時間
にすることで、トレンチの底端部6とその近傍のポリシ
リコン8を残渣ポリシリコン9として残すことができ
る。また、第1犠牲酸化膜7は、ポリシリコンエッチン
グの際に、シリコン基板1(トレンチ内表面)の保護膜
として利用される(同図(d))。
Next, by a low pressure CVD method or the like, polysilicon 8 is deposited on the entire surface of the wafer (not shown) and inside the trench 2 by, for example, about 100 to 300 nm (FIG. 2C). Next, for example, the polysilicon 8 deposited by the isotropic polysilicon etching apparatus is removed. At this time, by setting the etching time to about 30 seconds to 90 seconds, the bottom end portion 6 of the trench and the polysilicon 8 in the vicinity thereof can be left as the residual polysilicon 9. In addition, the first sacrificial oxide film 7 is used as a protective film for the silicon substrate 1 (inner surface of the trench) during polysilicon etching ((d) in the figure).

【0015】つぎに、第1犠牲酸化膜7をフッ酸で除去
することで、トレンチ2の表面層に形成されたダメージ
が除去される(同図(e))。つぎに、2回目の熱酸化
を800℃から1000℃程度の低温で行うことによ
り、トレンチの底端部6の残渣ポリシリコン9とトレン
チの底面4と側壁面3を酸化して第2犠牲酸化膜10を
形成する。残渣ポリシリコン9は、シリコン基板1より
数倍早く酸化されるため、残渣ポリシリコン9は短時間
で全て酸化され、第2犠牲酸化膜10に取り込まれる。
この残渣ポリシリコン9が酸化されている間に、側壁面
3や底面4のシリコン基板1は深く酸化され、一方、残
渣ポリシリコン9のある底端部6のシリコン基板1は浅
く酸化される。このようにして、トレンチの底端部6の
第2犠牲酸化膜10とシリコン基板1との界面形状は、
シリコン基板1の内部方向に向かって、凹状に丸められ
た形状となる(同図(f))。
Next, the first sacrificial oxide film 7 is removed with hydrofluoric acid to remove the damage formed on the surface layer of the trench 2 (FIG. 7E). Next, the second thermal oxidation is performed at a low temperature of about 800 ° C. to 1000 ° C. to oxidize the residual polysilicon 9 at the bottom end portion 6 of the trench, the bottom surface 4 and the side wall surface 3 of the trench, thereby performing the second sacrificial oxidation. The film 10 is formed. Since the residual polysilicon 9 is oxidized several times faster than the silicon substrate 1, the residual polysilicon 9 is entirely oxidized in a short time and taken into the second sacrificial oxide film 10.
While the residual polysilicon 9 is being oxidized, the silicon substrate 1 on the side wall surface 3 and the bottom surface 4 is deeply oxidized, while the silicon substrate 1 at the bottom end 6 having the residual polysilicon 9 is shallowly oxidized. In this way, the interface shape between the second sacrificial oxide film 10 at the bottom end 6 of the trench and the silicon substrate 1 is
The silicon substrate 1 has a shape rounded in a concave shape toward the inside (FIG. 6 (f)).

【0016】つぎに、第2犠牲酸化膜10をフッ酸など
で除去する(同図(g))。つぎに、底端部6が凹状に
丸められたトレンチ2の内部にキャパシタ用酸化膜11
を形成する(同図(h))。つぎに、トレンチ内部に図
示しないポリシリコンを充填して、MOSキャパシタが
完成する。
Next, the second sacrificial oxide film 10 is removed with hydrofluoric acid or the like (FIG. 9 (g)). Next, the oxide film 11 for a capacitor is provided inside the trench 2 whose bottom end 6 is rounded in a concave shape.
Are formed ((h) in the figure). Next, the trench is filled with polysilicon (not shown) to complete the MOS capacitor.

【0017】このポリシリコンとキャパシタ用酸化膜と
シリコン基板で、トレンチ型MOSキャパシタが形成さ
れる。このように、トレンチの底端部6を丸めること
で、形状による電界集中を防止と、この箇所でのキャパ
シタ用酸化膜11の薄膜化を防止しすることができる。
その結果、キャパシタ用酸化膜11の絶縁破壊が防止さ
れる。
A trench type MOS capacitor is formed by the polysilicon, the capacitor oxide film and the silicon substrate. By thus rounding the bottom end portion 6 of the trench, it is possible to prevent electric field concentration due to the shape and to prevent thinning of the capacitor oxide film 11 at this portion.
As a result, dielectric breakdown of the capacitor oxide film 11 is prevented.

【0018】図2は、この発明の第2実施例の半導体装
置の製造方法であり、同図(a)から同図(h)は工程
順に示した要部工程断面図である。この工程図はトレン
チ型MOSキャパシタの要部工程断面図である。図1と
の違いは、図2(e)の工程において、第1犠牲酸化膜
を除去しないで、つぎの工程へ進む点である。この第2
実施例においても、第1実施例と同様の効果が期待でき
る。
FIG. 2 shows a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS. 2A to 2H are sectional views showing the essential steps in the order of steps. This process drawing is a cross-sectional view of a main part of a trench type MOS capacitor. The difference from FIG. 1 is that in the step of FIG. 2E, the first sacrificial oxide film is not removed and the process proceeds to the next step. This second
In the embodiment, the same effect as that of the first embodiment can be expected.

【0019】また、トレンチ型MOSトランジスタのゲ
ート部分にもこの方法は適用できることは勿論である。
その場合は、図3のように、表面層にウエル領域12、
ソース領域13を形成したシリコン基板1に、トレンチ
2を形成する。その後の工程は図1(b)から図1
(h)の工程と同じであり、キャパシタ用酸化膜11は
ゲート酸化膜14となる。この場合も、図1と同じ効果
が得られる。
Of course, this method can also be applied to the gate portion of a trench type MOS transistor.
In that case, as shown in FIG. 3, the well region 12,
The trench 2 is formed in the silicon substrate 1 on which the source region 13 is formed. Subsequent steps are shown in FIG.
This is the same as the step (h), and the capacitor oxide film 11 becomes the gate oxide film 14. Also in this case, the same effect as that of FIG. 1 can be obtained.

【0020】また、前記キャパシタ用酸化膜11やゲー
ト酸化膜14は窒化膜などの絶縁膜であっても構わな
い。
Further, the capacitor oxide film 11 and the gate oxide film 14 may be an insulating film such as a nitride film.

【0021】[0021]

【発明の効果】この発明によれば、トレンチの底端部を
残渣ポリシリコンを用いて丸めることにより、形状によ
る電界集中を防止と、この箇所でのキャパシタ用酸化膜
やゲート酸化膜の薄膜化を容易に防止しすることができ
る。その結果、キャパシタ用酸化膜やゲート酸化膜の絶
縁破壊が防止される。
According to the present invention, the bottom end of the trench is rounded by using the residual polysilicon, so that the electric field concentration due to the shape is prevented and the oxide film for the capacitor and the gate oxide film at this position are thinned. Can be easily prevented. As a result, dielectric breakdown of the capacitor oxide film and the gate oxide film is prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1実施例の半導体装置の製造方法
であり、(a)から(h)は工程順に示した要部工程断
面図
FIG. 1 is a method for manufacturing a semiconductor device according to a first embodiment of the present invention, in which (a) to (h) are process cross-sectional views of essential parts shown in the order of processes.

【図2】この発明の第2実施例の半導体装置の製造方法
であり、(a)から(h)は工程順に示した要部工程断
面図
FIG. 2 is a sectional view showing the essential part of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, in which (a) to (h) are shown in the order of steps.

【図3】本発明を、トレンチ型MOSトランジスタのゲ
ート部分適用した例を示す図
FIG. 3 is a diagram showing an example in which the present invention is applied to a gate portion of a trench type MOS transistor.

【図4】従来のトレンチ型MOSキャパシタの製造方法
であり、(a)から(e)は工程順に示した要部工程断
面図
FIG. 4 is a cross-sectional view of a main part of a method of manufacturing a conventional trench type MOS capacitor, in which (a) to (e) are shown in the order of steps.

【図5】図4(c)のB部拡大図であり、(a)は側壁
面と底面が直角に交差した場合、(b)は側壁面と底面
が鈍角に交差した場合の図。
5A is an enlarged view of a portion B in FIG. 4C, where FIG. 5A is a view when the side wall surface and the bottom surface intersect at a right angle, and FIG. 5B is a view when the side wall surface and the bottom surface intersect at an obtuse angle.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 トレンチ 3 側壁面 4 底面 5 交差箇所 6 底端部 7 第1犠牲酸化膜 8 ポリシリコン 9 残渣ポリシリコン 10 第2犠牲酸化膜 11 キャパシタ用絶縁膜 12 ウエル領域 13 ソース領域(エミッタ領域) 14 ゲート酸化膜 1 Silicon substrate 2 trench 3 Side wall surface 4 bottom 5 intersections 6 bottom edge 7 First sacrificial oxide film 8 Polysilicon 9 Residual polysilicon 10 Second sacrificial oxide film 11 Insulating film for capacitors 12 well area 13 Source region (emitter region) 14 Gate oxide film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板の表面層にトレンチを形成する
工程と、該トレンチ内壁に第1犠牲酸化膜を形成する工
程と、該第1犠牲酸化膜上にポリシリコンを形成する工
程と、前記トレンチの底面と側壁面の交差箇所を含みそ
の近傍に前記ポリシリコンを残し、それ以外の前記ポリ
シリコンを除去する工程と、露出した前記第1犠牲酸化
膜を除去する工程と、前記トレンチの底面と側壁面と、
前記残渣ポリシリコンとを、酸化して第2犠牲酸化膜を
形成する工程と、該第2犠牲酸化膜を除去し、前記交差
箇所に、凹状の丸みを形成する工程と、前記トレンチ内
壁に絶縁膜を形成する工程と、を含むことを特徴とする
半導体装置の製造方法。
1. A step of forming a trench in a surface layer of a semiconductor substrate, a step of forming a first sacrificial oxide film on an inner wall of the trench, a step of forming polysilicon on the first sacrificial oxide film, A step of leaving the polysilicon in the vicinity including the intersection of the bottom surface of the trench and the side wall surface and removing the polysilicon other than the intersection, a step of removing the exposed first sacrificial oxide film, and a bottom surface of the trench And the side wall surface,
Oxidizing the residual polysilicon to form a second sacrificial oxide film, removing the second sacrificial oxide film, and forming a concave roundness at the intersection, and insulating the inner wall of the trench. A method of manufacturing a semiconductor device, comprising the step of forming a film.
【請求項2】半導体基板の表面層にトレンチを形成する
工程と、該トレンチ内壁に第1犠牲酸化膜を形成する工
程と、該第1犠牲酸化膜上にポリシリコンを形成する工
程と、前記トレンチの底面と側壁面の交差箇所を含みそ
の近傍に前記ポリシリコンを残し、それ以外の前記ポリ
シリコンを除去する工程と、前記第1犠牲酸化膜が形成
されたトレンチの底面と側壁面と、前記残渣ポリシリコ
ンとを、酸化して第2犠牲酸化膜を形成する工程と、該
第2犠牲酸化膜を除去し、前記交差箇所に、凹状の丸み
を形成する工程と、前記トレンチ内壁に絶縁膜を形成す
る工程と、を含むことを特徴とする半導体装置の製造方
法。
2. A step of forming a trench in a surface layer of a semiconductor substrate, a step of forming a first sacrificial oxide film on an inner wall of the trench, a step of forming polysilicon on the first sacrificial oxide film, A step of leaving the polysilicon in the vicinity including the intersection of the bottom surface of the trench and the side wall surface, and removing the polysilicon other than that; a bottom surface and a side wall surface of the trench in which the first sacrificial oxide film is formed; Oxidizing the residual polysilicon to form a second sacrificial oxide film, removing the second sacrificial oxide film, and forming a concave roundness at the intersection, and insulating the inner wall of the trench. A method of manufacturing a semiconductor device, comprising the step of forming a film.
【請求項3】前記絶縁膜が、MOS型デバイスのゲート
絶縁膜もしくは集積回路装置に形成されるコンデンサの
絶縁膜のいずれかであることを特徴とする請求項1また
は2に記載の半導体装置の製造方法。
3. The semiconductor device according to claim 1, wherein the insulating film is either a gate insulating film of a MOS device or an insulating film of a capacitor formed in an integrated circuit device. Production method.
JP2001235727A 2001-08-03 2001-08-03 Manufacturing method of semiconductor device Expired - Fee Related JP4670198B2 (en)

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JP4670198B2 JP4670198B2 (en) 2011-04-13

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109888A (en) * 2005-10-13 2007-04-26 Denso Corp Method of manufacturing semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529541A (en) * 1991-07-18 1993-02-05 Kawasaki Steel Corp Method for manufacturing semiconductor device
JPH0621214A (en) * 1992-07-03 1994-01-28 Seiko Epson Corp Manufacture of semiconductor device
JPH08263692A (en) * 1995-03-11 1996-10-11 Philips Electron Nv Reproduction method of face of object

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529541A (en) * 1991-07-18 1993-02-05 Kawasaki Steel Corp Method for manufacturing semiconductor device
JPH0621214A (en) * 1992-07-03 1994-01-28 Seiko Epson Corp Manufacture of semiconductor device
JPH08263692A (en) * 1995-03-11 1996-10-11 Philips Electron Nv Reproduction method of face of object

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109888A (en) * 2005-10-13 2007-04-26 Denso Corp Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
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