JP2003046002A - Nonvolatile semiconductor memory device and method of operating the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To shorten the time of the entire writing operation cycle including reading and erasing, increase the affinity with the CMOS process, and easily realize a low-cost memory-embedded system LSI. A MIS transistor and a memory transistor sharing a channel are provided, and a gate dielectric film GD1 of the memory transistor is formed by laminating a plurality of dielectrics, and includes a discrete charge storage means therein. . During writing, hot electrons HE generated near the boundary between the MIS transistor and the memory transistor are injected into the gate dielectric film GD1 from the source S side (FIG. 8A). At the time of erasing, hot holes HH1 and HH2 generated on the drain D side are injected from the drain D side into the distribution region of the electrons accumulated in the gate dielectric film GD1 (FIG. 8B).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a memory transistor and a MIS type transistor connected in series, and a gate dielectric film of the memory transistor is formed by laminating a plurality of dielectrics. The present invention relates to a non-volatile semiconductor memory device having discretized charge storage means and an operating method thereof.

[0002]

2. Description of the Related Art In advanced information society or high speed, wide area network society, large capacity file memory, AV
There is a great need for application memory. In particular, a non-volatile semiconductor memory is the first candidate as a substitute for a large-capacity disk memory or as a small and highly reliable removable storage medium used in a mobile information terminal.

On the other hand, one system or subsystem itself which is currently mainly realized on a printed circuit board is
System LSI for the purpose of realizing with one LSI
Is attracting attention as a key device that influences the size, performance, and price of future information equipment. Many system LS
In I, a non-volatile semiconductor memory that does not require a standby power supply is essential. In the non-volatile memory embedded in the system LSI, large capacity, high speed, low voltage,
In addition to the performance required for conventional non-volatile memories such as low power consumption, high affinity with CMOS processes for forming other digital circuits and analog circuits is required.

In the non-volatile memory for mixed use, conventionally, the NO using the floating gate FG as the charge storage layer is conventionally used.
R-type memory cells have been used. However, in this memory cell, since the floating gate FG functioning as a charge storage means is made of a single-layer conductive film such as polysilicon, when a leak path is locally generated in the tunneling film below the floating gate FG, a large amount of stored charge is generated. It disappears to the substrate side through the leak path, and as a result, the charge retention characteristics tend to deteriorate.

Due to the fact that it is difficult to receive such a disadvantage, the gate dielectric film is formed by laminating a plurality of dielectrics,
Attention has been focused on a MONOS type memory device including a discrete charge storage means such as a charge trap therein. In the MONOS type, since the charge storage means is spatially discretized, the retained charges around the leak path only leak locally, and as a result, the charge retaining characteristic is superior to that of the FG type.

For the purpose of improving the writing speed, for example, a source side injection type MONOS transistor for injecting channel hot electrons (CHE) from the source side has been reported (IEEE Electron Device Letter 19,
1998, pp153). In this source side injection type MONOS transistor, MONOS is controlled by controlling the side gate.
Since a high electric field is generated on the source side of the transistor, the charge injection speed is improved.

[0007]

In the conventional non-volatile memory device described above, it is difficult to meet all the requirements especially when the device is embedded in the system LSI.

In the CMOS process of the system LSI,
The miniaturization of the device has progressed year by year, and a gate length of 1.3 μm is currently in practical use. However, in the FG type, it is difficult to scale the tunneling film due to the deterioration of the charge retention characteristics described above, which makes it difficult to scale the gate length as it is. Therefore, if it is attempted to maintain the use of the FG type in a mixed memory element of a system LSI, the affinity between the memory process and the CMOS process is lowered, and the commonality of process conditions cannot be maintained. For example, the impurity diffusion layers such as the source / drain regions need to be made higher in concentration and thinner in accordance with the miniaturization of the element. However, if the difference in the process rules is too wide, the memory section and the CMOS section are separated. It is necessary to form the impurity diffusion layer. Further, the FG type requires a high voltage of 10 V or more for programming and erasing, and requires a special process for maintaining a relatively high breakdown voltage. on the other hand,
In logic circuits and the like, lowering of voltage is progressing, and in this respect as well, the affinity of the process is decreasing.

In the prior arts described in the above-mentioned documents, the MO
The charge injection efficiency is improved by the source side injection to the NOS type element, which is effective in improving the writing speed. However, in a non-volatile memory operation cycle, generally, pre-erase erasure is performed to temporarily set the thresholds of all cells to be written at a low level, and then the required cells are written. Alternatively, in order to align the erase level, all cells may be aligned to the high level before further erasing. As described above, in order to shorten the operation cycle time of the non-volatile memory, it is not enough to improve the writing speed, but it is necessary to improve the erasing speed at the same time. Further, in this prior art, electrons are extracted from the top oxide film side by utilizing tunneling for erasing. Therefore, the erase speed is slow. Therefore, there is a disadvantage that the reduction of the operation cycle time is not sufficient.

As described above, in the conventional non-volatile memory device, the memory cell array method and the operation method are determined from the viewpoint of reducing the individual writing time and the erasing time, and these are determined from the viewpoint of reducing the time of the entire operation cycle. Not not. Further, as described above, the study from the viewpoint of being mixedly mounted on the system LSI is insufficient.

An object of the present invention is to newly propose a device structure, a cell array system and an operation method suitable from the viewpoint of reducing the time of the entire write operation cycle including reading and erasing, or from the viewpoint of an embedded memory. And

[0012]

In order to achieve the above object, in a method of operating a nonvolatile memory device according to a first aspect of the present invention, a channel connected in series between a source line and a bit line is provided. A non-volatile semiconductor memory device having a shared MIS type transistor and a memory transistor, a gate dielectric film of the memory transistor is formed by laminating a plurality of dielectrics, and including a discrete charge storage means inside the laminated film. Of the above-mentioned operation method, that is, hot electrons generated near the boundary between the MIS type transistor and the memory transistor at the time of writing are written in the gate dielectric film of the memory transistor from the source side. Hot holes generated on the drain side of the memory transistor during injection and erasing are removed by the gate dielectric of the memory transistor. It injected from the drain side to the electron accumulation region of.

This method is suitable for operations within a write cycle including erase. In this case, the memory cell array in which a plurality of memory cells having the MIS type transistors and the memory transistors are arranged in a matrix and the gates of the plurality of memory transistors belonging to the same row are connected by word lines are the nonvolatile memory. The write cycle for the memory cell array provided in the device is performed by the following steps, that is, a predetermined voltage is applied between all the bit lines connected to the drains of the memory transistors and the word line of the selected row. Apply to generate a hot hole in the drain of the memory transistor, inject the generated hot hole into the gate dielectric film of the corresponding memory transistor, and simultaneously erase the memory cells in the selected row, Source line and bit line connected to cells that require charge injection according to write data Applying a predetermined voltage between, and, by applying a predetermined voltage to the selected word line, to generate hot electrons in the channel, in a cell where hot electrons are generated,
Each step of injecting the hot electrons into the gate dielectric film of the memory transistor to perform writing is included.

Preferably, the voltage application to the source line and the voltage application to the bit line are performed for each column of memory cells. In addition, the operation method includes a verification read step, and the verification read step further includes the following steps, that is, supplying a voltage in the same direction as when the hot electrons are injected between the source line and the bit line, Each step of applying a predetermined voltage to the gate of the memory transistor and detecting the potential change of the bit line is further included.

In this operating method, the programming is performed by the source side injection and the erasing is performed by injecting the hot holes generated due to the band-to-band tunneling current, so that the cycle time of the programming operation including the pre-writing erasing is performed. It gets shorter. Further, in the case of including reading for verification after writing, it is sufficient to maintain the source line at the reference voltage and change the bit line potential at the time of writing to the bit line potential at the time of reading, and the source line and the bit line are large. No potential change in amplitude. Further, when the source line and the bit line are separated for each column, the memory cell rows connected to one word line can be operated collectively. As described above, by using the operation method according to the first aspect of the present invention, the cycle time of the write operation including erase and / or read is reduced even when the number of memory cells to be operated in parallel is large.

In a nonvolatile semiconductor memory device according to a second aspect of the present invention, a source line supplying a source voltage, a bit line supplying a drain voltage, a drain is connected to the bit line, and a gate dielectric film is formed. A memory transistor including a plurality of dielectrics laminated and including discrete charge storage means inside the laminated body, and the memory transistor and the source line were connected in series sharing the channel with the memory transistor. The MIS type transistor, a voltage for injecting hot electrons into the gate dielectric film of the memory transistor from the source side, and a voltage for injecting hot holes into the gate dielectric film of the memory transistor from the drain side are used. , The required voltage for the bit line, the gate of the memory transistor, and the gate of the MIS transistor And a voltage supply circuit for supplying at Bell and polarity. This voltage supply circuit preferably generates a band-to-band tunneling current on the drain side of the memory transistor, and a voltage of a magnitude and polarity required to inject hot holes resulting from the current into the gate dielectric film. Are supplied at least between the gate and drain of the memory transistor.

Since the non-volatile memory device having such a configuration has the voltage supply circuit having the above-mentioned function,
The above-described operation method of the present invention can be suitably implemented.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a block diagram showing a main configuration of a nonvolatile memory device according to an embodiment of the present invention. This non-volatile memory device roughly includes a memory unit and a CMOS unit such as a CPU or a logic circuit. Memory part and CMO
The S section is integrated on the same semiconductor substrate.

This memory section includes a memory cell array MC
A, row control circuit RC, column control circuit CC, power supply unit P
S, address control circuit AC. The row control circuit RC and the memory cell array MCA include a plurality of memory word lines M.
WL and a plurality of select word lines SWL are connected. The row control circuit RC uses these word lines MWL,
This is a circuit for controlling the SWL and includes a row decoder and a row buffer. The column control circuit CC and the memory cell array MCA are connected by a plurality of source lines SL and a plurality of bit lines BL. The column control circuit CC is a circuit for controlling these source lines and bit lines, and includes a column selection circuit, a sense amplifier, a write circuit, a column latch, an input / output buffer, and the like, which is required for writing, erasing and reading. Including all circuits. The power supply unit PS is a circuit that generates a predetermined voltage from the power supply voltage V _CC . Further, the address control circuit AC uses the address signal AD
It is a circuit that inputs R and outputs x-address X-ADR and y-address Y-ADR in synchronization with clock CLK, and includes an address buffer. Of these, the row control circuit R
The function of the "voltage supply circuit" of the present invention is embodied by C, the column control circuit CC, and the power supply section PS.

FIG. 2 is an equivalent circuit diagram of the separated source line NOR type memory cell array according to the first embodiment. Memory cells M11, M12, ..., M21, M22, ... Are arranged in a matrix in the memory cell array. Each memory cell is a memory transistor MT having a charge storage capability.
And a select transistor ST composed of MIS type transistors and having no charge storage capability. The memory transistor MT and the select transistor ST are connected in series between the source line and the bit line. That is, the bit line B to which the drain of the memory transistor MT corresponds
Are connected to Li (i = 1, 2, ...), the source of the select transistor ST is connected to the corresponding source line SLi, and the source of the memory transistor MT and the drain of the select transistor ST are connected.

The source line SLi and the bit line BLi are arranged in the column direction, and are provided for each memory cell column. The gate of the memory transistor MT is connected to the memory word line arranged in the row direction. That is, the memory transistors MT of the memory cells M11, M21, ... In the first row.
The gates of are connected to each other by a memory word line MWL1. In addition, the memory cells M12 and M2 in the second row
The gates of the memory transistors MT of 2, ... Are connected to each other by a memory word line MWL2. The gate of the select transistor ST is connected to the select word line arranged in the row direction. That is, the select transistor S of the memory cells M11, M21, ... In the first row.
The gates of T are mutually connected by a select word line SWL1. In addition, the memory cells M12 of the second row,
The gates of the select transistors ST of M22, ... Are connected to each other by a select word line SWL2.

FIG. 3 is a schematic plan view of this NOR type memory cell array. FIG. 4 is a bird's-eye view seen from the cross-section side along the line AA ′ in FIG. 3. FIG. 5 is a schematic cross-sectional view of the memory cell in the row direction.

In this NOR type memory cell array, as shown in FIG.
As shown in, a dielectric isolation layer ISO is formed from a trench, LOCOS, or the like on the surface of the p-type semiconductor substrate SUB (p well may be used). Dielectric isolation layer ISO
Has a parallel stripe shape that is long in the column direction, as shown in FIG. The memory word line MWLi and the select word line SWLi (i are substantially orthogonal to the dielectric isolation layer ISO.
= 1, 2, 3, 4, ...) are arranged. The memory word line MWLi and the select word line SWLi are arranged in parallel with each other with a thin dielectric film interposed therebetween.

In the semiconductor region within the distance between the dielectric isolation layers ISO, the substrate SU is placed in the space between the memory word line MWLi and the memory word line MWLi + 1 adjacent thereto.
An impurity of the conductivity type opposite to that of B is introduced at a high concentration to form the drain region D. Also, select word line SWL
In the space between i and the adjacent select word line SWLi + 1, the same impurities as the drain region D are collectively introduced to form the source region S. The size of the source region S and the drain region D is defined only by the distance between the dielectric isolation layers ISO in the row direction, and the distance between the memory word lines MWLi and MWLi + 1 or the select word lines SWLi and SWLi + 1 in the column direction. Specified by the interval between and. Therefore, the source region S and the drain region D
Are almost uniformly formed because almost no mask alignment error is introduced with respect to variations in size and arrangement.

The upper portions and side walls of the word lines MWLi and SWLi are covered with an insulating layer. That is, the word line M
An offset insulating layer is arranged on top of WLi and SWLi, and sidewall insulating layers are formed on both side walls thereof. The offset insulating layer and the sidewall insulating layer allow the memory word lines MWLi and MWLi + 1.
And space portions and select word lines SWLi and S
An elongated self-aligned contact hole is opened along the word line in the space portion with WLi + 1.

The self-aligned contact holes are alternately filled with conductive materials so as to partially overlap the source region S or the drain region D, whereby the bit contacts BC and the source contacts SC are formed.
In forming these contacts BC and SC, a conductive material is deposited so as to fill the entire self-aligned contact hole,
A resist pattern for an etching mask is formed thereon. At this time, a part of the resist pattern is overlaid on the dielectric isolation layer ISO. Then, using this resist pattern as a mask, the conductive material around the resist pattern is removed by etching. As a result, two types of contacts BC and SC are simultaneously formed.

A recess around the contact is filled with an insulating film (not shown). On this insulating film, bit lines BL1, BL2, ... Contacting the bit contacts BC and source lines SL1, ... Contacting the source contacts SC are alternately formed in parallel stripes.

In this NOR type cell array, contact formation with respect to the bit line or the source line is achieved by forming a self-aligned contact hole and forming a plug. In the formation of the self-aligned contact hole, insulation isolation from the word line is achieved, and the exposed surface of the source region S or the drain region D is uniformly formed. And
The formation of the bit contact BC and the source contact SC is performed by forming the source region S in the self-aligned contact hole.
Alternatively, it is performed on the exposed surface of the drain region D. Therefore, the size of the plug contact surface of the substrate in the column direction is substantially determined by the formation of the self-aligned contact holes, and the variation in the contact area is small accordingly.

It is easy to isolate the bit contact BC or the source contact SC from the word line. That is, the sidewall insulating layer is formed only by forming the offset insulating layer collectively at the time of forming the word line, and then forming the insulating film and etching the entire surface (etchback). Further, since the bit contact BC and the source contact SC, and further the bit line and the source line are formed by patterning the conductive layers of the same layer, the wiring structure is extremely simple, the number of steps is small, and the manufacturing cost is low. It has an advantageous structure to suppress it. Moreover, since there is almost no wasted space, when each layer is formed with the minimum line width F which is the wafer process limit, it is possible to manufacture with a cell area close to 8F ² .

In FIG. 5, the word lines MWLi and SWLi are sandwiched between the source region S and the drain region D.
The crossing point becomes a channel formation region CH of the memory transistor.

Drain region D on the channel formation region CH
The memory gate MG (memory word line MWLi) is stacked on the side portion with the first gate dielectric film GD1 interposed therebetween. In addition, the source region S on the channel formation region CH
The select gate MG (select word line SWLi) is stacked on the side portion with the second gate dielectric film GD21 interposed therebetween. These word lines MWLi, SWLi
Is composed of doped polycrystalline silicon in which p-type or n-type impurities are introduced at a high concentration, or a laminated film of doped polycrystalline silicon and refractory metal silicide. The effective gate length of the word line pair defined by the distance between the source region S and the drain region D is 0.13 μm or less, for example, about 100 nm. The first gate dielectric film GD1 extends between the select gate SG and the memory gate MG and is used as an isolation insulating film between both gates.

The first gate dielectric film GD1 is composed of a bottom dielectric film BTM, a charge storage film CHS, and a top dielectric film TOP in order from the lower layer. Bottom dielectric film B
The TM is used, for example, by forming a silicon dioxide film and nitriding it. The thickness of the bottom dielectric film BTM is 2.
It can be determined within the range of 5 nm to 6.0 nm, and here, it is set to 2.7 nm to 3.5 nm.

The charge storage film CHS is, for example, 6.0 nm.
Silicon nitride (Six Ny (0 <x <1,0 <y <
1)) composed of a membrane. This charge storage film CHS
Is produced by, for example, low pressure CVD (LP-CVD), and the film contains many carrier traps. The charge storage film CHS exhibits Frenkel pool type (FP type) electric conduction characteristics.

The top dielectric film TOP is a charge storage film CH.
It is necessary to form a deep carrier trap at a high density in the vicinity of the interface with S. Therefore, for example, it is formed by thermally oxidizing the nitride film after film formation. Top dielectric film TOP to HTO
(High Temperature chemicalvapor deposited Oxide)
A SiO ₂ film formed by the method may be used. When the top dielectric film TOP is formed by CVD, this trap is formed by heat treatment. The thickness of the top dielectric film TOP is at least 3.0 nm, preferably in order to effectively prevent injection of holes from the memory gate MG (memory word line MWLi) and prevent a decrease in the number of times data can be rewritten. Requires 3.5 nm or more.

In the manufacture of the memory transistor having such a structure, first, the dielectric isolation layer ISO and the p well W are formed on the prepared semiconductor substrate SUB, and then,
Ion implantation or the like for adjusting the threshold voltage is performed as necessary.

Next, on the semiconductor substrate SUB, a silicon dioxide film of, for example, several nm to tens of nm and doped polycrystalline silicon are formed, and these are patterned to form the second gate dielectric film GD2 and the select gate. A laminated film made of SG (select word line SWLi) is obtained. Next, the first gate dielectric film GD1 is formed on the entire surface. Specifically, for example, by a short time high temperature heat treatment method (RTO method), 1000
A heat treatment is performed at 10 ° C. for 10 seconds to form a silicon oxide film (bottom dielectric film BTM). Bottom dielectric film BTM
A silicon nitride film (charge storage film CHS) is deposited thereon by LP-CVD so as to have a final film thickness of 6 nm. This CVD is performed at a substrate temperature of 730 ° C. using, for example, a gas in which dichlorosilane (DCS) and ammonia are mixed. The surface of the formed silicon nitride film is oxidized by a thermal oxidation method to form, for example, a 3.5 nm silicon oxide film (top dielectric film TOP). This thermal oxidation is performed, for example, in a H ₂ O atmosphere at a furnace temperature of 950 ° C. for 4 hours.
Do about 0 minutes. As a result, a deep carrier trap having a trap level (energy difference from the conduction band of the silicon nitride film) of 2.0 eV or less is about 1 to 2 × 10 ¹³ / c.
It is formed with a density of m ² . Further, the thermal oxidation silicon film (top dielectric film TOP) is 1.5 n for the nitride film of 1 nm.
m, the nitride film thickness of the underlying layer is reduced by this ratio, and the final film thickness of the nitride film becomes 6 nm.

Polycrystalline silicon is deposited on the entire surface and is etched back to form conductive sidewalls on both sides of the select gate SG. By etching back at this time, the periphery of the conductive sidewall and the select gate SG
The upper first gate dielectric film GD1 is removed. An offset insulating film is formed on the select gate SG and the conductive sidewall on one side, and the conductive sidewall on the other side is removed using this as a mask. In this state, n-type impurities are ion-implanted into the substrate to form the source region S and the drain region D. Insulating sidewalls are formed on the side surfaces of the stacked body of the offset insulating film and the gates MG and SG. As a result, a self-aligned contact is formed, and the bit contact BC and the source contact S are formed in the source region S and the drain region D exposed by the self-aligned contact.
Form C. After that, the periphery of these plugs is filled with an interlayer insulating film, bit lines and source lines are formed on the interlayer insulating film, and then, if necessary, formation of upper layer wiring through the interlayer insulating layer, overcoat film formation, and pad opening. The nonvolatile memory cell array is completed through steps and the like.

FIG. 6 is a schematic sectional view showing another form of the memory cell structure. In this cell structure, an insulating spacer SPR is formed between the select gate SG and the memory gate MG in addition to the first gate dielectric film GD1. Further, the memory gate MG does not have a sidewall shape.

In the manufacture of this cell, after the laminated body of the second gate dielectric film GD2 and the select gate SG is formed,
Insulating sidewalls are formed on both sides, and
A first gate dielectric film GD1 is formed and polycrystalline silicon is deposited. The polycrystalline silicon is etched back from above to expose the first gate dielectric film GD1 on the select gate SG, and the first gate dielectric film GD1 on the select gate SG is removed by etching. An offset insulating layer made of a dielectric material is formed on the entire surface. At this time, one edge of the offset insulating layer is located above one edge of the select gate SG. With the resist used as a mask for forming the offset insulating layer as a mask, the memory gate M
The polycrystalline silicon that becomes G is separated. Then, the first gate dielectric film GD1 exposed around the offset insulating layer is removed by etching. At the same time, the insulating sidewall on one side of the select gate SG is removed,
The insulating sidewall on the other side is protected below the offset insulating layer and remains as an insulating spacer SPR.

Next, regarding the bias setting example and the operation of the nonvolatile memory having such a configuration, the memory cell M1
A case of writing data in 1 will be described as an example. FIG. 7 (A)
Is a circuit diagram showing bias conditions at the time of writing, FIG.
(B) is a circuit diagram showing bias conditions during erasing. 8A is a diagram showing a write operation, and FIG. 8B is a diagram showing an erase operation.

At the time of writing, as shown in FIG.
The substrate and the source line SL1 are held at the reference voltage, and a predetermined positive voltage, for example 4.0 V, is applied to the selected bit line BL1. Further, a predetermined program voltage, for example 5.0V, is applied to the selected memory word line MWL1, and a positive voltage lower than the program voltage, for example 1.8V, is applied to the selected select word line SWL1. At this time, the unselected memory word lines MWL2, ... And the unselected select word lines SWL2 ,.

Under this write condition, as shown in FIG. 8A, a channel is formed in the memory cell M11 to be written. At that time, a high electric field is generated below the boundary between the select gate SG and the memory gate MG. Channel electrons supplied from the source region S are accelerated by the source-drain voltage of 4 V, and high-energy electrons (hot electrons HE) are generated in the high electric field region.
Part of the hot electrons HE exceeds the energy barrier of 3.2 eV between silicon dioxide and silicon forming the bottom dielectric film BTM of the lowermost layer of the first gate dielectric film GD1 and passes through the inside of the first gate dielectric film GD1. The charge trap is injected from the source side and writing is performed. In this writing method, by determining whether the applied voltage of the other bit lines BL2, ... Is 4V or maintained at 0V,
Pages can be written.

At the time of erasing, as shown in FIG. 7B, the substrate is held at the reference voltage and the source line SL is opened, for example. A predetermined positive voltage, for example 5.0V, is applied to the selected bit line BL1, and a predetermined negative program voltage, for example, -5.0V is applied to the selected memory word line MWL1. At this time, 0V is applied to the selected select word line SWL1 or, if necessary, a negative voltage having a voltage value smaller than the program voltage is applied. Further, the unselected memory word lines MWL2, ... And the unselected select word lines SWL2 ,.

Under this erasing condition, as shown in FIG. 8B, the surface of the drain region D connected to the bit line BL1 is deeply depleted by the program voltage (negative voltage), and the energy band bends sharply. Become. At this time, electrons tunnel from the valence band to the conduction band due to the band-to-band tunnel effect and flow to the n-type impurity region (drain region D) side, and as a result, holes are generated. The generated holes slightly drift toward the center of the channel formation region,
There, the electric field is accelerated, and a part of it becomes a hot hole.
The high-energy charge (hot hole) generated at the edge of the n-type impurity region efficiently maintains the momentum (direction and size) of the n-type impurity region, loses little kinetic energy, and is high-speed at high speed. Injected into the charge trap inside.

In this erasing, the electric field in the channel forming region on the drain region D side is changed by the voltage applied to the select gate SG, and thereby the injection position of the hot hole can be controlled. For example, as shown in FIG. 8B, the drift amount of the hot holes changes depending on the voltage applied to the select gate SG, and the hot holes HH1 and HH2
As described above, charges can be injected into the first gate dielectric film GD1 from different positions. By this control, hot holes can be efficiently injected into the injection position of the hot electrons HE at the time of writing, and as a result, the erase efficiency is improved.

In reading, page reading is basically used. FIG. 9 is a circuit diagram showing a bias condition at the time of reading. This reading is performed with a forward bias in which the source-drain voltage application direction is the same as that during writing.
As shown in FIG. 9, a predetermined drain voltage, for example 1.0 V, is applied to the bit lines BL1, BL2, .... A predetermined read inhibit voltage, for example, -0.3V is applied to unselected memory word lines MWL2 ... And unselected select word lines SWL2 ... And 0V is applied to the source lines SL1, SL2 and the substrate. In this state, a voltage for turning on the select transistor ST, for example, 1.8 to 2.4 V is applied to the selected select word line SWL1, and a predetermined positive voltage, for example, 1.8 to 2.4 is applied to the selected memory word line MWL1. Apply 2.4V. As a result, in the memory cells M11, M21, ... Of the selected row, the memory transistor MT is turned on or off according to the write state, and the bit line voltage changes only when turned on. This voltage change is amplified by a sense amplifier (not shown) or the like and read.

When the select transistor ST is not provided, if hot hole injection is excessively performed at the time of erasing and the threshold voltage of the memory transistor MT is greatly reduced, the current amount at the time of reading varies and the current consumption is also wasteful. .

As in the present invention, the select transistor ST
In the cell structure having the
Has a threshold voltage Vth (ST) of, for example, 0.5 to 0.6 V
It is preset to the degree. Therefore, even if the memory transistor MT is over-erased, it is not affected by the reading. This is because the select transistor ST cuts off and functions as a limiter when the threshold voltage Vth (MT) of the memory transistor MT is greatly reduced and the read current is increased. Therefore, in this memory cell, the select transistor ST
There is an advantage that the upper limit of the read current can be controlled through the control of the threshold voltage, and unnecessary current consumption does not occur.

The current-voltage characteristics of the memory cell in the written state and the erased state were examined. As a result, the off-leakage current values from the non-selected cells M12, ... At the drain voltage of 1.0 V are the non-selected word lines MWLi, SW at the time of reading.
Since Li is biased to about -0.3 V, about 1 n
It was as small as A. Since the read current in this case is 1 μA or more, erroneous read of the non-selected cell does not occur. Therefore, it was found that the MONOS type memory transistor MT having a gate length of 100 nm has a sufficient margin of punch-through breakdown voltage at the time of reading. In addition, the read disturb characteristic at a gate voltage of 1.8 V was also evaluated, but it was found that reading could be performed even after a lapse of 3 × 10 ⁸ sec or more.

The bottom dielectric film BTM has a film thickness of 2.9 nm.
The data rewriting characteristic of the memory transistor MT of was examined. As a result, it was found that the narrowing of the threshold voltage difference up to 100,000 times was small and the number of rewrites was 100,000. Also, in any of the above cases, it was confirmed that a sufficient threshold voltage difference was maintained until the number of rewrites was 1 million. The data retention characteristics satisfied 85 ° C. for 10 years after the data was rewritten 1 × 10 ⁵ times.

From the above, the MONO having a gate length of 100 nm
It was confirmed that sufficient characteristics were obtained as an S-type non-volatile memory transistor.

Second Embodiment FIG. 10 shows an equivalent circuit of a memory cell array according to the second embodiment. FIG. 11 shows a bird's-eye view of this memory cell array viewed from the cross-sectional side in the row direction.

In the memory cell array shown in FIG. 10, as compared with the memory cell array according to the first embodiment of FIG. 2, two cells adjacent in the row direction share one source line SL. Therefore, when viewed from these two cells, two select transistors ST are connected to both sides of the central source line SL, and the memory transistor MT is arranged outside each of them. The drain of the select transistor ST and the source of the memory transistor MT are connected, and the drain of the memory transistor MT corresponds to the bit line BL.
1 or BL2.

In the memory cell array of FIG. 2, the gates (memory gates M of the memory transistors MT belonging to the same row are included.
G) was connected to the memory word line MWLi long in the row direction. On the other hand, in the memory cell array of FIG.
The gates of the memory transistors MT belonging to the same column are connected to the control line CLi long in the column direction.

The two columns of memory cell groups are repeated in the entire memory cell array. The memory cell groups in the two columns are isolated from each other by a dielectric isolation layer ISO1 such as a LOCOS or a trench element isolation layer. As described above, the memory cell array according to the second embodiment has the same array configuration as the so-called Hi-CR type in the FG type.

In FIG. 11, a p-well W is formed on the surface side inside the substrate SUB, and a dielectric isolation layer ISO1 made of parallel stripe-shaped STI long in the column direction is formed on the well surface side portion. Two dielectric isolation layers IS
In the well portion sandwiched by O1, three n ⁺ impurity regions are formed in a stripe shape parallel to the dielectric isolation layer ISO1. The two outer layers are adjacent to the dielectric isolation layer ISO1 and form the bit lines BL1 and BL2. Bit line BL
The central n ⁺ impurity region sandwiched between 1 and BL2 constitutes a shared source line SL.

Control gates SG are provided on the p-type well regions on both sides of the shared source line SL in the width direction with a single-layer second gate dielectric film GD2 interposed. The control gate SG is made of, for example, doped polycrystalline silicon, doped amorphous silicon, or the like, and a parallel stripe-shaped conductive material long in the column direction. However, this conductive material is discretely insulated at the location corresponding to the inter-cell region, thereby forming the dielectric isolation layer ISO2.

Select gate SG and dielectric isolation layer I
Control lines CL1 and CL2 made of conductive sidewalls are formed on the respective outer side surfaces of SO2 with a dielectric film, here a first gate dielectric film GD1, interposed. Control lines CL1 and CL2 are memory transistors MT
Function as a gate electrode (memory gate MG). The control line CL1 faces the p-type well surface region between the select gate SG and the bit line BL1 with the first gate dielectric film GD1 having a charge storage capability interposed therebetween. Similarly, the control line CL2 includes a select gate SG and a bit line B.
The p-type well surface region between L2 and L2 is faced with the first gate dielectric film GD1 having a charge storage capability interposed therebetween.

A plurality of control gates S belonging to cells in the same row
G is a word line WL1, which is composed of an upper layer wiring long in the row direction.
It is connected to any of WL2, ... Via a conductive plug or the like. Although not shown in particular, an insulating material forming an interlayer insulating film is buried around the conductive plug and the space between cells, and the word lines WL1, WL2, ... Are arranged on the interlayer insulating film.

In this memory cell, since the source line is shared between the two memory cell columns, the memory cell size in the row direction is slightly shortened as compared with the first embodiment, and the memory cell size is about 7F ²
A cell area of (= 3.5F × 2F) is realized.

The sectional structure of each memory cell is shown in FIG.
The same as the above, but a modification of FIG. 6 is also possible. Also, the first
The material of the second gate dielectric films GD1 and GD2 and the method of forming the same are the same as in the first embodiment. Furthermore, the basic write, erase and read operations are the same as in the first embodiment. Therefore, detailed description thereof is omitted here.

In the second embodiment as well, as in the first embodiment, in particular, since hot hole injection from the drain side is used for erasing and verification reading is performed with a forward bias, write operations including erasing and reading can be performed. There is an advantage that the cycle time can be shortened in total. Further, the MIS type transistor ST is formed in the center of the channel, and the threshold voltage V of the MIS type transistor ST is
th (ST) is preset to, for example, 0.5 to 0.6V. Therefore, as in the first embodiment, even when the memory transistor is over-erased, the MIS transistor functions as a current limiter at the time of reading, the upper limit of the read current is regulated, and unnecessary current consumption does not occur. There is an advantage.

Third Embodiment FIG. 12 shows an equivalent circuit of a memory cell array according to the third embodiment. FIG. 13 shows a plan view of this memory cell array, and FIG. 14 shows a bird's-eye view as seen from the sectional side along the line BB ′ of FIG.

In this memory cell array, the bit lines are hierarchized into main bit lines and sub bit lines, and the source lines are hierarchized into main source lines and sub source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the select transistor S11, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the select transistor S21. The sub-source line SSL1 is connected to the main source line MSL1 through the select transistor S12, and the main source line MSL2 is connected to the select transistor S22.
The sub-source line SSL2 is connected via.

Sub bit line SBL1 and sub source line SSL1
Memory transistors MT11 to MT1n (for example, n = 128) having a split gate structure are connected in parallel with each other, and memory transistors MT21 to MT2n are connected in parallel between the sub bit line SBL2 and the sub source line SSL2. There is. The n memory transistors connected in parallel to each other and two select transistors (S1
1 and S12, or S21 and S22) form a unit block forming a memory cell array.

The gates of the memory transistors MT11, MT21, ... Adjacent to the word direction are connected to the word line WL1. Similarly, the memory transistor MT1
, MT22, ... Gates are connected to the word line WL2, and memory transistors MT1n, MT2n ,.
Each gate of is connected to the word line WLn. The select transistors S11, ... Adjacent to the word direction are controlled by the select gate line SG11, and the select transistors S21, ... Are controlled by the select gate line SG21. Similarly, the select transistors S12, ... Adjacent to the word direction are controlled by the select gate line SG12,
The select transistors S22, ... Are select gate lines SG2.
Controlled by 2.

In this memory cell array, as shown in FIG. 14, the p well W is formed on the surface of the semiconductor substrate SUB. The p well W is a dielectric isolation layer IS in which trenches are filled with an insulator and arranged in parallel stripes.
O is electrically isolated in the word direction.

Each p separated by the dielectric separation layer ISO
The well portion becomes the active region of the memory transistor.
N-type impurities are introduced at high concentration in parallel stripes spaced apart from each other in the width direction in the active region, whereby the sub-bit lines SBL1 and SBL2 (hereinafter referred to as SBL) and the sub-source line SSL1 are formed. , SSL2 (hereinafter, SS
L) is formed. Each of the word lines WL1, WL2, WL3, WL4, ... (Hereinafter, referred to as WL is orthogonal to the sub bit line SBL and the sub source line SSL with an insulating film interposed therebetween.
Is written at equal intervals. These word lines WL are formed on the p-well W and the dielectric isolation layer I via a dielectric film or a single-layer dielectric film containing charge storage means inside.
It is in contact with SO. Sub bit line SBL and sub source line S
The intersection of the p well W with SL and each word line WL serves as a channel forming region of the memory transistor, the sub bit line portion in contact with the channel forming region functions as a drain, and the sub source line portion functions as a source. To do.

The upper surface and the side wall of the word line WL are covered with an offset insulating layer and an insulating side wall (in this example, a normal interlayer insulating layer may be used). Bit contacts BC that reach the sub-bit line SBL and source contacts SC that reach the sub-source line SSL are formed in these insulating layers at predetermined intervals. These contacts BC and SC are provided, for example, for every 128 memory transistors in the bit direction. In addition, the main bit line MB that comes into contact with the bit contact BC on the insulating layer
L1, MBL2, ... (hereinafter referred to as MBL), and main source lines MSL1 and MS that come into contact with the source contact SC.
L2, ... (Hereinafter, referred to as MSL) are alternately formed in parallel stripes.

In this memory cell array, the bit lines and the source lines are hierarchized, and it is not necessary to form the bit contact BC and the source contact SC for each memory cell. Therefore, there is basically no variation in the contact resistance itself. The bit contact BC and the source contact SC are provided for every 128 memory cells, for example, but if this plug formation is not performed in a self-aligned manner, the offset insulating layer and the insulating sidewall are not necessary. That is, a normal interlayer insulating film is deposited thickly to embed a memory transistor, and then contacts are opened by normal photolithography and etching.

Since there is almost no wasted space as a pseudo contactless structure in which the sub-bit line and the sub-source line are made of impurity regions, when each layer is formed with the minimum line width F of the wafer process limit, it becomes 8F ² . It can be manufactured with a very small cell area. Further, the bit line and the source line are hierarchized, and the select transistor S11 or S2
Since 1 separates the parallel memory transistor group in the unit block of non-selection from the main bit line MBL1 or MBL2, the capacity of the main bit line is significantly reduced and the speed is increased.
It is advantageous for low power consumption. In addition, the function of the select transistor S12 or S22 can separate the sub source line from the main source line to reduce the capacitance. In addition,
In order to further increase the speed, it is preferable that the sub bit line SBL and the sub source line SSL are formed of impurity regions to which silicide is attached, and the main bit line MBL and the main source line MSL are metal wiring.

FIG. 15 shows an enlarged cross-sectional view of the memory transistor in the row direction. In FIG. 15, a drain impurity region D forming a sub bit line and a source region S forming a sub source line.
A portion which is sandwiched between and and which intersects the word line WL becomes a channel formation region CH of the memory transistor.

On the channel forming region CH, the gate electrode (word line WL) of the memory transistor is laminated via the first gate dielectric film GD1 or the second gate dielectric film GD2. The first gate dielectric film GD1 is a film in which a plurality of dielectric layers are stacked and has many charge traps inside, and the second gate dielectric film GD2 is a single-layer film and has no charge storage capability. The first gate dielectric film GD1 is
It extends from the middle of the drain region D to the middle of the channel formation region CH. On the other channel formation region part,
On the drain region and the entire source region S,
The second gate dielectric film GD2 is formed. The film structure of the first gate dielectric film GD1 and the second gate dielectric film GD2, and the manufacturing method are the same as in the first embodiment.

The word line WL is generally formed of doped polycrystalline silicon in which p-type or n-type impurities are introduced at a high concentration to make it conductive, or a laminated film of doped polycrystalline silicon and a refractory metal silicide. The effective gate length of this memory transistor, which is defined by the distance between the source region S and the drain region D, is 0.13 μm or less, for example, 100 nm.
It is a degree. In the memory cell of the present embodiment, the electrode on the first gate dielectric film GD1 and the electrode on the second gate dielectric film GD2 are thus formed of a common conductive layer. This is the same as a so-called split gate structure.

In manufacturing this memory cell array,
First, the dielectric isolation layer I is added to the prepared semiconductor substrate SUB.
After forming the SO and p well W, the sub bit line SB
Impurity regions to be L (drain region D) and sub-source line SSL (source region S) are formed by ion implantation. Ion implantation for adjusting the threshold voltage is performed as necessary.

Next, the first gate dielectric film GD1 and the second gate dielectric film GD2 are separately formed on the p well W. Specifically, the first gate dielectric film GD1 is formed on the entire surface by the same method as in the first embodiment. This first gate dielectric film GD1 is patterned. That is, the first gate dielectric film GD1 is left in a necessary region (memory portion) including the end portion of the drain region D, and is removed in another region (non-memory portion). Then, the first gate dielectric film GD
The well surface from which 1 has been removed is thermally oxidized to form the second gate dielectric film GD2. The first gate dielectric film G
In forming D1, the bottom dielectric film BTM and the charge storage film C are formed.
Up to HS, the top dielectric film TOP of the first gate dielectric film GD1 may be formed simultaneously with the thermal oxidation of the second gate dielectric film GD2. Alternatively, in the step of removing the first gate dielectric film GD1, only the top dielectric film TOP and the charge storage film CHS are removed in the non-memory portion, and further the necessary thermal oxidation is performed to leave the bottom dielectric material remaining in the non-memory portion. The film thickness of the film BTM may be increased to form the second gate dielectric film GD2.

A laminated film of a conductive film to be the word line WL and an offset insulating layer (not shown) is laminated, and this laminated film is processed in the same pattern all at once. At this time, the first gate dielectric film GD1 and the second gate dielectric film GD2 around the word line are also removed. Subsequently, in order to obtain the memory cell array structure of FIG. 14, the self-aligned contact is opened by forming the insulating sidewall, and the drain region D (sub-bit line SBL) and the source region S (sub-electrode) exposed by the self-aligned contact are formed. The bit contact BC and the source contact SC are formed on the source line SSL).
Thereafter, the periphery of these plugs is filled with an interlayer insulating film, and the main bit line MBL and the main source line MSL are formed on the interlayer insulating film.
After forming, the memory cell array is completed through the formation of upper layer wiring via an interlayer insulating layer, the overcoat film formation, the pad opening step, and the like, which are performed as necessary.

Select transistors S11 to S of FIG.
The operation of turning on or off 22 is required, but other basic write, erase and read operations are the same as in the first embodiment. Therefore, detailed description thereof is omitted here.

However, in the split gate type transistor, the drain side memory portion on which the first gate dielectric film GD1 is formed and the source side non-memory portion on which the second gate dielectric film GD2 is formed are It is controlled by a common gate electrode. Therefore, the gate applied voltages of the memory section and the non-memory section are necessarily the same. In this respect, unlike the first embodiment, the operation in the present embodiment corresponds to the special case in which the applied voltages to the select gate SG and the memory gate MG are the same in the first embodiment. For this reason,
The injection efficiency of hot electrons HE during writing is the first
It may not be improved as much as the embodiment, and there is a limit to hot hole injection position control at the time of erasing. On the other hand, the gate structure of the memory cell of this embodiment is simpler than that of the first embodiment, and has the advantages that the number of manufacturing steps is small and the memory cell area can be easily reduced.

In the third embodiment as well, as in the first embodiment, in particular, hot hole injection from the drain side is used for erasing, and verification reading is performed with a forward bias, so that a writing operation including erasing and reading can be performed. There is an advantage that the cycle time can be shortened in total.

The present invention can be applied to cell array structures other than those shown in the first to third embodiments, for example, a virtual ground cell structure. Further, in the above first to third embodiments, the MONOS type has been described as the memory transistor, but the present invention has a charge storage means such as a so-called MNOS type, a silicon nanocrystal type, or a fine division FG type in at least the plane direction. It can be applied to all memory transistors having a discretized structure.

[0082]

As described above, according to the operating method of the non-volatile semiconductor memory device of the present invention, the cycle time of write operation including erase (and read) can be shortened in total. Moreover, since the number of cells for parallel operation can be increased, the operation time of the entire memory cell array can be shortened. Further, since the maximum operating voltage can be lowered to 5 V, the high breakdown voltage circuit of the peripheral circuit which is generally widely used is not required, and the peripheral circuit can be configured by the transistor of the low breakdown voltage specification. As a result, the number of masks can be reduced, and the cost can be reduced as a mixed NVM (Non-Volatile Memory).

The non-volatile semiconductor memory device according to the present invention has a structure capable of suitably carrying out the operating method having such effects. Further, since the charge storage means is discretized, the charge retention characteristics are excellent, the storage element can be easily scaled, and the operating voltage can be lowered. Therefore, it has a high affinity with the CMOS process and can be easily realized as a low-cost memory-embedded system LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is an isolated source line NO according to the first embodiment of the present invention.
It is an equivalent circuit diagram of an R-type memory cell array.

FIG. 3 is a schematic plan view of a memory cell array according to the first embodiment of the present invention.

FIG. 4 relates to the first embodiment of the present invention, and is AA ′ of FIG.
It is the bird's-eye view seen from the cross section along the line.

FIG. 5 is a schematic cross-sectional view in the row direction of the memory cell according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing another form of the memory cell structure according to the first embodiment of the present invention.

FIG. 7A is a circuit diagram showing bias conditions at the time of writing in the memory cell array according to the first embodiment of the present invention;
(B) is a circuit diagram showing bias conditions during erasing.

FIG. 8A is a diagram showing a write operation of the memory cell array according to the first embodiment of the present invention, and FIG. 8B is a diagram showing an erase operation.

FIG. 9 is a circuit diagram showing a bias condition at the time of reading of the memory cell array according to the first embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram of a memory cell array according to a second embodiment of the present invention.

FIG. 11 is a bird's-eye view of the memory cell array according to the second embodiment of the present invention as seen from the cross-sectional side in the row direction.

FIG. 12 is an equivalent circuit diagram of a memory cell array according to a third embodiment of the present invention.

FIG. 13 is a plan view of a memory cell array according to a third embodiment of the present invention.

FIG. 14 relates to the third embodiment of the present invention and is B- in FIG.
It is the bird's-eye view seen from the cross section side along the B ′ line.

FIG. 15 is an enlarged cross-sectional view in the row direction of the memory transistor according to the second embodiment of the present invention.

[Explanation of symbols]

MCA ... Memory cell array, RC ... Row control circuit (voltage supply circuit), CC ... Column control circuit (voltage supply circuit),
PS ... Power supply (voltage supply circuit), M11, etc .... Memory cell,
MT ... Memory transistor, ST ... Select transistor (MIS type transistor), MG ... Memory gate (first gate electrode), SG ... Select gate (second gate electrode), SL1, etc .... Source line, BL1, etc .... Bit line, MW
L1 and the like ... Memory word line (word line), SWL1 and the like ... Select word line, CL1 and the like ... Control line, GD1 ... First gate dielectric film, GD2 ... Second gate dielectric film.

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme coat (reference) H01L 29/792 F term (reference) 5B025 AA07 AC01 AD04 AD08 AE05 AE07 5F083 EP18 EP32 EP34 EP35 EP77 ER02 ER05 ER11 ER30 GA06 KA06 KA12 LA12 LA16 MA06 MA16 MA19 NA01 PR13 PR39 5F101 BA45 BC11 BD10 BD22 BD36 BE05 BE07

Claims (10)

[Claims] 1. A memory transistor comprising a MIS type transistor connected in series between a source line and a bit line and sharing a channel, and a memory transistor, wherein a gate dielectric film of the memory transistor is formed by laminating a plurality of dielectrics. A method for operating a nonvolatile semiconductor memory device including discrete charge storage means inside the laminated film, wherein the operating method includes the following steps, that is, a boundary between a MIS transistor and a memory transistor at the time of writing. Hot electrons generated in the vicinity are injected into the gate dielectric film of the memory transistor from the source side, and during erase, hot holes generated on the drain side of the memory transistor are stored in the electron storage area of the gate dielectric film of the memory transistor. A method for operating a non-volatile semiconductor memory device, including the steps of implanting from the drain side to the semiconductor device. 2. A memory cell array in which a plurality of memory cells having the MIS type transistors and the memory transistors are arranged in a matrix and the gates of the plurality of memory transistors belonging to the same row are connected by word lines. A write cycle for the memory cell array provided in a non-volatile memory device is performed between the following steps, that is, between all the bit lines connected to the drains of the memory transistors and the word line of the selected row. A voltage is applied to generate a hot hole in the drain of the memory transistor, and the generated hot hole is injected into the gate dielectric film of the corresponding memory transistor to simultaneously erase the memory cells in the selected row. And the source line and cell connected to the cell that needs to inject charge according to the write data. Apply a predetermined voltage between the
At the same time, a predetermined voltage is applied to the selected word line to generate hot electrons in the channel, and the hot electrons are injected into the gate dielectric film of the memory transistor in the cell where the hot electrons are generated. 2. The method for operating a nonvolatile semiconductor memory device according to claim 1, including each step of writing by writing. 3. The method for operating a nonvolatile semiconductor memory device according to claim 2, wherein the voltage application to the source line and the voltage application to the bit line are performed for each column of memory cells. 4. The operation method includes a verification read step, and the verification read step further includes the following steps, that is, supplying a voltage in the same direction as when the hot electrons are injected between the source line and the bit line. 2. The method of operating a nonvolatile semiconductor memory device according to claim 1, further comprising the steps of applying a predetermined voltage to the gate of the memory transistor and detecting a potential change of the bit line. 5. A source line supplying a source voltage, a bit line supplying a drain voltage, a drain connected to the bit line, and a gate dielectric film formed by laminating a plurality of dielectrics. A memory transistor including a charge storage means discretized therein, a MIS transistor connected in series between the memory transistor and a source line, sharing a channel with the memory transistor, and hot electrons used as a gate dielectric of the memory transistor. The voltage for injecting from the source side into the film and the voltage to inject hot holes from the drain side into the gate dielectric film of the memory transistor are the source line, the bit line, the gate of the memory transistor, the gate of the MIS type transistor. Each has a voltage supply circuit that supplies it with the required voltage level and polarity. Memory device. 6. The voltage supply circuit generates a band-to-band tunneling current on the drain side of the memory transistor, and the size and polarity required for injecting hot holes caused by the current into the gate dielectric film. Voltage of
The non-volatile semiconductor memory device according to claim 5, wherein at least it is supplied between the gate and the drain of the memory transistor. 7. A channel formation region made of a first conductivity type semiconductor, a source region and a drain region made of a second conductivity type semiconductor and sandwiching the channel formation region, and a channel formation region portion in contact with the drain region. A first charge storage unit which is composed of a plurality of dielectric films and is discretized in a plane facing the channel formation region;
A gate dielectric film, and a second gate dielectric film formed of a single-layer dielectric having no charge storage capability, formed on a channel formation region portion near the source side end of the first gate dielectric film. The first gate electrode formed on the first gate dielectric film, and the second gate electrode formed on the second gate dielectric film and insulated from the first gate electrode. Non-volatile semiconductor memory device. 8. A channel formation region made of a first conductivity type semiconductor, a source region and a drain region made of a second conductivity type semiconductor, sandwiching the channel formation region, and a channel formation region portion in contact with the drain region. A first charge storage unit which is composed of a plurality of dielectric films and is discretized in a plane facing the channel formation region;
A gate dielectric film and a second gate dielectric film formed of a single-layer dielectric formed on the channel formation region portion near the source side end of the first gate dielectric film and having no charge storage capability. The nonvolatile semiconductor memory device according to claim 5, further comprising a gate electrode formed on the first gate dielectric film and the second gate dielectric film. 9. A plurality of memory cells having the MIS type transistors and the memory transistors are arranged in a matrix, the gates of the plurality of memory transistors belonging to the same row are connected to a word line, and the plurality of memory cells belonging to the same column. The source of the MIS transistor is
The non-volatile semiconductor memory device according to claim 5, wherein the plurality of memory transistors belonging to the same column are connected to source lines separated for each column, and the drains of the memory transistors are connected to bit lines separated for each column. 10. A memory cell array in which a plurality of memory cells each having the MIS type transistor and the memory transistor are arranged in a matrix, a memory control circuit including the voltage supply circuit, and another formed by a CMOS process. 6. The non-volatile semiconductor memory device according to claim 5, wherein the circuits are integrated on the same semiconductor substrate.