JP2003045194A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: A semiconductor capable of improving the chip manufacturing yield even when a defect is recognized in a redundant memory cell replaced with a defective memory cell, which can be replaced with another redundant memory cell. It is an object to realize a storage device. When a redundant memory cell replaced to repair a defective memory cell is defective, the correspondence of the redundant program circuit to the redundant memory cell selection circuit is switched to a new redundant memory cell selection circuit. A switching circuit 2 for inactivating the function of the corresponding redundant memory cell selection circuit 3 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a yield is improved by using redundant memory cells.

[0002]

2. Description of the Related Art In order to improve the manufacturing yield of semiconductor memory devices, defective memory cells are generally replaced with redundant memory cells. In this case, it is general to perform replacement on a word line (row) basis or a bit line (column) basis. In this redundancy method, a row or column including a defective memory cell is made inactive, and when a corresponding address is selected, a redundant row or a column can be selected to repair the defective memory cell. To set the address, a method such as cutting a fuse due to laser or overcurrent is used.

However, with the recent increase in capacity of semiconductor devices, the area of the redundant memory cell area also increases, and it is fully possible that the redundant memory cell portion to be replaced may be defective before replacement. To be In the above-mentioned conventional method, for example, considering the case where a single bit defect is replaced with column redundancy, if the redundant column is defective, there is a redundant column that is not yet used, Since it is immediately regarded as a defective chip and discarded, there is a problem that it leads to a reduction in manufacturing yield.

[0004]

As described above, in the conventional semiconductor memory device, the replacement of the redundant memory cell with the defective memory cell is allowed, but when a defect is found in the replaced redundant memory cell, it is still not possible. There is a problem that a defective chip is immediately discarded and discarded even though there is a redundant memory cell that is not used. The present invention solves this problem by a relatively simple method, and even when a redundant memory cell replaced with a defective memory cell has a defect, it can be replaced with another redundant memory cell, resulting in a chip manufacturing yield. It is an object to realize a semiconductor memory device capable of improving

[0005]

In order to achieve the above object, the present invention provides a redundant address program means for allocating an address of a defective memory cell to a redundant memory cell, and a redundant address program means provided corresponding to the redundant address program means. A redundant memory cell selecting means for selecting the redundant memory cell when an address assigned by the redundant address programming means is designated, and replacing the defective memory cell with the redundant memory cell to relieve the defective memory cell. In the memory device, when the replaced redundant memory cell is defective, the correspondence of the redundant address programming means to the redundant memory cell selecting means is switched to a new redundant memory cell selecting means, and the redundant memory cell previously corresponding A switching means for deactivating the function of the selecting means. That.

Further, the semiconductor memory device for relieving the defective memory cell is provided with redundant address program selecting means for deactivating the function of the redundant address program means when the replaced redundant memory cell is defective. Characterize. As a result, even if a defective redundant memory cell is found to be defective, it can be replaced with another redundant memory cell by a relatively simple method, and the chip manufacturing yield can be improved.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a semiconductor memory device having a memory cell and a redundant memory cell capable of replacing a selected memory cell, and a test after replacement of a redundant memory cell replaced with a defective memory cell. The present invention provides a semiconductor device having a circuit for repairing a defective memory cell again by using an unused redundant memory cell when the defective memory cell is determined to be defective. In general, a redundant program circuit using a fuse or the like is used to replace a defective memory cell with a redundant memory cell. Normally, the address of the memory cell to be replaced is programmed by the redundant program circuit, and when the address is compared with the input address from the outside and read, the read / write operation from the programmed redundant memory cell is performed. The redundant program circuit and the redundant memory cell selection circuit usually correspond one to one.

However, the first invention of the present invention has the switching circuit capable of switching the connection between the redundant program circuit and the redundant memory cell selection circuit. The switching circuit has a function of connecting the program circuit connected to the redundant memory cell selection circuit to an unused redundant memory cell selection circuit when the replaced redundant memory cell is determined to be defective. In this circuit, the already programmed redundant program circuit is reused, so that the redundant program can be switched with a small number of fuse cuts. The switching circuit also has a function of deactivating the redundant memory cell selection circuit determined to be defective.

Further, in the second aspect of the present invention, means for inactivating the function of the redundant program circuit is provided, and when the replaced redundant memory cell is determined to be defective, the redundant memory cell selection circuit is dealt with. The redundant program circuit is deactivated and another redundant program circuit selects a redundant memory cell, and the defective memory cell is remedied again.

A semiconductor memory device according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a block diagram of an embodiment of a semiconductor memory device having a redundancy system of the present invention. In FIG. 1, reference numeral 1 is a redundant program circuit, reference numeral 2 is a switching circuit, reference numeral 3 is a redundant memory cell selection circuit, reference numeral 4 is a row decoder, reference numeral 5 is a column decoder, reference numeral 6 is a memory cell, and reference numeral 7 is a row redundant memory. Cell, reference numeral 8 is a column redundant memory cell,
Reference numeral 9 is a sense amplifier, reference numeral 10 is an input / output circuit,
This is a configuration in which a redundant memory cell selection unit 11 including a redundant program circuit 1, a switching circuit 2, and a redundant memory cell selection circuit 3 is added to the basic circuit of a semiconductor memory device having a conventional redundancy system.

On the other hand, FIG. 2 shows a block diagram of a semiconductor memory device having a conventional redundancy system. In FIG. 2, reference numeral 1
Is a redundant program circuit, reference numeral 3 is a redundant memory cell selection circuit, reference numeral 4 is a row decoder, reference numeral 5 is a column decoder, reference numeral 6
Is a memory cell, reference numeral 7 is a row redundant memory cell, reference numeral 8 is a column redundant memory cell, reference numeral 9 is a sense amplifier, and reference numeral 10 is an input / output circuit. There is no switching circuit 2 of 1 and the redundant program circuit 2 is directly connected to the redundant memory cell selection circuit 3.

FIG. 3 is a block diagram showing details of the redundant memory cell selection unit 11 of the semiconductor memory device of the present invention shown in FIG. 1, and FIG. 4 is a redundant memory cell of the conventional semiconductor memory device shown in FIG. It is a block diagram which shows the detail of the selection part 11 '. As can be seen from FIG. 3, the redundant memory cell selection unit 11 of the semiconductor memory device of the present invention includes the redundant program circuits 0 to 0.
n (1-0 to 1-n) and redundant memory cell selection circuits 0 to n
The switching circuit 2-1 is shown between (3-0 to 3-n). Reference numerals 21-0 to 21-n are enable signals for enabling the redundant memory cell selection circuits 3-0 to 3-n output from the redundant program circuits 1-0 to 1-n and program signals for programming addresses. Signal line.

FIG. 5 is a circuit diagram showing details of the switching circuit 2-1. The operation of the switching circuit 2-1 for switching the two redundant circuits will be described with reference to FIG. When the defective memory cell is repaired by using the redundant memory cell selection circuit 0 (3-0), the redundant program circuit 0 (1-
In 0), the address of the defective memory cell is programmed by a fuse or the like. When the address input of the external signal input from the address input terminal 22 is equal to the address programmed in the redundant program circuit 0 (1-0), the redundant memory cell selection circuit 0 (3-0) is connected. No redundant memory cells are selected. However, if the redundant memory cell connected to the redundant memory cell selection circuit 0 (3-0) is defective, the redundant memory cell is switched by the method described below.

1. In FIG. 5, the fuse 2-18 is cut, and the enable signal 2-25 from the redundant program circuit 0 (1-0) causes the redundant memory cell selection circuit 0 (3
-Disconnect the connection so that it is not input to 0).

2. Then the two FETs 2-13 and 2-
Fuse 2 connecting drain of 14 to power supply 2-9
By cutting -10 and applying a high (H) level pulse signal to the reset terminal 2-12, for example, the node 2-15 can be fixed at the low (L) level.
Before the fuse 2-10 is not blown, the node 2-
It is easy to see that 15 is at the high (H) level.

3. Multiplexer (mux) 2-20
When the node 2-15 is at the high (H) level, the redundant memory cell selection circuit 1 (3) outputs the enable signal from the redundant program circuit 1 (1-1) and the program signal 2-21.
-1), and has a function of outputting the enable signal and the program signal 2-22 from the redundant program circuit 0 (1-0) when the node 2-15 is at the low (L) level. .

4. The node 2-15 is connected to the pull-up PMOS transistor 2-17. Therefore, when the fuse switching circuit 2-10 is cut, the pull-up PMOS transistor 2-17 is turned on, and the enable signal 2-25 separated by cutting the fuse 2-18 is raised to the high (H) level. ,
The redundant memory cell selection circuit 0 (3-0) can be brought into a non-selected state.

5. As described above, the two fuses 2-1
By cutting 0 and 2-18, the redundant program circuit 0 (1-0) and the redundant memory cell selection circuit 0 (3-
0) is connected to the redundant program circuit 0
(1-0) and the redundant memory cell selection circuit 1 (3-1) can be switched to the connected state.

By doing so, when the same address programmed by the redundant program circuit 0 (1-0) is input from the address input terminal 22,
The redundant memory cell selection circuit 0 (3-0) is not selected, the redundant memory cell selection circuit 1 (3-1) is activated, the redundant memory cell connected to it is selected, and switching is realized.

FIG. 6 shows a block diagram of another embodiment of the redundant memory cell selection unit 11 of the semiconductor memory device of the present invention. In FIG. 3, the switching circuit 2-1 includes a redundant program circuit 0 (1-0) and a redundant program circuit 1 (1-
Although it is shown that it is provided between 1), as shown in FIG.
A plurality of redundant program circuits m and m + 1 may be provided between the redundant program circuits m and the redundant program circuits m + 1 to enable switching backup even if there are defective redundant memories.

FIG. 7 shows a block diagram of still another embodiment of the redundant memory cell selection section 11 of the semiconductor memory device of the present invention. As shown in FIG. 7, the switching circuit 2-1 is connected to the redundant program circuit 0 (1-0) and the redundant program circuit 1
The switching circuit 2-2 is provided between the (1-1) and the redundancy program circuit 1 (1-1) and the redundancy program circuit 2
By providing the switch between (1-2) and switching the redundant memory cell in two stages, it is possible to further back up the switched redundant memory if it is defective.

FIG. 8 shows a block diagram of another embodiment of the semiconductor memory device having the redundancy system of the present invention. Figure 9
Is the redundant memory cell selection unit 11 of the embodiment shown in FIG.
3 is a block diagram showing the details of FIG. The embodiment of FIG. 8 differs from that of FIG. 1 in that instead of providing the switching circuit 2 between the redundant program circuit 1 and the redundant memory cell selection circuit 3 in FIG. 1, a redundant program enable circuit 12 is provided. The point is that the effectiveness of the redundant program circuit 1 is selected by this circuit.

In this embodiment, as shown in FIG.
When the redundant memory connected to the redundant memory cell selection circuit 0 (3-0) is defective, the redundant memory cell selection circuit 0 (12-0) is used.
Redundant program circuit 0 (1-0) corresponding to (3-0)
Of the redundant program circuit 0 (1-0)
The address specified by is designated again by another redundant program circuit, for example, the redundant program circuit 1 (1-1). Thus, if the redundant memory replaced with the defective memory cell is defective, it can be replaced with another redundant memory for improvement.

FIG. 10 shows the redundant program enable circuit 1
An example of the detailed circuit diagram of 2 is shown. The operation of the redundant program enable circuit 12 will be described with reference to this figure. First, if you want to activate the enable signal, use the fuse 12-5.
Is cut, and a high (H) pulse is input once to the rst1 terminal. The rst2 terminal is kept low (L). Then, the enable signal becomes high (H) and becomes active.
To deactivate the once activated enable signal, cut the fuses 12-6 and 12-7 and input the high (H) pulse once to the rst2 terminal, and the enable terminal becomes low (L). Become inactive.

Although the redundant program enable circuit 12 is shown separately in FIGS. 8 and 9, the redundant program enable circuit 12 should be provided in the redundant program circuit (1). Is also possible. In addition, instead of deactivating the function of the redundant program circuit (1), the enable signal output from the redundant program circuit (1) to the redundant memory cell selection circuit (3) is raised to a high (H) level for redundancy. It is also possible to deactivate the memory cell selection circuit (3) and specify another redundant memory by another redundant program circuit.

[0027]

As described above, according to the first aspect of the present invention, a redundant program circuit for allocating an address of a defective memory cell to a redundant memory cell and a redundant program circuit provided and allocated corresponding to the redundant program circuit are provided. In a semiconductor memory device that has a redundant memory cell selection circuit that selects a redundant memory cell when an address is specified, and replaces the defective memory cell with the redundant memory cell to relieve the defective memory cell, if the redundant memory cell is defective. Further, a switching circuit for switching the correspondence of the redundant program circuit to the redundant memory cell selection circuit to the new redundant memory cell selection circuit and deactivating the function of the previously corresponding redundant memory cell selection circuit is provided. As a result, when the replaced redundant memory cell is determined to be defective, the program circuit connected to the redundant memory cell selection circuit can be connected to an unused redundant memory cell selection circuit to reallocate the redundant memory cell. Since the redundant program circuit already programmed is reused, the redundant program can be switched with a small number of fuse cuts. At this time, since the unused redundant circuit can be effectively used, the defect repair rate of the semiconductor memory device can be improved without increasing the chip area so much.

According to the second aspect of the present invention, the switching of the redundant program circuit to the new redundant memory cell selection circuit by the switching circuit and the inactivation of the function of the old redundant memory cell selection circuit are realized by cutting the fuse. It is characterized by As a result, the redundant memory cells can be stably switched without requiring a special device.

According to a third aspect of the present invention, a redundant program circuit for assigning an address of a defective memory cell to a redundant memory cell and an address assigned by this redundant program circuit are provided corresponding to the redundant program circuit. In a semiconductor memory device that has a redundant memory cell selection circuit that selects a redundant memory cell when designated and replaces the defective memory cell with the redundant memory cell to repair the defective memory cell, when the redundant memory cell is defective, It is characterized by comprising a redundant program enable circuit for deactivating the function of the redundant program circuit. As a result, when the replaced redundant memory cell is determined to be defective, it can be re-designated by the redundant program circuit, and the program circuit can efficiently repair the semiconductor memory device by using the unused redundant memory cell. Therefore, the defect relief rate of the semiconductor memory device can be improved without increasing the chip area so much.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device having a redundancy system of the present invention.

FIG. 2 is a block diagram of a conventional semiconductor memory device having a redundancy system.

FIG. 3 is a block diagram of a redundant memory cell selection unit of the semiconductor memory device of the present invention shown in FIG.

FIG. 4 is a block diagram of a redundant memory cell selection unit of the conventional semiconductor memory device shown in FIG.

5 is a circuit diagram showing details of a switching circuit of the semiconductor memory device of the present invention shown in FIG.

FIG. 6 is a block diagram of another embodiment of the redundant memory cell selection unit of the semiconductor memory device of the present invention.

FIG. 7 is a block diagram of still another embodiment of the redundant memory cell selection unit of the semiconductor memory device of the present invention.

FIG. 8 is a block diagram of another embodiment of a semiconductor memory device having a redundancy system of the present invention.

9 is a block diagram of a redundant memory cell selection unit of the semiconductor memory device of the present invention shown in FIG.

10 is a circuit diagram showing details of a redundant program enable circuit of the semiconductor memory device of the present invention shown in FIG.

[Explanation of symbols]

1, 1-0 to 1-n ... Redundant program circuit, 2, 2-
1, 2-2 ... Switching circuit, 2-9 ... Power supply, 2-10,
2-18 ... Fuse, 2-11, 12-8 to 12-10
... Inverter, 2-12, 12-11, 12-12 ... Reset terminal, 2-13, 2-14, 12-1 to 12-4
... FET, 2-15 ... Node, 2-17 ... PMOS transistor, 2-20 ... Multiplexer, 2-21, 2-
22 ... enable signal and program signal, 2-25
... enable signal 3, 3-0 to 3-n ... redundant memory cell selection circuit, 4 ... row decoder, 5 ... column decoder, 6 ... memory cell, 7 ... row redundant memory cell, 8 ... column redundant memory cell, 9 ... Sense amplifier, 10 ... Input / output circuit, 11, 11
??? ... Redundant memory cell selection section, 12 ... Redundant program enable circuit, 21-0 to 21-n ... Signal line, 22 ... Address input terminal.

Claims (3)

[Claims] 1. A redundant address program means for assigning an address of a defective memory cell to a redundant memory cell, and a redundant address program means provided corresponding to the redundant address program means, when the address assigned by the redundant address program means is designated. In a semiconductor memory device having redundant memory cell selecting means for selecting a redundant memory cell and repairing a defective memory cell by replacing the defective memory cell with the redundant memory cell, when the replaced redundant memory cell is defective, A switching means for switching the correspondence of the redundant address program means to the redundant memory cell selection means to a new redundant memory cell selection means and deactivating the function of the previously corresponding redundant memory cell selection means. A semiconductor memory device characterized by: 2. The switching means switches the redundant address program means to a new redundant memory cell selecting means, and the function of the old redundant memory cell selecting means is inactivated by fuse cutting. The semiconductor memory device according to claim 1. 3. A redundant address program means for allocating an address of a defective memory cell to a redundant memory cell, and the redundant address program means provided corresponding to the redundant address program means, when the address allocated by the redundant address program means is designated. In a semiconductor memory device having redundant memory cell selecting means for selecting a redundant memory cell and repairing a defective memory cell by replacing the defective memory cell with the redundant memory cell, when the replaced redundant memory cell is defective, A semiconductor memory device comprising redundant address program selection means for deactivating the function of the redundant address program means.