JP2002510162A - Transport stream remultiplexer with video program - Google Patents

Abstract

(57) [Summary] A transport packet is output in a timely manner using a descriptor-based system (122, 124, 129-4), and the descriptor and transport packet caching techniques (116, 122, 124, 114), the synchronous transmission / reception of the transport packet is separated from any asynchronous processing (160, 120, S2, 402, S4, 404), and the scramble / descramble control word (129-9) is used by using the descriptor. ), Replacing null transport packets with transport packet data, thereby optimizing the bandwidth of the transport stream, and using a technique (180) to generate multiple internal reference clock generators (180). 113) to lock the data (TS1 to TS5, TS1) on which the video program is loaded. How to re-multiplexing ～TS20) and a system (30, 30 ', 100, 100', 100 '', 100 ''').

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD [0001] The present invention relates to a communication system. In particular, the invention relates to selectively multiplexing a bitstream containing one or more programs, such as a real-time audio-video program. The program-specific information and other program-related information are adjusted so that the receiving side of the bitstream can identify, extract, and reproduce the program in real time.

2. Description of the Related Art Recently, techniques for efficiently compressing a digital audio video program for storage and transmission have been proposed. For example, ISO @ IEC IS13818-
1,2,3: Information technology-Generic coding of video and related audio information: system, video, audio ("MPEG-2"); ISO @ IEC IS11
172-1, 2, 3: Information Technology-Generic encoding of moving pictures and associated audio for digital storage media at about 1.5 Mbit / s or less: system, video, audio ("MPEG-1"); Dolby AC -3; see Motion JPEG, etc. As used herein, the term program refers to a collection of related audio-video signals having a common time base for the purpose of synchronizing presentations according to MPEG-2 terminology.

[0003] MPEG-1 and MPEG-2 allow streams to be classified hierarchically. That is, the audio-video program may include one or more encoded bitstreams, or "elementary streams"("ES") (eg, encoded video ES and encoded audio ES), second language encoding Audio ES,
It consists of closed caption text ES. Each ES, especially each of the audio ES and the video ES, is separately encoded. Next, the encoded ESs are combined into a system layer stream such as a program stream “PS” or a transport stream “TS”. The purpose of the PS or TS is to perform the extraction of the coded ES of the program, the separation and separate decoding of each ES, and the presentation synchronization of the decoded ES. TS or PS is
It is further encapsulated in a higher channel layer or storage format, which allows forward error correction.

[0004] The elementary stream audio ES is generally encoded at a constant bit rate, for example 384 kbps. On the other hand, Video ES uses MPEG-1 at a variable bit rate.
Alternatively, it is encoded by MPEG-2. This means that the number of bits per compressed / encoded video varies from video to video (the videos are presented or displayed at a constant rate). Video coding involves spatially coding and temporally coding a video image. The spatial encoding includes discrete cosine transform, quantization, (zigzag) scanning, run-length encoding, and variable-length encoding of a block of luminance pixel data and chrominance pixel data. Temporal coding uses macroblocks (
For example, the motion of the luminance block and the respective color difference blocks in a 4 × 4 array are estimated), motion vectors are specified, and these macro blocks are motion compensated to form a prediction error macro block. The prediction error macroblock is spatially coded, and the motion vector is variable-length coded. Some pictures, called I-pictures, are only spatially coded, while other pictures, such as P and B pictures, are both spatially coded and motion compensated coded (ie, , Temporally predicted from other videos). A coded I video has more bits than a coded P video, and a coded P video generally has more bits than a coded B video. In any case, the coded video of the same type tends to have a different number of bits.

[0005] MPEG-2 defines a buffer size constraint for the coded video ES. In particular, the decoder is considered to have a buffer with a defined maximum storage capacity. The coded video ES must not cause the decoder buffer to overflow (in some cases, it must not cause the decoder buffer to underflow). MPEG-2 compresses each video in terms of the bit rate of the video ES, the video display speed, and some video ordering constraints imposed (from the reference video when the video was predicted) to be able to decode the predicted video. The time to remove data from the decoder buffer is specified in detail. Given such restrictions, if the number of bits generated during video compression is adjusted (at a pace of about one macroblock), the buffer of the video ES will not underflow or overflow even in this video ES. It can be ensured that it does not occur.

Transport Stream The present invention is illustrated herein for a TS. For brevity, the discussion of PS is omitted. Nonetheless, one of ordinary skill in the art will recognize that some aspects of the invention apply to PS.

The data of each ES is made into a variable length program elementary stream, that is, a “PES” packet. A PES packet contains data dedicated to a single ES, but may also contain data for more than one decoding unit (eg,
Two or more compressed videos, two or more compressed audio frames, etc.). In the case of TS, the PES packet is first divided into several payload units and inserted into a fixed-length (188-byte length) transport packet. Each transport packet may carry only one type of payload data (eg, PES packet data for only one ES). Each TS has a 4-byte header containing the packet ID or "PID". The PID is similar to a tag that uniquely indicates the content of a transport packet. Therefore, one PID is designated as a video ES of a specific program, and another different PID is designated as an audio ES of a specific program.

[0008] The ES of each program is encoded for a single encoder system time clock. Similarly, the decrypted and synchronized presentation of the ES
Furthermore, it is synchronized with respect to the same encoder system time clock.
Therefore, the decoder must be able to decode each ES and restore the original encoder system time clock so that each decoded ES can be presented in a timely and mutually synchronized manner. Must. For this purpose,
The time stamp of the system time clock (called the program clock reference or "PCR") is inserted into the payload (specifically, the adaptation field) of the selected transport packet. The decoder extracts PCRs from the transport packets and uses these PCRs to restore the encoder system time clock. The PES packet may include a decoding timestamp or “DTS” and / or a presentation timestamp or “PTS”. The DTS indicates the time at which the next decoding unit (ie, compressed audio frame, compressed video image, etc.) will be decoded, relative to the restored encoder system time clock. PTS is
The time at which the next presentation unit (ie, restored audio frame, restored video image, etc.) is presented or displayed is shown relative to the restored encoder system time clock.

A TS, unlike a PS, may have a transport packet that carries program data for two or more programs. Each program may have been encoded by a different encoder for a different encoder system time clock.
The TS allows the decoder to revive a particular system time clock of the program for which the decoder seeks to decode. For this purpose, the TS needs to carry a separate set of PCRs, i.e. a set of PCRs, to restore the encoder system time clock of each program.

[0010] Further, the TS carries information unique to a program, that is, (PSI) in a transport packet. The PSI is for specifying a desired program or data of other information to help decode the program. The program association table carried in the transport packet, ie, "PAT" is PID0x
0000. The PAT correlates each program number with the PID of the transport packet that carries the program definition for this program. The program definition (1) indicates which ES constitutes the program corresponding to the program definition, (2) specifies the PID for each of these ESs, and (3) carries the PCR of this program. Indicates the PID of the transport packet, and (4) E
It identifies the S-specific entitlement control message (eg, decryption key) and the PID of the transport packet carrying other information. All program definitions for a TS are collectively called a program mapping table (PMT). Therefore, the decoder extracts the PAT data from the transport packet,
Using the AT, the PID of a transport packet carrying the program definition of a desired program can be specified. Next, the decoder extracts the program definition data of the desired program from the transport packet, and identifies the PID of the transport packet carrying the ES data constituting the desired program and the PID of the transport packet carrying the PCR. be able to. Next, using these identified PIDs, the decoder can extract the ES data of the ES of the desired program and the PCR of this program from the transport packets of the TS. The decoder restores the encoder system time clock from the PCR of the desired program, and presents the ES data to the restored encoder system time clock from time to time.

[0011] Other types of information optionally provided in the TS include an entitlement control message (ECM), an entitlement management message (EMM), a conditional access table (CAT), and a network information table (NIT). (CAT and NIT
Is also the type of PSI). The ECM is an ES-specific message that controls the ability of the decoder to decode the ES that the ECM involves. For example, the ES may be encrypted, and the decryption key or control word is the ECM. The ECM associated with a particular ES is included in the ECM's own transport packet and marked with a unique PID. In contrast, the EMM uses a set of decoders, which are in a system called a "conditional access system,"
This is a system-wide message that controls the performance of decoding a part of. EMM is
It is included in the transport packet of the EMM itself and is marked with a PID specific to the conditional access system with which the EMM is involved. Whenever there is an EMM, a CAT is provided to enable the decoder to locate the EMM of the conditional access system to which the decoder belongs (ie, that of the set of decoders into which the decoder is a component). I have. NIT stores various network parameters. For example, at different carrier frequencies to which the decoder receiver can tune, multiple T
When modulating S, the NIT can indicate on which carrier frequency (for the TS carrier) each program is to be modulated.

[0012] Like video ES, MPEG-2 requires that the TS be decoded by a decoder having a TS buffer of a defined size that stores the program ES and PSI data. MPEG-2 also defines the rate at which data flows to and from the buffer. Most importantly, MPEG-
No. 2 requires that the TS not cause overflow or underflow in the TS buffer.

Further, in order to prevent buffer overflow or underflow,
MPEG-2 requires that the data transported from the encoder to the decoder be subject to constant end-to-end delays and that proper programming and ES bit rates be maintained. Furthermore, in order to ensure that the ES can be decoded and presented in a timely manner, the relative arrival time of the PCR to the TS should not vary too much from the relative time indicated by such a PCR. Stated another way, each PCR indicates the time taken by the system time clock (resurrected at the decoder) when the last byte containing a portion of the PCR is received. Therefore, the reception time of successive PCRs should correlate with the time indicated by each PCR.

Remultiplexing It is often preferable to “remultiplex” the TS. Remultiplexing adds transport packets to the TS, removes transport packets from the TS,
The content of the TS is to be selectively modified, for example, by rearranging the order of the transport packets in the TS and / or modifying the data contained in the transport packets. For example, it is sometimes preferable to add a transport packet containing a first program to a TS containing another program. Such an operation requires more steps than simply adding transport packets of the first program. At least, PAT
PSI such as PMT and PMT must be modified to properly refer to the content of the TS. Nevertheless, the TS must be further modified to maintain a constant end-to-end delay for each program carried in the TS.
Specifically, the bit rate of each program must not change so that no underflow or overflow occurs in the TS or the video decoder buffer. In addition, any temporal inconsistencies that may lead to the PCR of the TS, for example as a result of changing the relative spacing / reception rate of successive transport packets carrying the PCR of the same program, must be eliminated.

The prior art has proposed a remultiplexing device for MPEG-2 TS. The proposed remultiplexing device is a high-performance dedicated multiplexer that can completely synchronize between the point receiving each incoming TS to be remultiplexed and the point outputting the final remultiplexed output TS. Hardware. That is, a single system time clock controls and synchronizes the reception, buffering, modification, transfer, reassembly, and output of transport packets. Although such remultiplexers can remultiplex TSs, the architecture of the remultiplexer is complex and requires a dedicated uniform synchronization platform.

It is an object of the present invention to provide a flexible re-multiplexing architecture that can for example reside on any (possibly asynchronous) platform.

TS that carries a single program by compressing the video and audio of the single program
Is known in the art. As noted above, MPE
G-2 imposes very strict constraints on the number of bits in the video decoder buffer at any one time and the bit rate of the TS. It is difficult to encode the ES, especially the video ES, and to keep this bit rate completely constant from time to time. More properly, the ES encoder must allocate some overhead bandwidth to each program as a result of generating an unexpected and significant amount of coding information to ensure that ES data is not dropped. In contrast, program encoders often do not output any encoded program data at a particular transport packet time slot. This is because the program encoder has reduced the number of bits output at that time to prevent overflow of the decoder buffer. Alternatively, this may occur because the program encoder unexpectedly requires a longer number of hours to encode the ES, and therefore no data is available at the time. To maintain the TS bit rate and prevent TS decoder buffer underflow, null transport packets are inserted into transport packet time slots.

[0018] The fact that a null transport packet is in the TS to be remultiplexed is often simply a constraint that needs to be accepted. It is an object of the present invention to optimize the bandwidth of a TS containing null transport packets.

[0019] Occasionally, TS or ES data is transferred over an asynchronous communication link. It is an object of the present invention to "re-time" the above non-timing data or asynchronous transfer data. It is a further object of the present invention to minimize the jitter of transport packets sent from the asynchronous communication link by timing the transmission of such transport packets.

Further, it is an object of the present invention to allow the user to dynamically change the content re-multiplexed in the re-multiplexed TS, ie without stopping the flow of transport packets to the output re-multiplexed TS. To make changes in real time.

A further object of the invention is to distribute the remultiplexing function over a network. For example, a communication network that is asynchronous (eg, Ethernet LAN)
The purpose is to place the source of one or more TSs or ESs at any node of the network and to place the remultiplexer at another node of such a network.

SUMMARY OF THE INVENTION These and other objects are achieved by the present invention. One exemplary application of the present invention is to remultiplex one or more MPEG-2 compliant transport streams (
TS). A TS is a bitstream that contains one or more compressed / encoded audio / video program data. Each TS is formed as a series of fixed length transport packets. Each compression program includes data for one or more compressed elementary streams (ES), such as digital video signals and / or digital audio signals. These transport packets also carry the program clock reference (PCR) for each program. These PCRs are encoder system time clock timestamps that synchronize the decoding and presentation of the respective programs. Each program has a predetermined bit rate and is to be decoded by a decoder having a video decoder buffer and a TS buffer of a predetermined size. Each program is encoded in such a way as to prevent overflow and underflow of these buffers. Information specific to the program (PSI)
By way of example, it may also be carried in selected transport packets of the TS to assist in decoding the TS.

According to one embodiment, the remultiplexing node comprises one or more adapters, each adapter having a cache, a data link control circuit connected to the cache, and a direct memory access circuit connected to the cache. Includes An adapter is a synchronous interface that has a specific function. The data link control circuit has an input port for receiving the transport stream and an output port for sending the transport stream. The direct memory access circuit can be connected to an asynchronous communication link with variable end-to-end communication delay, such as a bus for a remultiplexing node. With an asynchronous communication link, the direct memory access circuit can access the memory of the remultiplexing node. This memory can store one or more queues at a descriptor storage location, such as a queue designated for an input port and a queue designated for an output port. In addition, the memory may also store transport packets at transport packet storage locations pointed to by descriptors stored in such descriptor storage locations of each queue. Illustratively, the remultiplexing node includes a processor (connected to the bus described above) that processes transport packets and descriptors.

When inputting a transport stream using the adapter, the data link control circuit keeps an unused descriptor in one of a series of descriptor storage locations of a queue assigned to the input port. Assigned to each received transport packet. This assigned descriptor is at the descriptor location where control was gained by the cache. The data link control circuit accumulates each retained transport packet at the transport packet storage location pointed to by the assigned descriptor and controlled by the cache. The direct memory access circuit gains control of one or more unused descriptor locations in the queue in memory after the last descriptor location already gained control by the cache. In addition, the direct memory access circuit also gains control of the transport packet storage location pointed to by the above descriptor in one or more descriptor storage locations in memory.

When using the adapter to output a transport packet, the data link control circuit retrieves from the cache each descriptor in a series of descriptor locations in the queue designated for the output port. These descriptors are retrieved sequentially from the beginning of the series of descriptor locations. Further, the data link control circuit also fetches the transport packets stored in the transport packet storage location pointed to by these fetched descriptors from the cache. The data link control circuit outputs each extracted transport packet to a unique time slot of the transport stream output from the output port (ie, one transport packet per time slot). The direct memory access circuit may, after the last cached descriptor location in this series of descriptor locations, store the descriptor of the specified queue at the output port in the location. From the cache storage memory. Further, the direct memory access circuit also obtains each transport packet stored at the transport packet position indicated by the obtained descriptor.

According to another embodiment, (in addition to) each descriptor is used to indicate whether a transport packet is received at an input port at a reception timestamp or at which time a transport packet is sent from an output port. Is recorded. If a transport packet is received at the input port, the data link control circuit records the reception timestamp in the descriptor assigned to each transport packet received and retained, thereby:
The time at which each transport packet was received is indicated. These descriptors are kept in the receiving order in the receiving queue. When outputting a transport packet from the output port, the data link control circuit outputs
Each descriptor is fetched sequentially, and the transport packet pointed to by each fetched descriptor is also fetched. At the time corresponding to the dispatch time recorded in each retrieved descriptor, the data link control circuit assigns, in time slots of the output transport stream corresponding to the dispatch time recorded in the retrieved descriptor, respectively Send the fetch transport packet pointed to by the fetched descriptor.

By way of example, the processor of the remultiplexing node examines each descriptor in the receive queue and other queues containing descriptors pointing to the transport packets to be output. The processor allocates a descriptor (if any) for the transmit queue associated with the output port to which the transport packet pointed to by each examined descriptor is sent. The processor specifies, for example, the time of reception of the transport packet indicated by the descriptor and the dispatch time determined by the internal buffer delay between the reception and output of the transport packet in the assigned descriptor of the transmission queue. Further, the processor orders the descriptors of the transmit queue in order of increasing dispatch time.

A unique PCR normalization process is also performed. The processor schedules each transport packet to be output in a time slot at a specific dispatch time corresponding to a predetermined delay of the remultiplexing node. If the scheduled transport packet contains a PCR, the PCR, if there is any drift, is based on the drift of the local reference clock (s) and the system time clock from which the PCR was generated. Tuned for the program. The data link control circuit transmitting the transport packet carrying the PCR thus adjusted is based on the difference between the scheduled dispatch time of the transport packet and the actual time when the time slot occurs relative to the external clock. Then, each adjusted PCR time stamp is further adjusted.

By way of example, if two or more transport packets are output in the same time slot, each such transport packet is output in another consecutive time slot. The processor calculates an approximate adjustment value for each PCR in a transport packet scheduled to be output in one time slot other than a time slot determined using a predetermined delay. This approximate adjustment value is based on the output time difference between the time slot actually scheduled by the processor to output the transport packet carrying the PCR and the time slot determined by the predetermined delay. The processor adjusts the PCR according to the estimated adjustment value.

According to one embodiment, these descriptors are also used to control the encryption or decryption of transport packets. In the case of decryption, the processor defines one or more series of processing steps to be performed on each transport packet and orders the decryption processing within this series of processing steps. The processor stores control word information related to the content of the transport packet in the control word information storage location of the assigned descriptor. The data link control circuit is
A descriptor is assigned to each received and retained respective transport packet, each of which includes one or more processing indicators and a storage location for control word information. The data link control circuit sets one or more of the processing indicators of the assigned descriptor so that processing of the next stage in the series of processing steps is performed for each of the assigned descriptors. Indicate that A descrambler is provided to sequentially access each assigned descriptor.
If the processing indicator of the accessed descriptor is set to indicate that the decryption operation is to be performed on the accessed descriptor (and the transport packet pointed to by the accessed descriptor), The rambler processes the descriptor and the transport packet pointed to by the descriptor. Specifically, if the descriptor points to a transport packet that is to be decrypted, the descrambler
The transport packet is decrypted using the control word information in the accessed descriptor.

The descrambler may be located on the (receiving) adapter, in which case after processing by the data link control circuit (eg, assigning descriptors, recording reception time, etc.), except for direct memory access Circuit processing (for example,
Before the transfer to the memory, the descrambler process is performed. Alternatively, the descrambler may be another device connected to the asynchronous communication interface, in which case after processing by the direct memory access circuit, but by processing by the processor (e.g., approximate calculation time calculation, PID Before remapping)
A descrambler process is performed. In each case, the control word information is the base address of a PID indexable control word table maintained by the processor.

In the case of encryption, the processor determines one or more series of processing steps to be performed on each transport packet and orders the encryption process within this series of processing steps. The processor assigns the transmission descriptor of the transmission queue to each transport packet to be transmitted, and stores the content of the transport packet in the control word information storage position of the selected descriptor among the allocated descriptors. Store the relevant control word information. The processor then sets one or more of the descriptor's processing indicators to indicate that processing of the next stage in this series of processing steps will be performed on each of the assigned descriptors. . A scrambler is provided for sequentially accessing each assigned descriptor. The scrambler
Processes each accessed descriptor and the transport packet pointed to by the accessed descriptor, but sets the processing indicator of the accessed descriptor so that the encryption process Such processing is performed only if it indicates that it is to be performed on the descriptor (and the transport packet pointed to by the accessed descriptor). Specifically, the accessed descriptor is
When indicating the transport packet to be encrypted, the scrambler encrypts the transport packet indicated by the accessed descriptor using the control word information in the accessed descriptor.

The scrambler may be located on the (transmit) adapter, in which case after processing by the direct memory access circuit (eg, transfer from memory to cache), but by the data link control circuit Before (e.g., output in an appropriate time slot, final PCR correction, etc.), a scrambler process is performed. Alternatively, the scrambler may be another device connected to the asynchronous communication interface, in which case after processing by the processor (e.g., transmission queue descriptor assignment, dispatch time designation, PCR correction, etc.) However, the scrambler process is performed before the process by the direct memory access circuit. This control word information may be the base address of a PID indexable control word table maintained by the processor, as in the case of decryption. However, preferably, this control word information is the control word itself used to encrypt the packet.

Further, according to one embodiment, a method is provided for retiming data carrying a video program received over a synchronous communication link. Asynchronous interfaces (eg, Ethernet interface, ATM interface, etc.)
Connected to the processor of the remultiplexing node (eg, over a bus) to receive a bitstream carrying the video program from a communication link with variable end-to-end transmission delay. The processor determines a time at which each of the one or more received packets carrying data of the same program of the received bitstream appears at the output TS based on a plurality of timestamps of the program carried in the received bitstream. A synchronization interface, such as a transmission adapter, selectively sends selected transport packets carrying the received data to the output TS with a fixed end-to-end delay at a time determined by the above determined time.

Illustratively, the memory of the remultiplexing node accumulates in a receive queue packets containing data received from the received bitstream. The processor is
A first and a second containing a continuous time stamp of a program in the receive queue
Each packet containing the data of the program stored between the specific packets is identified. The processor determines a (transport) packet rate of the program based on a difference between the first time stamp and the second time stamp. The processor sets the transmission time specified by the first specific packet to the product of the (transport) packet rate and the offset of the identification packet from the first packet, as a transmission time, and calculates the transmission time. Specify for each identification packet.

[0036] Yet another embodiment provides a method for dynamically and uniformly changing remultiplexing according to changes in user specifications. An interface, such as a first adapter, selectively extracts only specific ones of the transport packets from the TS according to the initial user specifications for the remultiplexed TS content. A second interface, such as a second adapter, uses the extracted transport packet (and the PS
Among the transport packets containing I, the selected transport packet is reassembled to produce an output remultiplexed TS. Further, the second adapter is
The reassembled remultiplexed TS is output as a continuous bit stream. The processor may include one or more new users for the remultiplexed TS content specifying one or more of (I) different transport packets to be extracted and / or (II) different transport packets to be reassembled. While receiving the specification dynamically, the first and second adapters extract and reassemble the transport packets and output the remultiplexed TS. In response, the processor
The first and second adapters dynamically stop extracting or reassembling transport packets according to the initial user specifications without interrupting the output remultiplexing transport stream, and extract the transport packets according to the new user specifications. Alternatively, reassembly is started dynamically. For example, the processor may generate a substitute PSI referring to a different transport packet, as per the new user specification, for reassembly by the second adapter.

By way of example, using this uniform re-multiplexing modification technique, the appropriate ES information for that selected program is automatically rewritten, despite some changes in the ES structure of that program. , Output remultiplexing TS can always be reliably output. A controller may be provided that creates a user specification that indicates that one or more programs of the input TS are to be output on the output TS. The first adapter constantly captures the program definition of the input TS. The processor constantly determines from this captured program definition which elementary streams make up each program. The second adapter outputs each transport packet including the ES data of each ES determined to constitute each program to the output TS. In this case, each program outputs the output TS
Is output without interruption. Therefore, even if the PID (number or numerical value) of the ES constituting each program changes, the proper and complete ES data for each program is always output to the output TS.

According to yet another embodiment, a method is provided for optimizing the bandwidth of a TS into which null transport packets have been inserted. The first interface (adapter) receives a TS at a predetermined bit rate, and the TS includes a transport packet carrying variable compressed program data and one or more null transport packets. If none of the transport packets carrying this compressed program data can be used in the receiving TS for insertion into the respective transport packet time slot, a null trans- Each port packet is inserted into a time slot of the receiving TS. The processor selectively replaces one or more of the null transport packets with another transport packet that carries data to be remultiplexed. Transport packets carrying such replacement data include PSI
It may also contain data or bursty transaction data. The bursty transaction data does not have a bit rate or transmission latency requirement to constantly present information.

As an example, the processor extracts the selected transport packets from the transport packets of the received TS, and discards each unselected transport packet including each null transport packet. The selected transport packet is stored in the memory by the processor and the first adapter. As described above, the processor schedules each of the stored transport packets for output to the output transport stream at a time determined by the time at which each of the stored transport packets is received. The second interface (adapter) outputs each of the stored transport packets to a time slot that matches the schedule. If no transport packet is scheduled to be output in one of the time slots of the output TS, the second adapter outputs a null transport packet. Nevertheless, for the bandwidth occupied by null transport packets, the output TS is smaller than that of each input TS.

According to an additional embodiment, the bit stream carrying the compressed program data is
A method is provided for timely output over an asynchronous communication link. Synchronous interface (
Adapter) provides a bit stream containing transport packets. The processor specifies a dispatch time for each of the selected one or more of the transport packets, and maintains a predetermined bit rate of a program in which each of the selected transport packets carries data. In addition, an average waiting time is caused for each selected transport packet. At a time determined by each of these dispatch times, the asynchronous communication interface receives one or more commands and sends the corresponding selected transport packet approximately at the dispatch time to minimize jitter of the selected transport packet. To respond to those commands.

By way of example, these commands are generated as follows. The processor is
Put the send descriptor containing the above dispatch time into the send queue. The processor specifies the adapter of the remultiplexing node to use the transmit queue for the asynchronous interface. Each command is issued by the data link control circuit of the specified adapter when the dispatch time of these descriptors is equal to the time of the adapter's reference clock.

The use of various of these techniques can allow for network-distributed remultiplexing. The network includes one or more communication links and a plurality of nodes interconnected by these communication links to form a communication network. The destination node receives a first bitstream containing the data of one or more programs over one of these communication links. This first bitstream has a portion having one or more predetermined bit rates. The destination node can be said to be a remultiplexing node as described above, and in any case comprises a processor. The processor selects at least a portion of the received first bitstream for transmission, schedules to send a selected portion of the first bitstream, and selects the first bitstream. The selected part is output to the TS at a rate determined by a predetermined rate of the selected part of the first bit stream.

[0043] Alternatively, the communication links together form a shared communication medium. These nodes include a first set of one or more nodes that send one or more bitstreams over the shared communication medium and a second set of one or more nodes that receive the sent bitstreams from the shared communication medium. Divided into one or more nodes. The second set of nodes is:
A portion of the transmitted bitstream is selected and one or more remultiplexed TSs are sent as a bitstream containing these selected portions. Each of the transmitted remultiplexed TSs is different from the received bitstream of the transmitted bitstream. Selecting the first and second sets of nodes and selecting them according to one of a plurality of different signal flow patterns, including at least one signal flow pattern different from the topology of these nodes to the shared communication medium; Controller that allows a given node to interact with the bitstream over a shared communication medium
A node is provided.

Finally, there is provided a method for synchronizing reference clocks of respective circuits for transmitting and receiving transport packets in a remultiplexing system. The reference clock of each circuit that receives a transport packet indicates the time at which each transport packet is received by each circuit. The reference clock of each circuit that sends the transport packet indicates the time at which each transport packet is sent from each circuit. A main reference clock to which each of the reference clocks is synchronized is specified. The current time of the main reference clock is obtained periodically.
Each of the other reference clocks is adjusted by the difference between the respective time of the other reference clock and the current time of the main reference clock so that the time of each reference clock and the corresponding time of the main reference clock match. I have to.

Thus, the present invention provides a more flexible remultiplexing system. More flexibility increases multiplexing but still lowers overall system cost.

BEST MODE FOR CARRYING OUT THE INVENTION For clarity, the description of the present invention is divided into several sections.

FIG. 1 shows a basic remultiplexing environment 10 according to one embodiment of the present invention. Controller 10 provides instructions to remultiplexer 30 using, for example, any remote procedure call (RPC) protocol. Examples of RPCs that can be used include Digital Distributed Computing Environment Protocol (DCE) and Open Networking
There is a computing protocol (ONC). DCE and ONC allow client processes to execute subroutines locally on the same platform (eg,
Controller 20) or remotely on a different platform (
For example, a network protocol using a protocol stack that can be executed (within the remultiplexing device 30). In other words, the client process
Control commands can be issued by a simple subroutine call. The DCE or ONC process issues appropriate signals and commands to the remultiplexer 30 to perform the desired control.

The controller 20 may take the form of a computer, such as a PC compatible computer. The controller 20 comprises one or more Intel Pentis.
It includes a processor 21, such as an umII integrated circuit, a main memory 23, a disk memory 25, a monitor and keyboard / mouse 27, and one or more I / O devices 29, which are connected to a bus 24. The I / O device 29 includes a remultiplexing device 30
Any suitable I / O to interact with the remultiplexer 30 depending on the method of implementing
Device 29. Examples of such an I / O device 29 include an RS-422 interface, an Ethernet interface, a modem, and a USB interface.

The remultiplexing device 30 is implemented with one or more networked “black boxes”. In the following example of a remultiplexer architecture, the black box of the remultiplexer 30 may be a stand-alone PC compatible computer interconnected by a communication link such as an Ethernet, ATM, or DS3 communication link. For example, each of the remultiplexing apparatuses 30 includes an Ethernet network (10 BASE-T, 100 BASE-T, or 1000 BASE-T).
-T) which are interconnected by a standalone PC
One or more black boxes are included.

As shown in the figure, one or more TSs to be remultiplexed, ie, TS1,
TS2 and TS3 are received by the remultiplexing device 30. As a result of the remultiplexing operation of the remultiplexing device 30, one or a plurality of TSs, that is, TS4 and TS5 are output from the remultiplexing device 30. The remultiplexed TS (TS4 and TS5) illustratively includes at least some information (at least one transport packet) obtained from the input TS (TS1, TS2, TS3). At least one storage device 40,
For example, a disk memory or a server is also provided. The storage device 40 can generate a TS or data as the information to be input to be remultiplexed, and remultiplex the output TS (TS4 or TS5) using the remultiplexing device 30. Similarly,
The storage device 40 stores the TS information or data generated by the remultiplexing device 30, for example, transport packets extracted or copied from the input TS (TS1, TS2, or TS3), received by the remultiplexing device 30. Other information or information generated by the remultiplexing device 30 can be stored.

One or more data injection sources 50 and one or more data extraction destinations 60
Are also shown. The data injection source 50 and the data extraction destination 60 are themselves PC
Implemented as a compatible computer. However, the data injection source 50 is a camera,
It is also a device such as a video tape player, a communication demodulator / receiver, and the data extraction destination 60 is a display monitor, a video tape recorder, a communication modulator / receiver.
It may be a transmitter or the like. The data injection source 50 supplies TS, ES, or other data to the remultiplexing device 30 and outputs, for example, the output TS (TS4 and / or T4).
Remultiplexing is performed in S5). Similarly, the data extraction destination 60 is, for example, the input TS (TS
1, TS2, and / or TS3). The TS, ES, or other data extracted from TS3) is received from the remultiplexing device 30. For example, the input T to be remultiplexed
One data injection source 50 is provided to generate each of the S (TS1, TS2, TS3), and one data extraction destination 60 is provided to receive each output remultiplexed TS (TS4 and TS5).

The basic remultiplexing environment 10 is considered as a network. In such a case, in the basic remultiplexing environment 10, each “networked black box” of the controller 20, each data injection source 50, the storage device 40, the data extraction destination 60, and the remultiplexing device 30 is a communication network. Considered a node. Each node is connected by a synchronous or asynchronous communication link. Furthermore, the devices 20, 40, 50, 60 are separated from the remultiplexing device 30 merely for convenience. Alternatively, devices 20, 40, 50, 60 are part of remultiplexing device 30.

Remultiplexer Architecture FIG. 2 shows a black box or node 1 of the network of the remultiplexer 30.
00 (herein referred to as the "remultiplexing node" 100) shows the basic architecture. The particular remultiplexing node 100 shown in FIG.
It functions as a whole of the remultiplexing device 30. Alternatively, as can be seen from the following discussion, different portions of the remultiplexing node 100 can be distributed to separate nodes connected together by synchronous or asynchronous communication links. In yet another embodiment, a plurality of remultiplexing nodes 100 having the same architecture as shown in FIG. 2 are connected to each other via a synchronous or asynchronous communication link and can be programmed to work together. The latter two embodiments are referred to herein as network-distributed remultiplexers.

Illustratively, remultiplexing node 100 is a Windows NT compatible PC computer platform. Remultiplexing node 100 includes one or more adapters 110. Each adapter 110 is connected to a bus 130. Bus 13
0 is a PCI compatible bus as an example. The host memory 120 also has a bus 130
Connected to. Processor 1 such as an Intel Pentium II integrated circuit
60 is also connected to the bus 130. Note that the single bus architecture shown in FIG. 2 is a simplified representation of a more complex multiple bus structure.
Further, there may be two or more processors 160 that cooperate to perform the following processing functions.

By way of example, two interfaces 140 and 150 are provided. These interfaces 140 and 150 are connected to the bus 130, however, they are in fact connected directly to the I / O expansion bus (not shown) and An expansion bus is connected to bus 130 through an I / O bridge (not shown). The interface 140 is, by way of example,
An asynchronous interface such as an Ethernet interface. This also means that data sent through the interface 140 is not guaranteed to appear at any time, and may suffer from variable end-to-end delays. In contrast, interface 150 is a synchronous interface such as a T1 interface. The exchange on the communication link connected to the interface 150 is synchronized with the clock signal held on the interface 150. Data is sent through interface 150 at a particular time and is subject to a constant end-to-end delay.

FIG. 2 further illustrates that the remultiplexing node 100 may include an optional scrambler / descrambler (provided as an encryption / decryption device) 170 and / or a global positioning satellite (GPS) receiver. It also shows that 180 can be equipped.
The scrambler / descrambler 170 is for encrypting or decrypting data in a transport packet. The GPS receiver 180 receives a uniform clock signal for the purpose of synchronizing the remultiplexing node 100. The purpose and operation of these devices will be described in more detail below.

Each adapter 110 is a special type of synchronous interface. Each adapter 1
Reference numeral 10 denotes one or more data link control circuits 112, a reference clock generator 113, one or more descriptors and a cache 1 of transport packets.
14, optional scrambler / descrambler 115, one or more D
An MA control circuit 116 is provided. These circuits may be part of one or more processors. Preferably, these circuits use a finite state automaton, ie, one or more ASICs or gate arrays (PGAs).
, FPGA, etc.). The purpose of each of these circuits is described below.

The reference clock generator 113 is, for example, a 32-bit rollover counter that counts at 27 MHZ. Reference clock generator 11
3 is received by the data link control circuit 112.
Further, the processor 160 has direct access to the reference clock generator 113 as follows. Processor 160 includes reference clock generator 113
The current system time can be read from the I / O register. The processor 160 can load a specific value into this same I / O register of the reference clock generator 113. Finally, the reference clock generator 11
Processor 160 may set the reference clock generator's count frequency in an adjustment register so that 3 counts at some frequency within a particular range.

The purpose of the cache 114 is to temporarily store, during output from the adapter 110, the next one or more transport packets to be output, or the last one recently received by the adapter 10. One or more transport packets are temporarily stored. Using the cache 114, transport packets can be received and stored, or retrieved and output, with minimal latency (most notably, no transfer latency on the bus 130). Cache 114 also stores descriptor data for each transport packet. The purpose and structure of such a descriptor is described in further detail below. In addition, cache 114 also stores filter maps that can be downloaded and modified by processor 160 in normal operation. By way of example, cache 114 may also store control word information used in encryption or decryption, as described in more detail below. In addition to the processor 160, the cache 114 is accessed by a data link control circuit 112, a DMA control circuit 116, and an optional scrambler / descrambler 115.

As is well known, cache memory 114 may have duplicate or modified copies of data in host memory 120. Similarly, when needed, cache 114 should obtain a modified copy of any data in host memory, but need not have an old copy. The same is true for the host memory 120. An "ownership protocol" is used that allows only a single device, such as cache memory 114 or host memory 120, to modify the content of a data storage location at any one time. Here, it can be said that the control of the data storage position has been obtained when the cache memory 114 has the exclusive control for correcting the content of the data storage position. In general, the cache memory 114 gains control of the data storage location and a duplicate copy of the data stored in this storage location and modifies that copy, provided that the modified portion of the data is written to host memory. Is delayed until much later. Implicitly, when the cache memory writes data to a storage location in the host memory, the cache memory 114 relinquishes control over the host memory 120.

The DMA control circuit 116 is for transferring data of a transport packet and data of a descriptor between the host memory 120 and the cache 114. Once the DMA control circuit 116 stores a sufficient number of transport packets (and descriptors for those transport packets) in the cache 114, the data link control circuit 112 continuously outputs the transport packets. It can be possible to output to the TS (ie, to consecutive time slots). The DMA control circuit 116 can also gain control over a sufficient number of descriptor storage locations in the cache 114 and the packet storage locations to which these storage locations point. The DMA control circuit 116 obtains such control of the descriptor storage location and the transport packet storage location for the cache 114. This allows descriptors and transport packets to be received (ie, from consecutive time slots)
The descriptor storage location and the transport packet storage location can be constantly assigned to incoming transport packets.

The data link control circuit 112 is for receiving a transport packet from an incoming TS or sending a transport packet to an outgoing TS. When receiving transport packets, the data link control circuit 112 filters out only the selected transport packets received from the incoming TS as specified in the downloadable filter map (provided by processor 160). Hold. The data link control circuit 112 discards other transport packets. The data link control circuit 112 allocates the next unused descriptor to the received transport packet, stores the received transport packet in the cache 114, and transfers the received transport packet to the transport packet storage location indicated by the allocated descriptor. I do. Further, the data link control circuit 112 sets the reference time corresponding to the reception time of the transport packet to the reference clock generator 113.
Get from. The data link control circuit 112 records this time as a reception time stamp in a descriptor pointing to the transport packet storage location where the transport packet is stored.

When sending a packet, the data link control circuit 112 retrieves the descriptors for the outgoing transport packets from the cache 114 and decomposes their corresponding transport packets by the time of the reference clock generator 113, respectively. To the time slot of the outgoing TS that appears when it is approximately equal to the dispatch time indicated in the descriptor. Further, the data link control circuit 112 performs any final PCR correction of the output transport packets as necessary, and converts the PCRs indicated in these transport packets into the exact values of the transport packets in the output TS. Synchronize with the alignment line.

The processor 160 receives a control command from the external controller 20 (FIG. 1),
It is for sending commands to the adapter 110 and the interfaces 140 and 150 for the purpose of controlling them. In response to such an instruction, the processor 1
60 generates a PID filter map and downloads it to the cache 114 or modifies the PID filter map already in the cache 114 to selectively extract the desired transport packets. , Are used in the data link control circuit 112. Further, processor 160 generates a receive interrupt handler that processes each received transport packet based on its PID. The receive interrupt handler may cause the processor 160 to remap the PID of the transport packet, estimate the departure time of the transport packet, extract information in the transport packet for further processing, etc. . Further, by formulating and executing the transmit interrupt handler, the processor 160 properly orders the transport packets for output, generates a dispatch time for each transport packet, and generates a dispatch time for each transport packet. The PCR is roughly corrected and the PSI
Into the output TS. Processor 160 may also serve for encryption and decryption, as described in more detail below.

The host memory 120 is for storing transport packets and descriptors related to the transport packets. The storage locations of the host memory 120 are organized as follows. A buffer 122 is provided that contains a plurality of reusable transport packet storage locations used as a transport packet pool. The descriptor storage location 129 is organized to include multiple rings 12
Make 4 Each ring 124 has a starting storage address, or ring top 124-1.
, A series of descriptor storage locations 129 from the end storage address, i.e., the ring bottom 124-2. A ring 124 is provided for each outgoing TS sent from the remultiplexing node 100 and a ring 124 is provided for each incoming TS received at the remultiplexing node 100. Another ring 124 is provided, as described in more detail below.

The queue designates pointer 124-3 to the head of the queue (ie, the first used / allocated descriptor storage location 129 in the queue), and pointer 1
This is implemented in each ring 124 by designating 24-4 as the tail of the queue (ie, the last used / allocated descriptor storage location 129 in the queue). Descriptor storage location 129 is allocated to incoming transport packets, starting from unused / unallocated descriptor storage location 129 immediately after tail 124-4. The predicate storage location 129 for the outgoing transport packet starts at the descriptor storage location 129 pointed to by the head 124-3, and sequentially stores the tail 1
Until 24-4, it is removed from the queue. Whenever the descriptor at descriptor storage location 129 reaches the end of the ring 124-2, the assignment or retrieval of the descriptor from descriptor storage location 129 is performed at the top of the ring 124-1.
9 descriptors.

As shown in the figure, each descriptor stored in each descriptor storage location 129 has several fields 129-1, 129-2, 129-3, 129-4, 129-5.
129-6, 129-7, 129-8, 129-9 and 129-10. Briefly, the purpose of each of these fields is as follows. The field 129-1 is for storing a command attribute. The processor 160 uses the individual bits of the command attribute field to
0 transport packet transmission and descriptor data retrieval can be controlled.
For example, if the processor 160 presets one bit in the descriptor field 129-1 of the descriptor storage location 129 pointed to by the bottom pointer 124-2 of the ring 124, the descriptor storage location 129 indicated by the top pointer 124-1 Follows the descriptor storage location 129 pointed to by the bottom pointer 124-2.

The field 129-2 is for storing a software status bit. The software status bits are not accessed or modified by adapter 10 and, for purposes of
Can be used with

The field 129-3 indicates the number of bytes of a transport packet to be transmitted (188 bytes in general for an MPEG-2 transport packet,
When the descriptor points to a packet according to another transport protocol, i.e., "aggregate" and "distribution" that fragment the packet into multiple storage locations or assemble the packet from fragments stored in multiple packet storage locations Is supported to be set to a number that is larger or smaller than the above number of bytes).

Field 129-4 is for storing a pointer to the transport packet storage location corresponding to the descriptor. This is illustrated in FIG. 2 with an arrow pointing from the descriptor at location 129 in ring 124 to a particular location in transport packet pool 122.

The field 129-5 is for storing a reception time for a transport packet with reception or a dispatch time for an outgoing transport packet to be transmitted.

Field 129-6 is for storing various exceptions / errors that may have occurred. The use of bits in this field allows errors in the bus 130, errors in the data link of the communication link to which the data link control circuit 112 is connected, receipt of short or long packets (either shorter or longer than 188 bytes). ).

Field 129-7 is for storing status bits indicating various status aspects of the descriptor, such as whether the descriptor is valid or invalid (such as indicating an error packet). . For example, suppose that multiple devices need to process the descriptor and / or the packets that the descriptor points to one after another. In such a case, preferably four status bits are provided. The first two of these bits can be set to a value of 0, 1, 2, or 3. A value of 0 indicates that the descriptor is invalid. A value of 1 indicates that the descriptor is valid and will be processed by the last device that needs to process the descriptor and / or the packet it points to. A value of 2 indicates that the descriptor is valid and will be processed by the penultimate device that needs to process the descriptor and / or the packet it points to. A value of 3 indicates that the descriptor is valid and will be processed by the penultimate device that needs to process the descriptor and / or the packet it points to. The latter two bits indicate whether the descriptor has been moved from host memory 120 to cache 114, and whether the descriptor has completed processing at adapter 110 and is stored in host memory 120. Other status bits are provided, as described in more detail below.

The field 129-8 contains a transfer count indicating the number of bytes of the transport packet received.

Field 129-9 contains the scrambling / encryption / decryption /
For storing descrambling control words or other information. For example, the processor 160 may store the control word (encryption / decryption key) or base address in a table of control words stored in this field 129-9 in the cache 114.

Field 129-10 is for storing a scheduled approximate departure time, an actual departure time, or an actual reception time. As described in further detail below, this field is used by processor 160 to order incoming transport packets for output or to note the time of receipt of incoming transport packets.

By way of example, to receive a transport packet on a single input port,
One data link control circuit 112, one DMA control circuit 116, and one
One ring 124 is required, and one data link control circuit 112, one DMA control circuit 116, and one ring 124 are required to send a transport packet from a single output port. Descriptors stored in queues associated with input ports are referred to herein as receive descriptors, and descriptors stored in queues associated with output ports are referred to herein as transmit descriptors. As described below, the input and output ports shown above may be the input or output ports of the communication link to which the data link control circuit 112 is connected, or may be another port within the remultiplexing node 100. Interface 140 or 150
Input port or output port of the communication link. Adapter 110 is shown as having only a single data link control circuit 112 and a single DMA control circuit 116. This is for illustration only. That is, a plurality of data link control circuits 112 and DMA control circuits 116 can be provided on the same adapter 110. Alternatively or additionally, a plurality of adapters 110 are provided in the remultiplexing node 100.

Basic Transport Packet Reception, Remultiplexing, and Transmission Here, the basic operation of the remultiplexing node 100 will be considered. The operator has several choices on how to operate the remultiplexing node 100. In a first way of operating the remultiplexing node 100, the operator has two TSs (ie,
Assume that one wants to selectively combine the program information of TS1 and TS2) to create a third TS (ie, TS3). In this overview, it is assumed that the operator initially does not know what programs, ESs or PIDs are in the two TSs to be remultiplexed (TS1 and TS2). Further, TS1 is illustratively received at the first adapter 110, TS2 is illustratively received at the second adapter 110, and TS3 is illustratively at the third adapter 110 of the same remultiplexing node 100. Is sent from the adapter 110. Instead, as will be seen from the following description, TS1 and TS2 can be received at the same node or at different nodes, respectively, through a synchronous or asynchronous interface, and
Are transmitted to the third node through an optional network and are selectively combined to form TS3 at the third node.

The operation according to this method includes (1) inputting TSs to be remultiplexed (TS 1 and T
S2) Content information (program, ES, PAT, PMT, CAT, NIT
And their PIDs), (2) report the content information to the operator so that the operator can formulate the user specification, (3) receive the user specification, and output the remultiplexed TS ( TS3) and constructs the remultiplexed TS (TS) from the contents of the TSs (TS1 and TS2) to be remultiplexed according to the user specification.
3) can be summarized as building dynamically.

In order to be able to collect content information, the transport processor 1
60 allocates one receive queue to each of the first and second adapters 110 and causes those adapters to receive TSs (TS1 and TS2), respectively. TS
Initially, to collect the content of (TS1 and TS2), TS1 or TS2
The transport adapter 110 does not discard any transport packets. Accordingly, the processor 160 loads the filter map into the respective caches 114 of the first and second adapters 110 that receive the TSs (TS1 and TS2) so that each transport packet is retained and stored in the host memory 120. Will be transferred. As each transport packet of a TS (e.g., TS1) is received at its respective adapter 110, the data link control circuit 112 causes the next unused descriptor (in the descriptor location to be the tail 124 of the receive queue). -4 after the stored descriptor) is assigned to the incoming transport packet. The data link control circuit 112 stores each received transport packet in the transport packet storage location of the cache 114 indicated by the assigned descriptor.

The DMA control circuit 116 stores each transport packet in the host memory 120
And writes the descriptor data of the descriptor assigned to the transport packet to the respective descriptor storage location of the receive queue. Further, the DMA control circuit 116 may store the next few unassigned descriptor locations 129 in the receive queue (after the storage location of the series of descriptors 129 from which the DMA control circuit 116 had previously gained control). May obtain a copy of the descriptors stored in those locations, and control of the transport packet locations pointed to by these descriptors. Control of such unused and unassigned descriptors and transport packet locations is provided to cache 114 for use by data link control circuit 112 (ie, future transport packets received from TSI). Assignment).

After the DMA control circuit 116 writes i ≧ 1 transport packets and the data of the descriptors assigned to those transport packets to the pool 122 and the reception queue, the DMA control circuit 116 Causes an interrupt. As an example,
The number i is selected by the operator using the controller 20 and set by the processor 160. This interrupt causes processor 160 to execute the appropriate receive "PID" handler subroutine for each received transport packet. Alternatively, if another technique such as polling or timer-based processing is used, the receive PID handler subroutine for each received transport packet may be
60. For simplicity, the present invention is illustrated herein using an example of an interrupt. Referring to FIG. 3, the processor 160 illustratively includes each adapter 1 that receives or sends a TS during a remultiplexing session.
10 (or another device) has a set of PID handler subroutines. FIG. 3 shows a set of two types of PID handler subroutines, a set of receive PID handler subroutines and a set of transmit PID handler subroutines. Each DMA control circuit 116 generates an interrupt that is distinctly different so that processor 160 can determine which set of PID handler subroutines to use. In response to the interrupt by the DMA control circuit 116,
Processor 160 performs step S2, which causes processor 160 to look up the PID of each transport packet pointed to by the recently accumulated descriptor in the receive queue of interrupt adapter 110. For each PID, the processor 160
Examines a table of pointers to the receive PID handler subroutine 402 specific to the adapter 110 (or other device) that interrupted the processor 160.

Assume that the first adapter 110 receiving TS1 interrupts the processor 160. In this case, the processor 160 will consult a table of pointers to the receive PID handler subroutine 402 specific to the adapter 110 that received the TS (TS1). The table of pointers to the receive PID handler subroutine contains 8192 entries, including one entry indexed by each allowed PID (these PIDs have 13 bits according to MPEG-2). Each indexed entry has RIV0, RIV1,. . . ,
A pointer to RIV8191, or RIV0, RIV1,. . . , RIV
The address of 8191 contains a subroutine executed by the processor 160. Using the PID of each transport packet, processor 160
An entry in the table of pointers to D handler subroutine 402 is indexed to identify a pointer to a subroutine to be executed for a particular transport packet.

Each subroutine pointed to by each pointer and executed by the processor 160 is specifically mapped to each PID based on the pointer table 402 to realize a user specification. Each subroutine is advantageously predefined and simply mapped in the pointer table 402 according to user specifications. Each subroutine consists of a collection of one or more basic building block processes. Some examples of the basic building block process include: (1) PAT collection: Initially, this process is a subroutine pointed to by RIV0,
That is, it is included in the reception PID handler subroutine for PID 0x0000. When performing this process, processor 160 illustratively includes a PAT
Extract the portion carried in the currently processed transport packet
The AT part is loaded into the PAT stored in the memory. Note that multiple versions of PAT are used because the program carried in the TS may change from time to time. Processor 160 identifies different versions of the PAT,
A copy of each version of the AT is collected separately and stored in host memory 120.
Can be saved. Processor 160 can also identify at any time which version of the PAT is currently in use, based on information contained in various parts of the PAT. Further, processor 160 may use the information carried in each updated PAT portion to determine at that time the program number of the program carried in the TS, and the PMT portion or program definition for such a program number. Identify the PID. Using such a program number, the processor 160 uses the pointer table 4 for the received PID handler subroutine.
Modification of 02 allows the insertion of a pointer for the PMT (marked on the transport packet carrying the PMT portion) suitable for executing the subroutine containing the process of collecting the PMT portion or the program definition. (2) Collection of PMT part / program definition: In this process, the processor 160 fetches the PMT part or program definition contained in the currently processed transport packet, and retrieves the respective part of the PMT. Update with the data in the program definition or PMT part. Like the PAT, multiple versions of the PMT may be utilized, and the processor 160 may determine in which PMT the retrieved PMT portion or program-defined data should be stored. The processor 160 uses the PMT information to update the PID filter map used to discard transport packets of the program that should not be included in the remultiplexed TS, identify control words and decrypt the ES; P
P specified in the transport packet having the PID as specified by the MT
In some cases, a subroutine for processing the CR is selected. (3) PID remapping: This causes the processor 160 to overwrite the PID of the corresponding packet with another PID. This is preferable to guarantee the uniqueness of the PID designation. That is, MPEG-2 uses different content (eg,
Transport packets carrying data of different ESs, data of different PSI streams, etc.) are multiplexed and formed into the same output re-multiplexed TS and carried differently in such TSs. It is required that transport packets carrying content be marked with different PIDs. Otherwise, a decoder, or other device, would not be able to distinguish between transport packets carrying different types of data for retrieval, decoding, etc. T some PID
It can be used in S1 to mark the transport packet carrying the first type of data, and the same PID can be used in TS2 to mark the transport packet carrying the second type of data. . If the first and second types of transport packets are included in the output re-multiplexed TS (TS3), at least one of these two types of transport packets may be used to ensure uniqueness. It should be re-labeled with the new PID. (4) Transport Packet Discard: As the name implies, processor 160 simply discards the transport packet. To this end, processor 160 deallocates a descriptor pointing to the transport packet that is discarded. Descriptor deallocation is achieved by the processor 160 adjusting the set of descriptors in the queue's descriptor storage location 129 to remove the descriptor for the dropped transport packet (eg, , After the descriptor of the transport packet to be deleted in the ring 124, each of which goes to the descriptor storage space of the immediately preceding descriptor, all of its assigned descriptors are stored in the processor 16
0). When the descriptor is deallocated, a descriptor storage space 129 is created in the reception queue for reallocation. (5) PCR flag setting: The PMT indicates the PID of the transport packet carrying the PCR for each program. However, only a part of such a transport packet carries a PCR. This is easily determined by the processor 160 determining whether the appropriate indicator in the transport packet is set (adap in the transport packet header).
and a field_field_control bit and the PCR_
flag bits). If the processor 160 determines that there is a PCR, the processor 160 determines the attribute field 12 of the descriptor 129 associated with each packet.
Set the PCR flag bit in 9-1. The purpose of this attribute flag bit is
This will be described in more detail below. Further, the processor 160 calculates, as an example, the current drift of the reference clock generator 113 with respect to the encoder system time clock of the program using PCR as one sample. Drift is determined by the following formula: Drift = ΔRTS12−ΔPCR12 ΔRTS12 = RTS2-RTS1 ΔPCR12 = PCR1-PCR2 where ΔPCR12 is the difference between successive PCRs for this program and PCR2 is the currently processed PCR1 is the PCR received in the transport packet, PCR1 is the previously received PCR for this program, ΔRTS12 is the difference between successive receive timestamps, and RTS2 is the currently processed PCR containing PCR2. RTS1 is the previous reception time stamp for the transport packet containing the PCR1. After calculating this drift, PCR1 and RTS1 become PCR2 and RTS, respectively.
Set equal to S2. This drift is used to adjust the PCR (as needed) as described below. (6) Calculating the approximate calculated departure time: With this process, the processor 160 estimates the (ideal) departure time of the transport packet. Illustratively, this process is included in the receive interrupt handler for each incoming incoming transport packet that is remultiplexed into the outgoing TS. The approximate calculated transmission time can be calculated from the reception time of the transport packet (within the field 129-5) and the known internal buffering delay at the remultiplexing node 100. Processor 160 writes this expected departure time in field 129-10. (7) Insertion of scramble / descramble control word information: In general, in either the scramble technique or the descramble technique, in order to actually encrypt or decrypt data in a transport packet, an encryption key or a decryption key is used. A dynamically changing control word such as a decryption key is required. General scrambling and descrambling techniques use odd and even keys. With those techniques, one key is used to decrypt the ES data, and the next key used later is transferred to the TS at the same time. Next, a signal is sent indicating that the most recently transferred key should be used here. The scramble / descramble control word is either ES specific or used for a group of ESs (across the "conditional access system"). The descrambling or scrambling control word is stored in the PID indexable table of the remultiplexing node 100. As described in further detail below, processor 160 may insert the base address for the control word table, or the control word itself, into field 129-9 of the descriptor when performing this process.

Initially, processor 160 selects a PID handler and assigns each received TS
Collect the PATs of (TS1 and TS2) and then discard each processed transport packet. In the process of receiving the PAT, transport packets carrying other PSI (eg, program definition / PMT part, NIT, CAT
) And PIDs of other streams (for example, ES stream, ECM stream, EMM stream, etc.). Receive P for PID of PAT
The ID handler subroutine selects, for example, a reception PID handler subroutine that collects PMT, NIT, CAT, and the like. This allows such subroutines to be used, and is easily accomplished by simply changing the pointer of the entry in table 402 (indexed by the appropriate identifying PID) to point to the PID handler subroutine described above. Achieved. Note that such a simple PID handler subroutine selection process can be performed dynamically while the transport packet is received and processed for TS1 and TS2. This advantage is explained in more detail below.

Eventually, a sufficient amount of PSI is collected for each TS (TS1 and TS2) so that the operator can create a user specification of the information output to the remultiplexed TS (TS3). Processor 160 illustratively includes the collected PSI
The information is sent to the controller 20, for example, using the asynchronous interface 140. Sufficient information is sent to the controller 20 to select a user specification. This information is optional, eg, each TS indicating the program number contained in each TS.
Or a different kind of ES (represented by descriptive service specifications such as video, audio 1, secondary audio presentation, closed caption text, etc.). Alternatively, this information is exhaustive, including, for example, the PID of each program, the ECM of its ES, etc., and the controller 20 provides information to the operator in a consistent and useful manner. Only.

Using the provided information, the operator can output the TS to be remultiplexed (TS3
Create a user specification for). This user specification can specify: (1) program numbers in each TS (TS1 and TS2) that are retained and output to the remultiplexed TS (TS3); (2) retained or Or discarded retained program ES, (3) encrypt the decrypted and / or encrypted ES, ES group, program, or group of programs and respective ES, ES group, program, or group of programs. (4) any new ECM or EMM injected or included in the output remultiplexing TS (TS3); (5) automatically from the above selection Any new PSI information not included, eg,
NIT or CAT to be put in the outgoing TS (TS3), specific PIDs to be remapped, new PIDs to which those PIDs are remapped, generated at the remultiplexing node, and carried by the TS (TS3) PID designated for other information (eg, Bursty data, as described below), and the like. Next, the user specification is sent from the controller 20 to the remultiplexing node 100, for example, via the asynchronous interface 140.

The processor 160 receives the user specification and receives a PID handler for the appropriate PID of each received TS to be remultiplexed (TS1 and TS2).
Responds by selecting a subroutine. For example, for each PID marked on a transport packet containing data to be retained, processor 160 selects a subroutine in which the processor inserts a process that estimates its departure time. P marked on the transport packet containing the encrypted data
For each ID, processor 160 selects the subroutine that contains the process of selecting the appropriate control word and inserting it into the descriptor associated with such a transport packet. For each PID marked on the transport packet containing the PCR, the processor 160 can set a PCR flag and select a subroutine containing the process of calculating drift and the like. Dynamic adjustment of user specifications and / or PSI data is described in further detail below.

The processor 160 assigns a transmission queue to each device that sends the remultiplexed TS, that is, the third adapter 110 that outputs the TS (TS3). Further, the processor 160 loads the PID filter map into each cache 114 of the first and second adapters 110 that receives the TS (TS1 and TS2), along with the appropriate values, and outputs the same to the remultiplexed TS (TS3). Holding the transport packet described above,
The other transport packets containing I are held, the contents of TS1 and TS2 are recorded, and the other transport packets are discarded.

Select the receive PID handler subroutine, assign a transmit queue, and
In addition to loading the modified portion of the ID filter map, processor 160 illustratively selects a set of transmit PID handler subroutines for each adapter (or other device) that outputs the remultiplexed TS. . This is shown in FIG. The transmit PID handler subroutine is selected based on the PID and the transmit TS. As described above, reception of an identifiable interrupt (eg, output TS (eg, TS
In response to (3) sending from the data link control circuit 112 of the adapter 110), the processor 160 executes step S4. At step S4, the processor 160 proceeds to the receiving queue (and / or possibly another queue containing descriptors of transport packets not yet scheduled for output).
, And j descriptors indicating transport packets output from the interrupt adapter 110 are identified up to j ≧ 1. The number j may be illustratively programmable, and advantageously, the number k of transport packets sent from a particular adapter 110 sending an output TS while the particular adapter 110 interrupts the processor 160. Is set equal to

When executing the step S4, the processor 160 examines one by one the reception queue for the descriptor pointing to the transport packet destined for the specific output TS. Processor 160 examines a table of pointers to transmit PID handler subroutine 404 to determine which transport packets are destined for the output TS.
As in the case of the table 402, the table 404 stores each PID 0x0000-0.
Contains one entry for and indexed by x1FFF.
Each indexed entry has TIV0, TIV1,. . . , T
A pointer to IV8191, or TIV0, TIV1,. . . , TIV81
The subroutine executed in response to the address 91 and each PID is included. A table of pointers to the send PID handler subroutine 404 is:
With the user specifications received from the controller 20, it is formulated by the processor 160 and modified as described below.

The following is an exemplary process that can be combined into a transmit PID handler subroutine: (1) None: Remultiplexing TS of the device that issued the transmit interrupt to processor 160 (
Or, if no transport packet is currently output to another stream), the PID of such a transport packet maps to a subroutine that contains only this process. This process causes the processor 160 to simply skip the transport packet and the descriptor for the transport packet. The descriptor so examined is passed to the processor 160
Is not counted as one of the j transport packets output from the specific adapter 110 interrupted by. (2) Transmission order descriptor: If the current transport packet is to be output to the remultiplexing TS (or another stream) of the device that has issued the transmission interrupt to the processor 160, such a transport packet is output. Map to the subroutine containing this process (and possibly other processes). This process causes processor 160 to assign a transmit descriptor to this transport packet. Next, processor 160 copies the appropriate information in the receive descriptor pointing to this transport packet to the newly assigned transmit descriptor. The assigned transmit descriptor is then ordered in the correct order in the transmit queue for transmission (associated with the device that requested this interrupt). In particular, processor 160 calculates the approximate calculated departure time of the packet pointed to by the newly allocated descriptor and the actual dispatch time (the actual time at which the transport packet is sent) recorded in the other descriptors in the transmit queue. Compare. Preferably, this descriptor is placed before each descriptor in the transmit queue if the actual dispatch time is later than the approximate dispatch time for this descriptor, and the actual dispatch time is approximated for this descriptor. If it is earlier than time, it is placed after each descriptor. Such an insertion causes each transmission descriptor of the series of transmission descriptors when the actual dispatch time is later than the approximate calculated departure time of the descriptor to be inserted to be sequentially stored in the queue in the next descriptor storage location. 129 is achieved. The data of the assigned transmit descriptor can then be stored in a descriptor storage location 129 made available by copying the series of transmit descriptors. (3) Determining the actual dispatch time: The processor 160 can determine the actual dispatch time of the transport packet indicated by the assigned descriptor based on the approximate calculated transmission time of the transport packet. The actual dispatch time determines in which transport packet timeslot of the output remultiplexing TS (T3) the transport packet (to which the newly allocated and inserted transmit descriptor points) should be sent. Set by the thing. That is,
The transport packet time slot of this output remultiplexing TS (T3) is:
The one that is temporally closest to the above-mentioned approximate calculated departure time is selected. This transport packet is sent to the reference clock generator (s) 1 of adapter (s) 110 (which are mutually synchronized as described below).
It is considered that the data is output at the time of the selected transport packet time slot with respect to the internal reference time set at 13. The time associated with each transport packet time slot is specified as the actual dispatch time. Next, the actual dispatch time is stored in the field 129-5 of the transmission descriptor. As explained below, the actual dispatch time is actually determined by the data link control circuit 112 of the third adapter 110 (which outputs the remultiplexed TS (TS3)) by the corresponding transport packet for output. Is the approximate time to submit. The actual output time of the transport packet depends on the processor 1
As set by an external clock unknown to 60, the transport packet
Determined by time slot alignment. As a result of this misalignment, additional steps may be performed to eliminate PCR jitter, as described below. Consider that the bit rate of the TS from which the packet is sent (ie, TS1 or TS2) is different from the bit rate of the output TS (ie, TS3). Furthermore, these transport packets are buffered internally due to a predetermined delay (depending on the length of the receive queue and the transmit queue). Still, in the same transport packet time slot of the output remultiplexing TS (TS3), assuming that there is no contention between transport packets of different receiving TSs, all transport packets will be This results in almost the same waiting time. Since this average latency is the same, no jitter is introduced into these transport packets. Next, the two transport packets are sent to different TSs (ie, TS1 and T1).
From S2), received at about the same time and both transport packets are:
Consider the case where the data is output to the remultiplexing TS (TS3). Both transport packets may have different approximate calculated departure times, but their departure times still coincide with the same transport packet timeslot of the output remultiplexing TS (TS3) (most time-wise). near). The transport packet with the earliest approximate calculated departure time (or reception time) is designated for this time slot and the actual dispatch time for this time slot. Other transport packets are specified in the next transport packet time slot of the output remultiplexing TS (TS3) and the actual dispatch time of this time slot. Note that the latency introduced by the transport packet specified in the next time slot is different from the average latency invited by other transport packets of this program. Thus, the processor 160 takes action to eliminate the latency introduced by the transport packet, including, by way of example, adjusting the PCR of the transport packet (if the PCR is in the transport packet). . (4) PCR Drift and Latency Adjustment: This process is illustrative,
A subroutine is pointed to by the pointer of the table 404 indexed by the PID of the transport packet containing the PCR. Processor 160
Indicates that the transport packet is not specified in the transport packet time slot of the output remultiplexing TS (TS3) closest to the approximate calculated departure time of the transport packet (with respect to other transport packets of the program). It is determined that the adjustment of the PCR waiting time is necessary only when the PCR flag is set in each reception descriptor. PCR corrects for temporal displacement caused by assignment to non-ideal slots. This adjustment value is equal to a value obtained by multiplying the number of slots from the ideal slot required for moving the transport packet by the slot time.

Unless the input and output TSs are tightly aligned in time or the PCRs are received from an asynchronous communication link, all PCRs will drift as described below. adjust. In the former case, the drift of the internal clock does not affect the time for outputting the PCR. In the latter case, another drift adjustment is used, as described below. In all other cases, the time to output the received PCR is affected by the drift of the adapter 110 that received the transport packet and the reference clock generator 113 of the adapter 110 that transmits the transport packet, relative to the PCR program clock. Receive. That is, the reception time stamp obtained from the reference clock generator 113 is pressed on the transport packet containing the PCR. The received time stamp is used to determine the approximate calculated emission time and the actual dispatch time. As described in detail below, the transport packets are sent according to the actual dispatch time to the reference clock generator 113 on the adapter 110 sending the TS (TS3), and all the Reference clock generator 113 is kept in a synchronized state. However, the reference clock generators 113 are all synchronized with each other, but are subject to drift with respect to the transport packet and the encoder system time clock that generated the PCR. This drift can strongly affect the time to output each PCR from the remultiplexing node 100 to an output remultiplexing TS (eg, TS3).

According to the present invention, the remultiplexing node 100 corrects for such drift. As described above, part of the receive handler subroutine for PCR in each program is to keep the current measurement of drift. Encoder of each program
The drift measurement of the reference clock generator 113 with respect to the system time clock is maintained. For each PCR, the current drift for the PCR program (between the reference clock generator 113 and the encoder system time clock for this program) is subtracted from the PCR.

Using the above-described queue assignment, selection of the PID handler / subroutine, and modification of the PID filter map, remultiplexing is performed as follows. The transport packet of TS1 is received by the data link control circuit 112 of the first adapter 110. Similarly, the transport packet of TS2 is received by the data link control circuit 112 of the second adapter 110. The data link control circuit 112 in each of the first and second adapters 110 examines the local PID filter map stored in its cache 114 and selectively discards each transport packet having a PID, Indicates that this transport packet is not retained.
Each data link control circuit 112 retrieves the next unused / unassigned descriptor from cache 114 and determines the transport packet storage location associated with that descriptor. (As described above and below, the DMA control circuit 116
Is a set of one or more unused and unassigned next descriptors of the receive queue designated at the input port of the data link control circuit 112, and the transport packet storage locations to which those descriptors point. You are constantly in control. ) The next unused and unassigned descriptor is the tail pointer 129-4 (*
(Error of "124-4") comes after the descriptor stored in the descriptor storage location 129. The tail pointer 129-4 (* error of "124-4") can be used for the data link control circuit 112. (As described above, the tail pointer 129-4 (
* The error of "124-4" is the ring lower end address 129-2 (* "124-2").
), The tail pointer 129-4 (* "124-4")
), The command bit for the end of the descriptor ring is set by processor 160 in field 129-7. From this, the data link control circuit 112 determines that the ring upper end address 129-1 (* “124-1”
The descriptor stored in the descriptor storage location 129 is
Assigned using addressing techniques. This data link control circuit 112
Obtain the time of the reference clock generator 113 corresponding to the time of receiving the first byte of the transport packet, and store this value as the reception time stamp in the field 129-5 of its assigned descriptor. The data link control circuit 112 determines the number of bytes of the received transport packet in the field 129-
8 is stored. In addition, if any errors (eg, loss of the data link carrier of TS1, short packets, long packets, error packets, etc.) occur during the reception of the transport packet, the data link control circuit 112 may transmit 129
Setting the appropriate exception bit of -6 indicates such an error. next,
The data link control circuit 112 sets one bit in the status field 129-7 to indicate that the descriptor 129 has been processed or exceptionally processed, and the transport in the cache 114 pointed to by the pointer in the field 129-4. The transport packet is stored in the packet storage location. (In the case of long packets, a series of two or more unused and unassigned next descriptors is assigned to this received transport packet, and extra data is associated with such descriptors. Note that the appropriate set / dispersion bits may be set in the attribute field 129-1 of the first descriptor,
Indicates that this packet has more data than in the single transport packet storage space associated with this first descriptor. The corresponding bit is also set in the last descriptor attribute field 129-1 to indicate that the bit is the last descriptor of a multiple descriptor transfer. Such long packets typically occur when the adapter receives a packet from a stream other than the TS. )

The DMA control circuit 116 writes the transport packet to a corresponding transport packet storage location of the transport packet pool 122 in the host memory 120. Further, the DMA control circuit 116 also writes the descriptor data indicating the written transport packet to each descriptor storage location 129 of the reception queue designated for each adapter 110. The DMA control circuit 116 determines which descriptor sets the processing completion status bit in the field 129-7 and the storage location of the transport packet indicated by the descriptor, and writes which transport packet to the host memory 120. Note that it is possible to specify whether it should be included. Note that the DMA control circuit 116 can write the data one by one when the descriptor and the transport packet are completed, respectively. Alternatively, the DMA control circuit 116 can store a limited number of transport packets and descriptors. Next, the DMA control circuit 116 writes a series of i ≧ 1 plural completed descriptors and data of the transport packet.

In one embodiment, the scrambler / descrambler 115
0. In such a case, before the DMA control circuit 116 writes the data of the transport packet into the host memory 120, the scrambler / descrambler 115 decrypts each transport packet that needs to be decrypted. This is explained in more detail below.

When the DMA control circuit 116 writes the descriptor data and the transport packet into the host memory 130 (* error of “120”), the DMA control circuit 116 interrupts the processor 160. Such an interruption occurs when data is stored in the host memory 13.
It is woken up by the DMA control circuit 116 for every i ≧ 1 descriptor written to 0 (* error of “120”). Due to such an interrupt, the processor 160
One of the receive PID handler subroutines is executed for each transport packet that is unique to both the input TS and the input TS. As described above, the receive PID handler subroutine is selected by appropriately changing the pointers in the table 402 so that, among other things, the processor 160 discards transport packets that are not output to the remultiplexed TS and reduces the approximate calculated departure time. A descriptor indicating the transport packet to be output is written, and the PCR flag bit in the descriptor indicating the transport packet containing the PCR is set. Further, the selected receive PID handler subroutine preferably causes processor 160 to constantly collect and update PSI tables, adjust the PID filter map, and
If necessary, select additional receive PID handler subroutines to implement certain user specifications. For example, a user specification may specify that a particular program number be constantly output to a remultiplexed TS (TS3). Nevertheless, the ESs that make up this program are subject to change, especially to reach event boundaries. Preferably, processor 160 monitors for changes in the PAT and PMT to detect such changes in the ES structure and, if necessary, selects a receive PID handler subroutine to select the selected program. Regardless of the structure of the program, the ES of the program is constantly output to the remultiplexing TS (TS3).

At the same time, while performing the above functions related to the received transport packet, the DMA control circuit 116 and the data link control circuit 112 on the third adapter 110 also transmit the transport packet to the TS3. It also performs some functions related to sending to The data link control circuit 11 of the third adapter 110
Each time 2 outputs k ≧ 1 transport packets, the data link control circuit 112 causes a transmission interrupt. Illustratively, k is selected by processor 160. This transmit interrupt is received by processor 160, which executes the transmit PID handler subroutine appropriate for the output remultiplexing TS (TS3). In particular, processor 160 examines the descriptor of the head of each queue that contains a descriptor pointing to the transport packet output to TS3. As described above, the two receive queues include one receive queue related to the first adapter 110 (for receiving TS1) and one receive queue related to the second adapter 110 (for receiving TS2). And a descriptor indicating a transport packet output to TS3. As described below, the processor 160 may allocate an additional queue containing descriptors pointing to the transport packets output to TS3. Processor 160 identifies a descriptor pointing to the next j transport packets to be output to TS3. This is accomplished by executing a transmit PID handler subroutine of the set associated with the third adapter 110 and indexed by the PID of the transport packet in the head of the receive queue. As described above, if the transport packet corresponding to the descriptor in the queue examined by the processor 160 is not output from the third adapter 110 (which caused this interrupt), the PID of the transport packet is: Index the transmit PID handler subroutine for the third adapter 110 that does nothing. If the transport packet corresponding to the descriptor in the queue examined by the processor 160 is output from the third adapter 110 (which caused the interrupt), the PID of the transport packet transmits 1 pointer. Index the PID handler subroutine and have its transmit PID handler subroutine perform the following tasks: (1) assign a transmit descriptor to this transport packet; (2) associate with the third adapter 110 Order the transmit descriptors in the transmit queue in the proper transmit order, (3) specify the actual dispatch time for the assigned descriptors and transport packets, (4) if necessary,
A rough PCR correction is performed on the transport packet for the drift and the waiting time. By way of example, the processor 160 looks up the descriptors in the (receive) queue until j descriptors are identified that point to transport packets coming out of the TS3 or from the third adapter 110. These descriptors are
3 to tail 124-4 are examined in order. If multiple queues with candidate descriptors are available for inspection, the processor 160 may order the approximate calculated departure times or any other order that takes into account the contents of the transport packets pointed to by those descriptors as appropriate. (As described below), these queues may be examined in a round-robin fashion.

The DMA control circuit 116 fetches, from the host memory 120, data of a series of j ≧ 1 descriptors of the queue related to the TS3 or the third adapter 110. These descriptors are retrieved from the queue's descriptor storage location 129, in order from head pointer 124-4 to tail pointer 124-4. Further, the DMA control circuit 116 also fetches from the host memory 120 the transport packets at the transport packet storage locations of the pool 122 to which each such fetched descriptor points. The DMA control circuit 116 stores such retrieved descriptors and transport packets in the cache 114.

The data link control circuit 112 checks each descriptor (head pointer 1) in the transmission queue.
24-3), and the transport packets in the transport packet storage location indicated by the descriptor are sequentially fetched from the cache 114. When the time of the reference clock generator 113 of the third adapter 110 is equal to the time indicated in the dispatch time field 129-5 of the retrieved descriptor, the data link control circuit 112 transmits the descriptor (head pointer 124-3). The transport packet pointed to by (in the storage location pointed to by) is sent to TS3. This dispatch time is only an approximate transmission time since each transport packet must be sent aligned with the transport packet time slot boundary of TS3. Such boundaries are set with reference to an external clock unknown to processor 160. Furthermore, for the same reason, in the PCR of each transport packet,
Note also that there is likely to be some jitter. Therefore, the data link control circuit 112 finally corrects the PCR based on the exact transmission time of the transport packet containing the PCR. Specifically, this exact transmission time is less than the time lag of the transport packet from this estimate. The data link control circuit 112 uses the transport time slot boundary clock previously locked to the TS3 time slot boundary to finalize its approximate PCR (ie, dispatch time and actual transmission time). By adding to the PCR of the transport packet). Note that the data link control circuit 112 can use the PCR flag bit in this descriptor to determine whether the PCR is in the transport packet (and therefore whether the PCR should be corrected).

After sending the transport packet, data link control circuit 112 sets the appropriate status information in field 129-7 of the descriptor pointing to the sent transport packet, and assigns the descriptor. Cancel. Next, DMA control circuit 116 writes this status information to the appropriate descriptor storage location in the transmit queue.

In another method of operation, the operator is familiar with the content of the input TS to be remultiplexed. In this case, the operator simply creates a user specification and transmits the user specification from the controller 20 to the remultiplexing node 100 (or when a plurality of nodes cooperate in the network-distributed remultiplexing apparatus 100, It only sends to multiple remultiplexing nodes 100). Nevertheless, preferably, different types of information (eg, PAT, PMT, etc.) regarding the content of the incoming TS to be remultiplexed are constantly collected. From this, for example, the content can be immediately reported to the operator (through the processor 160 and the controller 20), thereby creating a modified user specification and also inputting the TS to be remultiplexed. ,
The re-multiplexing can be dynamically adjusted according to the modified user specification without stopping the output of the TS to be re-multiplexed and the re-multiplexing process of the re-multiplexing apparatus 100 described above.

In addition to the basic remultiplexing functions described above, remultiplexing node 100 can perform more advanced functions. These functions are individually described below.

Dynamic Remultiplexing and Insertion of Program-Specific Information As described above, by using the controller 20, the operator can use the controller 20 to store and discard programs and ESs, encrypt or decrypt (or both). A user specification can be created that specifies a program or ES, PID remapping, etc. Further, the processor 160 preferably continuously collects content information (eg, PAT, PMT, CAT, NIT, ECM table data, etc.). This allows user specifications to be changed simply dynamically, in real time, or in an "on-the-fly" manner, and re-multiplexing can be uniformly changed by new user specifications. Specifically, the operator can change the user specifications so that the remultiplexing device 30 can uniformly switch to the remultiplexing according to the new user specifications. Nevertheless, the remultiplexing device 30 ensures that each output remultiplexing TS is always a continuous bit stream containing a continuous stream of transport packets. Therefore, the output remultiplexing TS (s)
Is changed without interrupting the output remultiplexing TS (s) (ie, the sequence of output transport packets is uninterrupted and the output bitstream is not stopped).

The uniform changes described above are based on the I / O adapter 110 or interfaces 140 and 1
50 and other circuits such as descrambler / scrambler 170 may be affected by the use of programmable processor 160 to control the flow of transport packets. The decision to keep or discard another set of ESs can be affected simply by having processor 160 adjust the appropriate PID filter map and PID handler subroutine selected by processor 160 for each PID. Think about what's not. Whether some ESs or programs should be decrypted or encrypted can be changed by the processor 160 by modifying the PID handler subroutine executed in response to the PID specified for such ESs or programs. It can be determined by including appropriate encryption processing or decryption processing (above and below). Another selection of output ports to output another combination of output remultiplexing TSs is to use processor 160 to assign a new output port to a transmit descriptor queue and to select a transmit descriptor queue for output ports that are not needed. Deallocate and generate a table 404 of pointers pointing to the transmit PID handler subroutine for each new output port, and map each table 404 of pointers pointing to the transmit PID handler subroutine for each deallocated transmit queue. It can be achieved by throwing it away. Similarly, another selection of input ports is provided by the processor 160
To allocate and deallocate receive queues, and generate and discard a table 402 of pointers to receive PID handlers for such allocated and deallocated receive queues, respectively. Is done.

In addition to selecting the appropriate transport packet for output, the remultiplexing node 100 also provides, by way of example, the appropriate PSI for each output remultiplexed TS. This is achieved as follows. The controller 20 (FIG. 2) creates a user specification for the output TS. Consider the example above where the remultiplexing node 100 remultiplexes two TSs (ie, TS1 and TS2) to generate a third TS (ie, TS3). By way of example, Table 1 describes the respective contents of TS1 and TS2.

[Table 1] Preferably, the controller 20 programs the processor 160 to extract the information shown in Table 1 using the collection process of the receive PID handler subroutine described above.

It is assumed that the user specification retains only the programs A, B, F, and G and specifies that they be output to the output remultiplexing TS (TS3). The user uses the keyboard / mouse 27 (FIG. 1) to instruct the controller 20 (FIG. 1) with user specifications. The controller 20 determines whether the user specification is valid. In particular, the controller 20 determines that each output re-multiplexed TS (eg, TS3) has a designated program A, B, F, G and associated PSI (ie, program definitions a, b, f, g) as described below. Have sufficient bandwidth to output all of the new substitute PATs 3). Such bit rate information may be obtained from processor 160, if not already known. For example, the processor
A PID handler subroutine for determining the bit rate (or transport packet rate) of each program can be executed from the reception time stamp specified in each transport packet of each program carrying PCR. As mentioned above, such information is used by the processor 16 to perform PCR adjustments anyway.
Obtained using 0. If the user specification is not valid, the controller 20 does not download the user specification. If the user specification is valid, the controller 2
0 downloads the user specification to the processor 160.

It is assumed that the user specification is satisfied with the output bandwidth of TS3. If not already collected, the processor 160 determines the PAT and P of the input TS (TS1 and TS2).
Collect MT. Based on the information in PAT1 and PAT2, processor 160 determines the PI of program definitions a, b, f, and g related to programs A, B, F, and G.
Construct a surrogate PAT3 that includes only PAT1 and PAT2 entries indicating D. This may also be accomplished using a PID handler subroutine appropriate for the PIDs of PAT1 and PAT2, preferably running constantly so that any changes in those programs are reflected in PAT1 and PAT2. , Substitute P
We make sure that we can weave it into AT3. The processor 160 uses this new substitute P
A series of transport packets containing the AT3 are generated, and the transport packets are stored in the packet buffer 122. Processor 160 also generates a PAT queue of descriptors pointing to transport packets carrying PAT3. This queue is preferably implemented as a ring 124. The PAT descriptor queue for the PAT3 transport packet advantageously has a substitute PAT
This is a dedicated queue that stores only information. In addition, processor 160 generates approximated firing times and stores the estimated firing times in a PAT queue descriptor pointing to the PAT3 transport packet.

Here, the processor 160 can use the PAT3 descriptor queue in the same manner as any of the receive queues in response to a transmit interrupt. That is, when the data link control circuit 112 transmits k packets ≧ 1 and interrupts the processor 160, the processor 160 extracts the descriptor not only from the reception queue but also from the PAT3 queue. All queues containing descriptors pointing to transport packets to be output, for which no transmit descriptors in the transmit queue have yet been assigned, are collectively referred to herein as "connection queues."

Next, the processor 160 constructs an appropriate filter map, the first filter map to the first adapter 110 receiving TS1, the second filter map to the first adapter 110 receiving TS1, and the second filter map to receive TS2, respectively. To the adapter 110. For example, the first filter map is a PID, ie, PID (VA), PID (AA), PID
Extract and retain transport packets with (DA), PID (a), PID (VB), PID (AB), PID (b) (and possibly other PIDs corresponding to PSI in TS1) Can be shown. Similarly, the second filter map includes PIDs, that is, PID (VF), PID (AF), PID (DF
), PID (f), PID (VG), PID (A1G), PID (A2G), P
ID (DG), PID (ECMG), PID (g) (and possibly TS2
Extract the transport packet with the other PID corresponding to the PSI in
Can be shown to hold. In response, the first and second data link control circuits 112 receiving TS1 and TS2 extract only these transport packets from TS1 and TS2 according to the filter map provided by the processor 160. As described above, the first and second data link control circuits 112 store such extracted packets in the cache 114 and assign descriptors to those packets. The first and second DMA control circuits 116 periodically write the extracted transport packets and descriptor data for those transport packets to the host memory 120. Descriptor data written by the first DMA control circuit 116 is stored in a respective descriptor storage location 129 of a first receive queue for the first data link control circuit 112 and a second The descriptor data written by the DMA control circuit 116 is stored in the second data link control circuit 1
12 is stored in the descriptor storage location of the second reception queue.

Further, the third DMA control circuit 116 takes out descriptors from the transmission queue related to TS3 and transport packets corresponding to those descriptors, and stores them in the cache 114. Third data link control circuit 112 retrieves each descriptor from cache 114 and sends those descriptors to TS3. Third
The data link control circuit 112 generates an interrupt after transmitting k ≧ 1 transport packets. This causes the processor 160 to access a table of pointers pointing to the transmit PID handler subroutine for the transmit queue associated with the third data link control circuit 112. When executing the appropriate transmit PID handler subroutine, processor 160 may use the unused transmit descriptors of the TS3 transmit queue to connect queues available (ie, first receive queue, second receive queue, PAT3 queue). And the appropriate information is copied from the descriptors in the available connection queue to the descriptors thus allocated. These transmit descriptors are placed in an order determined by the estimated dispatch time of the receive
Assigned in the transmit queue.

Further, note that any type of PSI can be dynamically inserted, including new program definitions, EMM, ECM, CAT, or NIT.

Here, consider a situation in which a new user specification is created while re-multiplexing is performed according to the previous user specification. As before, the controller 20
First, make sure there is enough bandwidth to meet the new user specification. If so, download the new user specification to processor 160. The new user specification may be such that processor 160 extracts different programs and ESs, maps PIDs differently, or (a) transport packets carrying new PSI, (b) new PSI, (c) new PSI. , A descriptor pointing to the transport packet carrying the. When modifying the program or ES contained in TS3, the processor 160 modifies the PID filter map to retain the transport packets to be retained, and according to the new user specification, the transport packets to be discarded. throw away. These new filter maps are transferred to respective caches 114, which
Switching to transport packet extraction dynamically and immediately according to new user specifications. Processor 160 also includes pointer table 40 of the receive PID handler subroutine associated with the PID of the new to-be-held transport packet.
By modifying the pointer of No. 2, a reception PID handler subroutine suitable for the transport packet to be newly held is also selected. The pointer in the pointer table 402 of the receive PID handler subroutine indexed by the PID of the transport packet currently to be discarded can also be modified. In the case of a new PID remapping, the processor 160 selects an appropriate subroutine to perform a new PID remapping.

Such a change may require the generation of a new PSI (eg, a new PAT). The processor 160 generates a PID suitable for generating a new PSI.
Select a handler subroutine. For example, in the case of a new PAT, the PID handler subroutine may be triggered by the PID of the TS1 and TS2 PATs. Processor 160 generates a new PSI and inserts the new PSI into a transport packet. The descriptor in each PSI queue is assigned to such a new PSI transport packet. Processor 160 stops using any PSI descriptor queue pointing to the transport packet containing the old PSI (ie, reconstructs and forwards the transport packet from that PSI descriptor queue) and instead , Use the new PSI descriptor queue.

Since each change (ie, each time a newly selected PID handler subroutine, each time a PSI insertion correction, or each time a new PID filter map) is obtained, the appropriate data link control circuit 112 or processor 160 Changes its behavior uniformly. Until such a change is made, the data link control circuit 1
12 or processor 160 continues to operate based on previous user specifications. When the output remultiplexing TS is modified to always be MPEG-2 compliant, some attention must be paid to the ordering. For example, any change in the PID mapping, PID filtering, program, ES, ECM, etc. in the TS that strongly affects the PMT or PAT, preferably, the PMT (or its identification) Program definition) and / or P
The new version of the AT is output to the TS and is delayed until the TS indicates a new PMT, program definition, or instruction to switch to the PAT. Similarly, E
If MM is included or excluded for the conditional access system,
The introduction of such an EMM is delayed until a new version of the CAT is sent to the TS. By changing the PID filter map of each adapter 110, the PI
Before holding a transport packet having a D, etc., the appropriate entry in the pointer table of the receive PID handler subroutine, indexed by the PID of the transport packet to be held (previously discarded), Additional careful change ordering may be desirable for internal processing management of resources, such as storing pointers to subroutines.

The following is an example of modifying remultiplexing with new user specifications. The user shall provide a new user specification indicating that programs B and F should be removed and programs C and D should be retained instead. In response, the controller 20 first needs to generate all of the new program data, and for those new program data, when modifying the remultiplexed TS (TS3) with new user specifications. Sufficient bandwidth to accommodate some new PSI
It is determined whether it is in S (TS3). Assuming that this is the case, this new user specification is downloaded to the remultiplexing node 100. The processor 160 has a PID
A transport packet having a PID of (VB), PID (AB), or PID (b) is discarded, and PID (VC), PID (AC), PID (ECMC), PID
(C), PID (VD), PID (A1D), PID (A2D), PID (DD
), So as to hold a transport packet having a PID of PID (d),
Modify the PID filter map in the first adapter 110. Similarly, the processor 160 determines PID (VF), PID (AF), PID (DF), PID (f)
The second adapter 11 to discard the transport packet having the PID of
Modify the PID filter map in 0. The processor 160 executes a program definition update process for each of the PIDs (PID (c) and PID (d)),
Control word update process for ECMC, program C (for example, PID (VC
)), Including the decryption control word information insertion process of each of the encrypted ESs.
ID (VC), PID (AC), PID (ECMC), PID (c), PID (
VD), PID (A1D), PID (A2D), PID (DD), PID (d)
Select the PID handler subroutine for the PID. In addition, processor 1
60 is, for example, PID (0) for each of the first and second adapters 10.
In the process of executing the PID handler subroutine for
, B, c, d, and g, also generate another substitute PAT3.

Now, consider the case where another new user specification is provided that indicates the encryption of the VA video ES of program A. Also in this case, the controller 20 first determines whether or not TS3 has a sufficient bandwidth for storing the transport packet carrying the ECM for VA and the new program definition for Program A. This new user specification, if any, is downloaded to the remultiplexing node 100. Processor 160 allocates a queue to store a descriptor pointing to the transport packet containing the VA's ECM. Processor 160 selects a PID handler subroutine appropriate for the PID (VA), including inserting an encryption control word in the descriptor pointing to the transport packet containing the VA. Processor 160 also generates transport packets containing control words, such as ECMs for VAs, and assigns descriptors pointing to these transport packets. This may be achieved using a timer driven interrupt handler subroutine. Alternatively, additional hardware (not shown) or software running on processor 160 generates control words periodically and interrupts processor 160 when such control words are ready. . Processor 160 places the available control words in one or more transport packets, assigns an ECM descriptor from the ECM queue to such transport packets, and loads the new control words into the appropriate control word table. By that
Respond to such assignments. Further, the processor 160 executes the program definition a
And information on ECMA (for example, PID (ECMA),
This selects the receive PID handler subroutine for PID (a), including the process of adding the ES to encrypt, etc.

Scramble / descramble control One problem associated with scrambling and descrambling is selecting the right control word or key for each transport packet. That is, the scrambled transport packet data may be scrambled using a control word unique to the PID or a control word unique to one group of the PID. If the control words change accordingly, a rotation control word scheme may be used. In short, there may be many control words (eg, keys) associated with each TS, and the control words are changed periodically. In the case of descrambling, a mechanism must be provided to constantly receive control words for each ES or ES group to be descrambled and to select the appropriate control word at each point in time. In the case of scrambling, the appropriate control word is selected to encrypt the ES or ES group, and the control word used to scramble the ES well before any formation of any encrypted ES data. Must be provided in the output remultiplexing TS.

With the descriptors and the ordering of the descriptors in the receive and transmit queues,
TS scrambling and descrambling can be simplified. In particular, each receive descriptor is
Pertains to scrambling or descrambling, such as a control word used when scrambling a transport packet, or a pointer to an appropriate control word table containing control words used for scrambling or descrambling the transport packet. Field 129 where information can be stored
I have -9.

First, consider the actions taken when descrambling a transport packet. The TS including the transport packet to be descrambled includes a transport packet carrying ECM (conditional access unique to the ES) and EMM (conditional access unique to the entire ES group). E
The MM is carried in transport packets marked with a PID specific to the ES group to which the EMM corresponds, and the ECM is a PI specific to the specific ES to which each ECM corresponds.
It is carried in the transport packet marked D. EMM PID is CAT
, The EMM can be correlated to the corresponding specific ES group.
The PID of the ECM refers to the PMT and refers to each particular ES that the ECM corresponds to.
Can be correlated. The processor 160 selects the following PID handler subroutine: (1) Restore each CAT and PMT sent to the TS, and
PID handler subroutine that specifies which version of the ECM is currently being used. (2) A PID that restores the ECM table indexed by the PID of the transport packet carrying the ES corresponding to the ECM by referring to the PMT Handler subroutine.

Next, the processor 160 defines a series of processing steps to be performed on each transport packet and descriptor. That is, the processor 160 controls the reception adapter 11
0, the (optional) descrambler 115 of the receive adapter 110, the DMA control circuit 116, the (optional) descrambler 170, and the processor 160 of the receive adapter 110 are the receive descriptor or the receive descriptor. Specifies the specific order in which the packets pointed to by can be processed. To this end, the processor 160 forwards the appropriate control information to each of the devices 112, 115, 116, and in a specific order of its defined series of processing steps, as follows: And a descriptor indicating the transport packet may be processed by those devices.

When the descrambler 115 on the adapter is used, the processing order is as follows. The data link control circuit 112 of the adapter 110 receives the transport packets and assigns a receive descriptor to a selected one of these non-discarded transport packets according to the PID filter map described above. After storing each retained transport packet in cache 114, data link control circuit 112 illustratively sets status bit (s) 129-7 in the descriptor pointing to that transport packet. Here, it is shown that the transport packet is processed by the next device according to the determined sequence of a series of processing steps.

The descrambler 115 periodically checks the cache 114 and sets the status bit (s) 129-7 to indicate that the transport packet modification permission has been granted to the descrambler 115. Find one or more of the following descriptors: By way of example, the descrambler 115 accesses the cache 114 after processing m ≧ 1 descriptors. The descrambler 115 sequentially accesses each descriptor of the cache 114 from the descriptor previously accessed by the descrambler 115, and continues until accessing m ≧ 1 descriptors, or the status bit (1 (One or more) 129-7 to indicate that the processing of the previous step has been performed on the descriptor and the transport packet pointed to by the descriptor, according to the defined sequence of processing steps. Continue until the indicated descriptor is reached.

When processing descriptors and transport packets, descrambler 115 indexes the descrambling map in cache 114 using the PID of the transport packet pointed to by the currently examined descriptor. By way of example, the processor 160 periodically updates the descrambling map in the cache 114 as described below. The position of the descrambling map is determined by the descriptor field 12
Provided by the base address located in 9-9. By way of example, the processor 16
0 loads the field 129-9 of each descriptor with the base address of the descrambling map when allocating the receive descriptor queue. The indexed entry in the descramble map indicates whether the transport packet is encrypted, and if so, also indicates one or more control words that can be used to decrypt the transport packet. The indexed entry of the descrambling map contains a control word corresponding to the PID of the transport packet,
Alternatively, it may include a pointer to a storage location for storing each control word. If the indexed entry in the descrambling map indicates that the transport packet pointed to by the accessed descriptor is not descrambled, the descrambler 115 may return the status bit (s) 129 of the descriptor. It simply sets -7 to indicate that the next stage of processing is to be performed on the descriptor and the transport packet to which the descriptor points, according to the defined sequence of processing steps.

If the indexed entry of the descrambling map indicates the descrambling of the transport packet, the descrambler 115 obtains a control word corresponding to the PID of the transport packet, and uses the control word for the control word. Decrypts the transport packet data. Note that typical descrambling schemes use rotation (ie, odd and even) control words, as described above. The appropriate odd or even control word to use when descrambling the transport packet is transport_scrambling.
It is indicated by control bits in the transport packet, such as the _control bit. The descrambler 115, when indexing the appropriate control word,
These bits are used as well as the PID of the transport packet. That is, the map created and stored by the processor 160 is a PID, an odd number /
Even the index (s) are indexed. Next, the descrambler 115 stores the descrambled transport packet data in the transport packet storage location pointed to by the currently examined descriptor,
The previous decryption data of this transport packet is overwritten. Next, the descrambler 115 sends the status bit (s) 129 of the descriptor.
Setting -7 indicates that the next stage of processing will be performed on the descriptor and the transport packet pointed to by the descriptor in the order of the defined series of processing steps.

The DMA control circuit 116 periodically writes the transport packet data and the data of the descriptor indicating the transport packet data from the cache 114 to the respective storage locations 122 and 129 of the host memory 130. At that time,
DMA control circuit 116 periodically examines a series of one or more descriptors in cache 114 that follow the last descriptor processed by DMA control circuit 116 (in order of receive queue). Status bit (s) 129 of the examined descriptor
If -7 indicates that processing by the DMA control circuit 116 is to be performed on the examined descriptor, the DMA control circuit 116 determines the appropriate status bit (s) in this descriptor. 7 is set to indicate that the processing of the next step is to be performed on the descriptor and the transport packet indicated by the descriptor in the order of the determined series of processing steps. Next, the DMA control circuit 116 transmits the data of the descriptor and the data of the transport packet indicated by the descriptor to the host memory 130.
Write to. However, if the status bit (s) 129-7 are set to indicate that the processing prior to the processing performed by the DMA control circuit 116 is still being performed on the descriptor, The DMA control circuit 116 stops processing the descriptor and the transport packet indicated by the descriptor. By way of example, when possible, the DMA control circuit 116 examines the descriptors, such that the DMA control circuit 116 determines that the series of i ≧ 1 descriptors and the transformers to which such descriptors point. By writing the data of the port packet or by setting the status bit (s) 129-7, the processing of the previous step is still in the descriptor due to the defined sequence of processing steps. It continues until it encounters a descriptor indicating what is happening.

The processor 160 responds, for example, to an interrupt issued by the DMA control circuit 116 by executing an appropriate receive PID handler subroutine. Processor 160
Examines one or more descriptors in the receive queue corresponding to the adapter 110 that issued the interrupt, starting from the last descriptor processed by the processor 160. By way of example, processor 160 may include a status bit (s) 129-
7 only executes the receive PID handler subroutine appropriate to the descriptor indicating that processing by processor 160 is to be performed on the descriptor. Each time the processor 160 interrupts, the processor 160 illustratively includes:
Process the transport packets pointed to by those descriptors, and the process continues until the PID handler subroutine is executed on the condition of i ≧ 1 transport packets, or the appropriate status bits (one or Plural)
Setting 7 causes the processing of the previous processing step (in its defined sequence of processing steps) to continue until a descriptor is encountered indicating that it is still being performed on the descriptor.

In the course of executing the appropriate receive PID handler subroutine, processor 160 restores all control words for all ESs and decrypts them for use by descrambler 115 (or 170 as described below). And update the control word table or map. In the rotation control word method, the processor 160
Saves multiple (ie, odd or even) keys for each PID in a control word table or map. Processor 160 may also perform processing that allows the decrypted transport packet to be encrypted later (described below). After processing the received descriptors, the processor 160 sets the status bit (s) 129-7 of those descriptors to indicate that the descriptor is invalid (and thus the data link control Circuit 112 is the next device to process these descriptors), erase selected fields in this descriptor, or
Or reset, and further, set the head pointer 124-3 to the next descriptor storage location 1
By proceeding to 29, the allocation of these reception descriptors is released.

Here, the descrambler 115 is not provided on the adapter 110, or
Consider a case that is not used. Instead, the descrambler 1 on the bus 130
Use 70. A very similar procedure is performed as before. Nevertheless, in this outline, the order of the defined series of processing steps was changed to
A control circuit 116 processes these descriptors (and their corresponding transport packets) after the data link control circuit and before the descrambler, and the descrambler 170 (And their corresponding transport packets) are processed after the DMA control circuit 116 but before the processor 160. Therefore, the data link control circuit 1
12 assigns a descriptor to the transport packet and sends the appropriate status bits (
After setting one or more) 129-7 so that the next stage of processing can be performed on the descriptor and the transport packet, the DMA control circuit 116 returns to the descriptor and to which the descriptor points. Process transport packets. As mentioned above, D
The MA control circuit 116 sets the status bit (s) 129-7 to indicate that the next stage of processing is to be performed on the descriptor, and stores the transport packet and descriptor in host memory. Write to 130.

The descrambler 170 periodically examines the descriptors in the receive queue and sets the status bit (s) 129-7 so that the descrambling process can Identify a descriptor that indicates what to do with the indicated transport packet (in its defined sequence of processing steps). Descrambler 170 processes the identified transport packets in a similar manner as discussed above with respect to descrambler 115. After processing the transport packet, descrambler 170 sets one or more status bits 129-7 so that the next stage of processing (in accordance with its defined sequence of processing steps) is performed here. Indicates that the operation is performed on descriptors and the transport packets indicated by those descriptors.

The processor 160 performs the above-described processing in response to the interrupt issued by the DMA control circuit 116, including execution of an appropriate reception PID handler subroutine. Preferably, the length of the receive queue associated with the adapter 110 that has interrupted the processor 160 is sufficiently long compared to the processing time of the descrambler 170, and the descriptor for which the descrambler 170 has already processed the Is checked and processed. In other words, processor 160 and descrambler 170 preferably do not attempt to access the same descriptor simultaneously. More suitably, processor 160, as a descrambler 170, begins processing the descriptor at another point in the receive queue.

Here, let's consider processing related to scrambling. As in the case of descrambling, the status bit (s) 129-7 in the descriptor
Are used to order the processing steps of the processing performed on each descriptor and the transport packet pointed to by those descriptors according to a predetermined sequence of processing steps. The scrambling is preferably different from the descrambling, preferably by the processor 160.
Is assigned to the transport packet to be scrambled. Thus, the control word descriptor field 129-9 can be used in one of two ways. As in the case of descrambling, the address of the base of the scrambling map is placed in the control word descriptor field 129-9. However, preferably, the processor 160 places the appropriate control word in the control word descriptor field 129-9 because scrambling occurs after processing the descriptor in the transmit queue.

First, consider a scrambling process in which scrambling is performed by the scrambler 115 on the transmission adapter 110. Processor 160 obtains an ECM transport packet containing the control word, which is preferably encrypted. These ECM transport packets are queued to their respective connection queues and are scheduled for output at the appropriate time. That is, the ECM transport packet is scheduled such that the ECM transport packet is injected into the output TS well before the decrypted transport packet, so that the decoder can receive the descrambling transport packet before receiving it. The control word can be restored.

After sending the ECM transport packet containing the control word, at the appropriate time, the processor 160 modifies the control word table to use the new key corresponding to the recently sent control word. , So that the data can be encrypted. When a transport packet is sent from the output adapter, the processor 160 executes a send PID handler subroutine related to the PID of the transport packet pointed to by the descriptor in the examined connection queue. For each such transport packet to be scrambled, the transmit PID handler subroutine involves inserting control word information into the descriptor associated with the transport packet. This control word information may simply be the base address of the scrambling map used to specify the control word used when encrypting the transport packet. However, it can be said that the control word information is an appropriate control word used when encrypting the transport packet. Processor 160 may also include transport_scrambling_cont
Bits in the transport packet, such as the rol bit, can also be toggled to indicate which of the most recently sent control words should be used to decrypt or descramble the transport packet at the decoder. .
Further, processor 160 may illustratively include one of the newly assigned transmit descriptors.
By setting one or more status bits 129-7, the next stage of processing (according to the defined sequence of processing steps) is performed on the transmit descriptor and the transport packet pointed to by the transmit descriptor. Indicates what should be done.

[0136] The DMA control circuit 116 of the transmission adapter 110 periodically extracts descriptor data from the transmission queue and transport packets indicated by those descriptors. At that time, the DMA control circuit 116 examines the transmission queue for a descriptor subsequent to the last descriptor when the DMA control circuit 116 transferred the descriptor data to the cache 114. The DMA control circuit 116 outputs the status bit (s) 12
9-7 is set, and here, only the data of the transmission descriptor indicating that the processing by the DMA control circuit 116 is performed (in the order of the determined series of processing steps) is transferred. For example, the DMA control circuit 116 checks the transmission descriptor, and checks the transmission descriptor until a constant k ≧ 1 transmission descriptors which the DMA control circuit 116 has permission to process are specified, or the status bit 129-7. , And the processing of the previous processing stage is continued until a transmission descriptor and a descriptor indicating that the transport packet indicated by the transmission descriptor is being performed are identified. After transferring such transmission descriptors and the data of the transport packets pointed to by these transmission descriptors to the cache 114, the DMA control circuit 116 returns the status bits (1 Or multiple) 129-7,
Indicates that the next stage of processing (in accordance with the defined sequence of processing steps) will be performed on the transmit descriptors and the transport packets pointed to by those transmit descriptors.

Next, the scrambler 115 periodically checks the descriptor in the cache 114,
A series of one or more descriptors to be processed and the transport packets pointed to by those descriptors are determined. The scrambler 115 sets the one or more status bits 129-7 to indicate that the processing of the encryption processing step is to be performed (in accordance with its defined sequence of processing steps). Just handle. The scrambler 115 accesses the control word information field 129-9, and uses the information in the field to encrypt each transport packet to be scrambled. As mentioned above, this control word information can be used in one of two ways. If the control word information is the base address of the scramble map, the scrambler 115 indexes the scramble map using the base address of the transport packet and the PID information. The indexed entry in the scrambling map indicates whether the transport packet is encrypted and, if so, the control word to use when encrypting the transport packet. Alternatively, the control word information itself in field 129-9 also indicates whether the transport packet is scrambled,
If scrambled, it also indicates the control word used when encrypting the transport packet. If the transport packet of this processed descriptor is not encrypted, the scrambler 115 simply returns the appropriate status bit (1
(One or more) 129-7 so that the next stage of processing (according to its defined sequence of processing steps) is now the transmission descriptors and the transport packets to which they refer Is performed. If the transport packet of this processed descriptor is scrambled, the scrambler first scrambles the transport packet data and places the transport packet in the cache instead of the unscrambled transport packet. Store and then set the appropriate status bit (s) 129-7.

The data link control circuit 112 periodically checks the transmission descriptor in the cache 114 and sets one or more status bits 129-7 to indicate that the processing by the data link control circuit 112 is to be performed. The transmission descriptor to be indicated is obtained. With such transmission descriptors, data link control circuit 112 sends the transport packets pointed to by these descriptors at approximately the actual dispatch times indicated in those descriptors. Next, the data link control circuit 112 deallocates those descriptors (and then sets the status bit 129-7 to invalid). By way of example, each time data link control circuit 112 sends a series of k ≧ 1 descriptors, data link control circuit 112 raises a transmit interrupt for receipt by processor 160.

If scrambler 115 is missing or not used, scrambler 170 is used instead, as an example. The order of the above-described series of processing steps is changed so that the scrambler 170 transmits each transmission descriptor and the transport packet indicated by the transmission descriptor to the DMA control circuit 11 after the processor 160.
6 and the DMA control circuit 116 processes each transmit descriptor and the transport packet pointed to by the transmit descriptor after the scrambler 170 but before the data link control circuit 110. Like that.

Optimization of Bandwidth As described above, a null transport packet is often inserted into a TS carrying a program. In general, program encoders
Such null transport packets exist because extra bandwidth needs to be allocated. This is because when ESs are generated one by one, the amount of encoded data to be generated can only be controlled by that amount. Without such "overhead bandwidth," the coded ES data would frequently exceed the allocated bandwidth size, thereby omitting the coded ES data from the TS. Alternatively, an ES encoder (especially a video ES encoder) may not always have data available for output when a transport packet timeslot appears. For example, a special video may take an unexpectedly longer time than expected in advance, which may delay generation of encoded video ES data. Such time slots are filled with null transport packets.

At the remultiplexing node 100, the presence of null transport packets must be allowed, but it is desirable to reduce the number of such bandwidths that waste null transport packets. Nevertheless, the bit rate of each program must not be changed, and the end-to-
End delay must be kept constant. According to one embodiment, if other transport packet data to be remultiplexed is available, a technique for replacing a null transport packet with such another transport packet is used.

First, the processor 160 generates a descriptor for the transport packet to be scheduled (ie, the receive queue, PSI not yet transferred to the transmit queue).
Suppose you have multiple connection queues available that contain descriptors in queues, other data queues, etc. As described above, these descriptors are
Transport stream or another program-related stream generated by the processor 160, such as a PAT stream, a PMT stream, an EMM stream, an ECM stream, a NIT stream, a CAT stream, and the like. However, other types of scheduled transport packets, such as transport packets carrying private data of the time insensitive, "bursty" or "best effort" type, and a description for those transport packets. Child 129 may be available. For example, such extra transport packets may contain transactional computer data (eg, data exchanged between a web browser and a web server, etc.). (The remultiplexing node 100 includes a server, a terminal,
Alternatively, it is simply an intermediate node in the communication system connected to the "Internet". Such an Internet connection may be via modem, adapter 140 or 1
50 or the like. ) Such data does not have a fixed end-to-end delay requirement. More appropriately, such data is sent in bursts whenever bandwidth is available.

[0143] Processor 160 first causes each null transport packet to be discarded. This is accomplished by causing the processor 160 to discard all null transport packets using the receive PID handler subroutine. This technique is illustratively based on interface 140 or 150, such as
Used when receiving a null transport packet from a device other than the adapter 110. Alternatively, if a null transport packet is received from the adapter 110, the processor 160 may provide a PID filter map to the data link control circuit 112 to cause each null transport packet to be discarded. Next, according to the reception PID handler subroutine, each incoming transport packet output to the TS includes a transport packet reception time (recorded in a descriptor for the transport packet) and a remultiplexing node. The approximate calculated departure time is specified as a function of the internal buffering delay in 100. For each connection queue containing transport packets to be scheduled, this specified departure time may not be the continuous transport packet transmission time of the output TS (corresponding to adjacent time slots). More suitably, two consecutive descriptors for transport packets output on the same output TS have their approximate calculated departure times one or more of the output remultiplexing TSs on which the transport packets are sent. It may be separated by the transport packet transmission time (ie, time slot).

Preferably, a descriptor indicating a transport packet including program data, a descriptor indicating a transport packet including PSI, ECM, or EMM, and a descriptor indicating Bursty type data are respectively separated from each other. Stored in the connection queue. In implementation, each connection queue is assigned a usage priority determined by the data type in the transport packet pointed to by the queued descriptor. Preferably, program data received from outside the remultiplexing node (eg, via the receive adapter 110 or the interface 140 or 150) is assigned the highest priority. The same priority is also assigned to the connection queue that stores the PSI, ECM, or EMM stream generated by the remultiplexing node. Finally, connection queues with descriptors pointing to transport packets containing bursty data without specific continuity, propagation delay, or bit rate requirements are given the lowest priority. . Further, unlike the program, PSI, ECM, and EMM data, no approximate calculated start time is specified for the bursty type data carrying the transport packet and is not recorded in the descriptor of the bursty type data.

When executing the send PID handler subroutine, the processor 160
The descriptor related to the transport packet to be scheduled is transferred from each connection queue to the transmission queue. In so doing, processor 160 preferably uses each lower priority connection queue after using each connection queue of a given priority (ie, examining the descriptors in that connection queue). I do. When examining the descriptor, the processor 160 uses the high priority connection queue (ie,
Any examined descriptor (which contains the descriptor of the transport packet carrying the program, PSI, ECM, or EMM data) will send the transport packet that needs to be sent at the next actual dispatch time. Then, it is determined whether or not the packet is pointing based on the approximate calculated departure time specified in those transport packets. If so, the processor 160 assigns a transmit descriptor to each of the above transport packets, copies the appropriate information from the connection queue descriptor to the allocated transmit queue descriptor, and Specify an appropriate dispatch time for each transport packet to which a child is assigned. As described above, from time to time, two or more transport packets compete for the same actual departure time (ie, the same transport packet time slot of the output remultiplexing TS). In this case, a series of transport packets are designated for consecutive time slots and actual departure times. If necessary, the PC of such transport packets
R adjustment is performed.

Otherwise, when the processor 160 uses the connection queue, any transport packet in the higher priority connection queue is sent by the processor 160 to the transport packet next to the output remultiplex TS. It does not have an approximate calculated departure time to be assigned to the available time slots and the actual dispatch time.
Normally, in this case, an empty time slot of the output remultiplexing TS is generated. However, preferably, in this case, the processor 160 uses a lower priority connection queue. Processor 160 examines the lower priority connection queue (in order from head pointer 124-3) and sends a transmit descriptor to each of a series or sequence of one or more transport packets pointed to by the descriptor so examined. , And copy the appropriate information of this examined descriptor into its assigned transmit descriptor. The processor 160 selectively assigns one of the (usually vacant) time slots to each transport packet pointed to by the descriptor examined in this manner, and associates it with the specified time slot. The actual dispatch time of a given dispatch descriptor is stored in the corresponding assigned transmit descriptor.

Occasionally, any transport packet pointed to by a descriptor in a high priority or low priority connection queue may not be specified in a time slot of an output remultiplex TS. This is because no high-priority transport packet has an approximate dispatch time that matches the actual dispatch time of this time slot, and that no transport packet carrying bursty data It can be said that this happens because the data is not buffered during transmission on the. Alternatively, the transport packets carrying the bursty data may be buffered, however, the processor 160 may, at this particular point in time, transmit the transmit descriptor to those transport packets for reasons discussed below. Has been decided not to specify. In such a case, the descriptors in the transmit queue have their actual transmission times correspond to a non-contiguous series of transport packet time slots of the output remultiplex TS. When the data link control circuit 112 of the transmission adapter 110 encounters such an interruption, the data link control circuit 112 sends a null transport packet in each free time slot where no transport packet is specified (transmission descriptor). Based on the actual dispatch time). For example, the dispatch time of two consecutive descriptors in the transmit queue associated with the first and second transport packets is such that the first transport packet is sent in the first transport packet time slot; Assume also that the second transport packet indicates to be sent in a sixth transport packet timeslot. Data link control circuit 112 sends the first transport packet in a first transport packet time slot. Each of the second, third, fourth and fifth transport packet time slots has a data link control circuit 11
2 automatically sends a null transport packet. In the sixth transport packet time slot, the data link control circuit 112 sends a second transport packet.

Note that bursty or best effort data does not generally have strict receive buffer constraints. That is, most Bursty or best effort data receivers and receiving applications do not specify any maximum buffer size, data filling rate, or the like. Instead, transport packets, such as Transmission Control Protocol (TCP), are used, so that when the receiver's buffer is full, the receiver simply discards data subsequently received. The receiver does not acknowledge receipt of the discarded packet, and its source resends the packet with data that was not acknowledged. This effectively adjusts the effective data transmission rate to the receiver. While such an adjustment technique may effectively achieve a reasonable data rate to the receiver, this technique has two problems. First, the network must support two-way communication. Only a portion of all cable television networks support two-way communication between transmitter and receiver (no telephone uplink), and no direct broadcast satellite network supports such two-way communication. In any case, when two-way communication is supported, the upstream path from the receiver to the transmitter has a substantially lower bandwidth than the downstream path from the transmitter to the receiver, and often multiple receptions Machine must be shared. Therefore, TCP as a regulatory mechanism
The active use of Utilizes most of the upstream path, which must also be used for communication between other receivers and transmitters. Further, it is not preferable to waste the bandwidth of the downstream path for transmitting the discarded transport packets.

Preferably, even if data of Bursty type or Best effort type is inserted,
Such buffers must not overflow. By way of example, the PID handler subroutine (s) can control the rate at which the bursty data is inserted to achieve a certain average rate so as not to exceed a certain peak rate, or Given constant (or representative) receiver buffer occupancy and internal data penalty, it is even possible to simply prevent receiver buffer overflow. Thus, even when processor 160 can use bursty or best effort data to insert into one or more free time slots of a transport packet (no other data can be used for such insertion). , The processor 160 decides to insert bursty data only in some empty time slots of the transport packet, or inserts bursty data in every other or spaced time slot of the transport packet. Or to decide not to insert bursty data in any empty time slot of the transport packet, and to adjust the data transmission to the hypothetical receiver bursty data buffer, or Prevent buffer overflow It has to. Further, transport packets destined for multiple different receivers may interleave themselves, maintaining a certain data rate to the receiver, regardless of when the transport packets were generated.

In any case, the remultiplexing node 100 provides a simple way to optimize the bandwidth of the TS. Discard any null transport packets in the incoming TS. If transport packets are available, they are normally inserted into the time slots assigned to the discarded null transport packets. If no transport packets are available, the normal dispatch time assignment process leaves a gap in such a time slot. If the transport packet indicating that it is to be sent in the next available time slot of the output remultiplexing TS has no dispatch time, the data link control circuit 112 places the null transport packet in such a time slot. Insert automatically.

There are two advantages of such a bandwidth optimizing method. As a first advantage, a bandwidth gain is obtained for the output remultiplexing TS. Typically, the bandwidth wasted on null transport packets is used here to send information. As a second advantage, best-effort or bursty data does not specifically allocate bandwidth to the data (or allocates less bandwidth),
Can be output to For example, assume that the output remultiplexing TS has a bandwidth of 20 Mbit / s. Each of the 5 Mbit / s TSs carrying the four programs is remultiplexed and output to a 20 Mbit / s multiplexed TS. However, about 5% of the bandwidth of each of the TSs carrying the four programs is allocated to null transport packets. Thus, up to 1 Mbit / s may be (usually) usable to carry transport packets carrying best-effort or bursty data, provided that the end-to-end delay is constant. There are no or limited warranties.

Retiming of Non-Timing Data As described above, the program data to be remultiplexed
0 is received. This means that the interface 140 and the communication link to which it connects are not designed to send data at any particular time and are likely to introduce variable end-to-end delays into the communication data. From, it becomes a problem. As a comparison, a synchronous communication link (receiving adapter 11
For the program data received at the remultiplexing node 100 (which is connected to 0), it can be assumed that all the received transport packets are output without jitter. For this reason, all of the above packets have the same delay (ie, internal buffering delay) at the remultiplexing node 100.
Or if these packets do not introduce such a delay (as a result of timeslot contention, as described above), the additional delay is known,
This is because the PCR is adjusted to remove any jitter induced by such additional delay. In addition, the PCR is corrected for drift of the internal clock mechanism according to the system time clock of each program, and the mismatch between the scheduled output time of the PCR and the actual output time according to the slot boundary of the output TS. Is corrected for However, if the transport packet is
If received from zero, these transport packets are received at the remultiplexing node 100 at variable bit rates and with variable jitter times. Therefore, if the actual reception time of this transport packet is used as a basis for estimating the departure time of this transport packet, this jitter will remain. If there is jitter in the PCR,
Not only will the decoding and presentation break, but also buffer overflows and underflows will occur. The reason for this is that the bit rate of each program is carefully adjusted, assuming that the data is removed from the decoder buffer for decoding and presentation according to the system time clock of the program. .

According to one embodiment, these programs are overcome as follows. The processor 160 specifies the PCR of each program of the received TS. Using PCR,
Processor 160 determines a piecewise transport packet rate for the transport packets of each program between the PCR pairs. Each of each program (
Given the transport packet rate of a series of interleaved transport packets, processor 160 can specify a roughly calculated departure time based on the time at which each transport packet would have been received.

By way of example, when the interface 140 receives program data, the received program data is transferred from the interface 140 to the bucket buffer 122 of the host memory 120. Specifically, the interface 140
Accumulates received program data in some form of receive queue. Preferably, the received program data is in a transport packet.

The interface 140 periodically interrupts the processor 160 upon receiving data. The interface 140 may interrupt the processor 160 each time it receives any amount of data, or may
Interrupt. As in the case of the adapter 110, the pointer table 402 of the receive PID handler subroutine is specially devised for the interface 140. The subroutines pointed to by these pointers may be similar in many respects to the subroutines pointed to by the pointers in the pointer table of the receive PID handler subroutine associated with receive adapter 110. However, these subroutines differ in at least the following respects. First, asynchronous interface 140 may not assign a descriptor having the format shown in FIG. 2 to received program data, and may not receive program data in transport packets. For example, this program data is PES
Either packet data or PS packet data. In such a case, the subroutine executed by processor 160 for the PID of the retained transport packet includes, by way of example, a process of inserting program data into the transport packet. Further, a process is provided for assigning a receive descriptor for a queue designated to the adapter 140 to each received transport packet. Processor 160 stores a pointer to the storage location of the corresponding transport packet in pointer field 129-4 of each assigned descriptor. By way of example, the actual reception time field 129-5 is initially left blank.

Further, each transport packet containing a PCR includes the following process. When any program receives a transport packet carrying a PCR for the first time, the processor 160 sends the reference clock generator 113 of any adapter 110 (or the reference clock generator 11 of the adapter 110).
3. Obtain a timestamp from any other reference clock generator 113) synchronously locked to 3. As described below, the reference clock 113 is synchronously locked. The obtained time stamp is designated as the transport packet carrying the first always-received PCR of a program as the reception time of this transport packet. Another transport packet to be remultiplexed is the first
May have been received prior to the transport packet carrying the received PCR. The known internal buffering delay at the remultiplexing node 100, in addition to the reception timestamp, is the approximate calculated start time specified in this transport packet (which contains the first always-accepted PCR for a particular program). May be generated.

After receiving a second continuous transport packet carrying a PCR for a particular program, the processor 160 can estimate the transport packet rate between the PCRs of the program received over the asynchronous interface 140. This is achieved as follows. Processor 160 forms the difference between two consecutive PCRs of the program. Next, the processor 160 calculates the difference by the number of transport packets of the program from the transport packet containing the first PCR of the same program to the transport packet containing the second PCR. Divide. This gives the transport packet rate for that program. Processor 160 multiplies the transport packet rate for this program by the offset or displacement of each of the above transport packets from the transport packet containing the first PCR,
The departure time of each transport packet of the program during the PCR of the program is estimated. This offset is determined by subtracting the transport packet queue position of the transport packet carrying the first PCR from the transport packet queue position at which the approximate calculated start time is calculated. (Note that the transport packet queue position is for all received transport packets of all received streams.)
Processor 160 adds the approximate calculated emission time specified in the transport packet containing the first PCR to the product thus obtained. Processor 160
Stores, as an example, the approximate calculated start time of each transport packet in the field 129-10 of the descriptor indicating the transport packet.

After specifying the approximate calculated timestamp in the transport packets of the program, the processor 160 may discard the transport packets that are not output to the TS (by user specification). Next, the above process is constantly repeated for each successive PCR pair of each program carried in the TS.
Next, the descriptor data with the approximate calculated departure time is transferred to the appropriate transmit queue (s) as processor 160 executes the transmit PID handler subroutine. It should also be noted that initially, some transport packets are received for a program before receiving the first PCR of the program. With these transport packets alone, the transport packet rate is approximated as the transport packet rate between the first and second PCR of the program (these packets are the first
Between the first and second PCR). Next, the approximate calculated departure time is determined as described above.

As in the case of a PCR received from a synchronous interface such as the adapter 110, the PCR received through the asynchronous interface 140 is used to specify each program clock and the approximate receive timestamp and output transport packets. The drift with respect to the obtained local reference clock 113 is corrected. Unlike the transport packet received from the adapter 110, the transport packet received from the interface 140 does not have an actual reception time stamp. Therefore, there is no reference clock that is related to each transport packet and that can accurately measure drift. Instead, processor 1
60 estimates the drift at the remultiplexing node 100 using the length of the transmit queue or a measure of the current delay of the transmit queue. Ideally, the length of the transmission queue should not fluctuate at the remultiplexing node 100 from a predetermined known delay. Any variation in the length of the transmit queue is indicative of a drift of the reference clock generator (s) 113 of the adapter (s) 110 in response to the program clock of these programs. Accordingly, processor 160 adjusts the drift measure upward or downward depending on the difference between the current transmit queue length and the expected ideal transmit queue length. For example, each time a transmit descriptor is assigned to a transport packet, the processor 160 measures the length of the current transmit queue and reports the length to the remultiplexing node 10.
At 0, subtract from the ideal transmit queue length. This difference is the drift.
Using the drift calculated in this way, the PCR of the transport packet carrying such a PCR and the approximate calculated emission time are adjusted. That is, the drift thus calculated is subtracted from the PCR of the transport packet received through the asynchronous interface. In this case, the transport packet is put into a time slot that is later than a time slot corresponding to the approximate calculated transmission time of the transport packet. Similarly, this drift is subtracted from the approximate calculated launch time of the transport packet carrying the PCR before the actual dispatch time is specified. Note that this approximate drift is used only for transport packets received from asynchronous interface 140 and not for other transport packets received over a synchronous interface, such as adapter 110.

Now, consider the problem of contention. When two (or more) received transport packets contend for designation of the output remultiplexing TS to the same transport packet time slot (and actual dispatch time), one of the The transport packet is specified in a time slot, and the other transport packet is specified in the next time slot. If a PCR is included in another transport packet, the PCR is adjusted by the number of time slots transferred from the ideal time slot to reflect the designation of a later time slot.

Output Timing Support As described above, interface 140 does not receive transport packets at any particular time. Similarly, interface 140 does not send transport packets at any particular time. However, it is desirable for the interface 140 and the communication link to which it connects to provide as much of the end-to-end delay variation as possible without providing a constant end-to-end delay. Remultiplexing node 100 provides a way to minimize such variations.

According to one embodiment, the processor 160 assigns a transmission descriptor of the transmission queue specified to the interface 140 to each transport packet output through the interface 140. This is accomplished using a series of transmit PID handler subroutines appropriate for the transmit queue specified for the output port of interface 140. In addition, the processor 160
The adapter 110 is specified to manage the output of data from the. Although the transmit queue is technically “designated” to the interface 140, the DMA control circuit 116 of the adapter 110 designated to manage the output from the interface 140 actually writes the descriptor queue description designated to the interface 140. Gain control of the child. The data link control circuit 112 accesses the above descriptors, as described below, and these descriptors are stored in the cache 114. Thus, the set of transmit PID handler subroutines assigned to this queue and executed by processor 160 are actually triggered by an interrupt generated by data link control circuit 112 to cause this queue to be examined.

As described above, in response to such an interrupt, the processor 160 examines the descriptor to be scheduled (ie, in the connection queue) and checks one of these connection queues output from the output port of the interface 140. One or more descriptors are selected and the transmit descriptor is assigned to a connect queue select descriptor at the tail of the transmit queue associated with the output port of interface 140. Unlike the output of the transport packets described above, the processor 160 also collects the transport packets associated with the selection descriptor of the connection queue and, if buffering is needed at the interface 140, actually transfers those transport packets. May be physically organized into buffers such as queues.

As described above, the DMA control circuit 116 controls the series of one or more descriptors associated with the output port of the interface 140 after the last descriptor for which the DMA control circuit 116 has gained control. Get. (Note that it is irrelevant whether the transport packets corresponding to these descriptors are taken out. The data link control circuit 112 controls the output of the transport packets at the interface 114, so any transport The port packet is also the data link control circuit 1.
No signal is output from the output port connected to the output port 12. Alternatively, the data link control circuit 112 can operate properly as described above, thereby producing a mirror copy of the output TS. In such a case, a second copy of each transport packet that adapter 110 can access must also be provided. As described above, the data link control circuit 112 fetches each descriptor from its cache and, based on the indicated dispatch time recorded in the field 129-5, determines that the corresponding transport packet has the time indicated by the reference clock generator 113. In response to the,
Decide when to be sent. When the time of the reference clock generator 113 is approximately equal to this dispatch time, the data link control circuit 112 now causes an interrupt to the processor 160 to send a transport packet. This can be said to be the same interrupt that is generated by the data link control circuit 112 when the data link control circuit 112 sends k ≧ 1 transport packets. However, this interrupt is preferably raised for every k = 1 transport packet. In response, processor 160 consults the appropriate pointer table pointing to the transmit PID handler subroutine and
Execute the ID handler subroutine. When executing the transmit PID handler subroutine, processor 160 issues a command or interrupt that causes transport packets to be sent on interface 140. Thus, when the current time of the reference clock generator 113 substantially matches the dispatch time written in the descriptor corresponding to the next transport packet, the next transport packet itself is output from the output port of the interface 140. Sent. It should be noted that there is some bus and interrupt latency between the data link control circuit 112 issuing the interrupt and the interface 140 outputting the transport packet. Further, the communication link to which the interface 140 is connected may also have some latency (due to busy, collision, etc.). To some extent, such an average value of the waiting time can be accepted by the processor 160 judiciously selecting the dispatch time of the transport packet. Nevertheless, the time to output a transport packet may be fairly close to the proper time, but not less than the time achievable with adapter 110 or interface 150. Further, processor 160 also forwards the one or more descriptors to the transmit queue specified on the output port of interface 140, as described above.

Locking of Reference Clocks between Adapters A particular problem with any synchronous system using multiple clock generators is that the time or count of each clock generator is not exactly the same as each other clock generator. is there. More appropriately, the count of each clock generator is subject to drift (eg, as a result of manufacturing tolerances, temperature, power fluctuations, etc.). Such a problem also exists in the environment 10. Each remultiplexing node 100, data injector 50, data extractor 60, controller 20, etc. are connected to the adapter (s) 1
There may be a case where a reference clock generator such as ten reference clock generators 113 is provided. It is desirable to lock at least the reference clock generator of each node 50, 60, or 100 to the same TS signal flow path so that the reference clock generators have the same time.

In a broadcast environment, it is useful to synchronize any device that generates, edits, or transmits program information. In analog broadcasting, this is achieved using a black burst generator or SMPTE time code generator. Such synchronization allows for seamless splicing of real-time video feeds, while also reducing the noise associated with combining asynchronous video feeds together.

At the remultiplexing node 100, the need for synchronization is even more important. The reason for this is that the received transport packets are scheduled for departure based on one reference clock and are actually picked up for dispatch based on a second reference clock. At the remultiplexing node 100, any latency introduced by the transport packets is assumed to be the same. Nevertheless, such an assumption is valid only if there is only a negligible drift between the reference clock used to estimate the packet departure time and the reference clock used to actually dispatch the transport packets. .

According to one embodiment, locking is provided with a number of techniques, namely synchronization, reference clock generator 113. In each technique, each "slave"
The time of the reference clock generator is periodically adjusted with respect to the "master" reference clock generator.

According to the first technique, one reference clock generator 11
3 is called the master reference clock generator. Each of the other reference clock generators 113 of each of the other adapters 110 is referred to as a slave reference clock generator. Processor 160 includes a reference clock generator 113 including a master reference clock generator and a slave reference clock generator.
Get the current system time on a regular basis. By way of example, this may include sleeping (i.e., inactive for a specific time), wake-up, and processor 160
By using a process for obtaining the current time of each reference clock generator 113. The processor 160 controls each slave reference clock generator 1
13 and the current time of the master reference clock generator 113 are compared. Based on such a comparison, the processor 160 adjusts each slave reference clock generator 113 to synchronize the clock generators with the master reference clock generator 113. This adjustment may be simply reloading the reference clock generator 113, adding the adjusted time value to the system time of the reference clock generator 113, or voltage control that supplies a clock pulse to the counter of the reference clock generator 113. This is achieved by speeding up (filtering and) or slowing down the oscillator pulses. The last form of adjustment is similar to the phase locked loop feedback adjustment described in the MPEG-2 system specification.

Here, consider a case where the master reference clock generator and the slave reference clock generator are not at the same node but are connected to each other by a communication link. For example, the master reference clock generator is at a first remultiplexing node 100 and the slave reference clock generator is at a second remultiplexing node 100, where the first and second remultiplexing nodes are located. Are connected together by a communication link extending between the respective adapters 110 of the first and second remultiplexing nodes 100. Periodically, in response to the timer processing, the processor 160
A command for obtaining the current time of the master reference clock generator 113 is issued. Adapter 110 responds by providing the current time to processor 160. Next, the processor 160 sends the current time to each of the other slave reference clocks over the communication link. Next, this slave reference clock is, for example, as described above.
Adjusted.

Note that any time source or time server can be used as the master reference clock generator. The time of this master reference clock generator is passed through a dedicated communication link with a fixed end-to-end delay.
Sent to each other node that contains the slave reference clock.

The two or more nodes 20, 40, 50, 60, or 100 of the remultiplexing device 30
However, if they are separated by a large geographical distance, it may not be preferable to synchronize the reference clock generator of each node with the reference clock generator of any other node. The reason for this is that any signal sent on the communication link experiences some finite propagation delay. Such a delay causes a waiting time for transmission of a transport packet (in particular, a transport packet with a synchronization time stamp). Alternatively, it may be preferable to use a reference clock source that is further equidistant from each node of the remultiplexer 30. As is well known, the U.S. Government maintains both terrestrial and satellite reference clock generators. These sources reliably send time on a known carrier signal. Each node (eg, remultiplexing node 100) may include a receiver (eg, GPS receiver 180) that can receive a broadcast reference clock. Periodically, the processor 160 (or other circuit) of each node 20, 40, 50, 60, or 100 obtains a reference clock from the receiver 180. The processor 160 may transfer this obtained time to the adapter 110 and load it into the reference clock generator 113. However, preferably, the processor 160
By issuing a command to 0, the current time of the reference clock generator 113 is obtained. Next, the processor 160 uses the reference clock generator 113 based on the difference between the time obtained from the receiver 180 and the current time of the reference clock generator 113.
Issue a command to adjust (e.g., speed up or slow down) the voltage controlled oscillator.

Networked Remultiplexing Given the above operations, the various functions of remultiplexing are distributed over the network. For example, a plurality of remultiplexing nodes 100 may have various communication links, adapters 1
10. Connected to each other by interfaces 140 and 150. Each of these remultiplexing nodes 100 is controlled by a controller 20 (FIG. 1) to cooperate as a single remultiplexing device 30.

Such a network distributed remultiplexing apparatus 30 is desirable in terms of convenience or flexibility. For example, one remultiplexing node 100 is connected to multiple file servers or storage devices 40 (FIG. 1). Another remultiplexing node 100 is connected to a camera or other input sources such as a demodulator / receiver. Each of the other remultiplexing nodes 100 is connected to one or more transmitters / modulators or recorders. Alternatively, the remultiplexing nodes 100 are connected to provide redundancy, and therefore fault tolerance, if one remultiplexing node 100 fails or is intentionally taken out of use.

Consider the first network remultiplexing device 30 ′ shown in FIG. In this outline, a plurality of remultiplexing nodes 100 ', 100 ", 100'"
Connected to each other through an asynchronous network such as a 00BASE-TX Ethernet network. The first two remultiplexing nodes 100 ', 100''each receive four TSs (TS10-TS13 or TS14-TS17) and produce a single remultiplexed output TS (TS18 or TS19). The third remultiplexer 100 '''receives the TSs (TS18 and TS19) and generates an output remultiplexing TS (TS20). In the example shown in FIG. 3, the remultiplexing node 100 'receives the TS (TS10 to TS13) transmitted in real time from the demodulator / receiver through its adapter 110 (FIG. 2). On the other hand, the remultiplexing apparatus 100 ″ receives the previously stored TS (TS14 to TS17) from the storage device through the synchronization interface 150 (FIG. 2). Remultiplexing node 1
00 ′ and 100 ″ respectively have their respective output remultiplexing TSs (ie,
TS18 or TS19) is asynchronous (100B) of the remultiplexing node 100 '''.
ASE-TX Ethernet) interface 140 (FIG. 2) to the remultiplexing node 100 '''. Advantageously, the remultiplexing nodes 100 'and 100'
'' Each use the output timing assistance techniques described above to minimize end-to-end delay variation due to such communications. In any case, the remultiplexing node 100 '''estimates the bit rate of each program in TS18 and TS19, using the techniques for retiming non-timing data described above, and determines the jitter of TS18 and TS19. Is removed.

On at least one communication link of the system 30 ′, a bursty device 200 may optionally also be included. For example, this communication medium is LA
As in the case of N, it is shared with other terminals that execute normal data processing. Nevertheless, the bursty device 200 is also provided for injecting data into and / or extracting data from a TS (eg, TS20). For example, the bursty type device 200 is a server for performing Internet access, a web server, a web terminal, or the like.

Of course, this is merely an example of a network distributed remultiplexing device. Other configurations are possible. For example, the communication protocol of the network connecting the nodes is ATM, DS3, or the like.

Note two important properties of the network distributed remultiplexer 30 '. As a first property, in the particular network shown, any input port can receive data, such as bursty type data or TS data, from any output port. That is, the remultiplexing node 100 'can be the remultiplexing node 100 "or 100'"
0, data can be received, and the remultiplexing node 100 ″ can receive data from the remultiplexing node 100 ′ or 100 ′ ″ or the bursty device 200, and The remultiplexing node 100 '''can receive data from any of the remultiplexing nodes 100' or 100 '' or from the bursty device 200, and further, the bursty device 200
From any of the remultiplexing nodes 100 ′, 100 ″, or 100 ′ ″,
Data can be received. As a second property, the re-multiplexing node that extracts and discards the data, ie, the re-multiplexing node 100 ′ ″, has two or more sources (ie, the re-multiplexing node 100 ′) on the same communication link. Or 100 '
Or data can be received from the bursty device 200).

As a result of the above two properties, the “signal flow pattern” of the transport packet from the source node to the destination node in the remultiplexer is independent of the network topology to which these nodes are connected is there. In other words, in the network distributed remultiplexer 30 ', the transport packets passing through the communication link paths with the nodes do not depend on whether these nodes are strictly physically connected by the communication links. Therefore, a very general network topology is used. That is, the remultiplexing nodes 100 are connected in a somewhat arbitrary topology (bus, ring, chain, tree, star, etc.), but nevertheless, so as to effectively implement any type of inter-node signal flow pattern. ,
The TS can be remultiplexed. For example, nodes 100 ', 100'',100''',
And 200 are connected in a bus topology. Nevertheless, for the data to be sent (eg, TS), any of the following signal flow patterns can be implemented. That is, from node 100 'to 100'', then to node 100'''; from each of parallel nodes 100 'and 100''' to node 200; parallel node 2
00 and 100 'to node 100 "; node 100" to node 100'
To '', etc. In this type of transmission, time division multiplexing may be required to interleave signal flows between different sets of communication nodes. For example, FIG.
In the signal flow shown in (1), TS18 and TS19 are time-division multiplexed on a shared communication medium.

The above discussion is merely illustrative of the present invention. In general, those skilled in the art will be able to devise numerous alternative embodiments without departing from the spirit and scope of the following claims.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a remultiplexing environment according to another embodiment of the present invention.

FIG. 2 illustrates a remultiplexing node using an asynchronous platform according to one embodiment of the present invention.

FIG. 3 is a flow diagram that schematically illustrates how a transport packet is processed at a remultiplexing node according to a PID, according to one embodiment of the invention.

FIG. 4 is a diagram illustrating a network-distributed remultiplexing apparatus according to an embodiment of the present invention;

────────────────────────────────────────────────── ─── Continued on the front page (31) Priority claim number 09 / 007,334 (32) Priority date January 14, 1998 (Jan. 14, 1998) (33) Priority claim country United States (US) ( 31) Priority claim number 09 / 007,203 (32) Priority date January 14, 1998 (Jan. 14, 1998) (33) Priority claim country United States (US) (31) Priority claim number 09 / 007,204 (32) Priority date January 14, 1998 (Jan. 14, 1998) (33) Priority country United States (US) (31) Priority number 09 / 007,210 (32) Priority date January 14, 1998 (Jan. 14, 1998) (33) Priority claim country United States (US) (31) Priority claim number 09 / 006,963 (32) Priority date January 14, 1998 ( 1998.1.14) (33) Priority claim country United States (US) (31) Priority claim number 09 / 006,96 (32) Priority date January 14, 1998 (Jan. 14, 1998) (33) Priority claim country United States (US) (31) Priority claim number 09 / 007,198 (32) Priority date 1998 January 14, 1998 (Jan. 14, 1998) (33) Priority claiming country United States (US) (31) Priority claim number 09/007, 199 (32) Priority date January 14, 1998 (Jan. 1998) .14) (33) Priority country United States (US) (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE) , LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG , BR, BY CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GE, GH, GM, HR, HU, ID, IL, IS, JP, KE, KG, KP, KR, KZ , LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, UZ, VN, YU, ZW (72) Inventor Slattery, William United States of America, 95030, California, Los Gatos, Almendra Avenue 314 (72) Inventor Robinet, Robert United States, California 94025, Menlo Park, Cotton Street 485 F-term (reference) 5C059 KK22 KK35 KK43 MA00 RB01 RB10 RB16 RC02 RC03 RC04 RC09 RC35 SS02 SS06 UA02 5J104 AA01 JA04 5K028 EE 03 EE05 KK01 KK12 LL12 MM08 RR02 SS23 SS24

Claims (136)

[Claims] 1. A method for optimizing the bandwidth of a transport stream, comprising: (a) a transport stream including variable transport program data and one or more null transport packets; Is received at a predetermined bit rate, and if none of the transport packets carrying the compressed program data can be used for insertion into the transport packet time slot in the received transport stream, the null
Inserting each of the transport packets into a time slot of the received transport stream to maintain the predetermined bit rate of the transport stream; and (b) one of the null transport packets. Or selectively replacing a plurality with transport packets carrying other data to be remultiplexed. 2. The method according to claim 1, wherein the transport packet carrying the data to be remultiplexed contains program-specific information. 3. The transport packet carrying the other data to be remultiplexed contains transaction data having neither a bit rate for continuously presenting information nor a transmission latency requirement. The method of claim 1, wherein (C) extracting selected ones of said transport packets of said received transport stream, discarding each unselected transport packet, and further comprising: Discarding each; (d) storing the selected transport packet; (e) storing a transport packet carrying at least one other data; and (f) storing the stored transport packet. Scheduling each of the transport packets for output to an output transport stream; and (g) outputting each of the stored transport packets to a time slot corresponding to the schedule. The method of claim 1, comprising: And (h) a corresponding one of the stored transport packets.
Outputting, for each time slot of the output transport stream for which one is scheduled, the corresponding stored transport packet scheduled for the time slot; and Outputting a null transport packet when not scheduled to output to one of the output transport streams, wherein the output transport occupied by the null transport packet of the output transport stream is The method of claim 4, wherein the bandwidth of the stream is less than the bandwidth occupied by the null transport packets in each transport stream received in step (a). 6. The transport packet carrying the data for a receiver buffer by selectively designating a transport packet carrying the data in a time slot of the output transport stream. 4. The method of claim 3, further comprising the step of adjusting the transmission bit rate. 7. A remultiplexing device for optimizing the bandwidth of a transport stream, comprising: a transport packet carrying variable compressed program data; and a transport stream including one or more null transport packets. Is received at a predetermined bit rate, and if none of the transport packets carrying the compressed program data can be used for insertion into the transport packet time slot in the received transport stream, the null A first interface that inserts each of the transport packets into a time slot of the received transport stream to maintain the predetermined bit rate of the transport stream; and one of the null transport packets. Or multiple The re-multiplexing device characterized by comprising a processor replacing selectively transport packet carrying the data to be another remultiplexing, the. 8. The remultiplexing apparatus according to claim 7, wherein the transport packet carrying the other data to be remultiplexed contains information unique to a program. 9. The transport packet carrying the other data to be remultiplexed contains transaction data having neither a bit rate nor a transmission latency requirement for constantly presenting information. The remultiplexing device according to claim 7, wherein 10. The first interface and the processor extract a selected one of the transport packets of the received transport stream, discarding each unselected transport packet, and A remultiplexer for discarding each of said null transport packets, wherein said first interface and said processor store said selected transport packets, and said processor stores at least one other data packet. Storing a transport packet carrying the stored transport packets, further comprising: a memory for scheduling the processor to output each of the stored transport packets to an output transport stream; and The above Re-multiplexing device of claim 7 wherein a second interface for outputting to the time slot, and further comprising a corresponding Joule. 11. In each time slot of the output transport stream where a corresponding one of the stored transport packets is scheduled,
The second interface outputs the corresponding stored transport packet scheduled for the time slot, and any transport packet is scheduled to output on one of the time slots. If not, the second interface outputs a null transport packet, and furthermore, the output transport stream occupied by the null transport packet of the output transport stream has a respective bandwidth. The remultiplexing device according to claim 10, wherein the bandwidth occupied by the null transport packet in each received transport stream is smaller than the bandwidth occupied by the null transport packet. 12. The transmission bit rate of the transport packet carrying the data for a receiver buffer, wherein the processor selectively designates a transport packet carrying the data as a time slot of the output transport stream. 10. The remultiplexing apparatus according to claim 9, wherein 13. (a) A transport packet containing variable compressed program data and a transport stream containing one or more null transport packets are received at a predetermined bit rate, and the compressed program data is loaded. If none of the transport packets used for insertion into the transport packet timeslots in the received transport stream can be used, each of the null transport packets is replaced by the received transport stream. Inserting into a time slot to maintain the predetermined bit rate of the transport stream; and (b) transforming one or more of the null transport packets with other data to be remultiplexed. Selective for port packets A step of changing the bandwidth optimization transport stream characterized in that it is produced by. 14. (c) extracting a selected one of said transport packets of said received transport stream, discarding each unselected transport packet, and further comprising: Discarding each; (d) storing the selected transport packet; (e) storing a transport packet carrying at least one other data; and (f) storing the stored transport packet. Scheduling each of the transport packets for output to an output transport stream; and (g) outputting each of the stored transport packets to a time slot corresponding to the schedule. Claims characterized by being produced by a process 3 bandwidth optimization bitstream according. 15. Each time slot of the output transport stream to which a corresponding one of the stored transport packets is scheduled, the corresponding stored transport scheduled for the time slot. Outputting a packet; and (i) outputting a null transport packet if no transport packet is scheduled to output in one of the time slots. The bandwidth of the output transport stream generated and occupied by the null transport packets of the output transport stream is occupied by the null transport packets in each transport stream received in step (a). Less than the bandwidth 15. The bandwidth optimized transport stream according to claim 14, wherein: 16. In the step (b), a transport packet carrying data is selectively designated as a time slot of the output transport stream, and the transport packet carrying the data to a receiver buffer is provided. 14. The bandwidth optimized transport stream according to claim 13, further comprising the step of adjusting the transmission bit rate of the transport stream. 17. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A method for remultiplexing transport packets, including transport packets containing compressed data consisting of a program clock reference timestamp of a system time clock, comprising: (a) a transport packet from a particular input port; (B) assigning an unused descriptor to the received transport packet; and (c) assigning a received timestamp indicating the time at which the transport packet was received. Recording in a child, wherein the assigned descriptors are kept in order of receipt from the particular input port in a receive queue associated with the input port. 18. The method further comprising scheduling the transmission of the received transport packet according to the reception time stamp and an internal buffering delay between receipt of the transport packet and output of the transport packet. The method of claim 17, wherein: 19. A step of: (d) examining each descriptor in said receive queue; and (e) a transmit queue associated with an output port for sending a transport packet, if any, pointed to by each examined descriptor. (G) assigning a dispatch time to the assigned descriptor of the transmission queue; and (h) ordering the descriptors of the transmission queue in descending order of dispatch time. 18. The method of claim 17, further comprising: attaching. 20. (i) transferring each transport packet indicated by a corresponding descriptor in the transmission queue from the output port to an output transport stream corresponding to the dispatch time specified in the corresponding descriptor; The method of claim 19, further comprising sending to a time slot. 21. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A method for remultiplexing transport packets, including transport packets containing compressed data comprising a program clock reference timestamp of a system time clock, comprising: (a) each description from a queue of transmission descriptors; (B) sequentially extracting the transport packets pointed to by the descriptors, and (b) at times corresponding to the dispatch times recorded in the respective extracted descriptors, Sending the retrieved transport packet to a time slot of the output transport stream corresponding to the dispatch time recorded in the retrieved descriptor. 22. (c) examining each descriptor in one or more queues of descriptors pointing to the transport packet to be output; and (d) checking each descriptor, if any, Assigning a descriptor of the transmit queue associated with an output port to send the transport packet to point to; (e) assigning a dispatch time to the assigned descriptor of the transmit queue; 22. The method of claim 21, further comprising: ordering the descriptors of a transmit queue in descending dispatch time order. 23. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A remultiplexer for remultiplexing transport packets, including transport packets containing compressed data consisting of a program clock reference timestamp of a system time clock, comprising: a cache; Receiving a port packet and assigning an unused descriptor of the cache to the received transport packet, and further receiving a time stamp indicating when the transport packet was received;
A data link control circuit connected to the cache for recording in the assigned descriptor, wherein the assigned descriptor is located in a receive queue associated with the input port. A remultiplexing apparatus characterized by being maintained in the order of reception from an input port. 24. A processor for scheduling transmission of the received transport packet according to the reception time stamp and an internal buffering delay between receipt of the transport packet and output of the transport packet. The remultiplexing apparatus according to claim 23, wherein: 25. Examining each of the descriptors in the receive queue and assigning, if any, a descriptor of the transmit queue associated with an output port to send the transport packet pointed to by the inspected descriptor; Specifying a dispatch time in the assigned descriptor of the transmit queue, and further defining the descriptor of the transmit queue:
24. The remultiplexing apparatus according to claim 23, further comprising a processor for ordering the dispatch time in descending order. 26. Transfer each transport packet indicated by a corresponding descriptor in the transmission queue from the output port to a time slot of an output transport stream corresponding to the dispatch time specified in the corresponding descriptor. 26. The remultiplexing device according to claim 25, further comprising a second data link control circuit for transmitting. 27. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A remultiplexer for remultiplexing transport packets, including transport packets containing compressed data consisting of a program clock reference timestamp of a system time clock, comprising a cache and a queue of transmit descriptors. And the transport packet pointed to by each descriptor are sequentially fetched from the cache, and the fetched description is written at a time corresponding to the dispatch time recorded in each fetched descriptor. A data link control circuit connected to the cache for sending the fetched transport packet pointed to by a child to a time slot of an output transport stream corresponding to the dispatch time recorded in the fetched descriptor. A remultiplexing device, comprising: 28. Examining each descriptor in one or more queues of descriptors pointing to the transport packet to be output, and sending the transport packet pointed to by each examined descriptor, if any, to the output port. Assigning a descriptor of the transmit queue related to, assigning a dispatch time to the assigned descriptor of the transmit queue, and further ordering the descriptors of the transmit queue in descending dispatch time order The remultiplexing device according to claim 27, further comprising a processor. 29. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A transport stream containing transport packets, including transport packets containing compressed data consisting of a program clock reference timestamp of a system time clock, comprising: (a) a transport stream from a particular input port; Receiving a packet; (b) assigning an unused descriptor to the received transport packet; (c) being assigned a receive timestamp indicating a time at which the transport packet was received. Recording in a descriptor, wherein the assigned descriptor is maintained in a receiving queue associated with the input port in the order received from the particular input port. Port stream. 30. For each of one or more video programs,
Constant end-to-end communication delay requirements, independent bit rate, and independent encoder to synchronize the decoding and presentation of the video program
A transport stream containing transport packets, including transport packets containing compressed data consisting of a program clock reference timestamp of a system time clock, comprising: (a) each stream from a transmit descriptor queue; (B) sequentially extracting the descriptors and the transport packets pointed to by each of the descriptors; and Sending the fetched transport packet to a time slot of an output transport stream corresponding to the dispatch time recorded in the fetched descriptor. 31. A method for remultiplexing a transport stream carrying one or more programs, wherein each program comprises one or more elementary streams, and each transport stream comprises one or more basic streams. A method comprising a transport packet including a transport packet carrying basic stream data for a plurality of programs, the method comprising: (a) transporting the program according to an initial user specification relating to multiplexed transport stream content; Selectively extracting only particular ones of the transport packets from each of the port streams; (b) the selected ones of the extracted transport packets; and
Transport packets containing program-specific information (if any)
Reassembling to an output multiplexed transport stream according to the initial user specification for multiplexed transport stream content; and (c) outputting the reassembled multiplexed transport stream as a continuous bit stream. (D) when performing the steps (a), (b) and (c), (I) different transport packets extracted in the step (a), (II) the step (b) )) Dynamically receiving one or more new user specifications for multiplexed transport stream content specifying one or more of the different transport packets reassembled in: Suspending said output remultiplexing transport stream in response to receiving a new user specification of Dynamically stopping the extraction or reassembly of the transport packet according to the initial user specification, and dynamically starting the extraction or reassembly of the transport packet according to the new user specification. And how to. 32. Responding to the new user specification in step (b) by regenerating the different transport packets in step (b) by generating substitute program specific information referring to transport packets of different new user specifications. 32. The method of claim 31, comprising. 33. (f) receiving the initial user specifications and respective new user specifications; and (g) total bits of the remultiplexed transport stream reassembled according to each of the received user specifications. Determining a rate request value; and (h) steps (a), (b), and (b) only if the determined bit rate request value is less than or equal to the bit rate of the output remultiplexed transport stream. e)
32. The method of claim 31, further comprising: performing. 34. (f) constantly identifying a stream that can be used to assemble the output remultiplexed transport stream; and (g) identifying the identified stream as the content for the remultiplexed transport stream. Instructing the user about the new user specification specifying the selection of available streams. 32. The method of claim 31, further comprising: 35. The new user specification specifies a new mapping of a packet identifier of one or more transport packets reassembled in step (b), and wherein step (e) specifies the new mapping. 32. The method of claim 31, comprising mapping a packet identifier of the one or more transport packets according to: 36. The method according to claim 36, wherein the new user specification specifies a step of encrypting one or more specific elementary streams, the method comprising: (a) using a control word to specify the (B) providing a transport packet containing the control word and reassembling the transport packet into the remultiplexed transport stream; and (c) any transport. Generating a transport packet containing program-specific information identifying whether the packet contains the control word and to which elementary stream the transport packet carrying the control word corresponds, 32. The method of claim 31, wherein: 37. A method for remultiplexing transport packets of one or more input transport streams into one output transport stream, wherein at least one of the input transport streams has one Or a plurality of programs and program definitions, each of said programs comprising one or more elementary streams, and wherein each of said at least one input transport stream comprises a program definition, wherein said input transport stream Which transport packet contains the basic stream data for each basic stream contained in the basic stream data, and which of the basic streams constitutes each program contained in the input transport stream, program A method for identifying by definition: (a) creating a user specification indicating that one or more programs of the input transport stream are to be output to the output transport stream; and (b) the program (C) constantly determining from the captured program definitions which elementary streams make up each program; and (d) each basic determined in step (c). Each of the programs indicated to output each transport packet containing the basic stream data of the stream to the output transport stream and to output to the user specification without interrupting the output transport stream. Performing the steps of: 38. A remultiplexing apparatus for remultiplexing a transport stream carrying one or more programs, wherein each program comprises one or more elementary streams, and each transport stream comprises: A remultiplexing device comprising a transport packet comprising a transport packet carrying elementary stream data for one or more programs, the remultiplexing device comprising: an initial user specification for multiplexed transport stream content; A first interface for selectively extracting only a specific one of the transport packets from each of the transported transport streams; a selected one of the extracted transport packets; and ) Contains program-specific information The transport packet are, by the initial user specification of multiplexed transport stream content,
A second interface for reassembling to an output multiplexed transport stream and outputting the reassembled multiplexed transport stream as a continuous bit stream; and wherein the first and second interfaces convert transport packets. When extracting and reassembling the remultiplexed transport stream for output, (I) different transport packets extracted at the first interface; (II) reassembled at the second interface. Dynamically receiving one or more new user specifications for the multiplexed transport stream content specifying one or more of different transport packets, and responding to receiving the one or more new user specifications. And said output remultiplexing transport A processor for dynamically stopping the extraction or reassembly of the transport packet according to the initial user specification and dynamically starting the extraction or reassembly of the transport packet according to the new user specification without interrupting the stream. A remultiplexing device, comprising: 39. The processor reassembles the different transport packets by generating substitute program-specific information referring to transport packets having different new user specifications and assembling the different transport packets by the second interface. 39. The remultiplexer of claim 38, responsive to a new user specification. 40. Receiving said initial user specifications and respective new user specifications and determining a total bit rate requirement value of said remultiplexed transport stream reassembled according to each received user specification; The first and second interfaces are extracted and reassembled by each of the new user interfaces only if the determined bit rate requirement is less than or equal to the bit rate of the output remultiplexed transport stream. 39. The re-multiplexing device of claim 38, further comprising a controller that enables the re-multiplexing. 41. A remultiplexer wherein the processor constantly identifies a stream that can be used to assemble the output remultiplexed transport stream, wherein the content for the remultiplexed transport stream comprises: The remultiplexing apparatus according to claim 38, further comprising a controller for instructing a user on a new user specification designating selection of the identified usable stream. 42. The new user specification specifies a new mapping of a packet identifier of one or more transport packets reassembled at the second interface, and wherein the processor causes the new mapping to 1
39. The remultiplexing apparatus according to claim 38, wherein packet identifiers of one or more transport packets are mapped. 43. A remultiplexer wherein the new user specification specifies encryption of one or more specific elementary streams, wherein the transport of the specified elementary streams is performed using a control word. A scrambler for encrypting packets, wherein the processor obtains and reassembles the transport packets containing the control words into the remultiplexed transport stream, and further comprises: 39. The remultiplexing apparatus according to claim 38, wherein the transport packet contains program-specific information for identifying whether a control word is included and to which elementary stream the control word corresponds. 44. A remultiplexing apparatus for remultiplexing transport packets of one or more input transport streams into one output transport stream, wherein at least one of the input transport streams includes One or more programs and program definitions, each of said programs comprising one or more elementary streams, and each of said at least one input transport stream comprising a program definition; Which transport packet of the input transport stream contains the basic stream data for each basic stream contained in the transport stream, and which basic stream contains each program contained in the basic stream. Make up Or a remultiplexing device identified by the program definition, wherein the controller creates a user specification indicating that one or more programs of the input transport stream are output to the output transport stream; A first adapter that constantly captures the program definition; a processor that constantly determines which basic stream constitutes each program from the captured program definition; and a basic stream data of each determined basic stream. A second adapter that constitutes each program shown to output each transport packet to the output transport stream and output to the user specification without interrupting the output transport stream; Remultiplexing characterized by comprising Location. 45. An output remultiplexed transport stream remultiplexed from a transport stream carrying one or more programs, each program comprising one or more elementary streams, and each transport stream comprising: The output remultiplexed transport stream comprising transport packets including transport packets carrying elementary stream data for one or more programs, wherein: (a) the multiplexed transport stream; Selectively extracting only specific ones of the transport packets from each of the transport streams carrying the program according to an initial user specification for content; and (b) selecting the extracted transport packets. What was done, And,
Transport packets containing program-specific information (if any)
Reassembling to an output multiplexed transport stream according to the initial user specification for multiplexed transport stream content; and (c) outputting the reassembled multiplexed transport stream as a continuous bit stream. (D) when performing the steps (a), (b) and (c), (I) different transport packets extracted in the step (a), (II) the step (b) )) Dynamically receiving one or more new user specifications for multiplexed transport stream content specifying one or more of the different transport packets reassembled in: Suspending said output remultiplexing transport stream in response to receiving a new user specification of Dynamically stopping extraction or reassembly of transport packets according to the initial user specification and dynamically starting extraction or reassembly of transport packets according to the new user specification. An output remultiplexed transport stream, characterized in that: 46. An output transport stream remultiplexed from one or more input transport streams, wherein at least one of the input transport streams includes one or more programs and program definitions. And each of the programs comprises one or more elementary streams, and each of the at least one input transport stream includes a program definition for each elementary stream contained in the input transport stream. , Which transport packet contains the basic stream data, and which of the basic streams constitute each program contained in the input transport stream. (A) creating a user specification indicating that one or more programs of the input transport stream are to be output to the output transport stream; and (b) constantly taking the program definition. (C) continually determining from the captured program definitions which elementary streams make up each program; and (d) elementary streams of each elementary stream determined in step (c). Configuring each program indicated to output each transport packet containing data to the output transport stream and to output to the user specification without interrupting the output transport stream; Output remultiplexed transport stream characterized by being generated by 47. A method for multiplexing a bit stream carrying a first video program into a second bit stream, wherein the bit stream carrying the first video program is stored therein. A timestamp for each packet of the program in the first bitstream as compared to a system time clock of an encoder, the method comprising: (A) receiving the bit stream carrying the first program from a communication link with variable end-to-end transmission delay; and (b) receiving the bit stream carrying the first video program. Each of one or a plurality of packets carrying the data of the same program is stored in the first video program. Determining a time to appear in the second bitstream based on a plurality of timestamps of the program received from the bitstream carrying the program; and (c) a constant at a time determined by the determined time. Selectively sending a selected one of said one or more packets to said second bitstream with an end-to-end delay of. 48. The step (b) comprising: (b1) storing a packet containing data received from the bit stream carrying the received first video program in a reception queue; (b2) B) identifying in the receive queue each packet containing the program data stored between the first and second specific packets containing the continuous time stamp of the program; Determining a packet rate of the program based on a difference between the first and second stamps; and (b4) determining, at a transmission time specified for the first specific packet, the packet rate; Specifying the sum of the product of the identification packet and the offset of the identification packet from the packet as the transmission time for each of the identification packets. The method of claim 47, wherein a. 49. (b5) assigning a reception time according to a local clock to a packet carrying a first time stamp received for each program carried in the first bit stream; Specifying the sum of the specified reception time and a known buffering delay as a transmission time in a packet containing the data of the packet carrying the first time stamp. 49. The method according to claim 48, wherein 50. The method according to claim 50, wherein the step (c) comprises: (c1) inserting the identification packet into the second bit stream at the time determined by the determined time. 48. The method of claim 47, further comprising preventing a buffer overflow or underflow at a receiver. 51. The receiver buffer removes the identification packet from the second bitstream according to a timestamp corresponding to a variable compression portion of the program and a restored system time clock for the program. Wherein the variable compression portion of the bit stream carrying the first video program has an estimated storage capacity of the receiver buffer and a number of bits determined by a predetermined bit rate of the first video program. The method of claim 50, wherein: 52. The step (c) comprising: (c1) determining a packet time slot of the second bitstream that is closest in time to the determined transmission time for a packet; (c2) ) If two or more packets are closest in transport time to only one of the packet time slots, then each of the packets closest in time to the single packet time slot is: (C3) specifying the time stamp of each time-stamped packet specified in one of the packet time slots other than the single packet time slot; The packet timeslot from which the specified packet timeslot is shifted from said single packet timeslot The method of claim 51, further comprising: adjusting based on a number. 53. A method of inserting each of said selected received packets into a queue during transmission, wherein said step (c3) comprises: (c4) a current length delay of said queue and an ideality of said queue. Estimating a drift between each of the one or more system time clocks of the encoder that generated the received packet and a local clock in accordance with a difference between the local clock and the local clock; Further adjusting each of the adjusted time stamps with a corresponding one of the drifts of the encoder that generated the packet with the system time clock. 52. The method of claim 52. 54. The method according to claim 47, further comprising the step of: (d) receiving a bitstream carrying the first video program from a computer network. 55. The method of claim 47, further comprising the step of: (d) receiving a bitstream carrying the first video program from an Ethernet network. 56. The method of claim 47, further comprising the step of: (d) receiving a bitstream carrying the first video program from an ATM network. 57. A remultiplexing device for multiplexing a bit stream carrying a first video program into a second bit stream, wherein the bit stream carrying the first video program has And a set of time stamps for each program stored in the first bit stream, indicating the time at which each packet of the program appears in the first bit stream, relative to the system time clock of the encoder. An asynchronous interface for receiving a bit stream carrying the first program from a communication link having a variable end-to-end transmission delay; and receiving from a bit stream carrying the first video program. One or more packets carrying the same program data A processor connected to the asynchronous interface for determining a time to appear in the second bitstream based on a plurality of timestamps of the program received from the bitstream carrying the first video program; A synchronization interface for selectively sending selected ones of said one or more packets to said second bitstream with a constant end-to-end delay at a time determined by said time. Characteristic remultiplexing device. 58. A memory for storing, in a reception queue, packets containing data received from a bit stream carrying the received first video program, wherein the program is executed in the reception queue. 1st with time stamp
Identifying each packet containing the program data stored between the first and second specific packets, and determining a packet rate of the program based on a difference between the first and second stamps. Further, a product obtained by adding a product of the packet rate and an offset of the identification packet from the first packet to a transmission time designated for the first specific packet as a transmission time is used as the identification packet. 58. The remultiplexing apparatus according to claim 57, wherein the remultiplexing device is designated for each of the following. 59. The processor further comprising a local clock accessible to the processor, the processor further comprising a first timestamp received packet for each program carried in the first bitstream. Designates a reception time according to a clock, and designates, as a transmission time, a total of the designated reception time and a known buffering delay in a packet containing data of the packet carrying the first time stamp. 59. The remultiplexing apparatus according to claim 58, wherein: 60. At the time determined by the determined time, the processor sends the packet as described above such that a buffer overflow or underflow occurs at the receiver of the second bitstream. 58. The remultiplexing device of claim 57, wherein said remultiplexing device is prevented. 61. The receiver buffer removes the identification packet from the second bitstream according to a timestamp corresponding to a variable compression portion of the program and a restored system time clock for the program. Wherein the variable compression portion of the bit stream carrying the first video program has an estimated storage capacity of the receiver buffer and a number of bits determined by a predetermined bit rate of the first video program. The remultiplexing apparatus according to claim 60, wherein: 62. The processor, wherein the processor determines, in time, a packet time slot of the second bitstream that is closest to the determined transmission time for the packet; If the processor is closest in time to only one of the packet time slots, the processor sequentially packetizes each of the packets closest to the single packet time slot in transmission time. Specifying a time slot; and wherein the processor specifies the time stamp of each time-stamped packet specified in one of the packet time slots other than the single packet time slot. Packet time slot is shifted from the single packet time slot. - based on the number of time slots, adjusting, re-multiplexing device of claim 57, wherein. 63. The asynchronous interface further comprises a memory for inserting each of the selected received packets into a queue in the memory during transmission, the processor further comprising: a current length delay of the queue; Estimating a drift between each of the one or more system time clocks of the encoder that generated the received packet and a local clock in response to a difference from an ideal length delay of the queue; and Further adjusting each of the adjusted timestamps by a corresponding one of the drifts of the local clock and the system time clock of the encoder that generated the packet. 62. The remultiplexing apparatus according to 62. 64. A multiplexing process generated by multiplexing a bitstream carrying a first video program into a second bitstream, wherein the bitstream carries the first video program. Contains a set of multiple timestamps for each program contained therein, and compares the time at which each packet of the program appears in the first bitstream with the system time clock of the encoder. A multiplexing process, comprising: (a) receiving a bit stream carrying the first video program from a communication link having a variable end-to-end transmission delay; and (b) receiving the bit stream carrying the first video program. One or more packets carrying data of the same program received from a bit stream carrying a video program Each bet is, the first
Determining a time to appear in the second bitstream based on a plurality of timestamps of the program received from the bitstream carrying the video program; and a fixed time at a time determined by the determined time. Selectively sending selected ones of said one or more packets to said second bitstream with end-to-end delay. 65. A method for timely outputting a bit stream carrying compressed video program data, comprising: (a) compressed program data of one or a plurality of video programs each having a predetermined bit rate; Providing a bit stream having transport packets that also contain a program clock reference timestamp for each of the programs that synchronize the decoding and presentation of each program; and (b) one or more of the transport packets. A dispatch time is specified for each of the plurality of selected transport packets, a predetermined bit rate of a program to which the transport packets carry data is maintained, and an average waiting time for each of the transport packets is specified. Invite (C) issuing one or more commands to an asynchronous communication interface at a time determined by each of the dispatch times to substantially minimize the jitter of the selected transport packet. At dispatch time,
Causing said corresponding selected transport packet to be sent on said asynchronous communication interface. 66. (d) allocating, to each of said transport packets, a transmission descriptor in order of said dispatch time in a queue designated to said asynchronous interface; and (e) said respective transport Recording each of the dispatch times of the transport packet in a transmit descriptor assigned to a port packet; and (f) examining the dispatch times of each of the descriptors sequentially in the queue. (G) comparing the checked dispatch time with a time generated by a local reference clock; and (h) issuing each command at the time determined by the comparison. 66. The method of claim 65, wherein the method comprises: 67. (i) At least a part of the transport packet is:
Receiving from another interface; and (j) as a function of the estimated buffering delay of the time at which each of the transport packets is received, and the reception time and the time at which the asynchronous interface generates the output. 67. The method of claim 66, further comprising: generating the dispatch time. 68. (i) selecting a transmit PID handler subroutine to perform steps (b), (d) and (e); and (j) each time one of said commands is issued. 67. The method of claim 66, further comprising: trying to repeat steps (b), (d), (e). 69. receiving the transport packet sent from the asynchronous interface at another asynchronous interface of a receiving node; and (e) at the receiving node, jitter of the received transport packet. (F) re-multiplexing at least a portion of the transport packet from which the jitter has been removed to form a second bitstream output from the receiving node, wherein the second bitstream is 66. The method of claim 65, further comprising: having a continuous end-to-end delay for each program carried in the bitstream. 70. A remultiplexing device for outputting a bit stream carrying compressed video program data in a timely manner, the compressed data comprising one or a plurality of video programs each having a predetermined bit rate; A synchronization interface that provides a bit stream having transport packets that also include a respective program clock reference timestamp of the programs that synchronizes the decoding and presentation of each program; and one or more of the transport packets. For each of the selected transport packets, a dispatch time is specified, the transport packets maintain a predetermined bit rate of the program to carry data, and the average waiting time for each of the transport packets A processor that intervenes, at a time determined by each of the dispatch times, receiving one or more commands and substantially at the dispatch time to minimize jitter in the selected transport packet. An asynchronous communication interface that responds to such a command by sending a corresponding selected transport packet. 71. A memory for storing a queue of descriptors designated for the asynchronous interface, wherein the processor assigns a transmission descriptor to each of the transport packets, and wherein the transmission descriptor is in the queue. A memory in which the dispatch times are in order, and the processor further records each of the dispatch times of the transport packets in a transmission descriptor assigned to the respective transport packets; and The dispatch time of each child is examined in turn in the queue, the examined dispatch time is compared with the time generated by the local reference clock, and each command is issued at the time determined by the comparison. And an output data link control circuit for causing Multiplexing device of claim 70, wherein. 72. The synchronous interface receives at least a portion of the transport packet output on the asynchronous interface, and wherein the processor determines a time at which each of the transport packets is received, and a reception time, 73. The multiplexing apparatus of claim 71, wherein said asynchronous interface generates said dispatch time as a function of an estimated buffering delay with said time to generate said output. 73. The processor selects a transmit PID handler subroutine to specify a dispatch time for the transport packet and to allocate a descriptor, and further to the allocated descriptor for the specified descriptor. Recording a dispatch time, and each time one of the commands is issued, the processor:
Attempting to specify a dispatch time for the next group of the transport packets, assigning a descriptor to each transport packet of the next group, and assigning the dispatch time specified to the next group of the transport packets. 72. The multiplexing apparatus according to claim 71, wherein the multiplexing apparatus records the information in the descriptor. 74. A multiplexer comprising a plurality of nodes, a second asynchronous interface of a receiving node receiving the transport packet transmitted from the asynchronous interface; and the received transformer at the receiving node. A second processor of the receiving node for removing the jitter of the port packet; and re-multiplexing at least a part of the transport packet from which the jitter has been removed to form a second bit scream output from the receiving node. The second bitstream is for each program carried in this bitstream:
71. The multiplexing device of claim 70, further comprising: an output synchronization interface adapted to have a continuous end-to-end delay. 75. A bit stream containing compressed video program data, comprising: (a) compressed program data of one or more video programs each having a predetermined bit rate; and decoding of each program. Providing a bit stream having a transport packet that also contains a program clock reference timestamp of each of the programs that synchronizes the presentation and the encoding; Specifying a dispatch time for each of the transport packets, maintaining a predetermined bit rate of a program to which the transport packets carry data, and inducing an average wait time for each of the transport packets; , (C ) At a time determined by each of the dispatch times, issuing one or more commands to the asynchronous communication interface to substantially minimize the jitter of the selected transport packet;
Causing the corresponding selected transport packet to be sent on the asynchronous communication interface. 76. (d) receiving the transport packet sent from the asynchronous interface at another asynchronous interface of a receiving node; and (e) receiving the transport packet at the receiving node. (F) re-multiplexing at least a part of the transport packet from which the jitter has been removed to form a second bitstream output from the receiving node, wherein the second bitstream is 78. The bit stream of claim 75, wherein the bit stream is generated by a further step of: having a continuous end-to-end delay for each program carried in the bit stream. . 77. A method for remultiplexing one or more bit streams containing compressed program data in an asynchronous communication network having a plurality of nodes interconnected by one or more communication links. (A) transmitting, at a destination node of the asynchronous communication network, a first bit stream that contains data of one or more programs and has a part or a plurality of predetermined bit rates, Receiving from one of the communication links; (b) selecting at least a portion of the received first bitstream for transmission; and (c) selecting the selected portion of the first bitstream. Outputting the selected portion of the first bit stream to a transport stream at a rate determined by the predetermined bit rate of Scheduling the transmission of the selected portion of the first bitstream. 78. At a plurality of nodes of the communication network, one or more portions of the bit stream are remultiplexed to contain the compressed video program data.
One or more transport streams, comprising: (a) enabling exchange between a plurality of nodes connected to a shared communication medium by one or more respective communication links; and (b) B.) Selecting a first set of one or more of the nodes and sending one or more bitstreams over the shared communication medium; and c) a second set of one or more of the one or more of the nodes. Selecting a node to receive the sent bit stream from the shared communication medium, select a portion of the sent bit stream, and select one or more as the bit stream containing the selected portion; Sending a plurality of multiplexed transport streams, in which case each of said multiplexed transport streams sent as one bit stream (D) one of a plurality of different signal flow patterns, including at least one signal flow pattern different from the topology of the node to the shared communication medium. Transmitting the bit stream at the selected node over the shared communication medium. 79. A method wherein at least one node may receive a bitstream from each of a plurality of other nodes of said node through only one of said respective communication links, wherein said subset of said subset comprises a subset of said plurality of said nodes. The method of claim 78, further comprising selecting a plurality of other nodes and receiving a bitstream at the at least one node from only the selected subset of nodes. 80. The method of claim 78, wherein at least one node receives a bitstream from a plurality of others of said nodes via only one of said respective communication links. 81. A network distributed remultiplexer for remultiplexing one or more bitstreams containing compressed program data, comprising: one or more communication links; and one or more of the one or more communication links. A plurality of nodes interconnected by a communication link to form a communication network, containing data of one or more programs,
And in part, receiving a first bit stream having one or more predetermined bit rates over one of the communication links, and transmitting at least a portion of the received first bit stream for transmission. Selecting, and at a rate determined by the predetermined bit rate of the selected portion of the first bitstream, the selected portion of the first bitstream,
A processor that schedules transmission of the selected portion of the first bitstream to output to a transport stream; a plurality of nodes, including a destination node, comprising: Remultiplexer. 82. A network distributed remultiplexer for remultiplexing one or more portions of a bitstream into one or more transport streams containing compressed video program data, comprising: A shared communication medium comprising one or more communication links; and a plurality of nodes each connected to the shared communication medium by one or more of each of the communication links, wherein one or more bit streams are A first set of ones to send over the shared communication medium
One or more of the nodes; receiving the transmitted bit stream from the shared communication medium, selecting a portion of the transmitted bit stream, and selecting 1 as a bit stream containing the selected portion. One or more multiplexed transport streams, wherein each of the multiplexed transport streams sent as a bit stream is different from the received one of the sent bit streams. Selecting one or more of the two sets of nodes and the first and second sets of nodes and at least one signal flow pattern different from the connection of the nodes to the shared communication medium. At one of a plurality of different signal flow patterns at the selected node through the shared communication medium. Network distributed remultiplexing apparatus characterized by comprising: a plurality of nodes, the comprising a controller node for transmitting the Tsu bets streams, the. 83. The method according to claim 83, wherein the plurality of nodes comprises only one of the respective communication links.
Further comprising at least one node capable of receiving a bitstream from each of a plurality of other nodes of said node, wherein said controller node selects a subset of said plurality of other nodes; 83. The network-distributed remultiplexing apparatus of claim 82, wherein said at least one node receives bitstreams only from said selected subset of nodes. 84. The method according to claim 84, wherein the plurality of nodes include only one of the respective communication links.
83. The network distributed remultiplexing apparatus of claim 82, further comprising at least one node receiving bitstreams from a plurality of other ones of said nodes. 85. A method for locking a reference clock in a circuit for transmitting and receiving a transport stream formed from a series of transport packets containing compressed data for one or more programs, the method comprising: Has a program clock reference timestamp and an independent bit rate of an independent encoder system time clock for synchronizing the decoding and presentation of the program, wherein: (a) each first receiving a transport packet; Maintaining a reference clock at the circuit and at each second circuit sending the transport packets, wherein the reference clock at each first circuit indicates a time at which each transport packet is received at each first circuit; The reference clock in each second circuit is transmitted to each transport packet. (B) selecting a master reference clock that synchronizes each other of the reference clocks; and (c) determining the current time of the master reference clock. (D) adjusting another one of the reference clocks according to a difference between the time of each of the other reference clocks and the current time of the master reference clock; Matching the time of each reference clock with the corresponding time of the master reference clock. 86. A method wherein the reference clock in one of the first and second circuits is selected as the master reference clock, and (e) in each of the first and second circuits, (F) calculating a difference between the current time of the reference clock in the one circuit and each of the first and second circuits other than the one circuit; Forming, further comprising: (g) adjusting the reference clock in each of the first and second circuits other than the one circuit to reduce the difference. Item 85. The method according to Item 85. 87. A method wherein the first and second circuits are distributed over a plurality of nodes, comprising: (e) retrieving the current time of the master reference clock at a first one of the nodes. 86. The method of claim 85, further comprising: (f) sending the received current time from the first node to a second one of the nodes via a communication link. Method. 88. A method wherein the master reference clock is geographically remote from each of the first and second circuits, and (e) periodically broadcasting the current time of the master reference clock. (
86. The method of claim 85, further comprising: transmitting; and (f) receiving, at each of the plurality of remote first and second circuits, the broadcast (transmit) current time at the same time. The described method. 89. A remultiplexer for remultiplexing a transport stream formed from a series of transport packets containing compressed data for one or more programs, each of said programs comprising: A remultiplexer having a program clock reference timestamp and an independent bit rate of an independent encoder system time clock for synchronizing decoding and presentation of the program, each indicating a time to receive each transport packet. One or more first circuits for receiving transport packets with a first reference clock, and sending transport packets with a second reference clock each indicating a time to send each transport packet. One or more second circuits, and the master The first and the second to periodically obtain the current time of the reference clock;
A master reference clock for synchronizing each of the first and second reference clocks; a difference between the time at each of the first and second reference clocks and the current time of the master reference clock; A processor that adjusts each of the reference clocks so that the times of the respective first and second reference clocks match the corresponding times of the master reference clock. Multiplexer. 90. A remultiplexer wherein a reference clock in one of the first and second circuits is selected as the master reference clock, wherein the processor is configured to control the first and second circuits. In each case, the current times of the first and second reference clocks are simultaneously taken out, and the current times of the first and second reference clocks in the one circuit;
Forming a difference between each of the first and second circuits other than the one circuit, and further forming a first and second reference clock in each of the first and second circuits other than the one circuit. 90. The remultiplexing apparatus according to claim 89, wherein the difference is reduced by adjusting. 91. A remultiplexer wherein the first and second circuits are distributed over a plurality of nodes, the communication link connecting the first and second ones of the nodes, The first node further receives a communication link for receiving the current time of the master reference clock and transmitting the received current time from the first node to another one of the nodes via a communication link. 90. The remultiplexing apparatus according to claim 89, further comprising: 92. A remultiplexer, wherein said master reference clock is geographically remote from each of said first and second circuits, wherein a periodic broadcast of said current time of said master reference clock. 9. The system of claim 8, further comprising one or more receivers for receiving at the same time.
10. The remultiplexing apparatus according to 9. 93. Each of the one or more programs includes compressed program data and, in each program, a transport packet containing a program clock reference timestamp for synchronizing decoding and presentation of the program. A method for remultiplexing one or more transport streams formed from a series of transport packets, comprising: (a) providing one or more transport streams; and (b) the one or more transport streams. Or selecting one or more transport packets of a plurality of transport streams and outputting them to a remultiplexed transport stream; and (c) determining a portion of the transport packets with a predetermined delay. Time of output transport stream Scheduling to output to a slot, wherein each of said time slots appears approximately at a dispatch time, as indicated by a local clock; and (d) a transport carrying a respective scheduled program clock reference. Adjusting each program reference timestamp of the packet based on drift of the local clock and the program system time clock that generated the program clock reference timestamp (if any); and (e) the program clock. Based on the difference between the dispatch time of the time slot scheduled to output a transport packet carrying a reference time stamp and the actual time at which the time slot appears in response to an external clock, Method characterized by comprising between adjusted step further adjust the program clock reference time stamp, a. 94. (f) scheduling another transport packet to be output to a time slot of the output transport stream other than a time slot determined by the predetermined delay; and (g) the other transport packet. The approximate adjustment value of each program clock reference timestamp in the selected transport packet output to one of the time slots is calculated as an output time difference between the other one of the time slots and the time slot corresponding to the predetermined delay. And (h) calculating each program clock reference timestamp in a transport packet carrying a program clock reference timestamp scheduled to be output in one of said other time slots, Adjusting only the approximate adjustment value. 94. The method of claim 93, wherein: 95. Compressed program data in each of the one or more programs, and in each program, a transport packet containing a program clock reference timestamp for synchronizing decoding and presentation of said program, A remultiplexer for remultiplexing one or more transport streams formed from a series of transport packets, comprising: a local clock; and one or more transport streams responsive to the local clock. And selecting one or more of the transport packets to output to a remultiplexed transport stream, and outputting a portion of the transport packets to a time slot of the output transport stream determined by a predetermined delay. Invisibility The time slot, wherein each of the time slots appears at approximately the dispatch time, as indicated by the local clock, and the program clock reference time stamp in the transport packet carrying the respective scheduled program clock reference time stamp. Responsive to a drift between the local clock and the program system time clock that generated the program clock reference timestamp (if any); and responsive to transport packets scheduled by the processor. And the dispatch time of the time slot scheduled to output a transport packet carrying the program clock reference time stamp; and Based on the difference between the actual time appearing in response to an external clock, each adjustment program re multiplexer, characterized in that it comprises clock reference output data link control circuit further adjusts the time stamp, the. 96. The processor, wherein the processor schedules another transport packet to be output to a time slot of the output transport stream other than a time slot determined by the predetermined delay; The approximate adjustment value of each program clock reference timestamp in the transport packet carrying the program clock reference timestamp scheduled to be output to one of the other time slots and the predetermined delay. 97. The remultiplexing apparatus according to claim 95, wherein the remultiplexing apparatus calculates the program clock reference time stamp based on an output time difference from the time slot to be adjusted, and adjusts each program clock reference time stamp by the approximate adjustment value. 97. Each of the one or more programs includes compressed program data, and each program includes a transport packet containing a program clock reference timestamp that synchronizes the decoding and presentation of the program. A bit stream formed from a series of transport packets, comprising: (a) providing one or more transport streams; and (b) one or more of the one or more transport streams. Selecting a transport packet and outputting it to a remultiplexed transport stream; and (c) outputting a portion of the transport packet to a time slot of the output transport stream determined by a predetermined delay. Schedule and Wherein each of said time slots appears approximately at dispatch time, as indicated by the local clock; and (d) each program reference timestamp of a transport packet carrying a respective scheduled program clock reference, Adjusting based on drift of the local clock and the program system time clock that generated the program clock reference time stamp (if any); and (e) transport packets carrying the program clock reference time stamp. A respective adjusted program clock reference time based on the difference between the dispatch time of the time slot scheduled to output the time slot and the actual time at which the time slot appears in response to an external clock. A step of further adjusting the tamp, bit stream characterized in that it is produced by. 98. (f) scheduling another transport packet to be output in a time slot of the output transport stream other than a time slot determined by the predetermined delay; and (g) the other transport packet. The approximate adjustment value of each program clock timestamp in the selected transport packet output to one of the time slots is calculated as an output time difference between the other one of the time slots and the time slot corresponding to the predetermined delay. And (h) calculating each program clock reference timestamp in a transport packet carrying a program clock reference timestamp scheduled to be output in one of said other time slots, Adjusting only the approximate adjustment value, and further steps 100. The bit stream of claim 97, wherein the bit stream is formed. 99. In each program, a constant end-to-end communication delay requirement, an independent bit rate, and a program clock of an independent encoder system time clock for synchronizing decoding and presentation of the video program A method for remultiplexing a transport packet, including a transport packet containing compressed program data comprising a reference timestamp, comprising: (a) one of a series of descriptor locations in a series of descriptor locations controlled by a cache; Assigning a descriptor of use to each received transport packet to be retained, wherein the series of descriptor locations is part of a queue assigned to a particular input port; At the transport packet storage location where the cache has gained control, the assigned descriptor Storing each retained transport packet in a transport packet storage location pointing to it; and (c) storing one or more unread queues in the queue after the last descriptor storage location where the cache has already gained control. Gaining control of the descriptor storage locations of use, and also gaining control of the transport packet storage locations pointed to by these descriptors in the one or more descriptor storage locations, Storing the transport packet storage location in a memory away from the cache by an asynchronous communication link with variable end-to-end communication delay. 100. (d) Write the data of the allocated descriptor to a corresponding descriptor storage location in the memory, and write a transport packet to a transport packet storage location indicated by the allocated descriptor. 100. The method of claim 99, further comprising writing and further writing the data to the memory over the communication link. 101. periodically examining said descriptor data written to said descriptor storage location of each queue in said memory associated with an input port; and Processing the transport packet in a transport packet storage location pointed to by a descriptor; and (g) providing an output port to a selected one or more of the descriptors in the queue associated with an input port. Assigning a descriptor of a queue associated with the output port; and (h) assigning selected information from the selected descriptor of each of the one or more queues associated with the input port to the output port. (G) ordering the descriptors in the queue related to the output port in a specific transmission order from the output port. That step a further method of claim 100, wherein the containing. 102. (i) Retrieving each descriptor of the queue associated with the output port from a second cache, each descriptor being stored in a series of descriptor storage locations in the second cache. Retrieving each transport packet from the second cache, also retrieving from the beginning, and also transport packets stored in the transport packet storage location pointed to by the respective retrieved descriptor, (j) retrieving the respective transport packets. In a unique time slot of the transport stream output from the particular output; and (k) the descriptor in which the last cached descriptor of the series of descriptor storage locations is stored. A descriptor of the queue associated with the output port in the descriptor storage location after the storage location, and a transport packet pointed to by the descriptor. Each transport packet stored in the bets storage location, The method of claim 101, wherein the further comprising a, a step of obtaining from said memory for storage in the second cache. 103. Each program has a fixed end-to-end communication delay requirement, an independent bit rate, and a program code for an independent encoder system time clock that synchronizes the decoding and presentation of the program.
A method for remultiplexing transport packets, including transport packets containing compressed program data comprising a clock reference timestamp, comprising the steps of: Retrieving each descriptor from the cache, retrieving each descriptor from the beginning of the series of descriptor locations,
Fetching each transport packet stored in the transport packet storage location pointed to by each fetched descriptor from the cache; and (b) retrieving each fetched transport packet from the specific output port. Outputting to a unique time slot of the output transport stream; and (c) the queue after the descriptor storage location where the last cached descriptor of the series of descriptor storage locations is stored. Asynchronous communication with a fixed end-to-end communication delay between one or more of the descriptors in the descriptor storage location and each transport packet stored in the transport packet storage location pointed to by the descriptor. Obtaining from said memory for storage in said cache via a link. How to with. 104. An additional queue of descriptor storage locations containing one or more descriptors pointing to one or more transport packet storage locations where the transport packets to be output are stored. (E) periodically examining the descriptor data written in the memory at each of the descriptor storage locations of the additional queue; and (f) examining the descriptor data in the memory. Processing the transport packet within a transport packet location pointed to by the specified descriptor; and (g) assigning one or more of the descriptors to the selected one of the additional queues to the output port. Allocate a descriptor for the queue and assign selected information from each selected descriptor of the one or more additional queues to the output port Copying to the assigned descriptor of the queue and ordering the assigned descriptors of the queue designated to the output port in a particular transmission order from the output port. 104. The method of claim 103, wherein the method is characterized by: 105. Each program has a fixed end-to-end communication delay requirement, independent bit rate, and independent encoder system time clock program to synchronize the decoding and presentation of said program.
A remultiplexer for remultiplexing transport packets, including transport packets containing compressed program data comprising a clock reference timestamp, comprising: a cache; and a series of descriptor storage locations from which the cache has obtained control. Is assigned to each received transport packet to be retained, wherein the series of descriptor locations is part of a queue assigned to a particular input port;
Data connected to the cache for storing each retained transport packet in the transport packet storage location pointed to by the assigned descriptor at the transport packet storage location where the cache has obtained control. Link control circuitry; and gaining control of one or more unused descriptor locations in the queue after the last descriptor location in which the cache has already gained control, and the one or more descriptions. The transport packet storage locations pointed to by these descriptors in the child storage locations also gain control, and the queue of descriptor storage locations and the transport packet storage locations can be asynchronous with an uncertain end-to-end communication delay. A communication link connected to the cache stored in a memory remote from the cache; And a direct memory access circuit. 106. The direct memory access circuit writes the data of the allocated descriptor to a corresponding descriptor storage location of the memory, and transports a transport packet to the transport indicated by the allocated descriptor. Writing to a port packet storage location and further writing the data over the asynchronous communication link
107. The remultiplexing apparatus according to claim 105, wherein writing is performed to said memory. 107. In the memory associated with the input port, periodically examine the descriptor data written to the descriptor storage location of each queue, and the transport pointed to by the examined descriptor Processing the transport packet within a packet location and assigning a descriptor of a queue associated with the output port to a selected one or more of the descriptors of the queue associated with an input port; Copying selected information from each selected descriptor of the one or more queues associated with an input port to the descriptor in the queue associated with the output port; 2. The processor of claim 1 further comprising: a processor for ordering the descriptors in the queue related to a particular transmission order from the output port. 6 remultiplexing apparatus according. 108. Retrieve a second cache and each descriptor of the queue associated with the output port from the second cache, each descriptor being a series of descriptions in the second cache. Fetching each transport packet stored at the transport packet storage location pointed to by the respective fetched descriptor from the beginning of the child storage location from the second cache; and further fetching the respective fetched transport packet. A second data link control circuit for outputting a unique time slot of a transport stream output from the specific output port, and a last cached descriptor of the series of descriptor storage locations being stored. A descriptor of the queue associated with the output port in the descriptor storage location after the descriptor storage location; A second direct memory connected to the asynchronous communication link to obtain each transport packet stored at the transport packet location pointed to by the descriptor from the memory for storage in the second cache. 108. The remultiplexing apparatus according to claim 107, further comprising: an access circuit. 109. Each program has a fixed end-to-end communication delay requirement, an independent bit rate, and an independent encoder system time clock that synchronizes the decoding and presentation of the program.
A remultiplexer for remultiplexing transport packets, including transport packets containing compressed program data consisting of a clock reference timestamp, for storing a series of descriptors in a cache and a queue designated for an output port. Retrieve each descriptor for a location from the cache, retrieving each descriptor from the beginning of the series of descriptor locations, and storing each transport stored in a transport packet location pointed to by the respective retrieved descriptor. Fetching a packet from the cache, into a unique time slot of the transport stream output from the particular output port,
A data link control circuit connected to the cache for outputting each fetched transport packet; and a descriptor storage location where the last cached descriptor of the series of descriptor storage locations is stored. Subsequent one or more descriptors in the queue's descriptor storage location and each transport packet stored in the transport packet location pointed to by the descriptor are combined with a variable end-to-end communication delay. A direct memory access circuit connected to the cache for obtaining from the memory for storage in the cache via an asynchronous communication link. 110. To store an additional queue of descriptor locations containing one or more descriptors pointing to one or more transport packet storage locations where the transport packets to be output are stored. A memory connected to the asynchronous communication link; and periodically examining, in the memory, the descriptor data written to the respective descriptor storage locations of the additional queues, and pointing to the examined descriptor. Processing the transport packet within a transport packet location and assigning a descriptor of the queue designated to the output port to a selected one or more of the descriptors of the additional queue; The selected information from each selected descriptor of one or more additional queues to the queue of the queue designated to the output port. A processor for copying to the assigned descriptor and ordering the assigned descriptors of the queue designated to the output port in a particular transmission order from the output port. Multiplexer. 111. Each program has a fixed end-to-end communication delay requirement, independent bit rate, and a program clock for an independent encoder system time clock for synchronizing decoding and presentation of the video program. A transport stream containing a transport packet, including a transport packet containing compressed program data consisting of a reference timestamp, wherein: (a) one of a series of descriptor storage locations for which the cache has obtained control; Assigning an unused descriptor to each received transport packet to be retained, wherein the series of descriptor storage locations is part of a queue assigned to a particular input port; (b) In the transport packet storage location where the cache gained control, Storing each retained transport packet in a transport packet storage location pointed to by the assigned descriptor; and (c) storing the transport packet in the queue after the last descriptor storage location where the cache has already gained control. Gaining control of one or more unused descriptor locations and also gaining control of the transport packet locations pointed to by these descriptors in said one or more descriptor locations; Storing said queue of storage locations and transport packet storage locations in a memory separate from said cache by an asynchronous communication link with variable end-to-end communication delays. A transport stream that features. 112. Each program has a fixed end-to-end communication delay requirement, an independent bit rate, and a program code for an independent encoder system time clock that synchronizes the decoding and presentation of the program.
A transport stream containing transport packets, including a transport packet containing compressed program data comprising a clock reference timestamp, comprising: (a) a series of descriptor locations in a queue designated for an output port; From the cache, fetching each descriptor from the beginning of the series of descriptor locations, and retrieving each transport packet stored in the transport packet location pointed to by each fetched descriptor. Fetching from the cache; and (b) outputting each fetched transport packet to a unique time slot of a transport stream output from the specific output port; and (c) the series. The last cached descriptor of the descriptor location The one or more descriptors in the descriptor storage location of the queue after the current descriptor storage location, and each transport packet stored in the transport packet location pointed to by the descriptor, Obtaining from a memory for storage in said cache via an asynchronous communication link with a two-to-end communication delay. 113. A method for decrypting transport packets of a transport stream containing basic stream data of one or more video programs, comprising: (a) a series of steps performed on each transport packet; Defining one or more processing stages and ordering the stages of the decryption process within said sequence of processing stages; and (b) assigning a descriptor of a queue to each transport packet; The descriptor including a pointer to the transport packet to which the descriptor is assigned, one or more processing indicators, and a storage location for control word information; and (c) the transport packet. The control word information related to the content of the Storing in the control word information storage location; and (d) setting the one or more process indicators so that a next one of the series of process steps is performed by the assigned descriptor. (E) sequentially accessing each assigned descriptor; and (f) each accessed descriptor pointing to a transport packet to be decrypted. Setting the one or more processing indicators of the accessed descriptor to indicate that decryption processing is to be performed on the accessed descriptor and the transport packet pointed to by the accessed descriptor. Only in case, the control word information in the accessed descriptor is used to decrypt the transport packet pointed to by the accessed descriptor. Method characterized by comprising that the step. 114. The method according to claim 113, wherein said control word information is a base address of a control word table. 115. (g) searching the control word table using the base address during the decryption step, and retrieving a control word from one entry of the control word table indexed by a packet identifier of the transport packet. 115. The method of claim 114, further comprising the step of retrieving, where each packet identifier uniquely indicates elementary stream data contained in the transport packet. 116. The locating step comprises: fetching the control word;
The method of claim 115, further comprising using an odd / even control word indicator of the transport packet. 117. The method of claim 114, further comprising the step of: (g) storing a control word table containing the control words and decrypting the contents of the transport packet. 118. (g) Write the decrypted transport packet data to the transport packet storage location pointed to by the pointer of the assigned descriptor, thereby decrypting the transport packet last time. (H) after examining each descriptor containing a processing indicator indicating that a decryption process is to be performed, setting one or more of the processing indicators and 114. The method of claim 113, further comprising: indicating that processing next to said processing step is to be performed on a transport packet pointed to by said descriptor. 119. A method for encrypting transport packets of a transport stream containing elementary stream data of one or more video programs, comprising: (a) a series of steps performed on each transport packet; Defining one or more stages and ordering the stages of the encryption process within said sequence of stages; (b) assigning a descriptor of a queue to each transport packet, each assigned descriptor Contains a pointer to the transport packet to which the descriptor is assigned, one or more processing indicators, and a storage location for control word information; and (c) the content of the transport packet. The control word information of the selected one of the assigned descriptors. Storing in a storage location; and (d) setting the one or more processing indicators so that the next one of the series of processing steps is performed on each of the assigned descriptors. (E) sequentially accessing each assigned descriptor; and (f) each accessed descriptor pointing to a transport packet to be encrypted. , Only if the one or more processing indicators of the accessed descriptor are set to indicate what is to be done with the accessed descriptor and the transport packet pointed to by the accessed descriptor. Encrypting the transport packet pointed to by the accessed descriptor using the control word information in the accessed descriptor. A method comprising: 120. The method according to claim 119, wherein said control word information is a control word corresponding to the content of each transport packet. 121. (g) fetching the control word from an entry of a control word table indexed by a packet identifier of the transport packet during the allocating step, wherein each packet identifier is And (h) accumulating the fetched control word in the control word storage location of the descriptor. Item 120. The method according to Item 120. 122. The method of claim 121, further comprising: (i) storing a control word table containing the control words and encrypting the content of the transport packet. 123. (g) Writing encrypted transport packet data to a transport packet storage location pointed to by said pointer of said assigned descriptor, thereby encrypting said transport packet last time. Overwriting the data; and (h) setting one or more of the process indicators after examining each descriptor containing one or more process indicators indicating that an encryption process is to be performed. 120. The method of claim 119, further comprising: indicating that processing at a next stage of the series of processing steps is performed on the transport packet indicated by the descriptor. the method of. 124. A remultiplexer for decrypting transport packets of a transport stream containing basic stream data of one or more video programs, wherein a series of ones performed on each transport packet is provided. A processor that defines one or more processing steps and orders the decryption processing within the series of processing steps; assigns a descriptor of a queue to each transport packet; A pointer to the transport packet to which a descriptor is assigned, one or more processing indicators, and a storage location for control word information; and setting the one or more processing indicators, The next step in the series of processing steps is performed on each of the assigned descriptors. And a data link control circuit indicating, sequentially, each assigned descriptor, and for each accessed descriptor that points to a transport packet to be decrypted, the decryption process includes The accessed descriptor only when the descriptor and the one or more processing indicators of the accessed descriptor are set to indicate what to do with the transport packet pointed to by the accessed descriptor. A descrambler for decrypting the transport packet pointed to by the accessed descriptor using the control word information in the descriptor, wherein the processor associates the transport packet with the content of the received transport packet. Some control word information is also stored in the control word storage location of the corresponding descriptor among the descriptors. Remultiplexing apparatus characterized by accumulation. 125. The method according to claim 124, wherein said control word information is a base address of a control word table. 126. The descrambler searches the control word table using the base address, and extracts a control word from one entry of the control word table indexed by a packet identifier of the transport packet. The remultiplexing apparatus according to claim 125, wherein each packet identifier uniquely indicates basic stream data contained in the transport packet. 127. The remultiplexer of claim 126, wherein the descrambler indexes the control word table using odd / even indicators of the transport packet to locate the control word. apparatus. 128. The remultiplexing apparatus according to claim 126, wherein the processor stores a control word table containing the control word and decrypts the content of the transport packet. 129. The descrambler writes the decrypted transport packet data to a transport packet storage location pointed to by the pointer of the allocated descriptor, thereby writing a previous value of the transport packet. After examining each descriptor that is overwritten with the decryption data and that includes a processing indicator indicating that decryption processing is to be performed, one or more of the processing indicators are set and the series of processing is performed. 13. The method of claim 12, further comprising indicating that processing of a next step is performed on the descriptor and a transport packet indicated by the descriptor.
5. The remultiplexing device according to 4. 130. A remultiplexer for encrypting transport packets of a transport stream, containing basic stream data of one or more video programs, wherein a series of ones performed on each transport packet. One or more processing steps, ordering the encryption processing steps in the series of processing steps, assigning a descriptor of a queue to each transport packet, and assigning a description to each assigned descriptor. A pointer pointing to the transport packet to which the child is assigned, one or more processing indicators, and a storage location for control word information, containing control word information related to the content of the transport packet. Storing in the control word information storage location of the selected one of the assigned descriptors;
A processor that sets one or more of the processing indicators to indicate that processing of the next stage of the series of processing steps will be performed on each of the allocated descriptors; and a respective allocated description. For each accessed descriptor that sequentially accesses the child and points to the transport packet that is to be encrypted, the encryption process proceeds with the accessed descriptor and the transport pointed to by the accessed descriptor. The control word information in the accessed descriptor is used only when the one or more processing indicators of the accessed descriptor are set to indicate what to do with the packet. And a scrambler for encrypting the transport packet indicated by the specified descriptor. 131. The remultiplexing apparatus according to claim 130, wherein the control word information is a control word corresponding to the content of each transport packet. 132. The processor retrieves the control word from one entry of a control word table indexed by a packet identifier of the transport packet, wherein each packet identifier is a basic word contained in the transport packet. 131. The remultiplexing apparatus of claim 131, wherein the remultiplexing device uniquely indicates stream data and further stores the fetched control word in the control word storage location of the descriptor. 133. The re-multiplexing apparatus according to claim 132, wherein the processor stores a control word table containing the control word and encrypts the content of the transport packet. 134. The scrambler writes the encrypted transport packet data to a transport packet storage location pointed to by the pointer of the assigned descriptor, whereby the last After examining each descriptor overwritten with encrypted data and containing one or more processing indicators indicating that encryption processing is to be performed, one or more of the processing indicators may be set. 130. The re-multiplexing apparatus according to claim 130, wherein it indicates that processing in a next step of the series of processing steps is performed on the descriptor and a transport packet indicated by the descriptor. 135. A transport stream containing decrypted transport packets containing elementary stream data of one or more video programs, comprising: (a) a series of streams executed on each transport packet; Defining one or more processing steps and ordering the decryption processing within said sequence of steps; and (b) assigning a descriptor of a queue to each transport packet, and assigning each assigned descriptor a descriptor. Contains a pointer to the transport packet to which the descriptor is assigned, one or more processing indicators, and a storage location for control word information; and (c) the content of the transport packet; Relevant control word information is stored in the control word information of the selected one of the assigned descriptors. And (d) setting one or more of the processing indicators so that the next one of the series of processing steps is performed on each of the assigned descriptors. (E) sequentially accessing each assigned descriptor; and (f) each accessed descriptor pointing to a transport packet to be decrypted, , Only if the one or more processing indicators of the accessed descriptor are set to indicate what is to be done with the accessed descriptor and the transport packet pointed to by the accessed descriptor. Using the control word information in the accessed descriptor to decrypt the transport packet pointed to by the accessed descriptor. A transport stream generated by the transport stream. 136. A transport stream containing encrypted transport packets containing elementary stream data of one or more video programs, comprising: (a) a series of streams executed on each transport packet; Defining one or more processing steps and ordering the encryption processing within said sequence of steps; (b) assigning a descriptor of a queue to each transport packet, and assigning each assigned descriptor a Contains a pointer to the transport packet to which the descriptor is assigned, one or more processing indicators, and a storage location for control word information; and (c) the content of the transport packet; Relevant control word information is stored in the control word information record of the selected one of the allocated descriptors. And (d) setting one or more of the processing indicators and performing the next one of the series of processing steps on each of the assigned descriptors. (E) sequentially accessing each assigned descriptor; and (f) for each accessed descriptor pointing to a transport packet to be encrypted, the encryption process comprises: Only if the one or more processing indicators of the accessed descriptor are set to indicate what to do with the accessed descriptor and the transport packet pointed to by the accessed descriptor Using the control word information in the accessed descriptor to encrypt the transport packet pointed to by the accessed descriptor. A transport stream characterized by being performed.