JP2002330590A - Mosfet drive circuit - Google Patents
Mosfet drive circuitInfo
- Publication number
- JP2002330590A JP2002330590A JP2001136998A JP2001136998A JP2002330590A JP 2002330590 A JP2002330590 A JP 2002330590A JP 2001136998 A JP2001136998 A JP 2001136998A JP 2001136998 A JP2001136998 A JP 2001136998A JP 2002330590 A JP2002330590 A JP 2002330590A
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- Prior art keywords
- mosfet
- circuit
- drive circuit
- transformer
- pulse
- Prior art date
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- 238000004804 winding Methods 0.000 claims abstract description 43
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 230000001360 synchronised effect Effects 0.000 claims abstract description 7
- 230000036278 prepulse Effects 0.000 claims description 13
- 230000010355 oscillation Effects 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 238000009499 grossing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- Dc-Dc Converters (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は同期整流方式のＤＣ
／ＤＣコンバータのＭＯＳＦＥＴ駆動回路に関するもの
である。The present invention relates to a synchronous rectification type DC.
The present invention relates to a MOSFET drive circuit of a DC converter.
【０００２】[0002]
【従来の技術】図６に従来のＭＯＳＦＥＴ駆動回路を示
し、このＭＯＳＦＥＴ駆動回路の動作波形図を図５に破
線で示す。７はトランス、８は主スイッチＭＯＳＦＥ
Ｔ、３はパルス発振回路、９は二次の整流ＭＯＳＦＥ
Ｔ、１０は二次の転流ＭＯＳＦＥＴ、１１は出力チョー
ク、１２は平滑コンデンサ、１８は転流側制御ＭＯＳＦ
ＥＴ、１３は二次のダイオード、１４は二次の抵抗であ
る。2. Description of the Related Art FIG. 6 shows a conventional MOSFET drive circuit, and an operation waveform diagram of the MOSFET drive circuit is shown by a broken line in FIG. 7 is a transformer, 8 is a main switch MOSFE
T, 3 are pulse oscillation circuits, 9 is a secondary rectifying MOSFE
T, 10 is a secondary commutation MOSFET, 11 is an output choke, 12 is a smoothing capacitor, and 18 is a commutation side control MOSFET.
ET, 13 is a secondary diode, and 14 is a secondary resistor.
【０００３】従来のＭＯＳＦＥＴ駆動回路は、一次−二
次間が絶縁されたトランス７の一次巻線、二次巻線及び
三次巻線からなる同期整流回路であり、転流ＭＯＳＦＥ
Ｔ１０のゲート・ソース間に転流側制御ＭＯＳＦＥＴ１
８のドレイン・ソースを接続してある。また、トランス
７の一次巻線に主スイッチＭＯＳＦＥＴ８を接続し、主
スイッチＭＯＳＦＥＴ８のゲート・ソース間に、主スイ
ッチＭＯＳＦＥＴ８を駆動させるパルス発振回路３を接
続してある。A conventional MOSFET drive circuit is a synchronous rectifier circuit comprising a primary winding, a secondary winding and a tertiary winding of a transformer 7 in which the primary and secondary are insulated.
Commutation side control MOSFET 1 between gate and source of T10
8 are connected to the drain and source. A main switch MOSFET 8 is connected to the primary winding of the transformer 7, and a pulse oscillation circuit 3 for driving the main switch MOSFET 8 is connected between the gate and the source of the main switch MOSFET 8.
【０００４】出力チョーク１１と平滑コンデンサ１２と
の直列回路に転流ＭＯＳＦＥＴ１０を並列に接続し、こ
の転流ＭＯＳＦＥＴ１０の一端をトランス７の二次巻線
の一方側に直列に接続し、その他端を、整流ＭＯＳＦＥ
Ｔ９を介して二次巻線の他方側に接続してある。また、
整流ＭＯＳＦＥＴ９のゲートをトランス７の二次巻線と
出力チョーク１１との間に設けた接続部に接続してあ
る。さらに、転流ＭＯＳＦＥＴ１０のゲートをトランス
７の三次巻線の一方側に接続し、この三次巻線の他方側
にダイオード１３と抵抗１４とを並列に接続した回路を
接続し、この回路を転流側のＭＯＳＦＥＴ１０，１８の
ソース側に接続してある。なお、ダイオード１３のカソ
ードとトランス７の三次巻線とが接続してある。転流側
制御ＭＯＳＦＥＴ１８のゲート・ソース間にトランス７
の四次巻線を接続してある。A commutation MOSFET 10 is connected in parallel to a series circuit of an output choke 11 and a smoothing capacitor 12, one end of the commutation MOSFET 10 is connected in series to one side of a secondary winding of a transformer 7, and the other end is connected. , Rectifying MOSFE
It is connected to the other side of the secondary winding via T9. Also,
The gate of the rectifying MOSFET 9 is connected to a connection provided between the secondary winding of the transformer 7 and the output choke 11. Further, the gate of the commutation MOSFET 10 is connected to one side of a tertiary winding of the transformer 7, and the other side of the tertiary winding is connected to a circuit in which a diode 13 and a resistor 14 are connected in parallel. Are connected to the source sides of the MOSFETs 10 and 18 on the other side. The cathode of the diode 13 and the tertiary winding of the transformer 7 are connected. Transformer 7 between the gate and source of commutation side control MOSFET 18
Are connected.
【０００５】以上のように構成してあるＭＯＳＦＥＴ駆
動回路は、以下のように動作する。パルス発振回路３か
ら出力される矩形波パルスにより主スイッチＭＯＳＦＥ
Ｔ８がオンする時、二次側は、転流ＭＯＳＦＥＴ１０が
オン、整流ＭＯＳＦＥＴ９がオフ状態である。主スイッ
チＭＯＳＦＥＴ８のオンにより転流ＭＯＳＦＥＴ１０が
オフ、整流ＭＯＳＦＥＴ９がオンするが、この時、主ス
イッチＭＯＳＦＥＴ８と転流ＭＯＳＦＥＴ１０のオン期
間がごく短期間動作遅れにより重なるため、この期間、
トランス７を介して二次側に転流ＭＯＳＦＥＴ１０−整
流ＭＯＳＦＥＴ９のルートで二次側貫通電流が流れる。
その直後に転流ＭＯＳＦＥＴ１０がオフすると、短絡状
態は解除され、整流ＭＯＳＦＥＴ９−転流ＭＯＳＦＥＴ
１０のルートの貫通電流は出力チョーク１１及び平滑コ
ンデンサ１２に流れる。[0005] The MOSFET drive circuit configured as described above operates as follows. The main switch MOSFE is generated by a rectangular wave pulse output from the pulse oscillation circuit 3.
When T8 is turned on, the commutation MOSFET 10 is on and the rectifier MOSFET 9 is off on the secondary side. When the main switch MOSFET 8 is turned on, the commutation MOSFET 10 is turned off, and the rectification MOSFET 9 is turned on.
A secondary-side through current flows through the route of the commutation MOSFET 10 and the rectification MOSFET 9 to the secondary side via the transformer 7.
When the commutation MOSFET 10 is turned off immediately thereafter, the short-circuit state is released and the rectification MOSFET 9 -commutation MOSFET
The through current of route 10 flows through output choke 11 and smoothing capacitor 12.
【０００６】[0006]
【発明が解決しようとする課題】従来のＭＯＳＦＥＴ駆
動回路は、パルス発生回路３から出力される駆動用の矩
形波パルスを直接主スイッチＭＯＳＦＥＴ８のゲートへ
入力してある。そのため、充電時定数が小さく、主スイ
ッチＭＯＳＦＥＴ８は極めて短い遅れ時間でＯＮ状態に
なり、高効率化のために二次側に同期整流回路を採用し
ている場合などには、二次側整流回路の低いインピーダ
ンスのみによって制御される貫通電流が発生するという
課題が生じた。また、貫通電流により、同期整流用素子
に印加するサージ電圧も増加するため、耐圧オーバーを
引き起こすおそれもあった。In the conventional MOSFET driving circuit, the driving rectangular wave pulse output from the pulse generating circuit 3 is directly input to the gate of the main switch MOSFET 8. Therefore, the charging time constant is small, the main switch MOSFET 8 is turned on with an extremely short delay time, and when a synchronous rectification circuit is used on the secondary side for high efficiency, the secondary rectification circuit is used. However, there arises a problem that a through current controlled by only a low impedance is generated. Moreover, the surge voltage applied to the synchronous rectifying element increases due to the through current, so that the breakdown voltage may be exceeded.
【０００７】本発明は、上記課題に鑑みてなされたもの
であり、貫通電流を抑制し、整流素子に印加するサージ
電圧を低減するＭＯＳＦＥＴ駆動回路を提供するもので
ある。The present invention has been made in view of the above problems, and provides a MOSFET drive circuit that suppresses a through current and reduces a surge voltage applied to a rectifying element.
【０００８】[0008]
【課題を解決するための手段】請求項１の発明は、主ス
イッチ駆動回路を設けたことにより、主スイッチを駆動
する際、主スイッチのＭＯＳＦＥＴの非飽和領域を利用
し、一次側のスイッチで電圧を持たせながらＯＮさせる
ことで、貫通電流を抑制し、さらに、整流素子に印加す
るサージ電圧を低減させることを可能にした。According to the first aspect of the present invention, when the main switch is driven, the non-saturated region of the MOSFET of the main switch is used to drive the main switch. By turning on while giving a voltage, it is possible to suppress a through current and further reduce a surge voltage applied to the rectifying element.
【０００９】請求項３、４又は５の発明は、主スイッチ
駆動回路と事前パルス回路とを設けたことにより、電力
効率向上を可能にした。According to the third, fourth or fifth aspect of the present invention, power efficiency can be improved by providing a main switch drive circuit and a pre-pulse circuit.
【００１０】[0010]
【発明の実施の形態】以下、本発明に係るＭＯＳＦＥＴ
駆動回路の好ましい実施の形態を図面に基づいて説明す
る。図１は本発明に係るＭＯＳＦＥＴ駆動回路の好まし
い実施の形態を示す回路図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a MOSFET according to the present invention will be described.
A preferred embodiment of the drive circuit will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a preferred embodiment of a MOSFET drive circuit according to the present invention.
【００１１】本実施例のＭＯＳＦＥＴ駆動回路は、上記
従来例と同様に、一次−二次間が絶縁されたトランス７
の一次巻線、二次巻線及び三次巻線からなる同期整流回
路であり、転流ＭＯＳＦＥＴ１０のゲート・ソース間に
転流側制御ＭＯＳＦＥＴ１８のドレイン・ソースを接続
してある。The MOSFET drive circuit of the present embodiment has a transformer 7 whose primary and secondary are insulated in the same manner as in the conventional example.
The synchronous rectifier circuit includes a primary winding, a secondary winding, and a tertiary winding. The drain / source of the commutation-side control MOSFET 18 is connected between the gate and source of the commutation MOSFET 10.
【００１２】出力チョーク１１と平滑コンデンサ１２と
の直列回路に転流ＭＯＳＦＥＴ１０を並列に接続し、こ
の転流ＭＯＳＦＥＴ１０の一端をトランス７の二次巻線
の一方側に直列に接続し、その他端を、整流ＭＯＳＦＥ
Ｔ９を介して二次巻線の他方側に接続してある。また、
整流ＭＯＳＦＥＴ９のゲートをトランス７の二次巻線と
出力チョーク１１との間に設けた接続部に接続してあ
る。さらに、転流ＭＯＳＦＥＴ１０のゲートをトランス
７の三次巻線の一方側に接続し、この三次巻線の他方側
にダイオード１３と抵抗１４とを並列に接続した回路を
接続し、この回路を転流側のＭＯＳＦＥＴ１０，１８の
ソース側に接続してある。なお、ダイオード１３のカソ
ードとトランス７の三次巻線とが接続してある。転流側
制御ＭＯＳＦＥＴ１８のゲート・ソース間にトランス７
の四次巻線を接続してある。A commutation MOSFET 10 is connected in parallel to a series circuit of an output choke 11 and a smoothing capacitor 12, one end of the commutation MOSFET 10 is connected in series to one side of a secondary winding of a transformer 7, and the other end is connected. , Rectifying MOSFE
It is connected to the other side of the secondary winding via T9. Also,
The gate of the rectifying MOSFET 9 is connected to a connection provided between the secondary winding of the transformer 7 and the output choke 11. Further, the gate of the commutation MOSFET 10 is connected to one side of a tertiary winding of the transformer 7, and the other side of the tertiary winding is connected to a circuit in which a diode 13 and a resistor 14 are connected in parallel. Are connected to the source sides of the MOSFETs 10 and 18 on the other side. The cathode of the diode 13 and the tertiary winding of the transformer 7 are connected. Transformer 7 between the gate and source of commutation side control MOSFET 18
Are connected.
【００１３】本実施例は、一次側に主スイッチ駆動回路
１を設けてあることに特徴を有する。主スイッチ駆動回
路１はトランス７の一次巻線に接続した主スイッチＭＯ
ＳＦＥＴ８のゲートに接続してあり、この主スイッチ駆
動回路１は、インダクタ４とコンデンサ５とダイオード
６とをそれぞれ並列に接続し、このダイオード６はアノ
ードが主スイッチＭＯＳＦＥＴ８のゲートに接続される
向きに接続してある。また、主スイッチ駆動回路１と主
スイッチＭＯＳＦＥＴ８のソースの間にパルス発振回路
３を接続してある。なお、本実施例のパルス発振回路３
を集積回路で構成してある（以下「集積回路３」とい
う。）。This embodiment is characterized in that a main switch drive circuit 1 is provided on the primary side. The main switch drive circuit 1 includes a main switch MO connected to a primary winding of a transformer 7.
The main switch drive circuit 1 connects the inductor 4, the capacitor 5, and the diode 6 in parallel with each other. The diode 6 is connected in the direction in which the anode is connected to the gate of the main switch MOSFET 8. Connected. A pulse oscillation circuit 3 is connected between the main switch drive circuit 1 and the source of the main switch MOSFET 8. Note that the pulse oscillation circuit 3 of the present embodiment
Is constituted by an integrated circuit (hereinafter, referred to as “integrated circuit 3”).
【００１４】本実施例は以上のように構成し、以下のよ
うな作用をする。先ず、主スイッチＭＯＳＦＥＴ８がオ
ンすると、集積回路３から矩形波パルスが出力される。
そして、このパルス電圧は主スイッチ駆動回路１のコン
デンサ５と主スイッチＭＯＳＦＥＴ８の内部コンデンサ
で分圧され、主スイッチＭＯＳＦＥＴ８のゲートに印加
される。この時、コンデンサ５を主スイッチＭＯＳＦＥ
Ｔ８のゲート閾値電圧Ｖｔｈになるように容量選定すれ
ば、非飽和領域による貫通電流抑制効果が得られる。そ
の後、主スイッチＭＯＳＦＥＴ８のゲート閾値電圧Ｖｔ
ｈから主スイッチ駆動回路１のインダクタ４とコンデン
サ５及び主スイッチＭＯＳＦＥＴ８の内部コンデンサの
共振作用でゲート電圧は上昇し、パルス電圧の波高値ま
で上昇する。その際の時間は、インダクタ４の値の選択
で制御でき、大きくする程共振周波数が低くなるため緩
やかに上昇する。The present embodiment is configured as described above and operates as follows. First, when the main switch MOSFET 8 is turned on, the integrated circuit 3 outputs a rectangular wave pulse.
Then, this pulse voltage is divided by the capacitor 5 of the main switch drive circuit 1 and the internal capacitor of the main switch MOSFET 8 and applied to the gate of the main switch MOSFET 8. At this time, the capacitor 5 is connected to the main switch MOSFET.
If the capacitance is selected so as to be equal to the gate threshold voltage Vth of T8, an effect of suppressing a through current by the unsaturated region can be obtained. Thereafter, the gate threshold voltage Vt of the main switch MOSFET 8
From h, the gate voltage rises due to the resonance action of the inductor 4 and the capacitor 5 of the main switch drive circuit 1 and the internal capacitor of the main switch MOSFET 8, and rises to the peak value of the pulse voltage. The time at that time can be controlled by selecting the value of the inductor 4, and as the value is increased, the resonance frequency becomes lower, so that the time gradually increases.
【００１５】この際二次側は、整流ＭＯＳＦＥＴ９がオ
ンし、転流ＭＯＳＦＥＴ１０がオフするが、主スイッチ
ＭＯＳＦＥＴ８と転流ＭＯＳＦＥＴ１０のオン期間がご
く短期間動作遅れにより重なるため、この期間、前述の
ようにトランス７を介して二次側に転流ＭＯＳＦＥＴ１
０−整流ＭＯＳＦＥＴ９のルートで二次側貫通電流が流
れようとする。しかし、本実施例においては、主スイッ
チ駆動に非飽和領域による貫通電流抑制効果があるた
め、二次側貫通電流は制限される。従って、転流ＭＯＳ
ＦＥＴ１０がオフし短絡状態は解除されても、二次側の
電圧が急激に上昇せずに抑制され、転流ＭＯＳＦＥＴ１
０の耐圧オーバーは発生しない。At this time, on the secondary side, the rectifier MOSFET 9 is turned on and the commutation MOSFET 10 is turned off. Commutation MOSFET 1 to the secondary side via transformer 7
The secondary side through current tries to flow at the route of the 0-rectifier MOSFET 9. However, in this embodiment, since the driving of the main switch has the effect of suppressing the through current due to the non-saturation region, the secondary side through current is limited. Therefore, commutation MOS
Even if the FET 10 is turned off and the short-circuit state is released, the voltage on the secondary side is suppressed without abrupt increase, and the commutation MOSFET 1
No overvoltage of 0 occurs.
【００１６】図２は、図１とは別のＭＯＳＦＥＴ駆動回
路の実施形態を示す回路図であり、この実施例の方式に
よる動作波形図を図５に実線で示してある。この実施例
は前記実施例と略同様であるが、事前パルス送出回路２
を設けてあることに特徴を有する。本実施例のＭＯＳＦ
ＥＴ駆動回路にトランス７とは別にパルストランス１５
を設け、このパルストランス１５の一次巻線と並列にダ
イオード１７を設け、このダイオード１７のアノードと
主スイッチＭＯＳＦＥＴ８のゲートとが接続される向き
に接続してある。このように構成した回路に直列に且つ
ダイオード１７のカソードと接続する向きにコンデンサ
１６を接続し、これらを集積回路３と並列に接続すると
ともに、転流側制御ＭＯＳＦＥＴ１８のゲートと転流Ｍ
ＯＳＦＥＴ１０のソースの間にパルストランス１５の二
次巻線を接続してある。FIG. 2 is a circuit diagram showing an embodiment of a MOSFET drive circuit different from that of FIG. 1, and an operation waveform diagram according to the method of this embodiment is shown by a solid line in FIG. This embodiment is substantially the same as the previous embodiment, except that the pre-pulse sending circuit 2
Is provided. MOSF of the present embodiment
A pulse transformer 15 is provided separately from the transformer 7 in the ET drive circuit.
And a diode 17 is provided in parallel with the primary winding of the pulse transformer 15, and is connected in a direction in which the anode of the diode 17 and the gate of the main switch MOSFET 8 are connected. A capacitor 16 is connected in series to the circuit configured as described above in a direction to connect to the cathode of the diode 17, and these are connected in parallel with the integrated circuit 3, and the gate of the commutation side control MOSFET 18 and the commutation M
The secondary winding of the pulse transformer 15 is connected between the sources of the OSFET 10.
【００１７】本実施例は以上のように構成し、以下のよ
うな作用をする。先ず、主スイッチＭＯＳＦＥＴ８がオ
ンすると、集積回路３から矩形波パルスが出力される。
そして、このパルス電圧は主スイッチ駆動回路１のコン
デンサ５と主スイッチＭＯＳＦＥＴ８の内部コンデンサ
で分圧され、主スイッチＭＯＳＦＥＴ８のゲートに印加
される。この時、コンデンサ５を主スイッチＭＯＳＦＥ
Ｔ８のゲート閾値電圧Ｖｔｈになるように容量選定すれ
ば、非飽和領域による貫通電流抑制効果が得られる。そ
の後、主スイッチＭＯＳＦＥＴ８のゲート閾値電圧Ｖｔ
ｈから主スイッチ駆動回路１のインダクタ４とコンデン
サ５及び主スイッチＭＯＳＦＥＴ８の内部コンデンサの
共振作用でゲート電圧は上昇し、パルス電圧の波高値ま
で上昇する。その際の時間は、インダクタ４の値の選択
で制御でき、大きくする程共振周波数が低くなるため緩
やかに上昇する。The present embodiment is configured as described above and operates as follows. First, when the main switch MOSFET 8 is turned on, the integrated circuit 3 outputs a rectangular wave pulse.
Then, this pulse voltage is divided by the capacitor 5 of the main switch drive circuit 1 and the internal capacitor of the main switch MOSFET 8 and applied to the gate of the main switch MOSFET 8. At this time, the capacitor 5 is connected to the main switch MOSFET.
If the capacitance is selected so as to be equal to the gate threshold voltage Vth of T8, an effect of suppressing a through current by an unsaturated region can be obtained. Thereafter, the gate threshold voltage Vt of the main switch MOSFET 8
From h, the gate voltage rises due to the resonance action of the inductor 4 and the capacitor 5 of the main switch drive circuit 1 and the internal capacitor of the main switch MOSFET 8, and rises to the peak value of the pulse voltage. The time at that time can be controlled by selecting the value of the inductor 4, and as the value is increased, the resonance frequency becomes lower, so that the time gradually increases.
【００１８】集積回路３から矩形波パルスが出力される
と、事前パルス送出回路２を構成するパルストランス１
５に電流が流れ、転流側制御ＭＯＳＦＥＴ１８がオンす
る。これに伴い転流ＭＯＳＦＥＴ１０はオフする。ま
た、主スイッチＭＯＳＦＥＴ８がオンすることにより、
整流ＭＯＳＦＥＴ９がオンする。転流ＭＯＳＦＥＴ１０
は前述したように事前パルス送出回路２の作用によりオ
フする。即ち、本実施例により、主スイッチＭＯＳＦＥ
Ｔ８に非飽和領域を持たせることにより、転流ＭＯＳＦ
ＥＴ１０の電圧を抑制することができるとともに、事前
パルス送出回路２の作用により、主スイッチＭＯＳＦＥ
Ｔ８、整流ＭＯＳＦＥＴ９及び転流ＭＯＳＦＥＴ１０の
ＯＮ／ＯＦＦ切り替えをスムーズに行うことができ、選
り二次側貫通電流を低減可能とし電力効率を向上させる
ことができる。When a rectangular wave pulse is output from the integrated circuit 3, the pulse transformer 1 constituting the pre-pulse sending circuit 2
5, a commutation-side control MOSFET 18 is turned on. Accordingly, the commutation MOSFET 10 is turned off. When the main switch MOSFET 8 is turned on,
The rectifying MOSFET 9 turns on. Commutation MOSFET10
Is turned off by the action of the pre-pulse sending circuit 2 as described above. That is, according to the present embodiment, the main switch MOSFE
By providing the T8 with an unsaturated region, the commutation MOSF
The voltage of ET10 can be suppressed, and the operation of the pre-pulse sending circuit 2 allows the main switch MOSFE
ON / OFF switching of the T8, the rectifying MOSFET 9 and the commutation MOSFET 10 can be performed smoothly, and the selected secondary-side through current can be reduced to improve power efficiency.
【００１９】図３は、前記実施例とは別のＭＯＳＦＥＴ
駆動回路の実施形態を示す回路図である。この実施例は
前記実施例と略同様であるが、図２図示実施例とは異な
る構成の事前パルス送出回路２を設けてあることに特徴
を有する。本実施例のＭＯＳＦＥＴ駆動回路にパルスト
ランス１５を設け、このパルストランス１５の一次巻線
と主スイッチ駆動回路１との間にコンデンサ１６を接続
し、このコンデンサ１６とパルストランス１５の一次巻
線をパルス発振回路３と並列に接続してある。また、転
流側制御ＭＯＳＦＥＴ１８のゲートと転流ＭＯＳＦＥＴ
１０のソースの間にパルストランス１５の二次巻線を接
続し、この二次巻線と並列にダイオード１９を設け、カ
ソードが転流側制御ＭＯＳＦＥＴ１８のゲートに接続さ
れる向きに、このダイオード１９を接続してある。な
お、作用については、図３図示実施例と略同様である。FIG. 3 shows a MOSFET different from the above embodiment.
FIG. 3 is a circuit diagram illustrating an embodiment of a drive circuit. This embodiment is substantially the same as the previous embodiment, but is characterized in that a pre-pulse sending circuit 2 having a different configuration from the embodiment shown in FIG. 2 is provided. A pulse transformer 15 is provided in the MOSFET drive circuit of the present embodiment, a capacitor 16 is connected between the primary winding of the pulse transformer 15 and the main switch drive circuit 1, and the capacitor 16 and the primary winding of the pulse transformer 15 are connected. It is connected in parallel with the pulse oscillation circuit 3. Also, the gate of the commutation side control MOSFET 18 and the commutation MOSFET
The secondary winding of the pulse transformer 15 is connected between the sources of the DC / DC converter 10 and a diode 19 is provided in parallel with the secondary winding. Is connected. The operation is substantially the same as that of the embodiment shown in FIG.
【００２０】図４は、前記実施例とは別のＭＯＳＦＥＴ
駆動回路の実施形態を示す回路図である。この実施例は
図２図示実施例と略同様に構成してあり、主トランス駆
動回路１のインダクタ４を、パルストランス１５の巻線
にし、主トランス駆動回路１と事前パルス送出回路２と
を一体化してあることを特徴とする。なお、作用につい
ては、図２及び図３図示実施例と略同様である。なお、
図４図示実施例と略同様に構成し、主トランス駆動回路
１のインダクタ４を、パルストランス１５の巻線にする
ことも可能である。FIG. 4 shows a MOSFET different from the above embodiment.
FIG. 3 is a circuit diagram illustrating an embodiment of a drive circuit. This embodiment is substantially the same as the embodiment shown in FIG. 2, in which the inductor 4 of the main transformer driving circuit 1 is used as a winding of a pulse transformer 15, and the main transformer driving circuit 1 and the pre-pulse sending circuit 2 are integrated. It is characterized by having been converted. The operation is substantially the same as in the embodiment shown in FIGS. In addition,
4, the inductor 4 of the main transformer drive circuit 1 can be a winding of the pulse transformer 15.
【００２１】[0021]
【発明の効果】本発明の効果としては、請求項1の発明
により、主スイッチ駆動回路を設けたことにより、主ス
イッチを駆動する際、主スイッチのＭＯＳＦＥＴの非飽
和領域を利用し、一次側のスイッチで電圧を持たせなが
らＯＮさせることで、貫通電流を抑制し、さらに、二次
側整流素子に印加するサージ電圧を低減させることを可
能にした。加えて、主スイッチ駆動回路のコンデンサ及
び主スイッチＭＯＳＦＥＴの内部コンデンサの電圧を制
御することができ、主スイッチ駆動回路のコンデンサを
主スイッチＭＯＳＦＥＴのゲート閾値電圧になるように
容量選定することにより非飽和領域による貫通電流抑制
効果を得ることを可能にした。According to the present invention, the main switch drive circuit is provided according to the first aspect of the present invention, and when the main switch is driven, the non-saturated region of the MOSFET of the main switch is used and the primary side is driven. By turning on the switch while applying a voltage, the through current can be suppressed, and the surge voltage applied to the secondary-side rectifying element can be reduced. In addition, the voltage of the capacitor of the main switch drive circuit and the internal capacitor of the main switch MOSFET can be controlled, and the saturation of the capacitor of the main switch drive circuit is selected by selecting the capacitance so as to be the gate threshold voltage of the main switch MOSFET. It is possible to obtain the effect of suppressing the through current by the region.
【００２２】請求項３、４又は５の発明は、主スイッチ
駆動回路と事前パルス回路とを設けたことにより、電力
効率向上を可能にした。According to the third, fourth or fifth aspect of the present invention, power efficiency can be improved by providing the main switch driving circuit and the pre-pulse circuit.
【図１】本発明に係るＭＯＳＦＥＴ駆動回路の好ましい
実施の形態を示す回路図である。FIG. 1 is a circuit diagram showing a preferred embodiment of a MOSFET drive circuit according to the present invention.
【図２】図１図示実施例とは別のＭＯＳＦＥＴ駆動回路
の回路図である。FIG. 2 is a circuit diagram of another MOSFET drive circuit different from the embodiment shown in FIG. 1;
【図３】前記実施例とは別のＭＯＳＦＥＴ駆動回路の回
路図である。FIG. 3 is a circuit diagram of another MOSFET drive circuit different from the embodiment.
【図４】前記実施例とは別のＭＯＳＦＥＴ駆動回路の回
路図である。FIG. 4 is a circuit diagram of another MOSFET drive circuit different from the embodiment.
【図５】本発明の方式及び従来の方式による動作波形図
である。FIG. 5 is an operation waveform diagram according to a method of the present invention and a conventional method.
【図６】従来のＭＯＳＦＥＴ駆動回路の回路図である。FIG. 6 is a circuit diagram of a conventional MOSFET drive circuit.
１ 主スイッチ駆動回路 ２ 事前パルス送出回路 ３ パルス発振回路 ４ インダクタ ５ コンデンサ ６ ダイオード ７ トランス ８ 主スイッチＭＯＳＦＥＴ ９ 整流ＭＯＳＦＥＴ １０ 転流ＭＯＳＦＥＴ １１ 出力チョーク １２ 平滑コンデンサ １３ ダイオード １４ 抵抗 １５ パルストランス １６ コンデンサ １７ ダイオード １８ 転流側制御ＭＯＳＦＥＴ １９ ダイオード ２０ 主スイッチ駆動回路１と事前パルス送出回路２と
を一体化した回路DESCRIPTION OF SYMBOLS 1 Main switch drive circuit 2 Pre-pulse sending circuit 3 Pulse oscillation circuit 4 Inductor 5 Capacitor 6 Diode 7 Transformer 8 Main switch MOSFET 9 Rectification MOSFET 10 Commutation MOSFET 11 Output choke 12 Smoothing capacitor 13 Diode 14 Resistance 15 Pulse transformer 16 Diode 17 Diode 18 Commutation side control MOSFET 19 Diode 20 Circuit integrating main switch drive circuit 1 and pre-pulse sending circuit 2
Claims (5)
次巻線、二次巻線及び三次巻線からなる同期整流回路に
おいて、転流ＭＯＳＦＥＴのゲート・ソース間に転流側
制御ＭＯＳＦＥＴのドレイン・ソースを接続し、前記ト
ランスの一次巻線に主スイッチＭＯＳＦＥＴを接続し、
この主スイッチＭＯＳＦＥＴのゲートに、インダクタと
コンデンサとダイオードとをそれぞれ並列に接続して構
成してある主スイッチ駆動回路を接続し、この主スイッ
チ駆動回路と前記主スイッチＭＯＳＦＥＴのソースの間
に、パルス発振回路を接続してあることを特徴とするＭ
ＯＳＦＥＴ駆動回路。In a synchronous rectifier circuit comprising a primary winding, a secondary winding and a tertiary winding of a transformer having a primary-secondary insulation, a commutation-side control MOSFET of a commutation side MOSFET is provided between a gate and a source of a commutation MOSFET. Connecting the drain-source, connecting the main switch MOSFET to the primary winding of the transformer,
A main switch drive circuit configured by connecting an inductor, a capacitor, and a diode in parallel to each other is connected to the gate of the main switch MOSFET, and a pulse is applied between the main switch drive circuit and the source of the main switch MOSFET. M, characterized in that an oscillation circuit is connected.
OSFET drive circuit.
路において、前記パルス発振回路を集積回路で構成して
あることを特徴とするＭＯＳＦＥＴ駆動回路。2. The MOSFET drive circuit according to claim 1, wherein said pulse oscillation circuit is constituted by an integrated circuit.
駆動回路において、前記トランスとは別にパルストラン
スを設け、このパルストランスの一次巻線と並列にダイ
オードを設け、このダイオードのアノードと前記主スイ
ッチＭＯＳＦＥＴのゲートとが接続される向きに接続し
た回路を設け、この回路に直列に且つ前記ダイオードの
カソードと接続する向きにコンデンサを接続し、これら
を前記パルス発振回路と並列に接続するとともに、前記
転流側制御ＭＯＳＦＥＴのゲートと前記転流ＭＯＳＦＥ
Ｔのソースの間に前記パルストランスの二次巻線を接続
して構成してある事前パルス送出回路を設けてあること
を特徴とするＭＯＳＦＥＴ駆動回路。3. The MOSFET according to claim 1, wherein
In the drive circuit, a pulse transformer is provided separately from the transformer, a diode is provided in parallel with the primary winding of the pulse transformer, and a circuit is connected in a direction in which an anode of the diode is connected to a gate of the main switch MOSFET. A capacitor is connected to this circuit in series and in a direction to be connected to the cathode of the diode, and these are connected in parallel to the pulse oscillation circuit, and the gate of the commutation side control MOSFET and the commutation MOSFET are connected.
A MOSFET drive circuit, comprising: a pre-pulse sending circuit configured by connecting a secondary winding of the pulse transformer between sources of T.
駆動回路において、前記トランスとは別にパルストラン
スを設け、このパルストランスの一次巻線と前記主スイ
ッチ駆動回路との間にコンデンサを接続し、このコンデ
ンサと前記パルストランスの一次巻線を前記パルス発振
回路と並列に接続するとともに、前記転流側制御ＭＯＳ
ＦＥＴのゲートと前記転流ＭＯＳＦＥＴのソースの間に
前記パルストランスの二次巻線を接続し、この二次巻線
と並列にダイオードを設け、カソードが前記転流側制御
ＭＯＳＦＥＴのゲートに接続される向きに、このダイオ
ードを接続して構成してある事前パルス送出回路を設け
てあることを特徴とするＭＯＳＦＥＴ駆動回路。4. The MOSFET according to claim 1, wherein
In the drive circuit, a pulse transformer is provided separately from the transformer, a capacitor is connected between the primary winding of the pulse transformer and the main switch drive circuit, and the capacitor and the primary winding of the pulse transformer are connected to the pulse oscillation circuit. Connected in parallel with the circuit and the commutation-side control MOS
A secondary winding of the pulse transformer is connected between the gate of the FET and the source of the commutation MOSFET, a diode is provided in parallel with the secondary winding, and a cathode is connected to the gate of the commutation side control MOSFET. A MOSFET driving circuit, which is provided with a pre-pulse transmission circuit configured by connecting the diode in a predetermined direction.
駆動回路において、前記主トランス駆動回路のインダク
タを、前記パルストランスの巻線にし、前記主トランス
駆動回路と前記事前パルス送出回路とを一体化してある
ことを特徴とするＭＯＳＦＥＴ駆動回路。5. The MOSFET according to claim 3 or 4.
A MOSFET drive circuit, wherein an inductor of the main transformer drive circuit is used as a winding of the pulse transformer, and the main transformer drive circuit and the pre-pulse transmission circuit are integrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001136998A JP4845285B2 (en) | 2001-05-08 | 2001-05-08 | MOSFET drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001136998A JP4845285B2 (en) | 2001-05-08 | 2001-05-08 | MOSFET drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002330590A true JP2002330590A (en) | 2002-11-15 |
| JP4845285B2 JP4845285B2 (en) | 2011-12-28 |
Family
ID=18984164
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001136998A Expired - Fee Related JP4845285B2 (en) | 2001-05-08 | 2001-05-08 | MOSFET drive circuit |
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| Country | Link |
|---|---|
| JP (1) | JP4845285B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338864C (en) * | 2003-10-20 | 2007-09-19 | 艾默生网络能源有限公司 | DC/DC converter synchronous rectification circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104477A (en) * | 1985-10-30 | 1987-05-14 | Nec Corp | Driving circuit for freewheel fet |
| JPH0236764A (en) * | 1988-07-26 | 1990-02-06 | Tdk Corp | Switching power supply |
| JPH0360360A (en) * | 1989-07-28 | 1991-03-15 | Yaskawa Electric Mfg Co Ltd | gate drive circuit |
| JPH0684793U (en) * | 1993-04-28 | 1994-12-02 | 東光株式会社 | Switching power supply |
| JPH0716592U (en) * | 1993-08-25 | 1995-03-17 | 株式会社アマダ | Field effect transistor gate circuit |
| JP2000262051A (en) * | 1999-03-05 | 2000-09-22 | Murata Mfg Co Ltd | Insulated dc-to-dc converter |
| JP2000350446A (en) * | 1999-06-04 | 2000-12-15 | Densei Lambda Kk | Drive circuit of synchronous rectifying circuit |
-
2001
- 2001-05-08 JP JP2001136998A patent/JP4845285B2/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104477A (en) * | 1985-10-30 | 1987-05-14 | Nec Corp | Driving circuit for freewheel fet |
| JPH0236764A (en) * | 1988-07-26 | 1990-02-06 | Tdk Corp | Switching power supply |
| JPH0360360A (en) * | 1989-07-28 | 1991-03-15 | Yaskawa Electric Mfg Co Ltd | gate drive circuit |
| JPH0684793U (en) * | 1993-04-28 | 1994-12-02 | 東光株式会社 | Switching power supply |
| JPH0716592U (en) * | 1993-08-25 | 1995-03-17 | 株式会社アマダ | Field effect transistor gate circuit |
| JP2000262051A (en) * | 1999-03-05 | 2000-09-22 | Murata Mfg Co Ltd | Insulated dc-to-dc converter |
| JP2000350446A (en) * | 1999-06-04 | 2000-12-15 | Densei Lambda Kk | Drive circuit of synchronous rectifying circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338864C (en) * | 2003-10-20 | 2007-09-19 | 艾默生网络能源有限公司 | DC/DC converter synchronous rectification circuit |
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| Publication number | Publication date |
|---|---|
| JP4845285B2 (en) | 2011-12-28 |
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