JP2002319762A - Multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multilayer wiring board provided with microdiameter via holes having connection reliability. SOLUTION: An insulation film 5 having an upper pad 7 is boded to an insulation substrate having a lower pad 2 and both pads are connected through via holes 6 to produce a multilayer wiring board wherein a pad-like conductor layer 1 is provided on the rear surface of the insulation film. Since the interface between adhesive and polyimide is eliminated in the vicinity of the micro via hole by providing the pad-like conductor layer, interfacial peeling due to thermal stress is prevented and connection reliability of the micro via hole having a low connection strength can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a multilayer structure in which insulating layers and conductor layers are alternately stacked, and more particularly to a multilayer wiring board used for an interposer for mounting a semiconductor element and having a small diameter via hole. Regarding the substrate.

[0002]

2. Description of the Related Art Recently, semiconductor large-scale integrated circuits (LSIs)
In semiconductor devices such as, the degree of integration of transistors increases,
The operation speed reaches 1 GHz in clock frequency, and the number of input / output terminals exceeds 1000.

In order to mount such a semiconductor element on a printed wiring board, a BGA (Ball Grid Ar) is used.
ray) and CSP (Chip Size Package)
e) and other interposers have been developed and are now widely used. FIG. 4 shows an example in which a semiconductor element is mounted on an interposer having a BGA structure and mounted on a printed wiring board.

A bump 43 is formed of gold or the like on one surface of a multilayer wiring board 47 in which insulating layers and conductor layers are alternately laminated based on a copper-clad board or a ceramic board 47a in which glass cloth is impregnated with an epoxy resin or the like. The electrical connection with the electrode of the semiconductor element 41 is established. A pad 44 surface-treated with gold or the like is formed on the opposite surface, and is connected to a conductor layer 45 of a printed wiring board 51 via a solder ball 46.

[0005] Such a multilayer wiring board is formed by sequentially stacking an insulating layer and a conductor layer on a copper-clad board or a ceramic board. The insulating layer of the multilayer wiring board manufactured by this method is formed by applying a resin such as polyimide,
It can be thinned. Further, the conductor layer can be formed by plating, and fine wiring can be performed. On the other hand, the via hole connecting the upper and lower conductor layers can be formed by forming a hole by laser processing or the like and filling the inside with plating. For this reason, a multilayer printed wiring board that collectively stacks conventional copper-clad
Alternatively, higher wiring density, thinner film, and smaller size can be achieved as compared with a ceramic multilayer wiring substrate in which green sheets are stacked and fired at once.

[0006] In addition to the demand for lower cost of the interposer, the demand for functional aspects such as thermal stability of the insulating layer and further miniaturization of the wiring has been increasing. In order to meet these demands, a structure in which a polyimide film with a copper foil is bonded with an adhesive has been proposed. In this configuration, since a polyimide resin having high heat resistance can be used as the insulating layer, and in addition, the thin copper foil and the contact surface with the insulating layer can be smoothed, so that further fine wiring is formed. Enables higher wiring density,
It can be made thinner and smaller.

As the processing speed in a semiconductor device increases,
There is an increasing demand for higher speed transmission of signals transmitted through the interposer. At the same time, the number of input / output terminals of the semiconductor element also tends to increase, and the connection method with the interposer becomes completely compatible with wire bonding, and flip-chip connection in a grid arrangement is required. As a result, it is difficult to route the wiring from the connection terminal in the interposer with a single layer, and it is necessary to divide the wiring into at least two layers. In addition, in order to cope with high-speed signals, a microstrip structure, a strip structure, or a coplanar structure of wiring may be required, and the structure of the interposer is becoming more and more multilayered.

[0008] However, from the viewpoint of the manufacture of the interposer, an increase in the number of layers significantly reduces the manufacturing yield. For this reason, it is important how to design the wiring efficiently and reduce the number of layers. One of means for forming an efficient wiring is to reduce the land diameter of a via hole. As a result, in consideration of manufacturing accuracy, it is necessary to reduce the diameter of the via hole itself.

On the other hand, the introduction of excimer lasers and laser processing machines using the third and fourth harmonics of YAG have become popular, and the formation of small-diameter holes has been facilitated.

As a method of forming a via hole, a hole is formed by a laser or the like, a lower pad surface is exposed, and a seed layer for electroplating is formed by electroless copper plating or the like, and the seed layer is used as an electrode to form a via hole. A constant thickness of plating is formed on the side and bottom of the substrate. In recent years, attention has been paid to filled via plating in which the inside of a hole is filled with a plating metal in order to pass a high-speed signal or to increase a degree of freedom of wiring by forming a via hole right above the via hole.

However, a small via diameter inevitably reduces the contact area with the lower pad, thereby significantly lowering the connection reliability. For example, since the thermal expansion coefficient of the adhesive is larger than that of polyimide or a conductor, peeling at the interface of the adhesive is likely to occur in the temperature cycle test, and as a result, disconnection occurs in the minute via hole.

Generally, a method for roughening the copper surface has been established, so that a certain degree of strength can be secured at the interface between copper and the adhesive, but a method for maintaining the strength of the polyimide surface with various adhesives. Examples include plasma treatment and corona treatment, but they do not necessarily ensure highly reliable adhesion.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a multilayer wiring board having connection-reliable minute via holes.

[0014]

In order to achieve the above object, the present invention provides an adhesive film comprising an insulating film on which upper pads are formed and an insulating substrate on which lower pads are formed. Further, in the multilayer wiring board in which both pads are connected by a via hole, a pad-shaped conductor layer is provided on the back surface of the insulating film. According to a second aspect of the present invention, there is provided the multilayer wiring board according to the first aspect, wherein the insulating film is based on a polyimide resin.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to the present invention will be described with reference to a view near a via hole. FIG. 3 is a sectional view of a conventional multilayer wiring board. A via hole 35 electrically connects the lower pad 31 on the surface of the single-layer or multilayer insulating substrate 32 and the upper pad 36 on the surface of the insulating film. The insulating film is a polyimide film 34, which is bonded on the insulating substrate 32 via an adhesive 33. Here, the insulating substrate 32 may be an insulating film.

The via hole 35 is formed by first bonding a polyimide film with copper foil to an insulating substrate via an adhesive, and then forming a via hole by laser from the surface of the copper foil on the polyimide film 34 on the lower pad. Drill holes for By changing the oscillation frequency of the laser during processing, it is possible to process the insulating layer after processing the surface copper foil and stop on the lower pad. Examples of the type of laser include a carbon dioxide laser, a YAG (basic wave, a second harmonic, a third harmonic, and a fourth harmonic) laser, an excimer laser, and the like. YAG third harmonic, fourth harmonic, and excimer laser, which are wavelength lasers, are preferred.

A seed layer for electrolytic copper plating is formed by electroless plating on the inside of the hole and on the surface of the copper foil on the polyimide film, including the surface of the lower pad made of copper or the like exposed by the laser processing, and the remaining layer is formed by electrolytic copper plating. Fill the inside of the hole with plating metal. Finally, the upper pad 36 is formed on the surface of the conductor layer by photoetching.

As the diameter of the via hole decreases, the contact area with the lower pad 31 decreases, and the connection reliability decreases.

Therefore, in the present invention, as shown in FIG. 1, the pad-shaped conductor layer 1 is formed on the back surface of the insulating film 5 in the via hole. A pad-shaped conductor layer 1 is provided near the bottom of the via hole having a low bonding strength, and the surface of the conductor in contact with the adhesive layer is roughened to improve the adhesive strength between the adhesive layer and the upper and lower surfaces of the adhesive layer. Can be done. For this reason, the stress applied to the vicinity of the bottom of the via hole due to the difference in the thermal expansion coefficient between the adhesive layer and the conductor layer or the polyimide layer can be reduced, and as a result, disconnection of the via in the temperature cycle test can be suppressed.

The method for manufacturing the pad-shaped conductor layer 1 is as follows.
One side of the double-sided copper foil polyimide film can be formed by photo etching, which is a common method. The bonding strength between the copper foil and the polyimide film of the double-sided copper foil polyimide film is extremely high because the bonding is performed with the matte surface of the copper foil.

The shape of the pad-shaped conductor layer 1 is not particularly limited, but is preferably larger than the area of the corresponding lower pad. The pad-shaped conductor layer 1 may be electrically connected to another wiring or via hole, or may be electrically isolated from other than the via hole 6. Considering the properties, it is preferable to adopt an electrically isolated structure.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example of manufacturing a multilayer wiring board according to the present invention will be described with reference to FIGS.

An electrolytic copper foil 12 is formed on both sides of an insulating film 11 (thickness: 50 μm) made of polyimide shown in FIG.
PMER (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is coated as a photoresist on both sides of a polyimide tape (upisel, manufactured by Ube Industries, Ltd.) with a copper foil having a thickness of 18 μm.
C. and dried for 30 minutes. The film thickness after drying was 6 μm. The photoresist on the back side is exposed and developed through a photomask having a predetermined pattern to form a photoresist pattern. 50 ° C, 40 ° Be
The exposed copper portion was dissolved and removed with a ferric chloride solution to form a pad-shaped conductor layer 13 (FIG. 2B). The diameter of the pad-shaped conductor layer 13 was 200 μm.

Next, the surface of the pad-shaped conductor layer 13 is
The surface was roughened with a 200 g / l aqueous solution of ammonium persulfate at ℃.

As shown in FIG. 2C, an epoxy-based adhesive layer is formed on an insulating substrate 14 which is a glass-BT multilayer wiring substrate having a lower pad 16 having a diameter of 100 μm and subjected to a roughening treatment. The adhesive layer was laminated at 80 ° C. so that the center of the lower pad 16 and the center of the pad-shaped conductor layer 13 coincided with each other via 15. Thereafter, heat treatment was performed in an oven at 150 ° C. for 8 hours.

As shown in FIG. 2D, processing is performed from the surface of the copper foil 12 using the fourth harmonic of the YAG laser.
Holes 17 for forming via holes were formed. At this time,
The processing of the copper layer and the insulating layer was performed by changing the oscillation frequency, and the processing was stopped on the lower pad 16. The hole diameter of the copper foil 12 surface is 60
μm.

As shown in FIG. 2E, an electroless copper plating layer is formed inside the hole 17 and on the surface of the copper foil 12, and further,
The inside of the hole was filled with a plating metal by electrolytic copper plating to form a via hole 18 and a plating layer was formed on the surface of the copper foil. At this time, the thickness of the copper layer on the polyimide was 23 μm including the thickness of the copper foil.

As shown in FIG. 2 (f), PMER (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was coated as a photoresist on the copper foil on the surface, and dried at 80 ° C. for 30 minutes. The film thickness after drying was 6 μm. Further, exposure and development were performed through a photomask having a predetermined pattern to form a photoresist pattern. Further, the exposed copper portion was dissolved and removed with a ferric chloride solution at 50 ° C. and 40 ° Be, and the photoresist was removed to form a conductor layer such as the upper pad 19.

As shown in FIG. 2G, similarly, a polyimide film 21 having a pad-shaped conductor layer 22 is laminated via an adhesive 20, and further a via hole 23 is formed.
Then, the upper pad 24 was formed and multilayered to produce a multilayer wiring board of the present invention. In some cases, these steps can be repeated to laminate the required number of layers.

[0030]

According to the present invention, in a multilayer wiring board in which an insulating film with a conductive layer is bonded and laminated, a pad-like conductive layer is provided near a minute via hole to eliminate the interface between the adhesive and the polyimide, thereby reducing thermal stress. This can prevent the interface peeling due to the above, and can improve the connection reliability of the minute via hole having low connection strength.

[0031]

[Brief description of the drawings]

FIG. 1 is a sectional view showing a multilayer wiring board of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to the present invention.

FIG. 3 is a sectional view showing a conventional multilayer wiring board.

FIG. 4 is a cross-sectional view showing an embodiment in which a semiconductor element is mounted on a conventional multilayer wiring board and mounted on a printed wiring board.

DESCRIPTION OF SYMBOLS 1 ... Pad-shaped conductor layer 2 ... Lower pad 3 ... Insulating substrate 4 ... Adhesive layer 5 ... Insulating film 6 ... Via hole 7 ... Upper pad 11 ... Insulating film 12 ... Copper foil 13 ... Pad-shaped conductor layer 14 ... insulating substrate 15 ... adhesive layer 16 ... lower pad 17 ... hole 18 ... via hole 19 ... upper pad 20 ... adhesive layer 21 ... insulating layer 22 ... pad-shaped conductor layer 23 ... via hole 24 ... upper pad 31 ... lower pad 32 ... Insulating substrate 33 ... Adhesive layer 34 ... Insulating layer 35 ... Via hole 36 ... Top pad 41 ... Semiconductor element 42 ... Pad 43 ... Bump 44 ... Pad 45 ... Conductor wiring layer 46 ... Solder ball 47a ... Base substrate 47b ... Multilayer wiring layer 48 ... Via holes 49 ... Lower conductor wiring layer 50 ... Through holes 51 ... Printed wiring board

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Susumu Maba 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd. F-term (reference) 5E346 AA06 AA12 AA15 AA16 AA22 AA32 AA35 AA43 AA51 BB11 BB16 CC10 CC32 DD32 EE38 FF07 FF15 GG15 GG17 GG22 GG28 HH11 HH31

Claims (2)

[Claims] 1. A multilayer wiring board in which an insulating film on which an upper pad is formed and an insulating substrate on which a lower pad is formed are bonded and laminated, and the pads are connected by via holes. A multilayer wiring board provided with a conductor layer. 2. The multilayer wiring board according to claim 1, wherein the insulating film is based on a polyimide resin.