JP2002314032A - Semiconductor device - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a semiconductor device capable of reducing structural warpage and miniaturizing as compared with the related art. A first surface mount component (31, 32) mounted by wire bonding on one surface (20B) of a double-sided wiring board (20);
The second surface-mounted component 22 mounted on the other surface 20 </ b> A of the double-sided wiring board 20, and hermeticity so as to cover the entirety of the second surface-mounted component 22 and the entire other surface 20 </ b> A of the double-sided wiring board 20. By providing the storage portion 27 for storing and holding the second surface-mounted component 22, it is not necessary to stack the second surface-mounted component 22 on the first surface-mounted components 31 and 32 and perform wire bonding mounting. The double-sided wiring board 20
Area can be made smaller than before, and
Since the second surface-mounted component 22 is stored in the storage unit 2,
7, the warpage in the double-sided wiring board and the storage portion can be reduced as compared with the related art, and thus the warpage can be reduced and the size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
For example, it is suitable for application to a semiconductor module on which a plurality of bare chips are mounted.

[0002]

2. Description of the Related Art In recent years, semiconductor modules and CPUs (Central Processing Units) have been developed in semiconductor modules as various electronic devices such as mobile phones have become lighter, thinner, smaller and more sophisticated.
It) and the like are stacked and mounted on a predetermined substrate.

[0003]

As shown in FIG. 9, in a semiconductor module 1, bare chips 3 and 4, a spacer 10, and a bare chip 5 are sequentially laminated on one surface 2A of an organic substrate 2, and the bare chip 3, After electrically connecting each pad 6 of 4 and 5 and each land 7 on the organic substrate 2 corresponding to each pad 6 via a wire 8,
One surface 2A of the organic substrate 2 and the wire 8 by the sealing resin 9
(So-called wire bonding mounting).

In this case, in the semiconductor module 1,
Although the lands 7 are sequentially arranged at predetermined intervals in the circumferential direction of the organic substrate 2 to avoid contact between the wires 8, the organic substrates 2 are shifted by a predetermined amount in the peripheral direction. In this case, a large area must be secured, and as a result, there is a problem that the overall size becomes large.

[0005] The semiconductor module 1 measures the amount of warpage at the joint JP (FIG. 9) between the sealing resin 9 and the organic substrate 2 at the time of manufacture based on the measurement direction MS shown in FIG. As shown in FIG. 5, since the thermal expansion coefficient of the organic substrate 2 is larger than the thermal expansion coefficient of the bare chip 3, the one surface 2A
However, there is a problem that a warp (about 25 μm) corresponding to the solid line FL occurs with respect to the reference virtual line BL on the one surface 2A.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a semiconductor device capable of reducing warpage and miniaturizing as compared with the prior art.

[0007]

According to the present invention, there is provided a first surface-mounted component which is mounted by wire bonding on one surface of a double-sided wiring board and mounted on the other surface of the double-sided wiring board. By providing a second surface-mounted component and a storage portion that stores the second surface-mounted component while maintaining airtightness so as to cover the entire second surface-mounted component and the entire other surface of the double-sided wiring board, There is no need to laminate the second surface-mounted component on the first surface-mounted component and perform wire bonding mounting, and accordingly, the area of the double-sided wiring board can be reduced as compared with the conventional case, and the surface mounting accommodated in the storage portion can be reduced. The components can increase the structural strength of the storage section and can reduce the warpage between the double-sided wiring board and the storage section as compared with the related art.

In order to solve this problem, according to the present invention, the center of gravity of the storage portion and the center of gravity of the second surface mount component are accommodated in a state of being matched, so that the center of gravity with the highest load is centered. Can be effectively reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIGS. 1, 2 and 3 show the steps of manufacturing a semiconductor module 50 (FIG. 3) according to the present invention step by step. As a first step (FIG. 1A), a semiconductor module manufacturing apparatus (FIG. After performing an etching resist treatment with a dry film on one surface 20A of a double-sided copper-clad laminate (hereinafter, referred to as a bare chip mounting laminate) 20 made of a glass epoxy material for bare chip mounting. Then, a predetermined wiring 21 is formed by performing a wet etching process.

In the second stage (FIG. 1B), the semiconductor module manufacturing apparatus uses a bare chip (hereinafter referred to as a storage bare chip) 22 on which a circuit is formed (hereinafter referred to as a circuit forming surface). The gold stat bumps 23A and 23B are formed at predetermined positions of 22A.

In the semiconductor module manufacturing apparatus, the center of one surface 20A of the bare chip mounting laminate 20 coincides with the center of one surface of the anisotropic conductive film 24 for electrically and mechanically connecting the storage bare chip 22. Then, when the storage bare chip 22 is electrically and mechanically connected via the anisotropic conductive film 24 by mounting the anisotropic conductive film 24, the circuit forming surface 22A of the storage bare chip 22 is formed. And the center of the one-sided surface 20A of the bare chip mounting laminate 20 can be easily matched.

As a third step (FIG. 1C), the semiconductor module manufacturing apparatus forms the storage bare chip 22 on the storage bare chip 22 by the anisotropic conductive film 24 by thermocompression bonding in the direction of arrow a. Gold Stat Bumps 23A and 23B and Bare Chip Mounting Laminate 20
Is bonded (so-called flip-chip mounting) to the wiring 21 formed on the one surface 20A.

As a fourth step (FIG. 1D), first, the semiconductor module manufacturing apparatus performs the above-described first step (FIG. 1D).
In the same manner as (A)), a predetermined wiring is provided on one surface 25A of a double-sided copper-clad laminate (hereinafter referred to as a motherboard mounting laminate) 25 for mounting on a motherboard having the same shape as the bare chip mounting laminate 20. 26 is formed.

Next, the semiconductor module manufacturing apparatus places the one surface 25A of the motherboard mounting laminate 25 (the one surface 20A of the bare chip mounting laminate 20) on one surface 25A of the motherboard mounting laminate 25 on which the wiring 26 is formed. In addition to the insert prepreg 27A and the cover prepreg 27B of glass epoxy material having the same area, the bare chip mounting laminate 20 on which the flip chip is mounted is turned upside down and sequentially laminated.

Here, the interposed prepreg 27A is a laminate 20 for mounting bare chips and a laminate 2 for mounting mother boards.
5 is a prepreg for selecting the storage bare chip 22 at an intermediate position between the storage bare chip 22 and the cover bare prepreg 27B.
2 is the prepreg from which the volume 27C of 2 has been removed by the router processing.

Here, the semiconductor module manufacturing apparatus sets the thickness of the interposing prepreg 27A to
The thickness of the storage bare chip 2 can be set between the bare chip mounting laminate 20 and the motherboard mounting laminate 25 by appropriately changing the thickness of the storage chip 2.
2 can be selected appropriately.

The semiconductor module manufacturing apparatus can form the cover prepreg 27B by removing a part of the prepreg substantially in accordance with the volume of the storage bare chip 22. Thereby, the cover prepreg 27B is formed on the cover prepreg 27B. In order that the bare chip mounting laminate 20 on which the storage bare chip 22 is mounted can be easily laminated, and when the cover prepreg 27B is melted, it can be quickly diffused to the surroundings except for the circuit forming surface 22A of the storage bare chip 22. It has been done.

Therefore, as a fifth step (FIG. 2E), the semiconductor module manufacturing apparatus melts the insertion prepreg 27A and the cover prepreg 27B by heating to a predetermined temperature in a vacuum atmosphere. The insertion section prepreg 27A and the cover prepreg 27B are integrated, and then cured to form the storage section 27.

Thus, the semiconductor module manufacturing apparatus can
A storage section 27 is formed so as to cover and store the entirety of the storage bare chip 22 and the entire surface 20A of the bare chip mounting laminate 20 in an airtight manner.

In addition, in the semiconductor module manufacturing apparatus, one surface 20A of the bare chip mounting laminate 20 is provided.
Bare chip 2 mounted in the center of the flip chip
2 is the middle of the thickness TH of the storage section 27 (the middle between the laminate 20 for mounting the bare chip and the multilayer board 25 for mounting the motherboard) and the middle of the width WI of the storage 27, that is, the center of gravity of the storage 27 and the bare chip 22 for storage. The storage portion 27 can be stored with the center of gravity of the storage portion 27 being matched.

The storage portion 27 is designed to increase the structural strength by storing the storage bare chip 22 having a small coefficient of thermal expansion. In addition, the storage bare chip 22 is provided at the center of gravity of the storage portion 27. By storing the 22 with the center of gravity being matched, the structural strength can be increased uniformly.

Further, since the storage section 27 is fixedly stored with the circuit forming surface 22A of the storage bare chip 22 opposed to one surface 20A of the bare chip mounting laminated board 20, as shown in FIG. The other surface 25 of the laminate 25
The flow of moisture from B into the anisotropic conductive film 24 (that is, in the direction of arrow b) can be minimized.

In the sixth step (FIG. 2F), the semiconductor module manufacturing apparatus performs a drilling process to cause the mother board from the predetermined position on the other surface 20 B of the laminate 20 for bare chip mounting via the wirings 21 and 26. Mounting laminate 2
5, a through hole is formed substantially perpendicularly to the other surface 25B.

Next, the semiconductor module manufacturing apparatus performs a copper plating process on the inner peripheral surface of the through-hole to form through holes 28A and 28B, thereby forming the bare chip 22 for storage and the laminated board 20 for mounting the bare chip. One side 20
A and the other surface 20B are electrically connected to one surface 25A and the other surface 25B of the motherboard mounting laminate 25, respectively.

As a seventh step (FIG. 2G), first, the semiconductor module manufacturing apparatus performs the above-described first step (FIG. 1).
Similarly to (A)), the other surface 20 </ b> B of the bare chip mounting laminate 20 and the other surface 2 of the motherboard mounting laminate 25.
Predetermined wirings 29 and 30 are formed on 5B.

Next, the semiconductor module manufacturing apparatus forms a land (not shown) by performing a surface treatment by bonding gold plating on a predetermined portion of the other surface 20B of the bare chip mounting laminate 20.

As an eighth step (FIG. 3H), first, the semiconductor module manufacturing apparatus uses the bare chip mounting laminate 2.
0 on the other surface 20B, the center of the other surface 20B and the center of one surface of the bare chip (hereinafter referred to as the mounting bare chip) 31 are made to coincide with each other, so that the mounting bare chip 3
1 is the other surface 20 of the bare chip mounting laminate 20
B is evenly applied.

Next, in the semiconductor module manufacturing apparatus, the center of one surface of the mounting bare chip 31 and the center of one surface of the bare chip (hereinafter referred to as a “stacking bare chip”) 32 coincide with each other on the mounting bare chip 31. By doing so, the weights of the mounting bare chip 31 and the stacking bare chip 32 are evenly applied to the other surface 20 </ b> B of the bare chip mounting laminate 20.

Further, the semiconductor module manufacturing apparatus includes a pad 33 of the bare chip 31 for mounting and a bare chip 32 for lamination, and a land on the other surface 20B of the laminated board 20 for mounting the bare chip corresponding to each pad 33. Are connected via a wire 34, so that the storage bare chip 22 electrically connected in the above-described sixth step (FIG. 2 (F)), the one surface 20A and the other surface 20B of the bare chip mounting laminate 20 are connected. And one surface 25A and the other surface 25B of the motherboard mounting laminate 25,
1 and the stacking bare chip 32 are also electrically connected.

In the case of this embodiment, the semiconductor module manufacturing apparatus uses the circuit forming surface 22 A of the storage bare chip 22.
The other surface 2 of the laminate 20 for mounting bare chips
The area of the upper surface of the bare chip 31 for mounting on the chip 0B is selected to be large, thereby minimizing the inflow of moisture from the other surface 20B of the bare chip mounting laminate 20 to the anisotropic conductive film 24. It is made to be able to do.

As a ninth stage (FIG. 3I), the semiconductor module manufacturing apparatus applies a sealing resin 35 so as to cover the other surface 20B of the bare chip mounting laminate 20 and the wires 34, and performs the sealing. By heating and curing the resin 35 at a predetermined temperature, the mounting bare chip 31 and the laminating bare chip 32 are resin-sealed by the sealing resin 35 on the other surface 20B of the bare chip mounting laminate 20. The semiconductor module 50 can be manufactured.

This semiconductor module 50 is shown in FIG.
In addition to the mounting bear chip 31 selected to be larger than the storage bare chip 22 as shown in FIG. 5, a sealing resin 35 covering the entire mounting bear chip 31 and the entire other surface 20B of the mounting laminate 20 is used. The flow of moisture from the other surface 20B of the bare chip mounting laminate 20 to the anisotropic conductive film 24 (that is, the direction of arrow c) can be minimized.

As described above, as shown in FIGS. 4A and 4B, the semiconductor module 50 has a configuration in which the inflow of moisture can be avoided as much as possible. The accumulation of aqueous substances in the
As a result, the reliability of mounting on the motherboard can be improved by avoiding the so-called popcorn phenomenon or the like that explodes when subjected to thermal processing in mounting various electronic devices on the motherboard.

Further, the semiconductor module 50 is
By storing the storage bare chip 22 having a smaller coefficient of thermal expansion than the storage part 27 in the storage part 27 in a state where the center of gravity of the storage chip 7 and the center of gravity of the storage bare chip 22 are matched, as shown in FIG. Based on the measurement direction MS1, as shown in FIG. 6, the amount of warpage was measured for the joint JP1 (FIG. 3 (I)) between the sealing resin 35 at the time of manufacture and the other surface 20B of the bare chip mounting laminate 20. The other surface 20B of the laminated board 20 for mounting bare chips is moved by a heat treatment in the manufacturing process so that the solid line FL1
Minute warpage (18μm), the conventional warpage (25μm)
m) (FIG. 6C), it is possible to reduce not only the reduction in the warpage but also the reduction in the warpage.

As described above, in the semiconductor module 50, the mounting bare chip 31 and the stacking bare chip 32 wire-bonded to the other surface 20B of the bare chip mounting stack 20 and the bare chip mounting stack 2
The storage bare chip 22 is flip-chip mounted on one surface 20A of the storage chip 0, and the storage bare chip 22 is sealed and cured so as to cover the entirety of the storage bare chip 22 and the entire surface 20A of the bare chip mounting laminate 20. And a storage unit for storing the data.

Accordingly, the semiconductor module 50 is different from the conventional case (FIG. 9) in that all the bare chips are wire-bonded and mounted on the one surface 2A of the organic substrate 2 so that the land and the land of the storage bare chip 22 stored in the storage portion 27 are formed. The amount of wires can be avoided, whereby the area of the laminate 20 for mounting bare chips can be reduced, and thus the size can be reduced as compared with the conventional case.

In the semiconductor module 50, although the thickness of the bare chip mounting laminate 20 is made smaller than the thickness of the conventional organic substrate 2, the storage space 27 having a predetermined thickness has a higher heat than the bare chip mounting laminate 20. By storing the storage bare chip 22 having a small expansion coefficient, the structural strength of the storage portion 27 is increased, and as a result, the sealing resin 35 and the bare chip mounting laminate 20, the storage portion 27, and the motherboard mounting laminate are increased. The warpage of the plate 25 can be reduced.

In addition, the semiconductor module 50 includes
By storing the storage unit 27 in a state where the center of gravity of the storage unit 27 and the center of gravity of the storage bare chip 22 are matched with each other, it is possible to effectively reduce the warpage occurring around the center of gravity where the load is most applied, and as a result, the warpage is reduced. To a small extent, various electronic devices can be smoothly mounted on the motherboard, and when mounted on the motherboard, the bare chip mounting laminate 20, the housing 27, and the motherboard mounting laminate 25
Disconnection of the electrical connection due to the warpage of FIG. 3 (I) can be avoided, and thus the reliability of mounting on the motherboard can be improved.

According to the semiconductor module 50 as described above, the storage bare chip 22 flip-chip mounted on one surface 20A of the bare chip mounting laminate 20 is used as the whole of the storage bare chip 22 and the bare chip mounting laminate 2
Of the bare chip mounting laminate 20 by sealing and hardening so as to cover the entire surface 20A of the bare chip mounting surface 20A.
A and the area of the other surface 20B can be reduced, and the structural strength of the storage portion 27 can be increased. Thus, the warpage can be reduced and the size can be reduced as compared with the related art.

In the above-described embodiment, a case has been described in which a double-sided copper-clad laminate is used as a double-sided wiring board. However, the present invention is not limited to this. Various other double-sided wiring boards can be widely used. In this case, effects similar to those of the above-described embodiment can be obtained.

Further, in the above-described embodiment, the mounting bare chip 31 and the laminating bare chip 32 as the first surface mount components wire-bonded and mounted,
Although the case where the storage bare chip 22 is used as the surface mounting component has been described, the present invention is not limited to this. Can be used. In this case, effects similar to those of the above-described embodiment can be obtained.

Further, in the above-described embodiment, a case has been described in which the storage portion 27 is formed by the insertion prepreg 27A and the cover prepreg 27B made of a glass epoxy material. However, the present invention is not limited to this, and the present invention is not limited to this. The storage portion may be formed by an insertion prepreg and a cover prepreg made of a bismaleimide triazine material, or the storage portion may be formed in advance using another material or material.
The storage section may be a storage section which stores the bare chip 22 for storage while keeping airtightness so as to cover the entirety of the bare chip mounting laminate 20 and the entire other surface 20B of the laminated board 20 for mounting bare chips.

In this case, in particular, the semiconductor module in which the housing portion is formed by the insertion prepreg and cover prepreg made of polyphenylene ether or bismaleimide triazine material is formed by the insertion prepreg 27A and cover prepreg 27B made of glass epoxy material. The storage portion having a lower coefficient of thermal expansion can be formed as compared with the storage portion 27 which is formed, and thus the warpage can be further reduced, and as a result,
The reliability of mounting various electronic devices on the motherboard can be improved.

Further, in the above-described embodiment, two bare chips (the mounting bare chip 3) mounted by wire bonding on the other surface 20B of the bare chip mounting laminate 20 are provided.
1 and the laminated bare chip 32), a single storing bare chip 22 mounted on one surface 20A, and a storing section 27 for storing the entire storing bare chip 22. ,
The present invention is not limited to this, and is configured by one mounting bare chip 31 wire-bonded, one storing bare chip 22 flip-chip mounted, and a storage portion 27 for storing the entirety of the storing bare chip 22. Semiconductor chip or one mounting bare chip 31 and two or more stacked bare chips 32 mounted by wire bonding
And a storage unit 27 for storing the entirety of the storage bare chip 22 that is flip-chip mounted and a storage unit 27 that stores the entirety of the storage bare chip 22, and a mounting bare chip 31 and a stacked bare chip that are mounted by wire bonding. 32 and other various bare chips (the mounting bare chip 31, the laminated bare chip 32, and the storing bare chip 22) such as a semiconductor device including a storage portion 27 that stores the entirety of two or more storing bare chips 22. Semiconductor devices configured in combination can be applied to the present invention.

In this case, for example, as shown in FIG. 7 in which the same reference numerals are given to portions corresponding to FIG.
, The axis AL in the direction perpendicular to the other surface 20B of the laminate 20 for mounting bare chips passing through the center of gravity of the storage portion 27
The storage bare chip 22 flip-chip mounted thereon
The storage unit 27 covers the entire storage bare chip 22 and the entire other surface 20B of the bare chip mounting laminate 20 in a state where the centers of gravity of the storage bare chips 22 wire-bonded and mounted via the spacers 40 are matched. In addition to the fact that the storage bare chip 22 mounted with flip chips can effectively reduce the warp generated around the center of gravity where the load is most applied, the warp generated in the storage portion 27 by the storage bare chip 22 and the spacer 40 can be effectively reduced. The power can be distributed, and thus the reliability of mounting on the motherboard can be further improved.

By the way, in the semiconductor device 60, if the storage bare chip 22 mounted with the flip chip is positioned at the center of gravity of the storage section 27, the storage bare chip 22 mounted with wire bonding necessarily passes through the center of gravity of the storage section 27. The bare chip mounting laminate 20 need not be stored on the axis AL in the direction perpendicular to the other surface 20B of the laminate 20.

Also, as shown in FIG. 8, for example, in which the same reference numerals are given to the corresponding parts in FIG. 3 (I), in the semiconductor device 70, the width of the bare chip mounting laminated board 20 passing through the center of gravity of the storage portion 27 On the axis AL1 in the direction WI2,
The storage section 27 covers the entire storage bare chip 22 and the entire other surface 20B of the bare chip mounting laminate 20 in a state in which the respective centers of gravity of the four storage bare chips 22 flip-chip mounted near the peripheral side surface are matched. With such storage, the warp generated around the center of gravity where the load is most applied by the storage bare chip 22 stored at the position of the center of gravity of the storage portion 27 can be effectively reduced, and the vicinity of the peripheral side surface of the storage portion 27 can be reduced. The warp force generated in the vicinity of the peripheral end of the storage portion 27 can be reduced by each of the storage bare chips 22, and thus, the mounting reliability on the motherboard can be further improved.

Incidentally, in the semiconductor device 60, the storage bare chip 22 stored in the position of the center of gravity of the storage section 27 is inserted into the storage section 2.
7, the width direction WI <b> 2 of the bare chip mounting laminate 20 that necessarily passes through the center of gravity of the storage unit 27 for each storage bare chip 22 near the peripheral side surface of the storage unit 27.
Need not be stored on the axis AL1.

[0050]

As described above, according to the present invention, the first surface-mounted component mounted on one surface of the double-sided wiring board by wire bonding and the second surface mounted component mounted on the other surface of the double-sided wiring board The second surface mounting is provided by providing a component and a storage portion that stores the second surface mounting component while maintaining airtightness so as to cover the entire second surface mounting component and the entire other surface of the double-sided wiring board. There is no need to stack the components on the first surface mount component and perform wire bonding mounting, and accordingly, the area of the double-sided wiring board can be reduced as compared with the conventional case, and the surface mount components housed in the housing portion allow the housing portion to be mounted. , The warpage in the double-sided wiring board and the storage portion can be reduced as compared with the related art, and thus the warpage can be reduced and the size can be reduced.

Further, according to the present invention, as described above, the storage is made in a state where the center of gravity of the storage section and the center of gravity of the second surface mount component are matched, so that the center of gravity with the highest load is centered. The generated warpage can be effectively reduced, and thus the warpage can be further reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing step (1) of a semiconductor module.

FIG. 2 is a schematic sectional view showing a manufacturing step (2) of the semiconductor module;

FIG. 3 is a schematic sectional view showing a manufacturing step (3) of the semiconductor module;

FIG. 4 is a schematic cross-sectional view for explaining the inflow state of water.

FIG. 5 is a schematic diagram illustrating a measurement direction as viewed from a top surface of the semiconductor module.

FIG. 6 is a characteristic curve diagram showing a measurement result of a warpage amount.

FIG. 7 is a schematic sectional view showing a semiconductor module according to another embodiment.

FIG. 8 is a schematic sectional view showing a semiconductor module according to another embodiment.

FIG. 9 is a schematic sectional view showing a conventional semiconductor module.

FIG. 10 is a schematic diagram illustrating a measurement direction viewed from the top surface of a conventional semiconductor module.

FIG. 11 is a characteristic curve diagram showing a measurement result of a warpage amount in a conventional semiconductor module.

[Explanation of symbols]

Reference numeral 20: laminated board for mounting a bare chip, 22: bare chip for storing, 24: anisotropic conductive film, 25: laminated board for mounting a motherboard, 27: storage section, 27A: prepreg for insertion, 27B ... … Cover prepreg, 28A, 28B…
... Through hole, 31 ... Bear chip for mounting, 32 ...
Bare chip for lamination, 35 ... sealing resin, 50 ... semiconductor module.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tomoyasu Gunji 573-19 Toiso, Eniwa-shi, Hokkaido Inside Clover Electronics Co., Ltd. (72) Inventor Toshihiro Murayama 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Shosho Okachi 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Masayuki Yasuda 6-35-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (5)

[Claims] 1. A first surface-mounted component mounted on one surface of a double-sided wiring board by wire bonding, a second surface-mounted component mounted on the other surface of the double-sided wiring board, and the second surface-mounted component And a storage section for storing the second surface-mounted component while maintaining airtightness so as to cover the entirety of the second surface mounting board and the entire other surface of the double-sided wiring board. 2. The semiconductor device according to claim 1, wherein the housing section houses the second surface-mounted component by being sealed with a sealing material and cured. 3. The semiconductor device according to claim 1, wherein said housing portion is housed in a state where the center of gravity of said housing portion and the center of gravity of said second surface-mounted component coincide with each other. 4. The storage section stores the second surface-mounted component in a state where the center of gravity of the second surface-mounted component is aligned with an axis perpendicular to the other surface of the double-sided wiring board passing through the center of gravity of the storage section. The semiconductor device according to claim 1, wherein 5. The first surface-mounted component is disposed so as to face the second surface-mounted component, and the mounting area mounted on one surface of the double-sided wiring board is the second surface-mounted component. The semiconductor device according to claim 1, wherein the semiconductor device is selected to be larger than a mounting area of the semiconductor device.