JP2002314088A - Method of manufacturing thin film transistor array substrate and liquid crystal display device using thin film transistor array substrate manufactured by the method - Google Patents

Abstract

(57) [Problem] To provide a method of manufacturing a thin film transistor array substrate capable of reducing the number of photomasks to be used as compared with the conventional process, thereby reducing the manufacturing cost and shortening the construction period. An undercoat insulating film is provided on an insulating substrate, a gate electrode is provided thereon, a first insulating film is provided on the insulating substrate and the gate electrode, and a semiconductor layer and a source are provided above the first insulating film. An electrode and a drain electrode are provided so as to face each other other than the channel formation region immediately above the gate electrode; a second insulating film is provided on the insulating substrate, the source electrode, the drain electrode, and the channel formation region; A contact hole is provided on the drain electrode, and a pixel electrode is provided above the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a thin film transistor array substrate. In particular, a method for manufacturing a thin film transistor array substrate capable of reducing the number of photomasks used during a manufacturing process by using a substrate having an inverted staggered thin film transistor as one substrate and a liquid crystal display device using the thin film transistor array substrate manufactured by the method About.

[0002]

2. Description of the Related Art FIG. 3 is a cross-sectional view showing a manufacturing process of a thin film transistor array substrate provided with a reverse staggered thin film transistor, a gate wiring, a source wiring and the like in a conventional thin film transistor type liquid crystal display device. FIG. 10 is a plan view showing a manufacturing process of a thin film transistor array substrate provided with an inverted staggered thin film transistor, a gate wiring, a source wiring, and the like in the thin film transistor liquid crystal display device of FIG.

In such a thin film transistor array substrate, as shown in FIG. 4, a gate wiring 1 and a source wiring 2 are arranged in a matrix on a transparent insulating substrate 5 made of glass or the like. A region surrounded by the gate wiring 1 and the source wiring 2 becomes one pixel electrode 3, and a thin film transistor 4 is provided for each pixel.

In the thin film transistor 4, a gate electrode 6 extending from the gate wiring 1 is provided on a transparent insulating substrate 5, and a gate insulating film 7 is provided so as to cover the entire gate electrode 6. On the gate insulating film 7 above the gate electrode 6, amorphous silicon (a-S
i) is provided, and n such as phosphorus
Silicon (a-Si: n)
+) From the semiconductor film 8 to the gate insulating film 7 via the ohmic contact layer 9 made of
Source electrode 10 and drain electrode 11 extracted from
Is provided.

[0005] A passivation film 12 is provided to cover the thin film transistor 4 composed of the source electrode 10, the drain electrode 11, the gate electrode 6, and the like.
A contact hole 13 is provided in the passivation film 12 on the drain electrode 11.

Further, a pixel electrode 14 made of a transparent conductive film such as indium tin oxide (hereinafter referred to as "ITO") is provided which is electrically connected to the drain electrode 11 through the contact hole 13. Have been.

The right side of FIG. 3 shows a sectional structure of the gate terminal pad portion 15 and the source terminal pad portion 16 at the end of the gate wiring 1 located outside the display region. As shown in FIG. 3, the gate insulating film 7 and the passivation film 12 are formed on the lower pad layer 17 made of the gate wiring material on the transparent insulating substrate 5, and the passivation film 12 is formed on the lower pad layer 18 made of the source wiring material. The contact holes 19 and 20 are respectively provided therethrough, and the gate upper pad layer 21 and the source upper pad layer 22 electrically connected to the gate lower pad layer 17 and the source lower pad layer 18 through the contact holes 19 and 20, respectively. Is provided. Note that the upper pad layers 21 and 22 are formed of the same transparent conductive film as the pixel electrode 14.

When manufacturing this thin film transistor array substrate, first, a conductive film is formed on the transparent insulating substrate 5 and then patterned to form the gate electrode 6 and the gate wiring 1. Further, a lower pad layer 17 is formed in the gate terminal pad section 15.

Next, after forming a gate insulating film 7 covering the gate electrode 6 and the gate wiring 1, an a-Si film 8,
The a-Si: n + film 9 is sequentially formed, and the a-Si film 8 and the a-Si: n + film 9 are collectively patterned by using one photomask. As shown, the island portion 23 is formed on the gate electrode 6 with the gate insulating film 7 interposed therebetween.

Further, after forming a conductive film on the entire surface, the conductive film is patterned to form a drain electrode 11 made of a conductive film.
A source electrode 10 and a source wiring 2 are formed, and a-
The a-Si: n + film 9 on the channel portion of the Si film 8 is removed to form an ohmic contact layer composed of the a-Si: n + film 9.

Next, a passivation film 12 is formed on the entire surface, and is patterned to form a passivation film 12 and a gate insulating film 7 on a gate lower pad layer 17, a drain electrode 11 and a source lower pad layer 1.
A part of the passivation film 12 on the opening 8 is opened, a contact hole 13 for electrically connecting the drain electrode 11 and the pixel electrode 14, and a gate mounting terminal 15 and a source mounting terminal 16 are electrically connected. Contact holes 19 and 20 are formed respectively.

Finally, an ITO film is formed on the entire surface and is patterned to form the pixel electrode 14, the gate upper pad layer 21 and the source upper pad layer 22 as mounting electrodes. Through these steps, a conventional thin film transistor array substrate is completed.

[0013]

However, according to the above-mentioned method of manufacturing a thin film transistor array substrate, patterning for forming a gate electrode, patterning for forming an island portion, patterning for forming a source / drain electrode, and contact hole Patterning for forming, patterning for forming pixel electrodes, and a patterning step were required five times, and five photomasks were required in one process (hereinafter, referred to as “five-mask process”).

However, in manufacturing a thin film transistor array substrate, using many expensive photomasks and providing many photolithography steps during the manufacturing process causes a rise in manufacturing costs and a prolonged work period. Undesirably, it is desired to reduce the number of photomasks used (the number of photolithography steps) as much as possible.

On the other hand, wiring materials such as gate wiring and source wiring are made of Mo in order to reduce resistance and improve chemical resistance.
/ Al / Mo and low resistance materials such as Ti / Al / Ti
There is a need for a laminated structure in which barrier metal and cap metal are applied.

However, Mo / Al / Mo can be patterned by wet etching, but it is difficult to control the composition of the etching solution, and the step coverage characteristic of the gate wiring is affected by the variation in the taper control required for the gate wiring. And the yield is reduced due to the occurrence of an electrical short circuit between the gate wiring and the source wiring.

Further, Ti / Al / Ti can be patterned using dry etching.
Due to the generation of reaction products peculiar to Al dry etching, for example, when used as a gate material and a source material, the number of point defects due to film residue increases, and it is difficult to control the gate taper of the laminated film, so that step coverage of the gate wiring is reduced There is also a problem that the characteristics are deteriorated and the yield is reduced due to the occurrence of an electrical short circuit between the gate wiring and the source wiring.

According to the present invention, there is provided a method of manufacturing a thin film transistor array substrate which can reduce the number of photomasks to be used as compared with the conventional process, thereby reducing the manufacturing cost and shortening the work period. Another object of the present invention is to provide a method of manufacturing a thin film transistor array substrate suitable for reducing the resistance of wiring and a liquid crystal display device using the thin film transistor array substrate manufactured by the method.

[0019]

In order to achieve the above object, a method of manufacturing a thin film transistor array substrate according to the present invention comprises the steps of providing an undercoat insulating film on an insulating substrate, and forming a gate on the undercoat insulating film. A step of providing an electrode; a step of providing a first insulating film on the insulating substrate and the gate electrode; and a step of: Providing a semiconductor layer, a source electrode and a drain electrode, providing an insulating substrate, a source electrode, a drain electrode, a second insulating film over a channel formation region, and providing a contact hole over a gate electrode and a drain electrode. And a step of providing a pixel electrode above the contact hole.

With this configuration, patterning for forming a gate electrode and a gate wiring (hereinafter, referred to as a “gate portion”), a source electrode, a source wiring and a drain electrode (hereinafter, referred to as a “source / drain portion”), and an ohmic contact are performed. Patterning for forming a layer, patterning for forming an insulating film and a semiconductor film for forming a thin film transistor,
The patterning process is basically performed four times, such as patterning for forming a pixel electrode, and the number of photomasks used can be four.

That is, as compared with the conventional manufacturing process, after patterning for forming the gate portion, patterning of the island portion defining the shape of the semiconductor film is performed, but the gate insulating film, the semiconductor film, the impurity semiconductor film, After four successive layers of the conductive film of the source / drain portion are formed, the conductive film of the source / drain portion and the impurity semiconductor film are patterned by using the same photomask to form the source / drain portion and the ohmic contact layer. Form. Then, the thin film transistor is formed by patterning the insulating film, the semiconductor film, and the gate insulating film that are to be the passivation film using the same photomask, and finally, the pixel electrode is formed by patterning the transparent conductive film. The conventional five-mask process becomes a four-mask process, and the number of photomasks to be used can be reduced. Therefore, it is possible to reduce the manufacturing cost and the construction period.

In the method of manufacturing a thin film transistor array substrate according to the present invention, it is preferable that the material of the gate electrode, the source electrode and the drain electrode is a silver alloy. This is because, compared to dry etching, control of the etching shape is relatively easy, and patterning can be performed by wet etching that is advantageous for dust adhesion.

Further, since the gate electrode and the source / drain electrodes are made of the same material of silver alloy, it is sufficient to invest only in one film forming apparatus and one wet etching apparatus. In the production of a liquid crystal display device using, it is possible to improve the yield and reduce the production cost.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the material of the undercoat insulating film on the insulating substrate is preferably one of silicon dioxide, silicon nitride, and tantalum oxide.

Next, in order to achieve the above object, a liquid crystal display device according to the present invention is a liquid crystal display device in which a liquid crystal material is sandwiched between two opposing insulating substrates. A thin film transistor manufactured by the above-described method for manufacturing a thin film transistor array substrate is provided as a switching element on a surface of one insulating substrate which is in contact with a liquid crystal material.

With this configuration, as compared with the conventional manufacturing process, after patterning for forming the gate portion, patterning of the island portion that defines the shape of the semiconductor film is not performed, but the gate insulating film, the semiconductor film, and the impurity semiconductor are formed. After four consecutive layers of a film and a conductive film of the source / drain portion are formed, the conductive film of the source / drain portion and the impurity semiconductor film are patterned using the same photomask to form an ohmic contact with the source / drain portion. Form a layer. Then, the thin film transistor is formed by patterning the insulating film, the semiconductor film, and the gate insulating film that are to be the passivation film using the same photomask, and finally, the pixel electrode is formed by patterning the transparent conductive film. The conventional five-mask process becomes a four-mask process, and the number of photomasks to be used can be reduced. Therefore, it is possible to reduce the manufacturing cost and the construction period.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a thin film transistor array substrate according to an embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a thin film transistor array substrate according to the present embodiment is an example in which a silver alloy film is used as a gate material and a source material in an inverted staggered thin film transistor, and the manufacturing process is a four-mask process.

FIG. 1 is a sectional view showing a manufacturing process of a thin film transistor array substrate, which is one of the substrates facing each other with a liquid crystal layer interposed therebetween, in a liquid crystal display device using the thin film transistor array substrate according to the present embodiment. FIG. 4 is a plan view showing a manufacturing process of a thin film transistor array substrate which is one of the substrates facing each other with a liquid crystal layer interposed therebetween in a liquid crystal display device using the thin film transistor array substrate according to the present embodiment.

The thin film transistor array substrate according to the present embodiment is, as shown in FIGS.
A gate electrode 6 extending from the gate wiring 1 is provided thereon, and a gate insulating film 7 made of SiNx is provided so as to cover the gate electrode 6. In the present embodiment, a silver alloy film is used as a gate wiring material.

A semiconductor film 8 made of amorphous silicon (a-Si) is provided on a gate insulating film 7 above the gate electrode 6 and made of amorphous silicon (a-Si: n +) containing an n-type impurity such as phosphorus. A source electrode 10 and a drain electrode 11 extending from the source wiring 2 are provided on the semiconductor film 8 via the ohmic contact layer 9. These source wiring 2, source electrode 10 and drain electrode 11 are formed of the same silver alloy as gate electrode 6.

Then, a passivation film 12 made of SiNx is provided to cover the thin film transistor 4 composed of the source electrode 10, the drain electrode 11, the gate electrode and the like, and the passivation film 12 on the drain electrode 11 is provided.
Is provided with a contact hole 13. Further, a pixel electrode 14 made of ITO electrically connected to the drain electrode 11 through the contact hole 13 is provided.

The right part in FIG. 1 shows a cross-sectional structure of the gate terminal pad portion 15 at the end of the gate wiring 1 located outside the display area. As shown in FIG. 1, a lower pad layer 17 made of a gate wiring material on a glass substrate 5 is formed.
A contact hole 19 penetrating through the gate insulating film 7, the a-Si film, and the passivation film 12 is provided on the lower pad layer 17 through the contact hole 19.
Pad layer 21 made of ITO electrically connected to
Is provided.

When manufacturing this thin film transistor array substrate, first, as shown in FIGS. 1 and 2, silicon dioxide and a silver alloy of an undercoat film 24 are continuously formed on a glass substrate 5, and this is usually formed. Gate electrode 6 and gate wiring 1 by patterning using photolithography technology
To form Further, a lower pad layer 17 is formed in the gate terminal pad section 15. The purpose of the undercoat film 24 is as follows.
Silicon nitride and tantalum oxide may be used to improve the film adhesion of the silver alloy.

Next, the gate electrode 6, the gate wiring 1
, An a-Si film 8 (semiconductor film), an a-Si: n + film 9 (impurity semiconductor film), and a silver alloy film 10 are continuously formed on the entire surface of the substrate. On this occasion,
Continuous film formation can also be performed in the same vacuum atmosphere using the same film forming apparatus.

Next, after a photoresist (not shown) is applied on the silver alloy film 10, the photoresist is exposed and developed using one photomask to form a resist pattern. As a mask, only two layers of the silver alloy film 10 and the a-Si: n + film 9 out of the above four layers are etched. Thus, an ohmic contact layer made of the a-Si: n + film 9 and the drain electrode 11, the source electrode 10, and the source wiring 2 made of the silver alloy film 10 are formed.

Next, a SiNx film is formed on the entire surface to form a passivation film 12, a photoresist (not shown) is applied on the SiNx film, and the photoresist is exposed and developed using a single photomask. To form a resist pattern, and using the resist pattern as a mask, the passivation SiNx film 12, the a-Si film 9, the gate insulating film
The three layers of the iNx film 7 are etched. In this way,
The passivation film 12, the semiconductor film 8, and the gate insulating film 7 whose end positions are aligned are formed.

In this step, when the passivation film 12 is etched, the passivation film 12 on the drain electrode 11, the gate terminal pad 15 and the passivation film 12 on the lower pad 16 of the source terminal pad are partially removed. Open contact hole 1 for electrically connecting drain electrode 11 and pixel electrode 14
3. Form contact holes 19 and 20 for electrically connecting the lower pad layer 17 and the upper pad layer 18, respectively.

When the passivation film 12 is etched to form the contact holes 13, 19 and 20, the silver alloy in the contact holes will be exposed.
In the etching of the -Si film 8 and the etching of the gate insulation 7, the silver alloy in such a portion is not etched.

Next, an ITO film is formed on the entire surface, and is patterned by using a usual photolithography technique, so that the pixel electrode 14 and the gate terminal pad portion 15 are formed.
Upper pad layers 19 and 20 of the source terminal pad portion are formed. Through such steps, a thin film transistor array substrate can be manufactured. Then, a counter substrate on which the thin film transistor array substrate and the common electrode are formed is prepared, and a liquid crystal is sealed between the substrates to complete the liquid crystal display device having the above configuration.

In the method of manufacturing a thin film transistor array substrate according to the present embodiment and a liquid crystal display device using the thin film transistor array substrate manufactured by the method, patterning for forming a gate portion, formation of a source / drain portion, and formation of an ohmic contact layer are performed. For patterning,
The patterning process is performed four times, such as patterning the insulating film and the semiconductor film and patterning for forming the pixel electrode, and the number of photomasks used is four.

That is, in the method of manufacturing a thin film transistor array substrate according to the present embodiment, the source / drain layer and the ohmic contact layer and the ohmic contact layer are formed instead of being sequentially patterned from the lower layer as in the conventional manufacturing process. By patterning the insulating film and the semiconductor film with one photomask, the conventional five-mask process becomes a four-mask process, and the number of photomasks used can be reduced. As a result, in manufacturing the liquid crystal display device, it is possible to reduce the manufacturing cost and the construction period.

In the case of the present embodiment, if Ti / Al / Ti is used for the gate material and the source material, an etching reaction product peculiar to Al dry etching is generated when dry etching is performed. There remain problems such as an increase in the number of point defects, difficulty in controlling the gate taper of the laminated film, deterioration in the step coverage characteristics of the gate wiring, and reduction in the yield.

On the other hand, when a silver alloy is used for the gate material and the source / drain material, the control of the etching shape is relatively easy as compared with the dry etching, and the patterning is performed by using the wet etching which is advantageous for dust adhesion. It is possible to do.

Further, since the gate electrode and the source / drain electrodes are made of the same material of silver alloy, only one film forming apparatus and one wet etching apparatus can be invested. In manufacturing the liquid crystal display device, the yield can be improved and the manufacturing cost can be reduced.

[0045]

As described above, according to the method of manufacturing a thin film transistor array substrate according to the present invention, patterning for forming a gate portion, patterning for forming a source / drain portion and an ohmic contact layer, patterning for forming a thin film transistor, and forming a pixel electrode. As in the case of patterning, the number of patterning steps is basically four, and the number of photomasks used is four. As described above, according to the present invention, a plurality of films are collectively patterned using the same photomask, so that the conventional five-mask process becomes a four-mask process, and the number of photomasks used can be reduced. Because it is possible, in manufacturing the liquid crystal display device, it is possible to reduce the manufacturing cost and shorten the construction period.

Further, by using a silver alloy as a specific material of the gate electrode and the source / drain electrode, the gate shape can be easily controlled, which is advantageous for dust adhesion at the time of patterning the gate electrode and the source / drain electrode. Wet etching that requires a small capital investment can be used. As a result, it is possible to achieve both a reduction in capital investment and an improvement in the yield and a reduction in the resistance of the gate wiring and the source / drain wiring.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process of a liquid crystal display device using a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 2 is a plan view of a liquid crystal display device using the thin film transistor array substrate according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing process of a conventional thin film transistor array substrate and a liquid crystal display device using the same.

FIG. 4 is a plan view of a conventional thin film transistor array substrate and a liquid crystal display device using the same.

DESCRIPTION OF REFERENCE NUMERALS 1 gate wiring 2 source wiring 3, 14 pixel electrode 4 thin film transistor 5 transparent insulating substrate (glass substrate) 6 gate electrode 7 gate insulating film 8 semiconductor film 9 a-Si: n + film 10 source electrode 11 drain electrode DESCRIPTION OF SYMBOLS 12 Passivation film (insulating film) 13, 19, 20 Contact hole 15 Gate terminal pad part 16 Source terminal pad part 17 Gate lower pad layer 18 Source lower pad layer 21 Gate upper pad layer 22 Source upper pad layer 23 Island part 24 Undercoat film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/3205 H01L 29/78 616V 21/3213 626C 21/88 CMF term (Reference) 2H090 HA03 HA04 HB03X HB04X LA04 2H092 JA26 JA28 JA34 JA37 JA41 JA45 JA46 NA27 NA29 4M104 AA01 AA10 BB01 BB08 BB36 BB40 CC01 DD17 DD34 DD64 EE02 EE14 EE16 EE17 FF09 GG09 GG10 GG14 GG20 GG20 GG20 HH09 HH16 GG04 GG04 GG04 QQ19 QQ37 RR03 RR04 RR06 VV15 XX08 XX14 XX21 XX33 XX34 5F110 AA03 AA16 BB01 CC07 DD02 DD12 DD13 DD14 EE06 EE37 FF03 GG02 GG15 HK06 HK09 HK16 HK21 HK25 HL07 NN02 NN24 QQ09

Claims (4)

[Claims] A step of providing an undercoat insulating film on the insulating substrate; a step of providing a gate electrode on the undercoat insulating film; and forming a first insulating film on the insulating substrate and the gate electrode. Providing a semiconductor layer, a source electrode, and a drain electrode above the first insulating film so as to oppose each other in a portion other than a channel formation region immediately above the gate electrode; , The source electrode, the drain electrode,
Providing a second insulating film on the channel forming region, providing a contact hole on the gate electrode and the train electrode, and providing a pixel electrode above the contact hole. Of manufacturing a thin film transistor array substrate. 2. The method according to claim 1, wherein a material of the gate electrode, the source electrode, and the drain electrode is a silver alloy. 3. The method according to claim 1, wherein a material of the undercoat insulating film on the insulating substrate is any of silicon dioxide, silicon nitride, and tantalum oxide. 4. A liquid crystal display device comprising a liquid crystal material sandwiched in a gap between two opposing insulating substrates, wherein one of the insulating substrates has a surface in contact with the liquid crystal material. 4. A liquid crystal display device comprising a thin film transistor manufactured by the method for manufacturing a thin film transistor array substrate according to any one of 1 to 3 as a switching element.