JP2002314069A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of high-frequency operation and having a high drain withstand voltage. A semiconductor device according to the present invention includes a semiconductor substrate (12) of a first conductivity type, a gate electrode (3) formed on the semiconductor substrate (12), and one side of the gate electrode (3). A source region (41) made of a diffusion layer of the second conductivity type formed on the semiconductor substrate of the second type, and a diffusion layer of the second conductivity type formed on the semiconductor substrate (12) on the other side of the gate electrode (3) Drain region (44), source region (41) and drain region (4
4) and a first conductivity type diffusion layer (1) formed under the isolation insulating film (11) provided under the isolation insulating film (11).
5) the length of the second conductivity type diffusion layer (44) of the drain region in the gate length direction is longer than the length of the second conductivity type diffusion layer (41) of the source region. The impurity concentration at the end of the first conductive type diffusion layer (15) facing the drain region (44) is 1 × 10 ¹⁶ cm ⁻³ or more and 2 × 1
It is within the range of 0 ¹⁸ cm ⁻³ or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a transistor for amplifying a high-frequency signal.

[0002]

2. Description of the Related Art A silicon MOS technology is applied as a transistor for amplifying a high frequency signal of about 1 to 2 GHz of a mobile phone or the like to an electric power of about 0.1 to 100 W and transmitting the same as radio waves to the air via an antenna. LDMOS (Laterally
Diffused Metal Oxide Semiconductor) transistors are used.

FIG. 5 is a plan view of a conventional LDMOS transistor. In the figure, 1 is an active layer (silicon), 11 is an isolation oxide film (1 μm thick Si) provided outside the active layer 1.
O ₂ ), 2 is a P-type source wireless diffusion layer (silicon containing about 1 × 10 ¹⁷ cm ^{−3 of} boron (B)), and 3 is a gate electrode (thickness on a polycrystalline silicon having a thickness of 100 nm). 300 nm tungsten silicide (WS
i) is formed of a multilayer film), 41 is an N ⁺ diffusion layer on the source region side (silicon containing arsenic (As) of about 1 × 10 ²¹ cm ⁻³ , and the symbol “ ⁺ ” indicates impurities. Reference numeral 42 denotes an N ⁺ diffusion layer (silicon containing about 1 × 10 ²¹ cm ^{−3 of} arsenic (As)) on the drain region side. Here, the active layer 1 indicates a region other than the portion covered with the isolation oxide film 11.

FIG. 6 is a sectional view taken along line B-B 'in FIG.
Shows the structure. In the figure, reference numeral 12 denotes a specific resistance of 10 mΩ · cm.
P-type silicon substrate, 13 is on the P-type silicon substrate 12
Resistivity of 10Ω · formed by epitaxial growth
cm of silicon layer, 14 is formed under the oxide film 11 for isolation.
P-type isolation diffusion layer (boron (B) is 4 × 10^Fifteencm
^-3To the extent of silicon), 43 is a P-type diffusion layer
(Boron (B) is 1 × 10 ¹⁷cm^-3Degree included
Silicon), 44 is N provided on the drain region side.⁻diffusion
Layer (phosphorus (P) is 5 × 10¹⁷cm^-3Degree included
silicon,"⁻Indicates that the impurity is N⁺Lower concentration
5 is the first aluminum wiring (thickness: 500 n)
m) and 6 are the second aluminum wiring (thickness 2 μm), 7
a and 7b are interlayer insulating films (SiO₂), Respectively.

Next, the structure and operation of a conventional LDMOS transistor will be briefly described. N ⁺ on the source region side
Diffusion layer 41 is connected to source wireless diffusion layer 2 via first aluminum wiring 5 and second aluminum wiring 6. The source wireless diffusion layer 2 is further connected to a silicon substrate 12 having a specific resistance of 10 mΩ · cm. Therefore, since the source region of the LDMOS transistor can be electrically connected to the lead of the semiconductor package by grounding the silicon substrate 12, a bonding wire for the source on the semiconductor chip is not required. By the way, this is the reason for source wireless. By eliminating the bonding wire only on the source side and reducing the inductance component (resistance) of the bonding wire, stable operation in a high frequency band is enabled.

The N ⁺ diffusion layer 42 in the drain region is provided at a distance of about 7 μm from the end of the gate electrode 3, and a region other than the N ⁺ diffusion layer 42 within the active layer 1 in the drain region is an N ⁻ diffusion layer. 44 are provided. The N ⁺ diffusion layer 42 is connected to an external bonding wire (not shown) via the first aluminum wiring 5 and the second aluminum wiring 6.

When the voltage of the gate electrode 3 is 0 V, the voltage of the source electrode, that is, the voltage of the silicon substrate 12 is 0 V, and a positive voltage is applied to the drain terminal (bonding wire (not shown) connected to the drain region). think of. In this case, since the voltage of the gate electrode 3 is 0 V, the transistor is off and no current (drain current) flows between the source and the drain.

- 0008] Here the drain voltage increases, the drain depletion layer (not shown) is extended from the drain region side to the 3 below the gate electrode, in contact with the source region side N ⁺ diffusion layer 41, N ⁺ diffusion layer 41 , A so-called punch-through current flows between the source and the drain.
The drain voltage at which this punch-through current flows is
It is defined as the drain breakdown voltage.

In an LDMOS transistor, N in the source region
^{Since the} low-concentration N ⁻ diffusion layer 44 is relatively longer in the gate length direction than the ⁺ diffusion layer 41, a large drain voltage is required for the drain depletion layer (not shown) to contact the N ⁺ diffusion layer 41 on the source region side. Is required, the source-drain breakdown voltage is improved.

The P-type diffusion layer 43 is provided to set the threshold voltage (Vth) of the LDMOS transistor to about 1V. The reason why such a P-type diffusion layer is not provided on the drain region side is that the N ⁺ diffusion layer 42 and the N
^The reason is that the impurity concentration of the P-type impurity region (13 in the figure) in contact with the diffusion layer 44 is not increased as much as possible.

When the concentration of the P-type impurity on the drain region side increases, the depletion layer of the PN junction in the drain region becomes narrower,
The capacitance of the depletion layer increases, that is, the capacitance between the drain and the silicon substrate increases, which adversely affects high-frequency operation. Incidentally, the reason that the P-type diffusion layer 43 is not provided on the drain region side, that is, the existence of a concentration gradient in the gate length direction is the reason for Laterally Diffused LDMOS.

As described above, in the LDMOS transistor, the gate length is reduced (for example, 0.5 μm), the source wireless structure is adopted, and the threshold voltage (Vth) setting P-type diffusion layer is not provided in the drain region. The high-frequency characteristics are improved by devising, and the low-concentration N ⁻ diffusion layer 44, which is relatively longer in the gate length direction than the N ⁺ diffusion layer 41 in the source region, exists, so that a drain depletion layer (not shown) is formed. A large drain voltage is required to come into contact with the N ⁺ diffusion layer 41 on the source region side, so that the source-drain withstand voltage is improved.

[0013]

However, in recent years, there has been a need to increase the power supply voltage to 25 V or more (for example, 50 V) due to a demand for a transistor capable of higher output operation. Since the source-drain breakdown voltage of the high-frequency transistor needs to be three times as large as the power supply voltage, further improvement of the source-drain breakdown voltage of the LDMOS transistor (from the conventional 80 V to 150 V) has become indispensable.

Heretofore, the drain-depletion layer has been extended from the drain region side N ⁺ diffusion layer 42 to the source region side N ⁺ diffusion layer 41 as the drain voltage increases, and the source region side N ⁺ It was thought that it was determined by reaching the diffusion layer 41. Conventional LDM
Also in the OS structure, the drain depletion layer is extended longer by providing the drain region side N ⁻ diffusion layer 44 longer in the gate length direction than the source region side N ⁺ diffusion layer 41, and theoretically, the source voltage of about 150 V is applied.・ Drain breakdown voltage should have been obtained. However, only a withstand voltage of about 75 to 80 V was actually obtained.

[0015] Therefore, the present inventors have revealed that the pursuit of the causes, the drain region side N ⁺ diffusion layer 42 → the drain region side N ^- route of diffusion layer 44 → isolation diffusion layer 14 → the source region side N ⁺ diffusion layer 41 Thus, it was found that a current leak path was formed, and this was the cause of failure to obtain the original source-drain breakdown voltage. [Study on factors determining source-drain breakdown voltage]
The following describes the results of an investigation on factors that determine the breakdown voltage between the source and the drain.

Drain region side N⁺A positive high voltage is applied to the diffusion layer 42.
Pressure (drain voltage), as described above,
A rain depletion layer is formed under the gate electrode 3, that is, in the source region.
Side N ⁺It extends in the direction of the diffusion layer 41. At the same time,
The recon substrate 12 and the P-type silicon layer 13 are grounded.
Therefore, the drain depletion layer is an isolation diffusion layer below the isolation oxide film 11.
It also extends in the direction of 14. Incidentally, the separation oxide film 11
Is formed by LOCOS (Local Oxidation of Silicon) method
Have been.

In the LOCOS method, micro defects due to stress are generated in the silicon layer 13 below the end of the isolation oxide film 11. FIG. 7 shows a cross-sectional structure taken along the line CC ′ in FIG. 5, and the crosses in the figure indicate locations where such micro defects occur. The drain depletion layer extends to the isolation diffusion layer 14,
When the minute defect enters the drain depletion layer and the electric field in the region of the minute defect exceeds a certain value, an electron-hole pair is generated from the minute defect. The generated electrons and holes are accelerated by the electric field and cause avalanche collapse. The increased electrons go to the N ⁺ diffusion layer 42 on the drain region side (the direction opposite to the arrow D in FIG. 5), and the holes pass below the gate electrode 3 and go to the N ⁺ diffusion layer 41 on the source region side. (Arrow E in FIG. 5)
Direction).

Electric charges are generated from a small defect by a relatively low electric field.
, The drain region side N in the active layer 1⁺Diffusion layer
With the drain voltage determined by the distance between 42 and the gate electrode 3
Current between the drain and source (the arrows of D and E in FIG. 5 indicate the current
Flows), but the drain voltage
Is lower than the source-drain breakdown voltage. That is, LD
The breakdown voltage between the source and drain of the MOS
It has been found that it is determined by the small defects. Further
In addition, the source-drain breakdown voltage is N on the drain region side. ⁺diffusion
The distance between the layer 42 and the isolation oxide film 11 (shown by H in FIG. 7)
It is also clear that the distance decreases as the distance (7 μm) decreases.
It was ok.

The present invention has been developed based on the above research results.
In order to improve the breakdown voltage in the MOS from the state controlled by the drain breakdown voltage caused by the minute defect generated in the isolation diffusion layer 14 as described above to the original source-drain breakdown voltage, the impurity concentration in the isolation diffusion layer 14 is increased. It is an object of the present invention to provide an element structure in which the drain withstand voltage is improved by preventing the drain depletion layer from extending into the separation / diffusion layer 14 due to the high concentration.

[0020]

A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate, and a semiconductor substrate on one side of the gate electrode. A source region made of a diffusion layer of the second conductivity type, a drain region made of a diffusion layer of the second conductivity type formed on the semiconductor substrate on the other side of the gate electrode,
A gate electrode, an isolation insulating film provided outside the source region and the drain region, and an element isolation region comprising a first conductivity type diffusion layer formed in the semiconductor substrate below the isolation insulating film; The length of the second conductivity type diffusion layer in the drain region in the gate length direction is longer than the length of the second conductivity type diffusion layer in the source region, and the end of the first conductivity type diffusion layer facing the drain region is The impurity concentration is 1 × 10 ¹⁶
cm ⁻³ or more.

Further, in the semiconductor device according to the present invention, the second conductivity type diffusion layer in the drain region is provided inside the low-concentration diffusion layer and the low-concentration diffusion layer, and has a lower impurity concentration than the low-concentration diffusion layer. A high-concentration diffusion layer, and a distance between opposing ends of the high-concentration diffusion layer and the isolation insulating film in the gate width direction is set to a distance between the high-concentration diffusion layer and the gate electrode in the gate length direction. It is larger than the distance between the parts.

Further, in the semiconductor device according to the present invention, the distance between the opposing ends of the high concentration diffusion layer and the isolation insulating film in the gate width direction and the high concentration diffusion layer and the gate electrode in the gate length direction are provided. The difference between the distances between the opposing ends is 2 μm or more and 6 μm or less.

Further, in the semiconductor device according to the present invention, the first device provided with a predetermined width at the boundary of the element isolation region is provided.
A gate electrode comprising a portion having a gate length of the above and a portion having a second gate length other than this portion, and a length formed in the semiconductor substrate immediately below the gate electrode and substantially matching the gate length of the gate electrode A second diffusion layer of the first conductivity type, wherein the first gate length is longer than the second gate length.

Further, in the semiconductor device according to the present invention, the difference between the first gate length and the second gate length is set to 0.1.
It is not less than μm and not more than 0.6 μm.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. FIG. 1 is a plan view showing the structure of an LDMOS transistor according to Embodiment 1 of the present invention. In the figure, 1 is an active layer (silicon), 11 is an active layer 1
Isolation oxide film (1 μm thick Si
O ₂ ), 2 is a P-type source wireless diffusion layer (silicon containing about 1 × 10 ¹⁷ cm ^{−3 of} boron (B)), and 3 is a gate electrode (thickness on a polycrystalline silicon having a thickness of 100 nm). 300 nm tungsten silicide (W
41) an N ⁺ diffusion layer (silicon containing arsenic (As) of about 1 × 10 ²¹ cm ⁻³ ) on the source region side, and the symbol “ ⁺ ” represents impurities. Reference numeral 42 denotes an N ⁺ diffusion layer (silicon containing about 1 × 10 ²¹ cm ^{−3 of} arsenic (As)) on the drain region side.

FIG. 2 is a sectional view taken along line A-A 'of FIG.
FIG. In the figure, 12 is a P-type with a specific resistance of 10 mΩ · cm.
The silicon substrate 13 is formed on the P-type silicon substrate 12 by epitaxy.
Specific resistance of 10Ω · cm formed by axial growth
A silicon layer 15 is formed of a P layer formed under the oxide film 11 for isolation.
Mold separation diffusion layer (boron (B) is 1 × 10¹⁷cm⁻³degree
43) is a P-type diffusion layer (boron)
(B) is 1 × 10¹⁷cm ^-3Degree included silico
) And 44 are N provided on the drain region side.⁻Diffusion layer
(P) is 5 × 10¹⁷cm^-3Degree included silico
"⁻Indicates that the impurity is N⁺Indicates lower concentration
5) is a first aluminum wiring (500 nm thick),
6 is a second aluminum wiring (thickness 2 μm),
Show. This structure is the same as a conventional LDMOS transistor.
Like, N in the source area⁺Gate length direction compared to diffusion layer 41
Relatively long low concentration N⁻The diffusion layer 44 exists.

The separation diffusion layer 15 (FIG. 2) of the LDMOS transistor of the first embodiment contains boron as a P-type impurity at 1 × 10 ¹⁷ cm ⁻³ . Here, the impurity concentration refers to the concentration at the outermost surface of the separation diffusion layer 15 (the part facing the source / drain region side and close to the separation oxide film 11, the X part in FIG. 2). LDMOS in Embodiment 1
In the transistor, the impurity concentration of the separating diffusion layer 15 is a conventional LDMOS transistor (about 4 × 10 ¹⁵ cm ⁻³ ).
Since the concentration is higher, the drain voltage when the drain depletion layer reaches the minute defect existing in the isolation diffusion layer 15 becomes higher than in the case of the conventional structure.

As a result, the source-drain breakdown voltage, which was as low as about 80 V due to the presence of the conventional isolation diffusion layer having an impurity concentration of about 4 × 10 ¹⁵ cm ^{−3, is changed} to the N ⁺ diffusion of the source region in the present structure. The original withstand voltage between the source and the drain caused by the presence of the low-concentration N ⁻ diffusion layer 44 which is relatively longer in the gate length direction than the layer 41 can be improved to about 150 V.

Such an improvement effect can be obtained by the separation diffusion layer 15.
Has a P-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or more on the outermost surface,
More preferably, it occurs at 5 × 10 ¹⁶ cm ⁻³ . this is,
This is because the extension of the depletion layer is inversely proportional to the impurity concentration, and thus, by increasing the impurity concentration, the extension of the drain depletion layer in the isolation diffusion layer 15 is significantly suppressed.

Embodiment 2 FIG. Second Embodiment LD of the Present Invention
The MOS transistor will be described with reference to FIG. In the LDMOS transistor according to the second embodiment, boron, which is a P-type impurity, is contained in the isolation diffusion layer 15 by 5 × 10 ¹⁶ cm.
^-3 included. In addition, the distance (F in FIG. 3) between the N ⁺ diffusion layer 42 in the drain region and the isolation oxide film 11 in the gate width direction is about 10 μm, and the end of the gate electrode 3 facing in the gate length direction. It is set to be longer than the distance (G in FIG. 3, 5 μm) between the gate electrode and the drain region side N ⁺ diffusion layer 42 end. Therefore, the drain voltage when the drain depletion layer reaches the minute defect existing in the isolation diffusion layer 15 becomes higher than in the case of the first embodiment. As a result, the withstand voltage between the source and the drain is improved. When the difference between the distances is 2 μm or more, the effect of improving the source-drain withstand voltage is obtained.

On the other hand, if the difference between the distances exceeds 10 μm, the distance F between the N ⁺ diffusion layer 42 in the drain region and the active layer 1 is increased.
Becomes large, and this causes an increase in drain resistance, so that device characteristics are degraded. Therefore, in order to operate the LDMOS transistor according to the present invention satisfactorily, it is necessary to set the difference between the distances between 2 μm and 10 μm.

If the boron concentration of the isolation diffusion layer 15 is increased in the LDMOS transistor, as described in the first embodiment, the source-drain breakdown voltage is improved only by the effect. However, if the concentration of the isolation diffusion layer 15 is increased, the extension of the drain depletion layer is suppressed, and as a result,
The width of the drain depletion layer decreases and the parasitic capacitance between the drain and the silicon substrate increases. This increase in parasitic capacitance is due to the LDM
It degrades the high-frequency characteristics of the OS transistor. Example 1
In this case, although the source-drain breakdown voltage has the advantage of being improved to 150 V, the gain of the transistor at the time of operation at 2 GHz is reduced by 3 dB, which may cause inconvenience depending on the application.

Therefore, in the LDMOS transistor of the second embodiment, the N ⁺ diffusion layer on the drain region side in the gate width direction is used.
The distance F between the isolation oxide film 11 and the isolation oxide film 11 is relatively longer than the distance G between the gate electrode 3 and the drain region side N ⁺ diffusion layer 42 in the gate length direction.
Although the boron concentration of No. 5 is higher than that of the conventional structure, the parasitic capacitance is reduced by suppressing the element structure of the first embodiment, thereby improving the high frequency characteristics (there is almost no decrease in gain).
And an improvement in the withstand voltage between the source and the drain (150 V).

Embodiment 3 FIG. Example 3 LD of the Present Invention
The MOS transistor will be described with reference to FIG.

In the LDMOS transistor of the third embodiment, as in the second embodiment, the separation diffusion layer 15 contains boron as an impurity at 5 × 10 ¹⁶ cm ⁻³ . In addition to this,
The gate length (first gate length) of the gate electrode 31 near the boundary between the isolation oxide film 11 and the active layer 1 in the gate width direction is 1 μm, and the gate length of the gate electrode 3 inside the active layer 1 (second gate). Length) of 0.5 μm. The P-type diffusion layer 4 located below the gate electrode 31
3 (the second diffusion layer of the first conductivity type) also has a width substantially coincident with the gate electrode 31.

Generally, holes generated from minute defects in the isolation diffusion layer 15 pass through the lower part of the gate electrode 31 near the boundary between the isolation oxide film 11 and the active layer 1 so that the source region side N
⁺ Diffusion layer 41 flows. This inflow current is collected by the drain region side N ⁺ diffusion layer 42 as a collector, the P type diffusion layer 43 below the gate electrode 31 as a base, and the source region side N ⁺ diffusion layer 41.
Is the base current of the parasitic bipolar transistor having the emitter as the emitter. Therefore, the source-drain withstand voltage is also deteriorated by the fact that the parasitic bipolar transistor is turned on and a current of a gain times the current (of the parasitic bipolar transistor) flows between the drain and the source.

In the LDMOS transistor of the third embodiment,
Since the gate length of the gate electrode 31 in the region where the inflow current generated from the minute defect at the boundary between the isolation oxide film 11 and the active layer 1 flows is longer than the gate length of the gate electrode 3 on the active layer 1, The effect of effectively increasing the base width of the parasitic bipolar transistor is produced. As a result, the current between the drain and the source is suppressed because the gain of the parasitic bipolar transistor is reduced, and the withstand voltage between the source and the drain is further improved to about 170 V. Such an effect occurs when the difference between the two gate lengths is 0.1 μm or more.

On the other hand, even if the gate length of the gate electrode 3 on the active layer 1 is excessively long, the drain withstand voltage tends to be saturated, and the above-mentioned effect is effectively produced because the difference between the two gate lengths is zero. 0.6 μm or less.

The present invention is not limited to the above embodiment. Further, in the above embodiment, NM
Although the OS is used, a PMOS may be used.

Further, in the above-described embodiment, the LDMOS transistor has been described as an example. However, the present invention is not limited to such a structure. If the length of the source and drain regions in the gate length direction is asymmetric, the same applies. Effect is exhibited. In such a structure, the source-drain withstand voltage is higher than that of a general structure in which the lengths of the source region and the drain region are symmetric, and the influence of the drain withstand voltage due to minute defects in the diffusion layer below the isolation insulating film. This is because it is possible to prevent

Also, the material of the gate electrode has been described as an example of a laminated film of polycrystalline silicon and WSi. However, the material is not particularly limited as long as it has a low resistance and can withstand heat treatment during transistor formation. .

[0042]

According to the semiconductor device of the present invention, a semiconductor substrate of the first conductivity type, a gate electrode formed on the semiconductor substrate, and a second conductivity type formed on the semiconductor substrate on one side of the gate electrode are provided. And a second region formed in the semiconductor substrate on the other side of the gate electrode.
A drain region made of a conductive diffusion layer, a gate electrode,
An element isolation region formed of a first conductivity type diffusion layer formed in a semiconductor substrate below the isolation insulating film and the isolation insulating film provided outside the source region and the drain region; The length of the second conductivity type diffusion layer of the drain region is longer than the length of the second conductivity type diffusion layer of the source region, and the impurity concentration at the end of the first conductivity type diffusion layer facing the drain region is Since it is 1 × 10 ¹⁶ cm ⁻³ or more, the drain voltage at the time when the drain depletion layer reaches the minute defect existing in the separation diffusion layer becomes high, so that the source-drain withstand voltage is improved. A semiconductor device with improved drain-to-drain breakdown voltage can be realized.

In the semiconductor device according to the present invention, the second conductivity type diffusion layer in the drain region is provided with the low concentration diffusion layer and the impurity concentration lower than the low concentration diffusion layer provided inside the low concentration diffusion layer. A high-concentration diffusion layer having a high-concentration diffusion layer, and a distance between opposing ends of the high-concentration diffusion layer and the isolation insulating film in the gate width direction is set to an opposite end of the high-concentration diffusion layer and the gate electrode in the gate length direction. Since the distance is larger than the distance between the parts, the parasitic capacitance is reduced, thereby realizing both improvement of the high frequency characteristics and improvement of the withstand voltage between the source and the drain.

Further, in the semiconductor device according to the present invention, a portion having a first gate length provided at a boundary of the above-described element isolation region with a predetermined width and a portion having a second gate length other than this portion are provided. And a second first conductivity type diffusion layer formed in the semiconductor substrate immediately below the gate electrode and having a length substantially equal to the gate length of the gate electrode. Is larger than the second gate length, the gain of the parasitic bipolar transistor is reduced, so that the current between the drain and the source is suppressed and the withstand voltage between the source and the drain is further improved.

[Brief description of the drawings]

FIG. 1 is a plan view of an LDMOS transistor of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the LDMOS transistor of the semiconductor device according to the present invention, taken along line AA ′ in FIG.

FIG. 3 is a plan view of Embodiment 2 of the LDMOS transistor of the semiconductor device according to the present invention.

FIG. 4 is a plan view of an LDMOS transistor of a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a plan view of a conventional LDMOS transistor.

FIG. 6 shows a conventional LDMOS transistor.
It is sectional drawing along BB 'in a middle.

FIG. 5 in a conventional LDMOS transistor
It is sectional drawing along CC 'in the inside.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 active layer, 11 isolation oxide film, 12 silicon substrate, 13 P-type silicon layer, 14 P-type isolation diffusion layer formed under isolation oxide film 11, 15 isolation diffusion layer, 2 source wireless P-type diffusion Layers, 3, 31
Gate electrode, 41 N ⁺ diffusion layer on source region side, 42
N ⁺ diffusion layer on drain region side, 43P type diffusion layer, 4
4 N ^- diffusion layer on drain region side, 5 first aluminum wiring, 6 second aluminum wiring, 7a, 7b
Interlayer insulating film.

Continued on the front page F term (reference) 5F032 AA13 AC01 BA01 CA17 CA24 DA12 5F140 AA24 AA25 AC21 BA01 BA16 BF04 BF11 BF18 BF51 BF53 BH12 BH13 BH30 BH49 BJ05 BJ11 BJ15 CB01 CB03 CB10 CC03

Claims (5)

[Claims] A first conductive type semiconductor substrate; a gate electrode formed on the semiconductor substrate; and a second conductive type diffusion layer formed on the semiconductor substrate on one side of the gate electrode. A source region, a drain region formed of a second conductivity type diffusion layer formed on the semiconductor substrate on the other side of the gate electrode, and a separation provided outside the gate electrode, the source region, and the drain region. An element isolation region formed of a first conductivity type diffusion layer formed in the semiconductor substrate below the isolation insulating film, and a second conductivity type of the drain region in the gate length direction. The length of the diffusion layer is longer than the length of the second conductivity type diffusion layer of the source region, and the impurity concentration at the end of the first conductivity type diffusion layer facing the drain region is 1 × 10 ¹ A semiconductor device having a size of ⁶ cm ⁻³ or more. 2. A diffusion layer of a second conductivity type in the drain region, comprising: a low concentration diffusion layer; and a high concentration diffusion layer provided inside the low concentration diffusion layer and having a higher impurity concentration than the low concentration diffusion layer. Wherein the distance between the opposite ends of the high-concentration diffusion layer and the isolation insulating film in the gate width direction is the opposite end of the high-concentration diffusion layer and the gate electrode in the gate length direction. 2. The semiconductor device according to claim 1, wherein the distance is larger than a distance between the semiconductor devices. 3. A distance between opposing ends of the high-concentration diffusion layer and the isolation insulating film in the gate width direction and an opposition between the high-concentration diffusion layer and the gate electrode in the gate length direction. 2μ difference in the distance between the ends
3. The semiconductor device according to claim 2, wherein the length is not less than m and not more than 10 μm. 4. The gate electrode including a portion having a first gate length provided at a boundary of the element isolation region with a predetermined width, a portion having a second gate length other than the portion, and the gate electrode. A second first conductivity type diffusion layer formed in the semiconductor substrate immediately below and having a length substantially coinciding with the gate length of the gate electrode, wherein the first gate length is equal to the second gate length. 4. The semiconductor device according to claim 1, wherein the length is longer than the length. 5. The semiconductor device according to claim 4, wherein a difference between said first gate length and said second gate length is not less than 0.1 μm and not more than 0.6 μm.