JP2002314040A - Stacked semiconductor device - Google Patents

Abstract

(57) [Summary] An object of the present invention is to provide a stacked semiconductor device that can easily recognize each layer even when the number of stacked layers increases. A stacked semiconductor device includes three layers of a substrate on which a semiconductor chip is mounted and which has a position shift detection mark (or alignment mark) each having the same pattern shape and arranged at different rotation angles. It is characterized by being laminated as described above. Even if the number of layers is large, it is easy to recognize the positional deviation of each layer from the shape of the pattern. Further, since it is sufficient to observe the mark from the surface with X-rays, it is possible to perform a nondestructive inspection of the amount of positional deviation in the manufacturing process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a stacked semiconductor device in which a plurality of substrates on which semiconductor chips are mounted are stacked.

[0002]

2. Description of the Related Art A stacked semiconductor device is, for example, a chip / chip.
An n-layer substrate composed of an anisotropic conductor / glass epoxy or a polyimide tape or the like is laminated, and each substrate is electrically connected via a via. Instead of vias, a device for obtaining electrical connection by through holes is also included in the stacked semiconductor device.

In the above-mentioned stacked type semiconductor device, high functionality and low cost can be achieved by stacking n layers of substrates. However, as shown in FIG. Electrical connection becomes insufficient, resulting in a fatal failure.

FIG. 13 shows a conventional stacked semiconductor device, showing a state in which interlayer displacement has occurred during stacking of a stacked semiconductor package. In FIG. 13, reference numeral 20 denotes a functional layer in which a semiconductor chip 22 is mounted on a substrate 21 made of glass epoxy or polyimide tape with vias.
Reference numeral 3 denotes a substrate with vias on the surface of which an adhesive layer 24 is formed and connects each functional layer 20; 25, a built-in SUS plate; It is.

[0005] In FIG. 13, a deviation ΔD occurs between the upper functional layer 20 and the lower functional layer 20. In such a state, electrical connection between the upper and lower functional layers 20 cannot be established, resulting in a failure.

Heretofore, conventionally, the interlayer misalignment after lamination in the above-described stacked semiconductor device is performed by using a misalignment detection mark (or alignment mark) formed on the substrate 21.
It was grasped by observing the surface with X-rays or cutting the electrode portion and observing the cut surface.

[0007] However, the observation of the misalignment detection mark from the surface by X-rays cannot cope with the case where the number of stacked layers increases due to high integration. Up to two layers were the limit.

In the technique of cutting the electrode portion and observing the cut surface, the device is cut in two orthogonal directions, and by observing each cut surface, the amount of displacement in each of the X and Y directions can be grasped. In addition, there is a problem that it is difficult to determine the amount of cutting at a location and the amount of positional deviation in the θ direction (rotation direction). Moreover, because of the destructive test, inspection in the manufacturing process was impossible.

[0009]

As described above, the conventional stacked semiconductor device has a problem that it cannot cope with an increase in the number of stacked semiconductor devices.

[0010] Further, it is difficult to grasp the amount of cutting or the positional deviation in the rotation direction at a target location, and there is a problem that an inspection in a manufacturing process cannot be performed due to a destructive test.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a stacked semiconductor device which can easily recognize each layer even when the number of stacked layers is large. is there.

Another object of the present invention is to provide a stacked semiconductor device which can easily grasp the amount of positional deviation even when three or more layers are stacked, and can perform a nondestructive inspection of the amount of positional deviation in a manufacturing process. Is to do.

[0013]

SUMMARY OF THE INVENTION A stacked semiconductor device according to the present invention has a semiconductor chip mounted thereon, each having a misregistration detecting mark or alignment mark arranged in the same pattern shape and at different rotation angles. It is characterized in that three or more substrates are laminated.

Further, in the stacked semiconductor device of the present invention, a first substrate on which a semiconductor chip is mounted and which has a misregistration detection mark or an alignment mark each having the same pattern and arranged at different rotation angles. When,
A semiconductor chip is mounted, and three or more layers of a second substrate having a mark serving as a reference for a positional deviation limit of the positional deviation detecting mark or the alignment mark are laminated.

Further, in the stacked semiconductor device of the present invention, a first misalignment detection mark or a first alignment mark on which a semiconductor chip is mounted, each of which has the same pattern and is arranged at a different rotation angle. A plurality of first substrates having a semiconductor chip mounted thereon;
A second misalignment detection mark or a second alignment mark arranged in the same pattern shape as the first misalignment detection mark or the first alignment mark and at a different rotation angle, and the second misalignment detection A second substrate having a third misalignment detection mark or a third alignment mark disposed separately from the second alignment mark or the second alignment mark, and a semiconductor chip mounted thereon, each of which is provided with the above-described first and second alignment marks. A plurality of third displacement detection marks or fourth alignment marks having the same pattern shape as the third displacement detection mark or the third alignment mark and arranged at rotation angles different from each other. And a substrate.

Still further, in the stacked semiconductor device of the present invention, a first misalignment detection mark or a first alignment mark, on which a semiconductor chip is mounted, each of which has the same pattern and is arranged at a different rotation angle. A plurality of first substrates having marks and a second position on which a semiconductor chip is mounted and arranged in the same pattern shape as the first position deviation detection mark or the first alignment mark and at a different rotation angle. A misalignment detection mark or a second alignment mark, and a third misalignment detection mark or a third alignment mark disposed separately from the second misalignment detection mark or the second alignment mark A second substrate having a mark and a semiconductor chip mounted thereon, each of which is provided with the third position detection mark or the third position detection mark. A plurality of third substrates having a fourth misalignment detection mark or a fourth alignment mark arranged in the same pattern shape as the alignment mark and at different rotation angles from each other, and the first and second positions A first mark serving as a reference for a displacement limit of the displacement detection mark or the first and second alignment marks, and the third and fourth displacement detection marks or the third and fourth alignments; And a fourth substrate having at least one of a second mark serving as a reference for a positional deviation limit of the use mark.

In the stacked semiconductor device of the present invention, when a semiconductor chip is mounted and the number of stacked semiconductor chips is n, an n-gonal center region and at least one protruding region radially protruding from the center region are provided. The position misalignment detection mark or alignment mark
It is characterized by stacking n substrates sequentially arranged at n rotation angles.

Further, in the stacked semiconductor device of the present invention, when a semiconductor chip is mounted and the number of stacked semiconductor devices is n, n
A misalignment detection mark or an alignment mark having a square central region and at least one projecting region radially projecting from the central region are respectively aligned with 36
N first substrates sequentially arranged at a rotation angle of 0 ° / n;
A semiconductor chip is mounted thereon, and a second substrate having a mark serving as a reference for a position deviation limit of the position deviation detection mark or the alignment mark is laminated.

Further, in the stacked semiconductor device of the present invention, a semiconductor chip is mounted, and a first positional shift detection having an n-gonal central region and at least one projecting region radially projecting from the central region is provided. N-1 first substrates on which semiconductor marks or first alignment marks are sequentially arranged at a rotation angle of 360 ° / n, a semiconductor chip is mounted, and an n-gonal central region and this central region And at least one projecting area radially projected from the second position, the second position being arranged at a rotation angle of 360 ° / n with respect to the first positional deviation detection mark or the first alignment mark. A third position having a shift detection mark or a second alignment mark, an m-square central region, and at least one protruding region radially protruding from the central region. A second substrate having a misalignment detection mark or a third alignment mark, a semiconductor chip mounted thereon, having an m-square central region, and at least one protruding region radially protruding from the central region; The fourth misalignment detection mark or the fourth alignment mark is sequentially arranged at a rotation angle of 360 ° / m with respect to the third misalignment detection mark or the third alignment mark. And one third substrate.

Furthermore, in the stacked semiconductor device of the present invention, a semiconductor chip is mounted, and a first positional shift having an n-gonal center region and at least one protruding region radially protruding from the center region. Each of the detection mark and the first alignment mark is 360 ° / n
N-1 first substrates sequentially arranged at a rotation angle of, a semiconductor chip is mounted, and has an n-gonal central region, and at least one protruding region radially protruding from the central region, The first position deviation detection mark or the first position deviation detection mark
The second misalignment detection mark or the second misalignment detection mark arranged at a rotation angle of 360 ° / n with respect to the second alignment mark.
And a third misalignment detection mark or a third alignment mark having a m-square central region and at least one protruding region radially protruding from the central region. A fourth misalignment detection mark or a fourth alignment mark having a m-square central region on which the semiconductor chip is mounted and at least one protruding region radially protruding from the central region. And m-1 third substrates which are sequentially arranged at a rotation angle of 360 ° / m with respect to the third misalignment detection mark or the third alignment mark, respectively, and the first and second alignment marks. A first mark serving as a reference for a displacement limit of the displacement detection mark or the first and second alignment marks, and the third and fourth displacement detection marks; Use mark or the third and fourth
And a fourth substrate having at least one of the second marks serving as a reference for the positional deviation limit of the alignment mark.

According to the above configuration, each layer can be easily recognized even if the number of layers increases. In addition, even when three or more layers are stacked, the amount of misalignment can be easily grasped, and nondestructive inspection of the amount of misalignment in the manufacturing process becomes possible.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1 (a) and 1 (b)
2A and 2B show functional layers in the stacked semiconductor device according to the first embodiment of the present invention, wherein FIG.
The figure is a cross-sectional view along the line AA 'in FIG. FIG.
In (a) and (b), 1 is a glass epoxy or polyimide tape with a via, 2 is a Cu wiring, 3 is a core hole,
Numeral 4 denotes a semiconductor chip, numeral 5 denotes an anisotropic conductive film, numeral 6 denotes a misregistration detection mark (or alignment mark), and numeral 7 denotes a via in which a plug is embedded.

The semiconductor chip 4 comprises an anisotropic conductive film 5 and Cu
The wiring 2 is mounted on the glass epoxy or polyimide tape 1 with vias. The misalignment detection mark (or alignment mark) 6 is used for positioning and detecting the amount of misalignment when a plurality of functional layers are stacked. The core hole 3 is used for laminating through the positioning pin when mounting on the built-in SUS board 14.

FIG. 2 shows a stacked package in which the functional layers shown in FIGS. 1A and 1B are stacked. FIG.
In the figure, 8 is a substrate with a via having an adhesive layer 9 formed on the surface, 10 is a solder ball, 11 is a surface layer, and 12 is a via in which a plug is embedded.

The plurality of functional layers 13 are formed on the substrate 8 with vias.
Are laminated using the via 12 with the functional layers 13 interposed therebetween.
The substrate 8 with vias is bonded by an adhesive layer 9. At this time, the positions of the upper functional layer 13 and the lower functional layer 13 are aligned by detecting the amount of positional deviation by the positional deviation detecting mark (or alignment mark) 6.

FIG. 3 shows a stacked semiconductor device formed by stacking the stacked packages shown in FIG.
Reference numeral 14 denotes a built-in SUS board.
Are provided with positioning pins 15 for positioning each of the stacked packages 16.

FIGS. 4 (a) and 4 (b) correspond to FIGS.
5 is a plan view of the via-attached substrate 8 in FIG. (A) is a plan view of the entire substrate 8 with vias, and (b) is a mark for detecting misalignment between the substrates in FIG. (A) (the same is true for the misalignment detection mark or alignment mark in FIG. 1).
Is shown.

When the four layers of the substrate interlayer displacement detecting marks 6 are laminated, they have an L-shaped pattern shape. For example, the overall width D1 is 0.3 ± 0.05 mm and the corners (center Area) width D2 is 0.07 ± 0.02 mm
It is.

As shown in FIGS. 5 (a) to 5 (d), the second layer of the via-mounted substrate is positioned relative to the substrate interlayer detection mark 6-1 provided on the lowermost via-mounted substrate. The substrate interlayer misalignment detection mark 6-2 provided on the third-layer via-attached substrate has a 90 ° counterclockwise rotation angle of 18 °.
At 0 °, the mark 6-4 for detecting interlayer misalignment provided on the fourth-layer (uppermost layer) substrate with vias is 27 counterclockwise.
It is arranged rotated by 0 °. In other words, 90
Are sequentially arranged at a rotation angle of °. At this time, the center 6-6 of the corner portion of the substrate interlayer displacement detection marks 6-1 to 6-4.
1C to 6-4C are arranged at the same position (the same coordinates).

Therefore, four via-coated substrates 8 are laminated,
When the mark is observed by X-rays from the surface, if there is a positional deviation between the substrate layers, the L-shaped pattern shown in FIG. If there is no displacement, a cross-shaped pattern shape as shown in FIG.

Therefore, even if the number of layers increases, it is easy to recognize the positional deviation of each layer from the shape of the pattern. Further, since it is sufficient to observe the mark from the surface with X-rays, it is possible to perform a nondestructive inspection of the amount of positional deviation in the manufacturing process.

In the first embodiment, the case where four layers are stacked has been described. However, when eight layers are stacked, the L-shaped pattern is provided on the substrate with vias located at the lowermost layer. Mark for detecting misalignment between substrate layers 6-1
On the other hand, the mark 6-2 for detecting the interlayer displacement between the substrates provided on the second-layer substrate with via is 45 °, and the mark 6-2 for detecting the interlayer displacement between the substrates provided on the third-layer substrate with via is provided.
The reference numeral 3 denotes 90 °, and the marks 6-4 for detecting the displacement between the substrate layers provided on the fourth-layer substrate with vias are 135 ° and 45 ° in order.
It is sufficient to displace them one by one.

As a result, if there is no positional deviation between the eight substrate layers, the pattern shape becomes as shown in FIG.

In the case of three layers, five layers, and six layers, the marks for detecting the displacement between the substrates are arranged at the center of the triangle, pentagon, or hexagon as shown in FIGS. The pattern may be provided with a pair of arms (protruding regions) radially protruding from the position, and may be arranged by being shifted by 120 °, 72 °, and 60 °, respectively. 60 ° with one arm
, 36 °, and 30 °, respectively, can be similarly applied to six, ten, and twelve layers.

[Second Embodiment] FIGS. 9 (a) to 9 (e)
Is for describing a stacked semiconductor device according to a second embodiment of the present invention, and shows extracted marks for detecting a displacement between the substrates in the via-attached substrate 8 in FIGS. 2 and 3. . The pattern shape of the marks for detecting the interlayer displacement between the substrates is the same as that of FIG. Is made possible. The first to third interlayer displacement detection marks are the same as those in FIGS. 5A to 5C, and FIGS.
(E) shows the pattern shapes of the fourth to eighth layers of the interlayer displacement detection marks.

That is, as shown in FIG. 8A, in the via-attached substrate 8, in addition to the positions corresponding to the first to third via-attached substrates, the substrate-to-substrate displacement detecting marks 6 are located at different positions. -1 ′ is provided. The fifth to seventh layers of the board interlayer displacement detection marks 6-5 to 6-7 are respectively 90 °, 180 °, and 270 ° counterclockwise with respect to the board interlayer displacement detection mark 6-1 ′. It is arranged to rotate. At this time, the centers 6-4C 'to 6-7C of the corners of the substrate interlayer displacement detection marks 6-4 to 6-7 are arranged at the same position (the same coordinates).

In the eighth layer of the substrate 8 with vias, marks 6-8 'for detecting interlayer displacement between substrates are further provided at different positions in addition to the positions corresponding to the fourth to seventh layers of the substrate with vias. I have. In the case of laminating nine or more layers, alignment and measurement of the amount of misalignment are performed in the same manner by using the mark 6-8 'for detecting inter-substrate misalignment.

According to such a configuration, even when a larger number of layers are stacked, the alignment and the measurement of the amount of positional deviation become easy.

In the above description, the case where the L-shaped marks for detecting the displacement between the substrates are laminated at a rotation angle of 90 ° has been described as an example. However, the marks may be laminated at a rotation angle of 45 °. Needless to say, a pattern-to-substrate-offset detection mark having a pattern shape as shown in FIGS. 8A to 8C may be used.

[Third Embodiment] FIG.
4B is a plan view of the via-equipped substrate 8 in FIGS. 2 and 3 for explaining the stacked semiconductor device according to the third embodiment of the present invention.
The mark for detecting a displacement between substrate layers (a mark for detecting a displacement or a mark for alignment) is shown.
(A) is a plan view of the entire substrate 8 with vias,
FIG. 2B shows the shape of the mark for detecting the displacement between the substrates in FIG. As shown in the drawing, a step is provided in the mark for detecting a displacement between the substrate layers.

The mark 17 for detecting the displacement between the substrates is L
For example, the overall width D1 is 0.3 ± 0.05 mm, the width (D2) of the corner (center region) is 0.07 ± 0.02 mm, and the height of the step is The widths D3, D4, D5, and D6 are each 0.1 mm.

As shown in FIGS. 11 (a) to 11 (d), the second layer of the via-mounted substrate corresponds to the substrate interlayer displacement detection mark 17-1 provided on the lowermost via-mounted substrate. 17-2 mark for detecting interlayer displacement between substrates provided in
Is 90 ° counterclockwise, and the substrate interlayer shift detection mark 17-3 provided on the third via-mounted substrate is 180 ° counterclockwise provided on the fourth viad (uppermost) substrate. The mark 17-4 for detecting interlayer displacement between the substrates is rotated 270 ° counterclockwise and arranged. At this time, the centers 17-1C to 17-4C of the corners of the substrate interlayer displacement detection marks 17-1 to 17-4 are arranged at the same position (the same coordinates).

When such a pattern shape is used, when a plurality of marks for detecting interlayer displacement between the substrates are overlapped, the above-mentioned step is used as a scale for measuring the amount of positional displacement, and the amount of interlayer displacement can be grasped more accurately. it can.

It should be noted that the steps may be provided also in the case of the pattern shapes as shown in FIGS. 8A to 8C. Alternatively, the marks for detecting the displacement between the substrate layers may be arranged at a rotation angle of 45 °, and eight layers may be laminated.

[Fourth Embodiment] FIG. 12 is for describing a stacked semiconductor device according to a fourth embodiment of the present invention. The substrate 8 with vias shown in FIGS. FIG. 3 is a plan view showing a state in which the layers are stacked, and focuses on a mark for detecting a displacement between substrate layers. As shown in the drawing, a mark (circular in this case) 18 serving as a reference for a positional deviation limit is provided on one of the via-attached substrates 8 to be laminated. Then, the center position of the L-shaped mark of another layer (X
If there is an intersection in the Y direction), it is within the positional deviation limit. FIG.
In the example shown in FIG. 2, the marks 6-1 and 6 for detecting the displacement between the substrate layers are provided.
The first, second and fourth via-mounted substrates provided with −2 and 6-4 are within the positional deviation limit, and the third layer provided with the substrate interlayer deviation detecting mark 6-3. It is determined that the substrate with vias has exceeded the positional deviation limit.

Therefore, if such a pattern shape is used, the amount of interlayer misalignment can be easily grasped using the mark serving as the reference for the positional misalignment limit.

In the case of the pattern shapes as shown in FIGS. 8A to 8C, a mark serving as a reference for the positional deviation limit may of course be provided. In the case where a plurality of interlayer displacement detection marks are provided separately as in the embodiment, a mark serving as a reference for a displacement limit may be provided in each of the marks.

The present invention has been described with reference to the first to fourth embodiments. However, the present invention is not limited to the above embodiments, and at the stage of implementation, does not depart from the gist of the present invention. Various modifications are possible. Also,
The above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.

[0049]

As described above, according to the present invention, it is possible to obtain a stacked semiconductor device in which each layer can be easily recognized even if the number of stacked layers increases.

Further, even when three or more layers are stacked, the amount of positional deviation can be easily grasped, and a stacked semiconductor device capable of nondestructive inspection of the amount of positional deviation in the manufacturing process can be obtained.

[Brief description of the drawings]

FIGS. 1A and 1B show functional layers in a stacked semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG. 1B is a line AA ′ in FIG. Sectional view along.

FIG. 2 is a diagram showing a stacked package in which the functional layers shown in FIGS. 1A and 1B are stacked.

FIG. 3 is a diagram illustrating a stacked semiconductor device formed by stacking the stacked packages illustrated in FIG. 2;

4A and 4B are plan views of the substrate with vias in FIGS. 2 and 3, focusing on marks for detecting a displacement between the substrates, and FIG. 4A is a plan view of the entire substrate with vias, and FIG. The figure is a figure which expands and shows the mark for board | substrate interlayer displacement detection in FIG.

5A and 5B are diagrams for explaining a pattern shape of a mark for detecting a displacement between the substrates when four layers are stacked, and FIG.
FIGS. 4A to 4D show marks for detecting a displacement between the substrate layers provided on the substrate with vias located at the uppermost layer from the lowermost layer.

FIG. 6 shows a pattern shape when a four-layered substrate with vias is laminated and a mark is observed from the surface with X-rays;
(A) shows the case where there is a positional deviation between the substrate layers, and (b) shows the case where there is no positional deviation between the substrate layers.

FIG. 7 is a diagram showing a pattern shape when there are no positional shifts between substrate layers when an eight-layered substrate with vias is laminated and a mark is observed from the surface by X-rays.

8A and 8B are diagrams for explaining a modification of the mark for detecting displacement between the substrates, wherein FIG. 8A shows a case of three layers, FIG. 8B shows a case of five layers, and FIG. The figure which shows the pattern shape of.

FIG. 9 is a view for explaining a stacked semiconductor device according to a second embodiment of the present invention. FIG. 9 is a diagram showing extracted marks for detecting a displacement between the substrates in the substrate with vias in FIGS. 2 and 3. FIGS. 7A to 7E are diagrams showing pattern shapes of marks for detecting a displacement between the fourth to eighth layers between the substrates.

FIG. 10 is a plan view of a substrate with vias in FIGS. 2 and 3 for describing a stacked semiconductor device according to a third embodiment of the present invention, and FIG. FIG. 2B is a plan view of the entire substrate, and FIG. 2B is an enlarged view showing a mark for detecting a displacement between the substrates in FIG.

FIG. 11 is a diagram for explaining a pattern shape of a mark for detecting displacement between the substrates when four layers are laminated;
(A) FIGS. (A) to (d) are marks for detecting a displacement between the substrate layers provided on the substrate with vias located from the lowermost layer to the uppermost layer.

FIG. 12 is a plan view illustrating a state in which the via-equipped substrates 8 in FIGS. 2 and 3 are stacked, for explaining a stacked semiconductor device according to a fourth embodiment of the present invention; FIG. 3 is a diagram showing the interlayer displacement detection mark.

FIG. 13 shows a conventional stacked semiconductor device, and shows a state in which interlayer displacement has occurred during stacking of the stacked semiconductor package.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass epoxy or polyimide tape with a via, 2 ... Cu wiring, 3 ... Core hole, 4 ... Semiconductor chip, 5 ... Anisotropic conductive film, 6, 6-1-6-4, 17, 17-1-17 -4: misregistration detection mark (or alignment mark), 7: via, 8: substrate with via, 9: adhesive layer, 10: solder ball, 11: surface layer, 12: via with embedded plug, 13 ... Functional layer, 14 ... embedded SUS plate, 15 ... Positioning pin, 16 ... Laminated package.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoko Omizo 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture In the Toshiba Microelectronics Center Co., Ltd. (72) Inventor Mikio Matsui Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa No. 1, Toshiba Town, Toshiba Microelectronics Center Co., Ltd. (72) Inventor Takao Sato No. 1, Komukai Toshiba Town, Koyuki-ku, Kawasaki City, Kanagawa Prefecture, Japan Toshiba Micro Electronics Center Co., Ltd.

Claims (22)

[Claims] 1. A semiconductor device comprising three or more stacked substrates each having a semiconductor chip mounted thereon and each having a misregistration detection mark or an alignment mark arranged in the same pattern and at a different rotation angle from each other. Stacked semiconductor device. 2. A first substrate having a semiconductor chip mounted thereon, a first substrate having a misalignment detection mark or alignment mark each having the same pattern shape and arranged at different rotation angles, and a semiconductor chip mounted thereon. A stacked semiconductor device comprising three or more layers of a second substrate having a mark serving as a reference for a positional deviation limit of a positional deviation detecting mark or alignment mark. 3. The method according to claim 1, wherein when a misalignment detection mark or an alignment mark of the substrate of each layer is superimposed,
3. The stacked semiconductor device according to claim 1, wherein only a part of the regions overlaps, and layers are recognized in a region other than the overlapping part. 4. 4. The apparatus according to claim 1, wherein the position deviation detection mark or the alignment mark has a step portion serving as a scale for measuring a position deviation and a deviation amount from an upper surface. 13. The stacked semiconductor device according to item 9. 5. The semiconductor device according to claim 1, further comprising a substrate having a mark serving as a reference for a positional deviation limit of the positional deviation detecting mark or the alignment mark. 3. The stacked semiconductor device according to item 1. 6. The position deviation detection mark or alignment mark is an L-shaped pattern.
90 with the corners of the character pattern overlapped
The stacked semiconductor device according to claim 1, wherein the stacked semiconductor devices are sequentially stacked at an angle of rotation of 45 ° or 45 °. 7. A first semiconductor device having semiconductor chips mounted thereon, each of which has the same pattern shape and is arranged at a different rotation angle from each other.
A plurality of first substrates each having a first misalignment detection mark or a first alignment mark, and a semiconductor chip, and having the same pattern shape as the first misalignment detection mark or the first alignment mark. And a second misregistration detection mark or a second alignment mark arranged at different rotation angles,
A second substrate having a third misalignment detection mark or a third alignment mark spaced apart from the second misalignment detection mark or the second alignment mark; and a semiconductor chip. Fourth position shift detection mark or fourth alignment mark mounted on each other and arranged in the same pattern shape as the third position shift detection mark or the third alignment mark and at different rotation angles from each other. And a plurality of third substrates having the following. 8. A first semiconductor device having semiconductor chips mounted thereon, each of which has the same pattern and is arranged at a different rotation angle from each other.
A plurality of first substrates each having a first misalignment detection mark or a first alignment mark, and a semiconductor chip, and having the same pattern shape as the first misalignment detection mark or the first alignment mark. A second misalignment detection mark or a second alignment mark arranged at different rotation angles;
A second substrate having a third misalignment detection mark or a third alignment mark spaced apart from the second misalignment detection mark or the second alignment mark; and a semiconductor chip. Fourth position shift detection mark or fourth alignment mark mounted on each other and arranged in the same pattern shape as the third position shift detection mark or the third alignment mark and at different rotation angles from each other. A plurality of third substrates having: a first mark serving as a reference for a positional deviation limit of the first and second positional deviation detecting marks or the first and second alignment marks; And the fourth and fourth alignment marks or the third and fourth alignment marks with respect to the second mark which is a reference for the positional deviation limit. Stacked semiconductor device characterized by comprising a fourth substrate having one. 9. When the first misalignment detection mark or the first and second alignment marks on the first and second substrates are overlapped, only a part of the regions overlaps, and the other than the overlapping portion. The first and second substrate layers are recognized in the region (a), and the third and fourth misregistration detection marks or the third and fourth alignment marks on the second and third substrates are aligned. 9. The stacked mold according to claim 7, wherein when overlapping, only a part of the regions overlaps, and recognition of the layers of the second and third substrates is performed in regions other than the overlapping portion. 10. Semiconductor device. 10. The first to fourth misalignment detection marks or the first to fourth alignment marks have a step portion serving as a scale for measuring the misalignment and the amount of misalignment from the upper surface. 7. The method according to claim 7, wherein
10. The stacked semiconductor device according to any one of Items 9 to 9. 11. A first mark serving as a reference for a positional deviation limit of the first and second positional deviation detecting marks or the first and second alignment marks, and the third mark.
And a fourth substrate having at least one of a fourth misalignment detection mark and a second mark serving as a reference of a misalignment limit of the third and fourth alignment marks. Claims 7, 9, and 1
0. The stacked semiconductor device according to any one of the above items. 12. The first to fourth misalignment detection marks or the first to fourth alignment marks are each L-shaped patterns, and the corners of the L-shaped patterns are overlapped. 90 ° or 45
The stacked semiconductor device according to any one of claims 7 to 11, wherein the stacked semiconductor devices are sequentially stacked at a rotation angle of °. 13. When a semiconductor chip is mounted and the number of layers to be stacked is n, a misalignment detection mark or a mark having an n-gonal central region and at least one protruding region radially protruding from the central region. Alignment marks are sequentially arranged at a rotation angle of 360 ° / n.
A stacked semiconductor device comprising a plurality of substrates stacked. 14. When a semiconductor chip is mounted and the number of layers to be stacked is n, a misalignment detection mark or a mark having an n-gonal central region and at least one protruding region radially protruding from the central region. Alignment marks are sequentially arranged at a rotation angle of 360 ° / n.
A plurality of first substrates, and a second substrate on which a semiconductor chip is mounted, and a second substrate having a mark serving as a reference for a position deviation limit of the position deviation detection mark or the alignment mark. Stacked semiconductor device. 15. The method according to claim 15, wherein when the misalignment detection mark or the alignment mark of the n-layer substrate is overlapped, the central regions overlap, and the layer is recognized in the protruding region. 15. The stacked semiconductor device according to 13 or 14. 16. The position deviation detecting mark or alignment mark has a step in the projecting region serving as a scale for measuring a position deviation and a deviation amount from an upper surface. 16. The stacked semiconductor device according to item 15. 17. The semiconductor device according to claim 13, further comprising a substrate having a mark serving as a reference for a positional deviation limit of the positional deviation detecting mark or the alignment mark. 3. The stacked semiconductor device according to item 1. 18. A first misalignment detection mark or a first alignment mark having a semiconductor chip mounted thereon and having an n-gonal central region and at least one protruding region radially protruding from the central region. N-1 first substrates, each of which is sequentially arranged at a rotation angle of 360 ° / n, a semiconductor chip mounted thereon, an n-gonal central region, and at least one radially protruding from the central region. A second misalignment detection mark or a second alignment which has a projecting area and is arranged at a rotation angle of 360 ° / n with respect to the first misalignment detection mark or the first alignment mark. A mark for use, a central area of an m-square,
A second substrate having a third misalignment detection mark or a third alignment mark having at least one protruding region radially protruding from the center region; a m-square having a semiconductor chip mounted thereon; A fourth misalignment detection mark or a fourth misalignment detection mark having a central region and at least one protruding region radially protruding from the central region;
And m-1 third substrates in which the alignment marks are sequentially arranged at a rotation angle of 360 ° / m with respect to the third misalignment detection mark or the third alignment mark, respectively. A stacked semiconductor device, comprising: 19. A first misalignment detection mark or first alignment mark having a semiconductor chip mounted thereon and having an n-gonal central region and at least one projecting region radially projecting from the central region. N-1 first substrates, each of which is sequentially arranged at a rotation angle of 360 ° / n, a semiconductor chip mounted thereon, an n-gonal central region, and at least one radially protruding from the central region. A second misalignment detection mark or a second alignment which has a projecting area and is arranged at a rotation angle of 360 ° / n with respect to the first misalignment detection mark or the first alignment mark. A mark for use, a central area of an m-square,
A second substrate having a third misalignment detection mark or a third alignment mark having at least one protruding region radially protruding from the center region; a m-square having a semiconductor chip mounted thereon; A fourth misalignment detection mark or a fourth misalignment detection mark having a center region and at least one protrusion region radially protruding from the center region;
M-1 third substrates in which the alignment marks are sequentially arranged at a rotation angle of 360 ° / m with respect to the third displacement detection mark or the third alignment mark, respectively; A first mark serving as a reference for a position shift limit of the first and second position shift detection marks or the first and second alignment marks, and a third position shift detection mark or the fourth position shift detection mark; A stacked substrate comprising: a fourth substrate having at least one of a second mark serving as a reference for a positional deviation limit of the third and fourth alignment marks. 20. When the first and second misalignment detection marks or the first and second alignment marks on the first and second substrates are overlapped, the central regions overlap each other, and Recognizing the layers of the first and second substrates in the region, and superimposing the third and fourth misalignment detection marks or the third and fourth alignment marks on the second and third substrates. When aligned, the central areas overlap and the second and third
20. The stacked semiconductor device according to claim 18, wherein recognition of the layer of the substrate is performed. 21. The first to fourth misalignment detection marks or the first to fourth alignment marks have a stepped portion serving as a scale for measuring the misalignment and the amount of misalignment from the upper surface. Claim 1 characterized by the following:
21. The stacked semiconductor device according to any one of Items 8 to 20. 22. A first mark serving as a reference for a positional deviation limit of the first and second positional deviation detecting marks or the first and second alignment marks, and the third mark.
And a fourth substrate having at least one of a fourth misalignment detection mark or a second mark serving as a reference of a misalignment limit of the third and fourth alignment marks. Claims 18, 20,
21. The stacked semiconductor device according to any one of the items 21.