JP2002368557A - Operational amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operational amplifier circuit having a wide input/output dynamic range. SOLUTION: A differential input stage 1 is constituted of a constant current source M2 and a differential input pair M3 and M4. An amplifying stage 2 consists of a cascode current mirror part 3 constituted of a p-channel MOS transistor, a cascode current mirror part 4 constituted of an n-channel MOS transistor, reference voltage sources M6, M8, M9 and M18, reference current sources M5, M7 and M19 and M1 and M20 which control the reference current sources. The drains of the transistor M3 and M4 are respectively connected to the drains of M14 and M15 of the amplifying stage, the drain node voltage of the input stage is made to be the minimum and an input dynamic range is extended to the maximum. The voltage between the drain and the source of each MOS transistor constituting the respective current mirror parts (3 and 4) is adopted as Vdsat being the minimum voltage value for saturation in the transistors and, then, the minimum value of the output dynamic range is made to down to 2 Vdsat.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an operational amplifier circuit, and more particularly, to an operational amplifier circuit for expanding an input / output dynamic range.

[0002]

2. Description of the Related Art As a circuit configuration of an operational amplifier (opamp) using a MOS transistor,
For example, reference 1 (Analog Integrated Circuit Design, Analog Integrated Circuit Design, published in 1997, Chapters 3 and 6)
References such as T DESIGN, Chapter 3, 6)) are referred to. In the above document 1, a differential output of a differential pair in an input stage is respectively supplied to a first current mirror circuit (input current:
Output current = 1: K), a third current mirror circuit which is turned back by the second current mirror circuit (input current: output current = 1: 1) and receives the outputs of the second and first current mirror circuits as inputs, respectively. (Input current: output current = 1: K), and a current mirror operational amplifier in which the output terminals of the first and third current mirror circuits are connected to an output terminal, or a wide swing cascode current mirror operational amplifier (wi)
A de swing cascode current mirror opamp configuration is disclosed.

[0003] Reference 2 (IEEE, CMOS CIR)
CUIT DESIGN, LAYOUT, SIMULA
TION PARTIII CMOS Analog
Circuit, p. 656), two transistors whose gates are connected in common are vertically stacked in four stages between a high-side power supply and a low-side power supply, and the transistor pair of the first and second stages has a wide swing cascode current. Mirror (wide
A configuration is disclosed in which a swing cascode current mirror is configured and an output of an input-stage differential pair is connected to a connection point of a third-stage and fourth-stage transistor pair.

As a basic operational amplifier circuit using a MOS transistor and a current mirror as a load, for example, a configuration as shown in FIG. 5 is known. Referring to FIG. 5, this operational amplifier circuit has a p-channel MOS transistor MP having a source connected to a higher power supply VDD, a gate applied with a bias voltage Vbias1, and a constant current source.
1 and the source are connected in common and connected to the drain of the transistor MP1, and the gates are connected to the signal input terminals VinP and Vi.
Inputting a differential voltage from nM to form an input stage differential pair p
An n-channel M connected between the drains of the differential pair transistors MP2 and MP3 and the lower power supply and forming a current mirror;
OS transistors MN1 and MN2 (an n-channel MOS transistor MN1 having a drain and a gate connected is a reference current input side transistor, and an n-channel MOS transistor
The transistor MN2 is a mirror current output side transistor) and constitutes an input stage differential circuit.
The sources are connected to the higher power supply VDD, the gates are connected in common, and p-channel MOS transistors MP4 and MP5 forming a current mirror (the p-channel MOS transistor MP4 having a drain and a gate connected is a reference current input side transistor. The p-channel MOS transistor MP5 is a mirror current output side transistor) and the drain is a p-channel MOS transistor M5.
N- are connected to the drains of P4 and MP5, respectively, have their gates connected in common, and receive a bias voltage Vbias2.
Channel MOS transistors MN3 and MN4; n-channel MOS transistors MN5 and MN6 whose drains are connected to the sources of the n-channel MOS transistors MN3 and MN4, whose sources are connected to the lower power supply, and whose gates are commonly connected; And an n-channel MO
The gate and the drain of the S transistor MN5 are connected,
The MOS transistors MN5 and MN6 form a current mirror. p-channel MOS transistor MP
2. The drain of MP3 is connected to the connection point between the sources of the n-channel MOS transistors MN3 and MN4 and the drains of the n-channel MOS transistors MN5 and MN6, respectively. The operation of this circuit is roughly as follows.

V + ΔV is applied to the terminal VinP, and V−Δ is applied to the terminal VinM.
When a signal voltage of dV (differential input voltage = 2ΔV) is input, a differential output current gm2ΔV is output from the differential pair in accordance with the voltage fluctuation, with the mutual conductance as gm. In other words, the gate-source potential of p-channel MOS transistor MP2 decreases, the drain current decreases, and p-channel MOS transistor MP2
The gate-source potential of P3 increases, and the drain current increases. Variations of the differential output current (the drain currents of MP2 and MP3) are defined as -ΔI and + ΔI, respectively. The output difference current of the differential pair flows to the drain node of the n-channel MOS transistor MN5 and the drain node of the n-channel MOS transistor MN6 forming the current mirror, respectively.

The generation of a difference current between -ΔI and + ΔI at the output of the differential pair causes an n-channel MOS transistor MN5
And the amount of current flowing to the drain of MN6 changes. In the n-channel MOS transistor MN5, the inflow of current into the drain node is reduced by -ΔI,
In the OS transistor MN6, the flow of current into the drain node increases by + ΔI, so that the drain voltage of the n-channel MOS transistor MN6 fluctuates.
As a result, a voltage amplitude corresponding to the difference voltage between the input signals VinP and VinM is output from the output terminal Vout connected to the drain of the n-channel MOS transistor MN4.

The circuit shown in FIG. 6 is a modified version of the current mirror circuit shown in FIG. 5, and uses a cascode current mirror circuit. P-channel MOS in which the source is connected to the higher power supply VDD and the gate is connected in common
The transistors MP6 and MP7 and the sources are respectively connected to the drains of the p-channel MOS transistors MP6 and MP7, the gates are commonly connected, and the bias voltage Vbias
2 is applied to the p-channel MOS transistor MP
4 and MP5, and the commonly connected gates of the p-channel MOS transistors MP6 and MP7 are connected to the drain of the p-channel MOS transistor MP4 to form a cascode current mirror circuit. As an operational amplifier having the cascode current mirror shown in FIG. 6, a configuration in which a differential pair in an input stage is configured by n-channel MOS transistors and output by a source follower is described in the literature (IEEE).
E, CMOS CIRCUIT DESIGN, LAY
OUT, SIMULATION PARTIII CM
FIG. 2 on page 656 of OS Analog Circuit
5.43 etc., folded cascode operational amplifier (fold
edcascode opamp).

However, in the cascode current mirror circuit shown in FIGS.
The minimum saturation voltage Vdsat of the MOS transistor is set by the transistor MN6, and the n-channel MOS transistor MN4
Therefore, a potential difference of Vdsat + Vth is generated, so that the output dynamic range is a voltage value = 2Vdsat + Vth on the low potential side.
Can only be secured from. This will be described below.

When the gate voltage (gate-source voltage) is constant, the MOS transistor takes a maximum value Idsat at a specific value Vdsat of the drain voltage VD, and this point is defined as a current limiting characteristic, that is, a starting point of a characteristic called saturation. is there. MO
In order for the S transistor to operate in the saturation region, the drain-source voltage VDS must be greater than Vdsat, and Vdsat is the drain-gate voltage VGS, the threshold value is Vth, and Vdsat = It is given by VGS-Vth.

The gate potential VG3 of the transistor MN3 is
VG3 = VGS5 (gate-source potential of MN5) + VGS3
(Gate-source potential of MN3), and VG3 = 2Vdsat + 2Vth. The potential VDS6 between the drain and source of the transistor MN6 is VDS6 = VG3-VGS4 (the potential between the gate and source of MN6) = VG3- (Vdsat + Vth) = Vdsat + Vth

Therefore, the minimum value of the output terminal voltage Vout (the drain voltage of the transistor MN4) is VDS6 + Vd
It is given by sat = 2Vdsat + Vth, so that Vout> 2Vdsat + Vth.

Generally, the threshold voltage Vth of a MOS transistor is larger than Vdsat and is a value that is physically determined. As a result, the operational amplifier having the cascode current mirror in the load cannot have a large output dynamic range.

Further, regarding the input dynamic range, the voltage VDS between the drain and the source of the n-channel MOS transistor MN1 on the terminal VinP side is Vdsat
Therefore, the minimum value of the input dynamic range cannot be set to 0 V or less.

[0014]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an operational amplifier circuit capable of obtaining a wide input dynamic range and an output dynamic range.

[0015]

According to one aspect of the present invention, there is provided a means for solving the above-mentioned problems, in which an input signal from a first and a second input signal terminal is differentially amplified and output. An operational amplifier circuit comprising: a differential pair of MOS transistors to perform an input and amplify an output signal of the differential pair and outputting an output signal from an output terminal; An n-channel MOS transistor pair whose gates are connected in common is cascaded in two stages between the lower power supplies, and an n-channel
The drain of one MOS transistor of the S transistor pair is connected to the output terminal, and at least the second-stage n-channel MOS transistor pair of the two-stage cascade-connected n-channel MOS transistor pair is in a saturation region. And a reference voltage source for applying a reference voltage such as to operate to the commonly connected gates of the pair of n-channel MOS transistors in the second stage.

According to the present invention, there is provided a differential pair comprising a constant current source and a MOS transistor pair driven by the constant current source and differentially amplifying and outputting an input signal from first and second input signal terminals. And an amplifying stage that receives and amplifies the output signal of the differential pair and outputs an output signal from the output terminal. A two-stage cascade connection of a pair of channel MOS transistors, and a commonly connected gate of the first-stage n-channel MOS transistor pair is connected to the drain of one MOS transistor of the second-stage n-channel MOS transistor pair And a first cascode current mirror circuit in which the drains of the other MOS transistors of the second-stage MOS transistor pair are connected to the output terminal. A reference voltage such that at least the second stage of the n- channel MOS transistor pair of the first cascode current mirror circuit operates in a saturation region, the 2
A first reference voltage source is provided to the commonly connected gates of the n-channel MOS transistor pair at the stage.

[0017]

Embodiments of the present invention will be described. The present invention, in one of its preferred embodiments,
A differential pair (M3, M4 in FIGS. 1, 3, and 4) composed of MOS transistors for differentially amplifying and outputting input signals from the first and second input signal terminals (VinP, VinM), and And an amplification stage that receives and amplifies an output signal of a dynamic pair (M3 and M4 in FIGS. 1, 3, and 4) and outputs an output signal from an output terminal. N whose gate is connected in common between the terminal and the lower power supply
-Channel MOS transistor pairs are cascaded in two stages (M14, M15, M16, M1 in FIGS. 1, 3, and 4).
7) The second stage n-channel MOS transistor pair (M
14, M15) has a drain connected to the output terminal (Vout), and at least a second stage n-channel MOS transistor pair of the two-stage cascade-connected n-channel MOS transistor pair. A reference voltage source (M9, M8 in FIG. 1) for applying a reference voltage such that the channel MOS transistor pair (M14, M15) operates in the saturation region to the commonly connected gates of the second stage n-channel MOS transistor pair. , M3 of FIGS. 3 and 4)

More specifically, first and second input terminals (V
inP, VinM) as a differential input and a constant current source (M
A differential pair consisting of a pair of first conductivity type MOS transistors (M3, M4) driven by 2), and arranged vertically between a first power supply (VDD) and a second power supply (VSS); ,
A first cascode current mirror unit (3) formed by cascode-connecting a first conductivity type MOS transistor pair (M10 and M11, M12 and M13) each having a gate connected thereto, and a second conductivity type MOS transistor, respectively; A second cascode current mirror unit (4) in which transistor pairs (M14 and M15, M16 and M17) are cascode-connected.
And The MOS transistor pair (M10, M11, M1) of the first cascode current mirror unit (3)
2 and M13) are referred to as first and second current mirror circuits, and the MOS of the second cascode current mirror unit (4)
The transistor pairs (M14 and M15, M16 and M17) are called third and fourth current mirror circuits.

The differential pair of MOS transistors (M3, M
4) The pair of output nodes are connected to the connection points of the current mirror circuits (M14 and M15) and the current mirror circuits (M16 and M17) of the second cascode current mirror unit (4), respectively, and the first cascode current mirror The output node of the current mirror circuit (M12 and M13) of the section (3) and the third node of the second cascode current mirror section.
Of the current mirror circuit (M14 and M15) are connected to the output terminal (Vout).
And the current mirror circuits (M12 and M13) of the second cascode current mirror section (3, 4), (M16 and M1
7) are provided with reference voltage sources (M18 and M6 in FIG. 4) for supplying reference voltages, respectively.

The reference voltage source supplies a reference voltage for operating the MOS transistors constituting the first and second current mirror circuits of the second cascode current mirror section (4) in a saturation region.

First cascode current mirror unit (3)
A first reference voltage source (FIGS. 1, 3 and 4) comprising a MOS transistor of the first conductivity type for applying a reference voltage to the common gate of the second current mirror circuit (M12 and M13)
M18) and a second reference voltage source (a MOS transistor of the second conductivity type) that applies a reference voltage to a common gate of the fourth current mirror circuit (M16 and M17) of the second cascode current mirror unit. A first reference current source (M8 and M9 in FIG. 1, M6 in FIGS. 3 and 4) and a second conductivity type MOS transistor for supplying a reference current to the first reference voltage source (FIG. 1). M19 in FIGS. 3 and 4)
Supplying a reference current to the second reference voltage source;
A second reference current source (M7 in FIG. 1, M5 in FIGS. 3 and 4) composed of a conductive type MOS transistor.

In this embodiment, the first cascode current mirror section (3) comprises a first conductivity type MOS transistor for applying a reference voltage to a common gate of the second current mirror circuit (M12 and M13). , The first reference voltage source (M18 in FIG. 1), and the third current mirror circuit (M14 and M14) of the second cascode current mirror unit.
15) A second reference voltage source (FIG. 1) comprising a second conductivity type MOS transistor for applying a reference voltage to the common gate.
M6) and a second and a second MOS transistors of the second conductivity type that apply a reference voltage to a common gate of the third and fourth current mirror circuits (M16 and M17) of the second cascode current mirror unit. 3 reference voltage sources (M in FIG. 1)
8, M9) and a second conductivity type MOS transistor for supplying a reference current to the first reference voltage source.
Reference current source (M19), and second and third reference current sources (M5, M7) comprising first conductivity type MOS transistors for supplying a reference current to the second and third reference voltage sources.
And

In this embodiment, a second conductivity type MOS transistor (M19 in FIGS. 3 and 4) constituting a first reference current source and a first conductivity type MOS transistor constituting the second reference current source are provided. Type MOS transistor (M in FIGS. 3 and 4)
5) and first and second control circuits (M20, M1) for supplying a gate voltage to the first power supply and the second power supply, respectively, are provided in series between the first power supply and the second power supply.

In this embodiment, as a reference voltage source, a reference voltage is applied to a common gate of a second current mirror circuit of the first cascode current mirror section.
A second conductivity type MOS transistor of a first conductivity type, which applies a reference voltage to a first reference voltage source and a common gate of the third and fourth current mirror circuits of the second cascode current mirror unit. Consisting of MOS transistors,
A first reference current source comprising second and third reference voltage sources, a second conductivity type MOS transistor for supplying a reference current to the first reference voltage source, and the second and third reference voltage sources; And a second and third reference current source, which comprises a first conductivity type MOS transistor and supplies a reference current to the reference voltage source.

In this embodiment, a second conductivity type MOS transistor (M19) constituting the first reference current source and a first conductivity type MOS transistor constituting the second and third reference current sources are provided. First and second control circuits (M20, M1) for supplying gate voltages to the MOS transistors (M5, M7) are provided in series between the first power supply and the second power supply.

The first control circuit has a first conductivity type MOS transistor (M1) having a source connected to the first power supply and a gate supplied with a bias voltage (Vref) supplied to the constant current source (M2). ), The second control circuit is connected to the drain and gate of the first control circuit, is connected to the drain of the MOS transistor of the first conductivity type of the first control circuit, and has the source connected to the second power supply. MOS transistor (M20).

In this embodiment, the second reference voltage source is diode-connected, and a MOS transistor pair (M14, M15) whose gate constitutes a third current mirror circuit of the second cascode current mirror unit. A second conductivity type MOS transistor (M6) having a common gate connected to the gate, a source connected to the second power supply, and a drain connected to the second reference current source,
A third reference voltage source has a common gate connected to the gate of the MOS transistor pair (M16, M17) constituting the fourth current mirror circuit of the second cascode current mirror unit, and the source is connected to the second power supply. A source is connected to the connected second conductivity type first MOS transistor (M9) and the drain of the second conductivity type first MOS transistor (M9), and the drain is the second cascode current mirror unit. Of the MOS transistor pair (M14, M15) forming the third current mirror circuit of the second type, and the gate is connected to the gate of the first MOS transistor (M9) of the second conductivity type. The second MOS transistor of the second conductivity type has a drain connected to a third reference current source (M7). It is connected.

The fourth cascode current mirror section of the second
The common gate of the second conductivity type MOS transistors (M16 and M17) of the current mirror circuit of (1) is provided with a reference voltage such that the second conductivity type MOS transistor of the fourth current mirror circuit operates in a saturation region. Is given. The common gate of the second conductivity type MOS transistors (M14 and M15) of the third current mirror circuit of the second cascode current mirror unit is connected to the fourth gate.
Of the second conductivity type constituting the current mirror circuit of FIG.
This is provided from a reference voltage such that the S transistor operates in a saturation region.

The outline of the present invention and its operating principle will be described. The present invention provides a circuit having a load composed of a cascode-connected current mirror circuit in an amplification stage, and obtaining a wide input dynamic range and an output dynamic range by optimizing a bias power supply. That is, as shown in FIG. 1, a circuit for realizing the maximum input / output dynamic range includes a differential input stage (1) and an amplification stage (2). The differential input stage (1) comprises a power supply (VDD), a constant current source (M2), and a differential pair (M3, M4) composed of a pair of transistors of the first conductivity type of the input stage.

The amplification stage (2) includes a first cascode current mirror unit (3) (transistor M10) formed by cascade-connecting (cascading) a current mirror circuit composed of MOS transistors of the first conductivity type in two stages. , M11 and two stages of transistors M12 and M13) and a current mirror circuit composed of MOS transistors of the second conductivity type in a cascade connection (cascade) in two stages. 4) (Two stages of transistors M14 and M15 and transistors M16 and M17) and the first cascode current mirror unit (3) are provided with a reference voltage (reference voltage).
ge) reference voltage source
e) and a reference current (reference curl) to a reference voltage source (transistor M18).
rent) reference current source
e) and a transistor group (M6, M8, M9) serving as a reference voltage source for applying a reference voltage (bias) to the second cascode current mirror unit (4).
And transistors (M5, M7) serving as reference current sources for supplying a reference current to the reference voltage sources (M6, M8, M9), and transistors (M1, M20) for controlling the reference current sources.

The differential pair transistor (M) of the input stage (1)
3, M4) is connected to the two-stage transistor (M1) of the second cascode current mirror unit (4) of the amplification stage.
4, M15) and transistors (M16, M17) (middle stages).

As described above, the drain nodes of the differential pair transistors (M3, M4) of the input stage (1) are connected to the second stage of the amplification stage.
Of the input stage differential pair transistors (M3, M3)
4) The drain node voltage can be minimized. That is, the input dynamic range can be extended to the maximum.

As for the output, the transistors (M5, M6, M8, M9, M1) constituting each reference voltage source
By making 8) the optimal channel shape (dimension),
The drain-source voltage VDS of each MOS transistor constituting the first current mirror section (3) and the second current mirror section (4) can be set to the minimum voltage Vdsat at which the transistors are saturated. As a result, the minimum value of the output dynamic range becomes operable from 2 × Vdsat.

[0034]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, the source is the higher power supply V
A source is commonly connected to a p-channel MOS transistor M2 which is connected to DD and has a gate connected to a reference voltage Vref to form a constant current source, and has sources connected to signal input terminals VinP and VinM.
P-channel MOS transistors M3 and M4 respectively connected to the input stage 1 constitute a differential pair.

The p-channel MOS transistors M1, M5 and M7 whose sources are connected to the higher power supply VDD and whose gates are connected to the reference voltage Vref, and whose drain and gate are p
An n-channel MOS transistor M connected to the drains of the channel MOS transistors M1 and M5, respectively.
20, M6 and M8, the sources of the n-channel MOS transistors M20 and M6 are connected to the lower power supply VSS, and the source of the n-channel MOS transistor M8 is connected to the drain of the n-channel MOS transistor M9. And an n-channel MOS transistor M
9 is connected to the lower power supply VSS.

Further, the sources are connected to the drains of the p-channel MOS transistors M10 and M11 whose sources are connected to the higher power supply VDD and the gates are connected in common, and the gates are connected in common to the drains of the p-channel MOS transistors M10 and M11. P-channel MOS transistor M1
2 and M13, and the gate of the p-channel MOS transistor M10 is
12 is connected to the drain.

A p-channel MOS transistor M12,
An n-channel MOS transistor M14 having a drain connected to the drain of M13 and a gate commonly connected,
M15 and n-channel MOS transistors M14, M
N-channel MOS transistors M16 and M17 having a drain connected to the source of No. 15 and a gate connected in common
And n-channel MOS transistor M
The gates of M16 and M17 are connected to the gate of the n-channel MOS transistor M9 and to the drain of the n-channel MOS transistor M8.
The gates of the n-channel MOS transistors M14 and M15 are connected to the gates of the n-channel MOS transistors M6 and M8.

A p-channel MOS transistor M18 having a source connected to the higher power supply VDD, a gate and a drain connected to a commonly connected gate of p-channel MOS transistors M12 and M13, An n-channel MOS transistor M19 having a drain connected to the drain of the MOS transistor M18 and a source connected to the lower power supply VSS.
The gate of the channel MOS transistor M19 is n-
It is connected to the gate of the channel MOS transistor M20.

The drain of the MOS transistor M13 and M
The output terminal Vout is connected to the connection point of the drain of the OS transistor M15.

The drains of the transistors M3 and M4 are connected to the connection points of the transistors M14 and M15 and the transistors M16 and M17 of the cascode current mirror unit 4, respectively.

The drain current flowing through the differential pair transistors M3 and M4 in the input stage is defined as ID2 / 2.

Next, when the signal voltage VinP = V + is applied to the gate of the transistor M3 and the signal voltage VinM = V- is applied to the gate of the transistor M4,
The changes in the current flowing through M4 are -ΔI and + ΔI, respectively.

Further, currents ID5, ID7, and ID19 from the reference current sources M5, M7, and M19, respectively, and currents ID1 and M1 from the current mirrors M10 and M11 that constitute the current mirror unit 3 respectively.
0 and ID11 flow.

Here, the channel lengths L of the transistors are assumed to be equal. Also, the saturation voltage Vdsat of the transistor n
n is given by Vdsatn = VGS-Vth.

The relation between the saturation voltage Vdsatn of the MOS transistor and the drain current ID is as follows: ID = (1/2) μS · C0X (W / L) (VGS−Vth) ² (μS is the carrier surface mobility, and C0X is the unit. The gate capacitance per area, W and L are the gate width and gate length of the transistor, VGS is the gate-source voltage, and Vth is the threshold voltage.)

Vdsatn = VGSn−Vth = {{A · IDn / (Wn / Ln)} (1)

Here, √ {} is a square root
Where VGSn is a gate-source voltage of the transistor n, Vth is a threshold voltage, A is a physically determined constant (A = 2 / (μS · C0X)) by the transistor, and Wn, Ln Represents the gate width and gate length of the transistor n.

Further, the drain current I of the n-channel MOS transistors M2, M7, M10, M11, M18
D2, ID7, ID10, ID11, and ID18 are defined by equation (2).

I≡ID2 / a = ID7 / b = ID10 / c = ID18 / d = ID10 = ID11 (2) where a, b and c are constants (real numbers).

A signal at the gates of the transistors M3 and M4 is input, and the drain current of the transistor M3 is set to ID2.
/ 2-ΔI, the drain current of transistor M4 is ID2 /
The case where 2 + ΔI is reached will be described.

At this time, the transistors M10, M12,
The current ID10 (the drain current of the transistor M10) flows through the drain node of M14, and the transistor M1
The current ID11 is connected to the drain nodes of M1, M13 and M15.
(The drain current of the transistor M11).

Further, the sum of the current flowing from the drain of the transistor M14 to the source thereof and the current flowing from the drain of the transistor M3 at the drain node of the transistor M16 is given by ID2 / 2 + ID10-ΔI.

Similarly, the drain current flowing through the transistor M17 is the sum of the current flowing from the drain of the transistor M15 to the source and the current flowing from the drain of the transistor M4, and is given by ID2 / 2 + ID11 + ΔI.

At this time, since the gate-source voltages VGS of the n-channel MOS transistors M9, M16 and M17 are equal, and the threshold voltages Vth of these n-channel MOS transistors are equal, Vdsat16 = Vdsat9. From this result, and equations (1) and (2), equation (3) is obtained for the gate widths W9, W16 and W17 of the n-channel MOS transistors M9, M16 and M17.

W9 = ｛c / (1 + a)｝ W16 = ｛c / (1 + a)｝ W17 (3)

Further, the MOS transistors M16 and M1
7, the maximum saturation voltage Vdsat16 and Vdsat17 become maximum when the respective drain currents become maximum from the equation (1). In the case of the MOS transistor M16, this is ΔI = −ID2 / 2 = −aI / 2.

At this time, the voltage required for the MOS transistor to operate in the saturation region can be expressed by equation (4).

VGS6 ≧ VGS14−VDS16 (4) From this relation and the relation of the equation (1), the relational expression of the channel width W of the MOS transistors M6, M16 and M17 becomes the following equation (5).

√ (b / W6) ≧ √ (1 / W14) + √ {(1 + a) / W16｝ (5)

From equation (3), the MOS transistor M
The gate widths W16 and W17 of 16 and M17 are W16 = W17.

Next, in order to set the drain-source voltage VDS8 of the MOS transistor M8 to the minimum saturation voltage value Vdsat8, VDS8 can be expressed by Expression (6), so that the condition of Expression (7) is obtained.

VGS6 ≧ VGS8 + VDS9 (6)

√ (b / W6) ≧ √ (c / W8) + √ (c / W9) (7)

In order to satisfy these conditions, MOS transistors M6, M8, M9, M14, M15, M1
6, M17 and the channel width W of the constant current sources M5, M7, M10 are set, and the voltage used in the cascode current mirror unit 4 is equal to the drain voltages of the transistors M15 and M17.
There is only 2Vdsat which is the sum of the source-to-source voltages.

Further, the drain voltages of the MOS transistors M3 and M4 are Vdsat16 and Vdsat17 since they are the drain-source voltages of the transistors M16 and M17.

From this, the minimum input voltage to the operable MOS transistor M3 is VinP = Vdsat16-Vth.

Similarly, the minimum input voltage to the MOS transistor M4 is VinN = Vdsat17-Vth.

From the above, the minimum value of the output dynamic range can be reduced to 2 Vdsat.

Further, the minimum input dynamic range can be reduced to Vdsat-Vth, that is, lower than the power supply voltage.

Further, the saturation voltage Vdsatn is a value depending on the drain current IDn as shown in the equation (1).
That is, by reducing the drain current IDn, the minimum values of the input dynamic range and the output dynamic range can be reduced.

As a result, the device operates in the entire range from VSS to VDD with respect to the input dynamic range and the minimum value -Vth with respect to the output dynamic range.

Next, the cascode current mirror unit 3
Generally, a wide swing cascode current mirror (wide
Known as a swing cascode current mirror, the voltage dropped by this circuit is 2 Vdsat.

The input stage MOS transistors M3, M
4 may be an n-channel MOS transistor. FIG. 2 is a diagram showing a circuit configuration when the input-stage differential pair is formed by n-channel MOS transistors.

Referring to FIG. 2, the source is the lower power supply V
An n-channel MOS transistor M2, which is connected to SS and has a gate connected to the reference voltage Vref and forms a constant current source, is connected in common to the source, and has signal input terminals VinP and VinM.
The n-channel MOS transistors M3 and M4 respectively connected to the input stage 1 form a differential pair.

The n-channel MOS transistors M20, M6 and M9 whose sources are connected to the lower power supply VSS and whose gates are connected to the reference voltage Vref, and whose drains and gates are the drains of the n-channel MOS transistors M20 and M6, respectively. The source of the p-channel MOS transistors M1, M5, M8 is connected to the higher power supply VDD, and the source of the p-channel MOS transistor M8 is connected to the p-channel MOS transistors M1, M5, M8. The drain of the p-channel MOS transistor M7 is connected to the drain of the channel MOS transistor M7.
7 is connected to the higher power supply VDD.

Further, the sources are connected to the drains of the n-channel MOS transistors M16 and M17 whose sources are connected to the lower power supply VSS and the gates are connected in common, and the gates are connected in common to the drains of the n-channel MOS transistors M16 and M17. N-channel MOS transistor M1
4 and M15, and the gate of the n-channel MOS transistor M16 is an n-channel MOS transistor M16.
14 is connected to the drain.

The n-channel MOS transistor M14,
A p-channel MOS transistor M12 whose drain is connected to the drain of M15 and whose gate is commonly connected,
M13 and p-channel MOS transistors M12, M
13, p-channel MOS transistors M10 and M11 whose drains are connected to their sources and whose gates are commonly connected
And p-channel MOS transistor M
The gates of the transistors 10 and M11 are connected to the gate of the p-channel MOS transistor M7 and to the drain of the p-channel MOS transistor M8.
The gates of the p-channel MOS transistors M12 and M13 are connected to the gates of the n-channel MOS transistors M5 and M8.

An n-channel MOS transistor M19 having a source connected to the lower power supply VSS, a gate and a drain connected to the commonly connected gates of the n-channel MOS transistors M14 and M15, and an n-channel MOS transistor The drain of the transistor M19 has a drain connected to the source and a source connected to the higher power supply VDD.
A channel MOS transistor M18, and a gate of the p-channel MOS transistor M18 is connected to a gate of the p-channel MOS transistor M1.

The drain of the MOS transistor M13 and M
The output terminal Vout is connected to the connection point of the drain of the OS transistor M15.

The drains of the MOS transistors M3 and M4 are respectively connected to the MOS transistors M10 and M11 and the MOS transistors M12 and M12 of the cascode current mirror section.
It is connected to the connection point of M13.

Another embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the third exemplary embodiment of the present invention. Referring to FIG. 3, the basic configuration of this embodiment is the same as that of the embodiment described with reference to FIG. 1, but the reference voltage source is improved. In FIG. 3, the transistors M7, M8, and M9 in FIG. 1 are omitted to reduce power consumption. By using this circuit, the drain current
Power consumption by ID7 can be eliminated. Referring to FIG. 3, the transistor M16 of the cascode current mirror unit
And M17 have their gates connected together and connected to the drain of transistor M14, and the commonly connected gates of transistors M14 and M15 are connected to the gate of diode-connected transistor M6 (reference voltage source).

Next, a fourth embodiment of the present invention will be described. FIG. 4 is a diagram showing the configuration of the fourth embodiment of the present invention. Referring to FIG. 4, this embodiment further reduces power consumption. This is a circuit in which the circuits M1 and M20 for adjusting the constant current source M19 are realized by a transistor M6. That is, referring to FIG. 4, in this embodiment, the MOS transistors M1 and M20 are deleted from the circuit configuration shown in FIG. 3, and the gates of the MOS transistors M16 and M17 of the cascode current mirror unit are connected in common and the MOS transistors are connected. The drain of the transistor M14, the commonly connected gates of the transistors M14 and M15 are connected to the diode-connected MOS transistor M
6 (reference voltage source), and the gate and drain of the MOS transistor M6 are connected to the MOS transistor M1.
9 gates.

In the embodiments shown in FIGS. 3 and 4, the input differential pair may be an n-channel MOS transistor. In this case, as shown in FIG. 2, the connection form of the cascode section, the reference voltage source, the reference current source, etc.
The transistor is inverted as shown in FIG.

The present invention is not limited to the above-described embodiments, but naturally includes various modifications and alterations that can be made by those skilled in the art within the scope of the invention set forth in the appended claims. It is.

[0086]

As described above, according to the present invention,
A wide input dynamic range and an output dynamic range can be realized. The reason for this is that, in the present invention, the first conductive type channel MOS transistor including the differential input stage including the constant current source and the differential input pair and the first conductive type channel MOS transistor.
Cascode current mirror section, a second cascode current mirror section composed of a second conductivity type MOS transistor, a reference voltage source, a reference current source, and a circuit for controlling the reference current source. An output node is connected to a connection point between the second cascode current mirror unit and the current mirror, and each MO constituting the current mirror unit is connected.
This is because the drain-source voltage of the S transistor is set to Vdsat, which is the minimum voltage value at which the transistor is saturated, and the minimum value of the output dynamic range can be set to 2 Vdsat.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an operational amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration in which an input transistor is an n-channel MOS transistor in the operational amplifier circuit of FIG. 1;

FIG. 3 is a diagram showing a configuration of an operational amplifier circuit according to another embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an operational amplifier circuit according to another embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a basic operational amplifier circuit.

FIG. 6 is a diagram showing an operational amplifier circuit in which a current mirror of an amplification stage is improved.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input differential pair MOS transistor 2 Amplification stage 3 Amplification stage p-channel cascode current mirror circuit 4 Amplification stage n-channel cascode current mirror circuit VDD High power supply voltage VSS Low power supply voltage VinP Positive input terminal voltage VinN Negative input terminal voltage Vout Output Voltage Vref, Vbias Reference voltage

Claims (21)

[Claims] 1. A differential pair comprising MOS transistors for differentially amplifying and outputting input signals from first and second input signal terminals, and inputting and amplifying an output signal of the differential pair for output. And an amplifying stage for outputting an output signal from a terminal. An n-channel MOS transistor pair having a gate commonly connected between the output terminal of the amplifying stage and a lower power supply.
The drain of one MOS transistor of the pair of n-channel MOS transistors in the second stage is connected to the output terminal, and at least two of the pair of n-channel MOS transistors in the two stages are connected in cascade. A reference voltage at which the n-channel MOS transistor pair at the stage operates in the saturation region is
An operational amplifier circuit comprising a reference voltage source applied to a commonly connected gate of the second-stage n-channel MOS transistor pair. 2. The two-stage cascade-connected n-channel MO.
First stage n-channel MOS of S transistor pair
2. The semiconductor device according to claim 1, further comprising a reference voltage source that supplies a reference voltage for operating the transistor pair in a saturation region to a commonly connected gate of the first-stage n-channel MOS transistor pair. The operational amplifier circuit described. 3. A reference current source for supplying a reference current to a reference voltage source for applying a reference voltage to a commonly connected gate of the pair of n-channel MOS transistors of the second stage,
The operational amplifier circuit according to claim 1, wherein: 4. The n-channel MOS of the first and second stages
3. The operational amplifier circuit according to claim 2, further comprising a plurality of reference current sources that respectively supply a reference current to a plurality of reference voltage sources that respectively provide a reference voltage to the commonly connected gates of the transistor pair. 5. The differential pair comprises a pair of p-channel MOS transistors, and the drains of the pair of p-channel MOS transistors are connected to the first-stage n-channel MOS transistor pair and the second-stage n-channel MOS transistor pair. 2. The operational amplifier circuit according to claim 1, wherein the operational amplifier circuit is connected to a connection point of the MOS transistor pair. 6. A constant current source and a first current source driven by the constant current source.
A differential pair composed of a MOS transistor pair for differentially amplifying and outputting an input signal from a second input signal terminal; and inputting and amplifying an output signal of the differential pair, and outputting an output signal from the output terminal. An amplifying stage for outputting an n-channel MOS transistor having a gate connected in common in two stages between a lower power supply and said output terminal, The pair of commonly connected gates is connected to the drain of one MOS transistor of the second stage n-channel MOS transistor pair, and the other MOS transistor pair of the second stage is connected to the other MOS transistor.
A first cascode current mirror circuit having a drain of the S transistor connected to the output terminal, wherein at least the second-stage n-channel MOS transistor pair of the first cascode current mirror circuit operates in a saturation region An operational amplifier circuit comprising: a first reference voltage source for supplying a reference voltage as described above to a commonly connected gate of the second-stage n-channel MOS transistor pair. 7. The differential pair includes a pair of p-channel MOS transistors, and the drains of the pair of p-channel MOS transistors are connected to the first-stage n-channel MOS transistor pair and the second-stage n-channel MOS transistor pair. 7. The operational amplifier circuit according to claim 6, wherein the operational amplifier circuit is connected to a connection point of the MOS transistor pair. 8. A p-channel MOS transistor pair having a gate connected in common between a higher power supply and said output terminal.
The gates of the first stage p-channel MOS transistor pair connected in common are connected to the drain of one MOS transistor of the second stage p-channel MOS transistor pair. 7. The operational amplifier circuit according to claim 6, further comprising a second cascode current mirror circuit having a drain of another MOS transistor of the MOS transistor pair connected to the output terminal. 9. The differential pair includes an n-channel MOS transistor pair, and the drains of the n-channel MOS transistor pair are the first-stage p-channel MOS transistor pair and the second-stage p-channel 9. The operational amplifier circuit according to claim 8, wherein the operational amplifier circuit is connected to a connection point of the pair of MOS transistors. 10. A high-side power supply and a low-side power supply,
7. The operational amplifier circuit according to claim 6, further comprising: a first reference current circuit connected in series with said first reference voltage source and supplying a reference current to said first reference voltage source. 11. A constant current source, driven by the constant current source,
A first conductivity type MOS transistor having a differential pair consisting of a first conductivity type MOS transistor pair for differentially inputting and differentially amplifying and outputting signals from first and second input terminals, and having a gate commonly connected. A first cascode current mirror unit formed by connecting the pairs in a two-stage cascade, and a second cascode current mirror unit formed by connecting a pair of second conductivity type MOS transistors whose gates are commonly connected in a two-stage cascade. A cascode current mirror unit, and a cascode current mirror unit are vertically stacked between a high-potential power supply and a low-potential power supply. An output node of the differential pair is connected to a connection point of a two-stage second-conductivity-type MOS transistor pair forming the second cascode current mirror unit; A drain-source of a MOS transistor comprising a plurality of reference voltage sources for applying a reference voltage to the first and second cascode current mirror sections, and constituting a cascode current mirror section connected to the output terminal and a low potential power supply side An operational amplifier circuit, wherein the inter-voltage is a minimum voltage at which the MOS transistor operates in a saturation region. 12. A constant current source, driven by said constant current source,
A differential pair comprising a first conductivity type MOS transistor pair for differentially inputting signals from the first and second input terminals, differentially amplifying and outputting the signals, and disposed between the first power supply and the second power supply; A first cascode current mirror section, which is formed by two-stage cascode connection of first and second current mirror circuits each including two MOS transistors of the first conductivity type; A second cascode current mirror unit formed by cascode-connecting third and fourth current mirror circuits each including a MOS transistor. An output node of the differential pair of MOS transistor pairs is connected to the second cascode current. A connection point between the third current mirror circuit and the fourth current mirror circuit of the mirror unit, and a connection point of the first cascode current mirror unit; A connection point between an output node of the second current mirror circuit and an output node of the second cascode current mirror unit to a third current mirror circuit is connected to an output terminal; and the first and second cascode current mirror units And a reference voltage source for supplying a reference voltage to each of the current mirror circuits. 13. The system according to claim 13, wherein said reference voltage source is said first and second
A reference voltage for operating a MOS transistor constituting a cascode current mirror section connected between the output terminal and a lower power supply of the first and second power supplies in a saturation region in the cascode current mirror section give,
The operational amplifier circuit according to claim 12, wherein: 14. A first reference voltage comprising a first conductivity type MOS transistor for applying a reference voltage to a common gate of a pair of MOS transistors constituting a second current mirror circuit of the first cascode current mirror section. And a second reference voltage source comprising a second conductivity type MOS transistor for applying a reference voltage to a common gate of a pair of MOS transistors constituting a fourth current mirror circuit of the second cascode current mirror unit. A first reference current source comprising a MOS transistor of a second conductivity type for supplying a reference current to the first reference voltage source; and a first conductivity supplying a reference current to the second reference voltage source. 13. The operational amplifier circuit according to claim 12, further comprising: a second reference current source comprising a MOS transistor of a type. 15. A first reference voltage comprising a first conductivity type MOS transistor for applying a reference voltage to a common gate of a pair of MOS transistors constituting a second current mirror circuit of the first cascode current mirror section. A second conductivity type MOS transistor for applying a reference voltage to a common gate of a pair of MOS transistors forming third and fourth current mirror circuits of the second cascode current mirror unit. A third reference voltage source, a first reference current source comprising a second conductivity type MOS transistor for supplying a reference current to the first reference voltage source, and the second and third reference voltage sources And a second and a third reference current source comprising a first conductivity type MOS transistor for supplying a reference current to the first and second reference current sources, respectively. 13. The operational amplifier circuit according to claim 13. 16. A gate voltage is applied to each of a second conductivity type MOS transistor forming the first reference current source and a first conductivity type MOS transistor forming the second reference current source. 15. The power supply according to claim 14, wherein first and second control circuits are provided in series between the first power supply and the second power supply.
The operational amplifier circuit described. 17. A second conductivity type MOS transistor forming the first reference current source, and a first conductivity type M transistor forming the second and third reference current sources.
16. The system according to claim 15, further comprising a first and a second control circuit for supplying a gate voltage to each of the OS transistors in series between the first power supply and the second power supply.
The operational amplifier circuit described. 18. The first control circuit comprises a first conductivity type MOS transistor having a source connected to a first power supply and a gate supplied with a bias voltage supplied to a constant current source. A second control type MOS transistor having a drain and a gate connected to the drain of a first conductivity type MOS transistor of the first control circuit, and a source connected to the second power supply; 17. The operational amplifier circuit according to claim 16, further comprising: 19. The second reference voltage source is diode-connected, and the gate is connected to the common gate of a pair of MOS transistors forming a third current mirror circuit of the second cascode current mirror unit. A source is connected to the second power supply, and a drain is formed of a second conductivity type MOS transistor connected to the second reference current source. The third reference voltage source is connected to the second cascode current. MO constituting the fourth current mirror circuit of the mirror section
A common gate of the S transistor pair is connected to the gate, and a source is connected to the second power supply.
The source is connected to the drain of the S transistor and the first MOS transistor of the second conductivity type, and the drain is connected to the common gate of the MOS transistor pair forming the third current mirror circuit of the second cascode current mirror unit. A second MOS transistor of the second conductivity type, the drain of which is connected to the gate of the first MOS transistor of the second conductivity type, and the drain of the second MOS transistor of the second conductivity type is Connected to a third reference current source,
The operational amplifier circuit according to claim 15, wherein: 20. A second conductivity type M constituting a fourth current mirror circuit of the second cascode current mirror section.
The common gate of the OS transistor pair is supplied with a reference voltage such that the second conductivity type MOS transistor constituting the fourth current mirror circuit operates in a saturation region. Item 13. The operational amplifier circuit according to Item 12. 21. A common gate of a MOS transistor pair of the second conductivity type of the third current mirror circuit of the second cascode current mirror unit, the second conductivity type constituting the third current mirror circuit. 13. The operational amplifier circuit according to claim 12, wherein the MOS transistor is supplied from a reference voltage that operates in a saturation region.