JP2002368143A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the chip occupation area of a memory cell. When a semiconductor memory device includes a plurality of memory cells MC and a data line DL capable of inputting and outputting data to and from the memory cells, an electrically rewritable nonvolatile memory element 21 is provided. And a switch transistor provided between the nonvolatile memory element and the data line to constitute the memory cell. At this time, the switch transistor is a bipolar transistor 23, and a base electrode of the transistor is connected to the nonvolatile transistor. By sharing the drain diffusion layer of the non-volatile memory element 21,
A reduction in the chip area occupied by memory cells is achieved by eliminating the need for a word line dedicated to switch transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and is effective when applied to, for example, an electrically erasable EEPROM (electrically erasable and programmable read only memory). Technology.

[0002]

2. Description of the Related Art EEPRO is an example of a semiconductor memory device.
M can rewrite data on the board. The EEPROM has a structure using a floating gate and a structure using a trap at an interface between different kinds of insulators. In any case, since the tunnel effect is used for writing and erasing, writing and erasing currents are extremely small, and multifunctional products such as a mode for simultaneously erasing all bits and writing and erasing in page units have been developed.

EEPR using floating gate
The OM injects and emits electrons between the floating gate and the drain via a tunnel oxide film formed on the drain electrode.

EE using traps at the interface between different insulators
MNOS (metal nitrid) as PROM
e silicon or metal nitride
(semiconductor) memory. In order to increase the readout speed and increase the capacity of this memory, silicon gate n-channel type is now mainstream, and SNOS
(Silicon nitride oxide si
silicon or silicon nitride o
This is sometimes referred to as “xide semiconductor”. Writing is enabled by applying a high voltage to the gate and injecting electrons into the trap by the tunnel effect. In erasing, holes are injected into traps by applying an electric field contrary to the case of writing.

[0005] An example of a document describing an EEPROM is "LSI Handbook (pages 520 to 520)" issued by Ohm Co., Ltd. on November 30, 1984.

[0006]

In an EEPROM using a different insulator interface trap type, charges leak even when a weak gate voltage is applied during a read operation. Therefore, at the time of reading, the gate voltage is set to 0 V, and reading of logical values "1" and "0" is enabled depending on the difference between the depletion state and the enhancement state. And
In this case, a switch transistor is provided between the nonvolatile memory element and the data line in order to prevent a current from flowing to a non-selected bit in a read operation. This switch transistor is formed by a MOS transistor. For example, as shown in FIG. 4, one bit of the memory includes a nonvolatile memory element 21 and a MOS transistor 22 coupled to the nonvolatile memory element 21 to form one memory cell. Here, the MOS transistor 22 is the switch transistor, and the MOS transistor is controlled to be turned off in a non-selected bit.

However, the nonvolatile memory element 21
And a MOS transistor 22 coupled thereto, constitutes one memory cell.
Compared to a flash memory in which a number of memory cells are formed, the area occupied by the memory cells on the chip must be increased, which hinders the reduction in the area occupied by the chips on the memory cells. Found by the present inventor.

An object of the present invention is to provide a technique for reducing a chip area occupied by a memory cell.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, when a semiconductor memory device includes a plurality of memory cells and a data line capable of inputting and outputting data to and from the memory cells, the memory cells are electrically rewritable nonvolatile memory. And a switch transistor disposed between the nonvolatile memory element and the source line, wherein the switch transistor is a bipolar transistor formed on the source electrode side of the nonvolatile memory element. And

According to the above means, by forming the bipolar transistor on the source electrode side of the nonvolatile memory element, the base electrode of the bipolar transistor can be shared with the source diffusion layer of the nonvolatile memory element. This eliminates the need for a switch transistor dedicated word line, which reduces the chip occupation area of the memory cell.

At this time, the layer forming the collector electrode of the bipolar transistor is shared with the P-type well of the nonvolatile memory element, and the layer forming the base electrode of the bipolar transistor is connected to the source of the nonvolatile memory element. By sharing with the diffusion layer, the bipolar transistor can have a vertical structure.
The size per unit can be reduced. At this time, the emitter electrode of the bipolar transistor can be easily obtained by laminating a P-type implantation layer on the layer forming the base electrode of the bipolar transistor. Further, in order to operate the bipolar transistor in accordance with an instruction of an erasing operation, a writing operation, and a reading operation of the memory cell, the bipolar transistor is operated in accordance with an instruction of an erasing operation, a writing operation, and a reading operation of the memory cell. Control means for controlling the operation of the bipolar transistor by switching the level of the voltage supplied to the transistor can be provided.

[0014]

FIG. 29 shows an EEPROM which is an example of a semiconductor memory device according to the present invention. The EEPROM shown in FIG. 1 is not particularly limited, but is an EEPROM using a trap at an interface between different kinds of insulators.
MNOS (metal nitride silico)
n or metal nitride semicon
A semiconductor memory is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The EEPROM 30 is provided with a logic control 32 and an input / output control circuit 33. The logic control 32 temporarily stores a control signal input from a host such as a microcomputer to be connected, and controls the operation logic based on the signal. Various signals such as a command, an external address, and program data input and output from the host are input to the input / output control circuit 33, and the command, the external address, and the data are respectively stored in the command register 34 and the address register based on the control signal. 35, output to the data register / sense amplifier 36.

The address register 35 is connected to a column address buffer 37 and a row address buffer 38 arranged at a subsequent stage. The column address buffer 37 and the row address buffer 38 temporarily store the address output from the address register 35.
The column address buffer 37 is connected to a column address decoder 39 disposed at a subsequent stage, and the row address buffer 38 is connected to a row address decoder 40 disposed at a subsequent stage. Column address decoder 3
9 decodes the column address signal output from the column address buffer 37. The row address decoder 40 decodes a row address signal output from the row address buffer 38. The data register / sense amplifier 36 is controlled by the control circuit 41.

The data register / sense amplifier 36 and the row address decoder 40 are connected to a memory cell array 42 capable of electrically erasing electrical data and requiring no power supply for storing data. In the memory cell array 42, memory cells, which are the minimum units of storage, are regularly arranged in an array.

The input / output control circuit 33 includes:
The voltage generation control unit 43 is connected. The voltage generation control unit 43 performs erasing, writing,
A voltage of various levels required for reading is generated and supplied to the memory cell array 42.

FIG. 31 shows a configuration example of the memory cell array 42.

The memory cell array 42 shown in FIG.
Although not particularly limited, a plurality of EEPROM word lines EEWL are arranged to intersect a plurality of source lines SL and data lines DL, and a memory cell MC is arranged at the intersection. Further, well power is supplied to the well region of the transistor constituting each memory cell MC via the well power supply path PW. All of the plurality of memory cells MC have the same configuration, and are formed by combining a nonvolatile memory element and a bipolar transistor, as described in detail later.

FIG. 1 representatively shows one of the plurality of memory cells MC shown in FIG.

As shown in FIG. 1, the memory cell MC
One nonvolatile memory element 21 and one bipolar transistor 23 are combined.

The nonvolatile memory element 21 is not particularly limited, but may be an MNOS utilizing a trap at an interface between different kinds of insulators.
The device has a gate electrode G, a drain electrode D, and a source electrode S, similarly to a normal MOS transistor. Although not particularly limited, the bipolar transistor 23 is of a pnp type, and has a base electrode B, an emitter electrode E,
And a collector electrode C. Here, the bipolar transistor 23 corresponds to a switch transistor in the present invention. In the nonvolatile memory element 21, the gate electrode is coupled to the EEPROM word line EEWL,
The source electrode is connected to the base electrode B of the bipolar transistor 23, and the drain electrode D is connected to the data line DL. In the bipolar transistor 23, the base electrode B is coupled to the source electrode of the nonvolatile memory element 21, the emitter electrode E is coupled to the source line SL, and the collector electrode C is shared with the well region of the nonvolatile memory element 21. Is done.

FIG. 2 shows a layout of two memory cells MC, and FIG. 3 shows a cross section taken along line AA ′ in FIG.

Assuming that a region where one memory cell MC is formed is an active region, a predetermined element isolation region is formed between the active region and an adjacent memory cell MC. This element isolation region is usually made equal to the minimum processing size of the semiconductor device. One of the two metal wires ML formed so as to cross the EEPROM word line EEWL is a data line DL, and the other is a source line SL.
The data line DL and the source line SL are respectively coupled to the semiconductor region via through holes TH. The memory cell MC depends on the center position of the through hole TH.
Is determined. As will be described later in detail, a P-type well / bipolar transistor forming P-type implant layer (P-well) is formed on a P-type silicon substrate (P-sub), and the P-type well / bipolar transistor forming P-type implanter layer is formed. In the layer (P-well), a diffusion layer N ⁻ ,
By stacking N ⁺ and the implant layer (P), a bipolar transistor 23 is formed on the source electrode side of the nonvolatile memory element 21.

Next, a more specific structure of the memory cell MC will be described.

FIG. 13 shows a more detailed sectional structure of the memory cell MC.

Reference numeral 1 denotes a P-type silicon (Si) substrate. The P-type silicon (Si) substrate has a P-type implant layer (collector layer) for forming a P-type well and a bipolar transistor.
In addition, an element isolation insulating film 2 for isolating elements is formed. 11D is a first drain diffusion layer.
A second drain diffusion layer is stacked on the drain diffusion layer 11D. 11S is a first source diffusion layer / bipolar transistor forming N-type implanted layer (base layer). The first source diffusion layer / bipolar transistor forming N-type implanted layer 11S includes a second source diffusion layer 13S, A P-type implantation layer (emitter layer) for forming a bipolar transistor is laminated. Reference numeral 15 denotes an element protection insulating film for protecting the element. Reference numeral 16 denotes a metal wiring for element connection. The metal wiring 16 for element connection corresponds to the source line SL, and is coupled to a P-type implanted layer (emitter layer) for forming a bipolar transistor by a through hole. 4
Is a channel implantation layer for initial threshold value adjustment. The channel implantation layer 4 for initial threshold value adjustment is used for adjusting the initial threshold value of the memory cell MC and controlling punch-through between the source and the emitter of the bipolar transistor. Is provided. A tunnel oxide film 5, a charge storage nitride film 6, a charge leakage protection and protection oxide film 7, a gate electrode 8, and a gate electrode protection insulating film 9 are laminated on the channel implantation layer 4 for adjusting the initial threshold value. Reference numeral 10 denotes a through film for diffusion layer implantation, and the through film for diffusion layer implantation 1
Numeral 0 is formed for the purpose of reducing contamination and damage to the P-type silicon substrate 1 during the implantation of the N-type implantation layer 11S for forming the first source diffusion layer and the bipolar transistor and the first drain diffusion layer 11D. Reference numeral 12 denotes an insulating film side spacer.

Here, the bipolar transistor 23
P-type well / bipolar transistor forming P-type implant layer (collector layer) 3, first source diffusion layer / bipolar transistor forming N-type implant layer 11S, second source diffusion layer 13S, and bipolar transistor forming P-type implant layer (Emitter layer) 14 is formed by junction. That is, the collector electrode of the bipolar transistor 23 is formed by the P-type well / bipolar transistor forming P-type implantation layer (collector layer) 3, and the first source diffusion layer / bipolar transistor forming N-type implantation layer (base layer) 11S. The base electrode of the bipolar transistor 23 is formed, and the P-type implantation layer (emitter layer) 14 for forming the bipolar transistor forms
An emitter electrode of the bipolar transistor 23 is formed. In other words, the collector electrode of the bipolar transistor is formed using the P-type well of the EEPROM 21 in order to reduce the chip occupied area of the memory cell.
Using the first source electrode layer of the PROM 21, the emitter electrode of the bipolar transistor 23 is formed.

Next, the manufacturing process of the memory cell MC will be described with reference to FIGS.

First, as shown in FIG. 14, an STI (Shallow T) is formed on a P-type silicon (Si) substrate 1.
The element isolation insulating film 2 is formed by a trench-isolation or the like. Next, as shown in FIG. 15, a P-type implanter layer (collector layer) 3 for forming a P-type well and a bipolar transistor is formed by a high-energy implantation device and an annealing process, and as shown in FIG. An initial threshold value adjusting channel implant layer 4 is formed for adjusting the threshold value in the initial state of the MC and controlling punch-through between the source and the emitter of the bipolar transistor. Thereafter, as shown in FIG. 17, a tunnel oxide film 5 is formed by heat treatment, and a charge storage nitride film 6 is formed by CVD (Chemical-Vapor-).
The charge leakage protection oxide film 7 is finally formed by thermal oxidation or CVD. Although not particularly limited, the thickness of the tunnel oxide film 5 is about 1.5 nm, and the thickness of the charge storage nitride film 6 is 18.5 n.
m. Then, as shown in FIG. 18, a gate electrode 8 is formed, and a gate electrode protection insulating film 9 is formed thereon.
Are laminated. Although the gate electrode 8 is not particularly limited,
It is a polysilicon layer, and although not particularly limited, 200 n
m. Further, as shown in FIG. 19, the gate protection insulating film 9 is processed by photolithography, dry etching, or the like, and using the mask as a mask, the gate electrode 8, the charge leakage protection insulating film 7, the charge storage nitride film 6 is formed. Then, a tunnel oxide film 5 is formed by dry etching or the like. Next, as shown in FIG. 20, a through film 10 for diffusion layer implantation is formed by a heat treatment or a CVD method. Thereafter, as shown in FIG. 21, the N-type implantation layer 1 for forming the first source diffusion layer and the bipolar transistor is formed.
1S and the first drain diffusion layer 11D are formed by implantation. Then, as shown in FIG. 22, LDD (Lightly Doped Drain)
n) To form a structure, a film to be the insulating film side spacer 12 is formed by a CVD method. Further, as shown in FIG. 23, insulating film side spacers 12 are formed by dry etching or the like. Next, as shown in FIG. 24, a second source diffusion layer 13S and a second drain diffusion layer 13D are formed by implantation. Thereafter, as shown in FIG. 25, a P-type implant layer 14 serving as an emitter electrode of the bipolar transistor 23 is formed. The P-type implant layer 14 is formed only on the source electrode side of the nonvolatile memory element 21 by using photolithography. Then, as shown in FIG. 26, the element protection insulating film 15 is formed by the CVD method. Further, FIG.
As shown in FIG. 7, a hole for connecting between the metal wiring and the terminal is opened by photolithography and dry etching. After that, as shown in FIG. 19, the metal wiring 16 for connection between elements is PVD (Physical-Vap).
or-deposition) method,
By processing it by photolithography or dry etching, a memory cell MC having a cross-sectional structure shown in FIG. 13 is obtained.

Next, the operation of the memory cell MC configured as described above will be described with reference to FIGS.

First, the erasing operation will be described.

In the case of the erasing operation, as shown in FIGS. 7 and 20, under control of the voltage generation control unit 43 (see FIG. 29), the EEPROM word line EEWL is set to -9.5 V, and the source line SL is set. The voltage is set to 1.5 V, the data line DL is set to 1.5 V, and the well power supply path PW is set to 1.5 V. As a result, holes are injected into the charge storage nitride film 6 (trap). At this time, the bipolar transistor 23 is turned off.

Next, the write operation will be described.

In the case of a write operation, as shown in FIGS. 9 and 10, EE is controlled by the voltage generation control unit 43.
The PROM word line EEWL is set to 3V and the source line S
L is set to -9.5 V, the data line DL is set to -9.5 V, and the well power supply path PW is set to -9.5 V. This allows
As shown in FIG. 10, electrons are injected into the charge storage nitride film 6 (trap) from the source electrode side by the tunnel effect. At this time, the bipolar transistor 23 is turned off.

Next, the read operation will be described.

In the case of a read operation, as shown in FIGS.
The EPROM word line EEWL is set to 0V, the data line DL is set to 1.5V, the source line SL is set to 3V, and the well power supply path PW is set to 0V. When the channel is formed in the erased state, the data potential (1.5 V) is supplied to the base electrode of the bipolar transistor 23, so that the bipolar transistor 23 is turned on. As a result, as shown in FIG. , A read current flows through the bipolar transistor 23. When electrons are injected into the charge storage nitride film 6 (trap) from the drain electrode side by writing, the drain potential (1.5 V) is not supplied to the base electrode of the bipolar transistor 23. 23
Is not turned on. Therefore, in this case, no read current flows through the bipolar transistor 23.

Next, a memory to be compared with the EEPROM 30 will be described.

FIG. 30 shows a memory cell array 420 in a memory to be compared with the EEPROM 30.

The memory cell array 420 has the EE
Similar to the memory cell array 42 in the PROM 30 (see FIG. 31), a plurality of EEPROM word lines EEWL
And a plurality of source lines SL and data lines DL are arranged to intersect, memory cells MC are arranged at the intersections, and a well power supply path PW is provided in a well region of a transistor constituting each memory cell MC. , But the configuration of the memory cell MC is greatly different. In other words, the memory cell MC forming the memory cell array shown in FIG. 31 includes a nonvolatile memory element 21 and a bipolar transistor 23 as shown in FIG. 1, whereas the memory cell array shown in FIG. The 420 includes the nonvolatile memory element 21 and the MOS transistor 22 as shown in FIG. In response to the provision of the MOS transistor 22, the EEPROM word line EEW is provided.
A switching word line SWWL is provided in parallel with L.
The MOS transistor 22 is of an n-channel type,
Connect the drain electrode of the nonvolatile memory element 21 to the data line DL.
Function as a switch for selective coupling to M
The drain electrode of OS transistor 22 is coupled to data line DL. The gate electrode of the MOS transistor 22 is
It is coupled to the switch word line SWWL. The source electrode of MOS transistor 22 is coupled to the drain electrode of nonvolatile memory element 21. Switch word line SWW
Only when L is set to the high level and the MOS transistor 22 is turned on, the drain electrode of the EEPROM element 21 is conducted to the data line DL.

FIG. 5 shows a layout of two memory cells shown in FIG. 4, and FIG. 6 shows a line segment A in FIG.
A cross section at -A 'is shown.

A nonvolatile memory element 21 and a MOS transistor 22 are formed immediately below the EEPROM word line EEWL and the switch word line SWWL, respectively. Thus, the EEPROM word lines EEWL,
In addition, since the switching word lines SWWL are provided in parallel, at least the minimum processing dimension of the device element is included between them. The cell size 501 for one memory cell MC must be large.

On the other hand, in the memory cell MC shown in FIGS. 1 to 3, the bipolar transistor 23 is used in place of the MOS transistor 22, so that the switching word line SWWL is not required. This bipolar transistor 23 is an EEPROM
Since the P-type well 21 and the collector layer of the bipolar transistor 23 have a common structure, and the source diffusion layer of the EEPROM 21 and the base layer of the bipolar transistor 23 have a vertical structure, the bipolar structure is separate from the EEPROM 21. Despite the provision of transistor 23, cell size 20 for one memory cell MC
1 is approximately half the cell size 501 of one memory cell MC shown in FIGS. Since the size of the memory cells MC can be reduced in this way, the chip occupation area of a memory cell array in which such memory cells MC are arranged in an array can be reduced.

According to the above example, the following functions and effects can be obtained.

(1) The base electrode of the bipolar transistor 23 formed on the drain electrode side of the non-volatile memory element 21 and the source diffusion layer of the non-volatile memory element 21 can be used in common. Since the word line is not required, the chip area occupied by the memory cell can be reduced.

(2) The layer forming the collector electrode of the bipolar transistor 23 is
By making the layer forming the base electrode of the bipolar transistor 23 common with the source diffusion layer of the nonvolatile memory element 21, the bipolar transistor 23 has a vertical structure. As a result, the chip occupied area of the memory cell can be reduced.

(3) The layer forming the collector electrode of the bipolar transistor 23 is
When the layer forming the base electrode of the bipolar transistor 23 is shared with the source diffusion layer of the nonvolatile memory element 21, the layer forming the base electrode of the bipolar transistor 23 is By stacking the mold implantation layers, the emitter electrode of the bipolar transistor 23 can be easily formed.

(4) In order to operate the bipolar transistor 23 in response to the instructions of the erasing operation, the writing operation, and the reading operation of the memory cell MC, the erasing operation, the writing operation, and the reading operation instruction of the memory cell MC are performed. The voltage generation control unit 43 that controls the operation of the bipolar transistor 23 by switching the level of the voltage supplied to the bipolar transistor 23 in accordance with the erasing operation, the writing operation, and the reading operation of the memory cell MC is provided. Operation is enabled.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the invention made mainly by the present inventor is described in the MNO
The one having the S element has been described.
Can be widely applied to.

The present invention can be applied on the condition that it includes at least an electrically rewritable nonvolatile memory element.

[0053]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the base electrode of the bipolar transistor formed on the source electrode side of the non-volatile memory element can be shared with the source diffusion layer of the non-volatile memory element. Therefore, the chip occupation area of the memory cell can be reduced.

The layer forming the collector electrode of the bipolar transistor is shared with the P-type well of the nonvolatile memory element, and the layer forming the base electrode of the bipolar transistor is shared with the source diffusion layer of the nonvolatile memory element. By doing so, the bipolar transistor can have a vertical structure, and the chip occupation area of the memory cell can be reduced.

The layer forming the collector electrode of the bipolar transistor is shared with the P-type well of the nonvolatile memory element, and the layer forming the base electrode of the bipolar transistor is shared with the source diffusion layer of the nonvolatile memory element. When forming the bipolar transistor, an emitter electrode of the bipolar transistor can be easily formed by laminating a P-type implantation layer on a layer forming a base electrode of the bipolar transistor.

In order to operate the bipolar transistor 23 in accordance with the instructions of the erasing operation, the writing operation, and the reading operation of the memory cell, in response to the instructions of the erasing operation, the writing operation, and the reading operation of the memory cell MC, By providing a voltage generation control unit for controlling the operation of the bipolar transistor by switching the level of the voltage supplied to the bipolar transistor, the erase operation, the write operation, and the read operation control of the memory cell MC can be optimized. it can.

[Brief description of the drawings]

FIG. 1 is an example of a semiconductor memory device according to the present invention;
FIG. 3 is a circuit diagram illustrating a configuration example of a memory cell in an EPROM.

FIG. 2 is a layout plan view of the memory cell.

FIG. 3 is a sectional view taken along line AA ′ in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration example of a memory cell in a memory to be compared with the EEPROM.

FIG. 5 is a layout plan view of the memory cell shown in FIG. 4;

FIG. 6 is a sectional view taken along line AA ′ in FIG. 5;

FIG. 7 is a circuit diagram for explaining an erase operation of the memory cell.

FIG. 8 is an explanatory diagram of an erase operation of the memory cell.

FIG. 9 is a circuit diagram for explaining a write operation of the memory cell.

FIG. 10 is an explanatory diagram of a write operation of the memory cell.

FIG. 11 is a circuit diagram for explaining a read operation of the memory cell.

FIG. 12 is an explanatory diagram of a read operation of the memory cell.

FIG. 13 is a cross-sectional view of a memory cell in an EEPROM which is an example of a semiconductor memory device according to the present invention.

14 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

FIG. 15 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

16 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

17 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

18 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

19 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

20 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

21 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

FIG. 22 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

23 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

24 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

FIG. 25 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG. 13;

26 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

FIG. 27 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

28 is an explanatory diagram of the manufacturing process of the memory cell shown in FIG.

FIG. 29 is a block diagram of an overall configuration example of an EEPROM which is an example of a semiconductor memory device according to the present invention.

FIG. 30 is a circuit diagram showing a configuration example of a memory cell array in a memory to be compared with an EEPROM which is an example of a semiconductor memory device according to the present invention.

FIG. 31 is a circuit diagram showing a configuration example of a memory cell array in the EEPROM shown in FIG. 29;

[Explanation of symbols]

 Reference Signs List 21 nonvolatile memory element 23 bipolar transistor 30 EEPROM 41 control circuit 42 memory cell array 43 voltage generation control unit MC memory cell DL data line SL source line EEWL EEPROM word line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AA04 AB01 AC02 AE00 AE08 5F083 EP18 EP21 EP61 EP63 EP67 EP68 ER09 ER11 KA01 MA06 MA19 PR09 PR29 PR36 5F101 BA46 BD03 BD09 BD14 BD18 BD22 BD31 BD35 BD36 BE02 BE05 BE07 BH09 BH

Claims (4)

[Claims] 1. A semiconductor memory device comprising: a plurality of memory cells; and a data line capable of inputting and outputting data to and from the memory cells, wherein the memory cells are electrically rewritable nonvolatile memory elements. And a switch transistor disposed between the nonvolatile memory element and the data line, wherein the switch transistor is a bipolar transistor formed on a drain electrode side of the nonvolatile memory element. Semiconductor storage device. 2. A layer forming a collector electrode of the bipolar transistor is shared with a P-type well of the nonvolatile memory element, and a layer forming a base electrode of the bipolar transistor is formed on a source of the nonvolatile memory element. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is shared with a diffusion layer. 3. A layer forming a collector electrode of the bipolar transistor is shared with a P-type well of the nonvolatile memory element, and a layer forming a base electrode of the bipolar transistor is formed on a source of the nonvolatile memory element. 2. The semiconductor memory device according to claim 1, wherein a P-type implantation layer for forming an emitter electrode of said bipolar transistor is laminated on a layer which is shared with a diffusion layer and forms a base electrode of said bipolar transistor. 4. A control means for controlling an operation of the bipolar transistor by switching a level of a voltage supplied to the bipolar transistor in accordance with an instruction of an erase operation, a write operation, and a read operation of the memory cell. The semiconductor memory device according to claim 1.