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JP2002365331A - Device evaluation holder - Google Patents

Device evaluation holder

Info

Publication number
JP2002365331A
JP2002365331A JP2001173724A JP2001173724A JP2002365331A JP 2002365331 A JP2002365331 A JP 2002365331A JP 2001173724 A JP2001173724 A JP 2001173724A JP 2001173724 A JP2001173724 A JP 2001173724A JP 2002365331 A JP2002365331 A JP 2002365331A
Authority
JP
Japan
Prior art keywords
evaluation
pattern
jig
evaluation jig
device evaluation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001173724A
Other languages
Japanese (ja)
Inventor
Akiko Murakami
暁子 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP2001173724A priority Critical patent/JP2002365331A/en
Publication of JP2002365331A publication Critical patent/JP2002365331A/en
Withdrawn legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a device evaluation holder, causing no peeling of the foot pattern of a product device, requiring no wiring area of a printed wiring board, nor use of an IC socket. SOLUTION: This device evaluation tool 1 is to be mounted on a surface opposite to the surface for mounting the product device 6 of a board 5. The holder 1 comprises a frame-like body 1b, an evaluation device 2 which is housed in the central space part of the body 1b, and a pattern 1a for contacting with the lead 2a of the evaluation device 2 is formed on the upper surface of the body 1; and the pattern 1a is extended to the lower surface of the body 1, and the pattern 1a of the lower surface makes contact with the pattern 7 of the board 5. A lid 3 for covering the upper surface of the frame-like body 1 of the device evaluation holder 1 may be provided, and the device evaluation holder 1 is set suitably attachably with respect to the board 5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、デバイス評価治具
に関し、特に、ガルウィングリードタイプのLSI等の
ICの評価に使用する治具に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device evaluation jig, and more particularly, to a jig used for evaluating an IC such as a gull wing lead type LSI.

【0002】[0002]

【従来の技術】従来、表面実装タイプのLSI(大規模
集積回路)やGA(ゲートアレイ)等の単体評価、ある
いはこれらの部品を搭載する基板上の回路の評価を行う
場合には、デバイスの交換が可能となるように、評価時
は、製品用デバイスとは別に、基板上の別の場所に評価
用デバイスを実装できるようなパターンを設けたり、I
Cソケットを使用していた。
2. Description of the Related Art Conventionally, when evaluating a single unit such as a surface mount type LSI (large-scale integrated circuit) or GA (gate array), or an evaluation of a circuit on a substrate on which these components are mounted, it is necessary to evaluate a device. At the time of evaluation, a pattern for mounting the evaluation device in another place on the board is provided separately from the product device so that the evaluation device can be replaced.
C socket was used.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記従来の技
術においては、評価用デバイスの試験を行う時、評価用
デバイスの実装に製品用デバイスのフットパタンを使用
するのが最も小型化を可能とするが、製品用デバイスの
フットパタンは、何度も着脱を行うと、パタン剥離を起
こす危険があり、評価用デバイスを直接実装するのは問
題であった。
However, in the above-mentioned conventional technology, when testing the device for evaluation, the use of the foot pattern of the product device for mounting the device for evaluation makes it possible to reduce the size most. However, if the foot pattern of a product device is detached and attached many times, there is a risk of peeling off the pattern, and directly mounting the evaluation device is a problem.

【0004】そのため、従来、評価用デバイスを取り付
けて試験を行う時には、試験評価用デバイスのためのフ
ットパタンを設け、ICソケットを用いて試験したりし
ていた。この方法では、試験回路を設けるため、プリン
ト配線板の配線エリアを十分に確保する必要があり、特
に、多ピンLSIの場合にはその影響が顕著であった
り、そのためにデバイスを搭載する基板、装置を小型化
できないという問題があった。また、部品の高さ制限が
ある場合、ICソケットには、高さの低いソケットが要
求されていた。
Therefore, conventionally, when a test is performed by attaching an evaluation device, a foot pattern for the test evaluation device is provided, and the test is performed using an IC socket. In this method, since a test circuit is provided, it is necessary to secure a sufficient wiring area of the printed wiring board. In particular, in the case of a multi-pin LSI, the effect is remarkable. There is a problem that the device cannot be miniaturized. In addition, when there is a restriction on the height of components, a low socket is required for the IC socket.

【0005】そこで、本発明は、上記従来のデバイス評
価治具における問題点に鑑みてなされたものであって、
製品用デバイスのフットパタンの剥離を生じさせること
なく、プリント配線板の配線エリアが不要で、ICソケ
ットを使用する必要のないデバイス評価治具を提供する
ことを目的とする。
Accordingly, the present invention has been made in view of the problems in the above-mentioned conventional device evaluation jig,
It is an object of the present invention to provide a device evaluation jig which does not require a wiring area of a printed wiring board and does not require the use of an IC socket without causing peeling of a foot pattern of a product device.

【0006】[0006]

【課題を解決するための手段】上記目的を解説するた
め、請求項1記載の発明は、デバイス評価治具であっ
て、基板の製品用デバイスを実装する面と反対側の面に
装着することを特徴とする。
In order to explain the above object, an invention according to claim 1 is a device evaluation jig which is mounted on a surface of a substrate opposite to a surface on which a product device is mounted. It is characterized by.

【0007】そして、請求項1記載の発明によれば、デ
バイス評価治具を、基板の製品用デバイスを実装する面
と反対側の面、すなわち、基板の半田面側に装着するた
め、基板内の製品用デバイスを実装する面に評価用デバ
イスのフットパタンを設ける必要がなく、プリント配線
板等の配線スペースを大幅に削減でき、基板のパタン設
計工数が削減できるとともに、プリント配線板等を小型
にすることができる。また、従来のようなICソケット
を使用する必要もないため、部品の高さ制限がある場合
にも対応することができる。
According to the first aspect of the present invention, the device evaluation jig is mounted on the surface of the substrate opposite to the surface on which the product device is mounted, that is, on the solder surface side of the substrate. It is not necessary to provide an evaluation device foot pattern on the surface on which the product device is to be mounted, so that the wiring space for the printed wiring board and the like can be significantly reduced, the man-hour for designing the pattern of the board can be reduced, and the printed wiring board and the like can be reduced in size. Can be Further, since there is no need to use an IC socket as in the related art, it is possible to cope with a case where the height of parts is limited.

【0008】請求項2記載の発明は、請求項1記載のデ
バイス評価治具の好ましい一形態として、前記デバイス
評価治具は、フレーム状本体を備え、該本体の中央空間
部に評価用デバイスが収容され、該本体の上面に前記評
価用デバイスのリードと接触するパタンが形成され、該
パタンは該本体の下面まで延設され、該下面のパタンが
前記基板のパタンと接触することを特徴とする。
According to a second aspect of the present invention, as a preferred embodiment of the device evaluation jig of the first aspect, the device evaluation jig includes a frame-shaped main body, and an evaluation device is provided in a central space of the main body. It is housed, a pattern is formed on the upper surface of the main body to come into contact with the leads of the evaluation device, the pattern extends to the lower surface of the main body, and the pattern on the lower surface contacts the pattern of the substrate. I do.

【0009】請求項3記載の発明は、請求項2記載のデ
バイス評価治具において、前記デバイス評価治具のフレ
ーム状本体の上面を覆う蓋を備えたことを特徴とする。
これによって、評価用デバイスの脱落を確実に防止する
ことができる。
According to a third aspect of the present invention, in the device evaluation jig of the second aspect, a lid for covering an upper surface of a frame-shaped main body of the device evaluation jig is provided.
This makes it possible to reliably prevent the evaluation device from falling off.

【0010】請求項4記載の発明は、請求項1、2また
は3記載のデバイス評価治具において、前記基板に対し
て前記デバイス評価治具を着脱可能としたことを特徴と
する。これによって、評価用デバイスの評価後、基板か
ら取り外すことにより部品の高さ制限を緩和することが
できる。
According to a fourth aspect of the present invention, in the device evaluation jig of the first, second or third aspect, the device evaluation jig is detachable from the substrate. Thereby, after the evaluation device is evaluated, the height limitation of the component can be eased by removing the evaluation device from the substrate.

【0011】[0011]

【発明の実施の形態】次に、本発明にかかるデバイス評
価治具の実施の形態の具体例を図面を参照しながら説明
する。
Next, a specific example of an embodiment of a device evaluation jig according to the present invention will be described with reference to the drawings.

【0012】図1乃至図4は、本発明にかかるデバイス
評価治具の一実施例を示し、このデバイス評価治具1
は、フレーム状に形成された本体1bを備える。本体1
bは、このデバイス評価治具1に装着される表面実装タ
イプのLSI評価用デバイス(以下、「評価用デバイ
ス」と略称する)2と同程度の厚さに形成され、評価用
デバイス2のリード2aと接触するデバイス評価治具1
上のパタン1aは、裏面まで配線されている。また、デ
バイス評価治具1には、四隅にねじ穴1cが螺設されて
いる。
FIGS. 1 to 4 show an embodiment of a device evaluation jig according to the present invention.
Includes a main body 1b formed in a frame shape. Body 1
b is formed to a thickness similar to that of a surface-mount type LSI evaluation device (hereinafter abbreviated as “evaluation device”) 2 mounted on the device evaluation jig 1, and leads of the evaluation device 2 are formed. Device evaluation jig 1 that contacts 2a
The upper pattern 1a is wired to the back surface. The device evaluation jig 1 is provided with screw holes 1c at four corners.

【0013】図3に示すように、評価用デバイス2は、
基板に直接実装される場合とは上下が逆にデバイス評価
治具1に取り付けられ、評価用デバイス2のリード2a
をデバイス評価治具1上のパタン1aとを接触させる。
そして、蓋3を被せ、ねじ4で蓋3をデバイス評価治具
1にねじ穴1c(図1参照)を介してねじ止めする。こ
れによって、評価用デバイス2の脱落を防ぐことができ
る。
As shown in FIG. 3, the evaluation device 2
The lead 2a of the evaluation device 2 is attached to the device evaluation jig 1 upside down when mounted directly on the substrate.
Is brought into contact with the pattern 1a on the device evaluation jig 1.
Then, the cover 3 is put on, and the cover 3 is screwed to the device evaluation jig 1 with the screw 4 via the screw hole 1c (see FIG. 1). This can prevent the evaluation device 2 from falling off.

【0014】図4は、デバイス評価治具1を基板5に取
り付けた状態を示す。デバイス評価治具1は、基板5の
製品用表面実装デバイス(以下、「製品用デバイス」と
略称する)6を実装する面と反対側の面(同図の上側の
面)に導電性接着剤や半田等で基板5に取り付けられ
る。
FIG. 4 shows a state where the device evaluation jig 1 is attached to the substrate 5. The device evaluation jig 1 is provided with a conductive adhesive on a surface opposite to a surface on which a product surface mount device (hereinafter abbreviated as “product device”) 6 of the substrate 5 is mounted (upper surface in FIG. 1). It is attached to the board 5 with solder or solder.

【0015】次に、上記構成を有するデバイス評価治具
1を用いたデバイス評価方法について説明する。
Next, a device evaluation method using the device evaluation jig 1 having the above configuration will be described.

【0016】評価試験時には、製品用デバイス6を基板
5に実装せず、デバイス評価治具1及び評価用デバイス
2のみを実装して評価試験を行う。評価試験後、製品用
デバイス6を基板5に実装し、デバイス評価治具1を評
価用デバイス1とともに取り外す。そのため、基板5と
デバイス評価治具1の着脱を1回行うだけで済むため、
半田付けにより製品用デバイス6のフットパタンを損傷
することはない。
At the time of the evaluation test, the evaluation test is performed by mounting only the device evaluation jig 1 and the evaluation device 2 without mounting the product device 6 on the substrate 5. After the evaluation test, the product device 6 is mounted on the substrate 5, and the device evaluation jig 1 is removed together with the evaluation device 1. Therefore, since only one attachment / detachment of the substrate 5 and the device evaluation jig 1 is required,
The foot pattern of the product device 6 is not damaged by soldering.

【0017】上記評価時において、評価用デバイス2の
実装方向を、基板5を挟んで製品用デバイス6と同じ向
きにすることができる。このとき、製品用デバイス6に
配線される基板上のパタン7はスルーホール8を介して
基板5の裏面に配され、そこでデバイス評価治具1のパ
タン1aと接続されて導通する。
At the time of the above evaluation, the mounting direction of the evaluation device 2 can be the same as that of the product device 6 with the substrate 5 interposed therebetween. At this time, the pattern 7 on the substrate wired to the product device 6 is arranged on the back surface of the substrate 5 via the through hole 8, where it is connected to the pattern 1 a of the device evaluation jig 1 to conduct.

【0018】[0018]

【発明の効果】以上説明したように、本発明によれば、
製品用デバイスのフットパタンの剥離を生じさせること
なく、プリント配線板の配線エリアが不要で、ICソケ
ットを使用する必要のないデバイス評価治具を提供する
ことができる。
As described above, according to the present invention,
It is possible to provide a device evaluation jig which does not require a wiring area of a printed wiring board and does not require the use of an IC socket, without causing a peeling of a foot pattern of a product device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明にかかるデバイス評価治具の一実施例を
示す上面図であって、デバイス評価治具を基板に搭載
し、蓋を取り外した状態を示す図である。
FIG. 1 is a top view showing an embodiment of a device evaluation jig according to the present invention, showing a state where a device evaluation jig is mounted on a substrate and a lid is removed.

【図2】図1のデバイス評価治具に蓋を取り付けた状態
を示す上面図である。
FIG. 2 is a top view showing a state where a lid is attached to the device evaluation jig of FIG.

【図3】図2のデバイス評価治具を示す断面図である。FIG. 3 is a sectional view showing the device evaluation jig of FIG. 2;

【図4】図2のデバイス評価治具を基板に実装した状態
を示す断面図である。
4 is a cross-sectional view showing a state where the device evaluation jig of FIG. 2 is mounted on a substrate.

【符号の説明】[Explanation of symbols]

1 デバイス評価治具 1a パタン 1b 本体 1c ねじ穴 2 評価用デバイス 2a リード 3 蓋 4 ねじ 5 基板 6 製品用デバイス 7 基板上のパタン 8 スルーホール DESCRIPTION OF SYMBOLS 1 Device evaluation jig 1a Pattern 1b Main body 1c Screw hole 2 Evaluation device 2a Lead 3 Lid 4 Screw 5 Board 6 Product device 7 Pattern on board 8 Through hole

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板の製品用デバイスを実装する面と反
対側の面に装着することを特徴とするデバイス評価治
具。
1. A device evaluation jig mounted on a surface of a substrate opposite to a surface on which a product device is mounted.
【請求項2】 前記デバイス評価治具は、フレーム状本
体を備え、該本体の中央空間部に評価用デバイスが収容
され、該本体の上面に前記評価用デバイスのリードと接
触するパタンが形成され、該パタンは該本体の下面まで
延設され、該下面のパタンが前記基板のパタンと接触す
ることを特徴とする請求項1記載のデバイス評価治具。
2. The device evaluation jig includes a frame-shaped main body, an evaluation device is accommodated in a central space portion of the main body, and a pattern that is in contact with a lead of the evaluation device is formed on an upper surface of the main body. 2. The device evaluation jig according to claim 1, wherein the pattern extends to a lower surface of the main body, and the pattern on the lower surface contacts the pattern on the substrate.
【請求項3】 前記デバイス評価治具のフレーム状本体
の上面を覆う蓋を備えたことを特徴とする請求項2記載
のデバイス評価治具。
3. The device evaluation jig according to claim 2, further comprising a lid that covers an upper surface of a frame-shaped main body of the device evaluation jig.
【請求項4】 前記基板に対して前記デバイス評価治具
を着脱可能としたことを特徴とする請求項1、2または
3記載のデバイス評価治具。
4. The device evaluation jig according to claim 1, wherein the device evaluation jig is detachable from the substrate.
JP2001173724A 2001-06-08 2001-06-08 Device evaluation holder Withdrawn JP2002365331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001173724A JP2002365331A (en) 2001-06-08 2001-06-08 Device evaluation holder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001173724A JP2002365331A (en) 2001-06-08 2001-06-08 Device evaluation holder

Publications (1)

Publication Number Publication Date
JP2002365331A true JP2002365331A (en) 2002-12-18

Family

ID=19015133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001173724A Withdrawn JP2002365331A (en) 2001-06-08 2001-06-08 Device evaluation holder

Country Status (1)

Country Link
JP (1) JP2002365331A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007122007A (en) * 2005-09-29 2007-05-17 Fujinon Corp Imaging lens

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007122007A (en) * 2005-09-29 2007-05-17 Fujinon Corp Imaging lens

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Date Code Title Description
A300 Withdrawal of application because of no request for examination

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Effective date: 20080902