JP2002360801A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a command from being missed by each of subordinate control means not only after a power source is turned on but also just after the power source is momentarily turned off. SOLUTION: A delay circuit 201 has a resistance value and capacitance, with which the total time required for a resistor 21 and a capacitor 22 to increase the inter-terminal voltage of the capacitor 22 charged through the resistor 21 to the threshold of a Schmidt trigger buffer 23 and the initializing processing time of a main control part 2 becomes equal to prescribed time exceeding the maximum initializing processing time of a pattern control part or the like, and further has a resistance value, with which time required for a resistor 24 to decrease the inter-terminal voltage of the capacitor 22 discharged through the serial circuit of a diode 25 and the resistor 24 to the threshold of the Schmidt trigger buffer 23 becomes equal to prescribed time shorter than holding time, smaller than that of the resistor 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko machine that can be reset for each symbol control function and other functions.

[0002]

2. Description of the Related Art Conventionally, in a pachinko machine, functions for controlling the entire pachinko machine are assigned to a main board, and specific functions performed according to commands from the main board, for example, a symbol control function, a voice control function, and the like. , A lamp control function, a prize ball payout control function, a firing control function, and the like are allocated to the sub-board. Power is supplied to such a main board and a sub-board by one power supply unit, and a power-on reset signal is supplied from the power supply unit to a CPU (central processing unit) of the main board.
Are supplied via a delay circuit and are also directly supplied to each CPU on the sub-board. This power-on reset signal is, for example, 100
Change from active to inactive after elapse of ms.

As the delay circuit, for example, a resistor 61,
A delay circuit having a capacitor 62 and a Schmitt trigger buffer 63 as shown in FIG. 6 is used, and the power-on reset signal is delayed by the delay circuit so that the initialization processing time of the main board is the maximum initialization processing time of the sub-board. Since the length is longer, the command from the main board is reliably received by each sub-board.

[0004] Here, the initialization processing time refers to the initialization time of the main board by the CPU of the main board in response to the power-on reset signal input to the CPU of the main board being changed from active to inactive. Processing, for example, the processing of setting input / output ports, clearing RAM and setting initial value data, and the like, until the CPU of the main board can issue a command to the sub-board. Regarding the sub-board, in response to the power-on reset signal input to the CPU of the sub-board changing from active to inactive, the CPU of the sub-board initializes the CPU, for example, setting input / output ports, R
This refers to the time from when processing such as clearing of AM and setting of initial value data is performed until the CPU of the sub-board can receive commands from the main board.

[0005]

However, when an instantaneous power failure occurs (FIG. 7 (a)), the power-on reset signal once falls, holds the low level for, for example, 5 ms, and then rises (FIG. 7 (a)). The input of the Schmitt trigger buffer 63 up to b)) is, for example, as shown in FIG. 7C, and the power-on reset signal is not supplied from the delay circuit of FIG. 6 (FIG. 7D). The main board is not reset. Therefore, no command is issued by the CPU of the main board.

On the other hand, each sub-board is reset, and when the power-on reset signal changes from active to inactive, CPU initialization processing, such as setting of input / output ports, clearing of RAM and setting of initial value data, etc. Is performed, and the command of the CPU after the CPU initialization processing can be received by the CPU of the sub board, but the command is not issued after the CPU initialization processing by the CPU of the main board, so that the pachinko machine malfunctions. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a gaming machine capable of preventing a loss of a command by each sub-control means not only after power-on but also after a momentary power-off. To provide.

[0008]

According to a first aspect of the present invention, there is provided a main control means, a plurality of sub-control means for performing predetermined control in accordance with a control command from the main control means, The main control means and the power-on reset signal which become inactive from active after a lapse of a predetermined time, and become inactive after holding an active state for a predetermined holding time shorter than the time after an instantaneous power failure. In a gaming machine having supply means for supplying to a plurality of sub-control means, the main control means comprises: a first resistor; a second resistor having a resistance smaller than the first resistor; a capacitor; a diode; Delay means for delaying a power-on reset signal supplied by the supply means, wherein the first resistor and the capacitor The total time of the time required for the voltage between the terminals of the capacitor charged through the first resistor to rise to the threshold voltage of the Schmitt trigger buffer and the initialization processing time of the main control means, Circuit having a resistance value and a capacitance that are equal to a predetermined time exceeding the maximum initialization processing time of the sub-control means, wherein the second resistor is formed by connecting the diode and the second resistor in series. And a delay means having a resistance value such that a time required for the voltage between the terminals of the capacitor discharged via the capacitor to fall to a threshold voltage of the Schmitt trigger buffer is equal to a predetermined time less than the holding time. It is characterized by the following.

According to a second aspect of the present invention, there is provided a main control means, a plurality of sub-control means for performing predetermined control according to a control command from the main control means, and a predetermined time having elapsed since the power was turned on. The main control means and the plurality of sub-control means, which later become active from inactive, and after a momentary power failure, hold the active state for a predetermined holding time shorter than the above-mentioned time and then become inactive and then become inactive, The main control means is a clock generation means for generating a clock, and a delay means for delaying a power-on reset signal supplied by the supply means; The output is made active by being reset by a power-on reset signal, while the inactive power-on reset is A counter which releases a reset by a signal and inactivates an output, wherein at the time of reset release, a clock generated by said clock generating means is set to a pulse width of said clock and a maximum initial value of said plurality of sub-control means. And a delay means having a counter for inactivating the output when a predetermined number is counted from the conversion processing time.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
An embodiment will be described. This is an example of a pachinko machine. In FIG. 1, reference numeral 1 denotes a power supply unit, which includes a regulator 101 and a power-on reset circuit 102.
The regulator 101 outputs voltages of 12V and 5V. The power-on reset circuit 102 outputs a power-on reset signal after a lapse of a predetermined time from the output of the 5 V voltage from the regulator 101. Reference numeral 2 denotes a main control unit which includes a delay circuit 201 and a CP
U202. The delay circuit 201 delays the power-on reset signal from the power-on reset circuit 102 by a predetermined time. The CPU 202 has a built-in ROM and RAM, and the CPU 202 has a delay circuit 2
01 is input.

A symbol control unit 3 includes a ROM and R
It has a CPU 301 with a built-in AM and drives and controls the display 4. A regulator 10 is provided in the symbol control unit 3.
1, 12V and 5V are applied. CPU3
A power-on reset signal is directly input to 01 from the power-on reset circuit 102. Reference numeral 5 denotes an audio control unit which has a CPU 501 with a built-in ROM and RAM, and controls the driving of the speaker 4. The voltage of 12 V and 5 V of the regulator 101 is applied to the audio control unit 5. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 501.

Reference numeral 7 denotes a lamp control unit which has a CPU 701 having a built-in ROM and RAM, and controls the operation of the indicator lamp 8. The voltage of 12 V and 5 V of the regulator 101 is applied to the lamp control unit 7. CP
The power-on reset signal is directly input from the power-on reset circuit 102 to U701. Reference numeral 9 denotes a payout control unit, which is a CPU 90 having a built-in ROM and RAM.
1 for controlling the dispensing device 10. The payout control unit 9 is supplied with voltages of 12 V and 5 V of the regulator 101. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 901. Reference numeral 11 denotes a firing control unit, which stores ROM and R
It has a CPU 1101 with a built-in AM and controls the launch device 12. The firing controller 11 is supplied with the voltages of 12 V and 5 V of the regulator 101. CP
The power-on reset signal from the power-on reset circuit 102 is directly input to U1101.

The symbol control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the firing control unit 11 are sub-control units for the main control unit 2, respectively.

FIG. 2 shows the configuration of the delay circuit 201 of FIG. The power-on reset signal input terminal is connected to the input terminal of the Schmitt trigger buffer 23 via the resistor 21. The node between the resistor 21 and the input terminal of the Schmitt trigger buffer 23 is connected to the ground via the capacitor 22. A circuit formed by connecting the resistor 24 and the cathode of the diode 25 is connected in parallel to the resistor 21.

According to the delay circuit 201 configured as described above, the rising edge of the power-on reset signal (FIG. 3)
(A)) uses the following equation:

[0017]

## EQU1 ## Trd = −C · R1 · ln (1− (Vth / Vh)) (1)

Where C is the capacitance of the capacitor 22, R1 is the resistance of the resistor 21, Vth is the threshold of the Schmitt trigger buffer, and Vh is the delay time Trd obtained from the high level voltage of the power-on reset signal. (See FIGS. 3B and 3C).

On the other hand, the delay circuit 201 thus configured
According to the equation, the falling edge of the power-on reset signal (FIG. 3A) is expressed by the following equation:

[0020]

Tfd = −C · R2 · ln (Vth / Vh) (2)

Where C is the capacitance of the capacitor 22, R2 is the resistance of the resistor 24, Vth is the threshold of the Schmitt trigger buffer, and Vh is the delay time Tfd obtained from the high level voltage of the power-on reset signal. (See FIGS. 3B and 3C).

Here, it is assumed that the threshold (Vth) of the Schmitt trigger buffer and the high level voltage (Vh) of the power-on reset signal are known in advance.

Therefore, the total time of the delay time Trd and the initialization processing time of the main board is calculated by the graphic control unit 3, the voice control unit 5,
The lamp control unit 7, the payout control unit 9, and the firing control unit 11 are set to a predetermined time exceeding the maximum initialization processing time, and the delay time Tfd is set to a low level once the level of the power-on reset signal at the time of an instantaneous power outage. When it is equal to a predetermined time shorter than the known holding time Tinst from the time of becoming to the high level, the equations (1) and (2) are satisfied.

[0024]

[Equation 3] Resistance value of resistor 21 >> Resistance value of resistor 24

A capacitor 22 and resistors 21 and 24 having a capacitance and a resistance value satisfying the above conditions are employed.

According to the delay circuit 201 employing the capacitor 22 and the resistors 21 and 24 having such capacitance and resistance values, the rising edge delay time of the rising edge of the power-on reset signal after the power is turned on and the initial time of the main substrate Time exceeds the maximum initialization processing time of the sub-substrate, and on the other hand, the falling edge of the power-on reset signal can be delayed by a predetermined time shorter than the time Tinst after a momentary power failure. At the same time, the total time of the rising edge delay time and the initialization processing time of the main substrate exceeds the maximum initialization processing time of the sub-substrate.

Therefore, not only after the power is turned on but also after a momentary power failure, it is possible to prevent the figure control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the emission control unit 11 from missing the command. be able to.

<Second Embodiment> This embodiment relates to a first embodiment.
The configuration of the delay circuit is different from the embodiment.

FIG. 4 shows a delay circuit according to this embodiment. This delay circuit comprises a counter 41 and an inverter 42
And an AND gate 43. The counter 41 is reset by a low-level power-on reset signal, the inverter 42 inverts the output level of the counter, and the AND gate 43 performs an AND operation on the output of the inverter 42 and the clock ck. Things.

When the counter 41 counts n clocks ck, the level of the output terminal is set to a high level.
One of the two input terminals of the ND gate 43 becomes low level, the clock ck is not output to the output of the AND gate 43, and therefore, the clock ck is not input to the counter 41.

The delay time Td is stored in the graphic control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the firing control unit 11.
Is set equal to a predetermined time exceeding the maximum initialization processing time.

Further, a relational expression between the pulse width t of the clock ck, the delay time Td, and the count number n of the counter 41, that is,

[0033]

## EQU4 ## Td ≦ t · n

It is assumed that n obtained from the above is adopted.

According to the delay circuit configured as described above, the counter 41 is reset and the level of the output terminal is set to the low level until the power-on reset signal from the power-on reset circuit 102 rises after the power is turned on. , And the output level of the inverter 42 is at the high level. As a result, the clock ck is input to the counter 41 via the AND gate 43, but since the counter 41 is in the reset state, the clock ck cannot be counted (FIGS. 5C and 5D).

Thereafter, when the power-on reset signal rises (FIG. 5B), the reset of the counter 41 is released, and the counter 41 starts counting the clock ck. Then, when n clocks ck are counted (FIG. 5D), the level of the output terminal of the counter 41 changes from low level to high level (FIG. 5E), so that the output level of the inverter 42 becomes low level. become. As a result, the clock ck is not input to the counter 41 via the AND gate.

On the other hand, once a momentary power failure (FIG. 5A) occurs, the power-on reset signal rises until the power-on reset signal rises.
That is, the level of the power-on reset signal is low until the time Tinst elapses after the power is supplied, so that the counter 41 is in the reset state, the level of the output terminal is low, and 4
2 is at the high level. Clock c
k is input to the counter 41 via the AND gate, but since the counter 41 is in the reset state, the clock ck cannot be counted (FIGS. 5C and 5D).

When the power-on reset signal rises (FIG. 5B), the reset of the counter 41 is released, and the counter 41 starts counting the clock ck. When the clock ck is counted n times (FIG. 5D), that is, when the clock ck is delayed by the rising edge delay time corresponding to the result of multiplying the pulse width of the clock ck by n, the level of the output terminal becomes low level. To high level (Fig. 5
(E)) Therefore, the output level of the inverter 42 becomes low. As a result, the clock ck is not input to the counter 41 via the AND gate.

According to the delay circuit 201, the total time of the rising edge delay time of the rising edge of the power-on reset signal after the power is turned on and the initialization processing time of the main board is the maximum initialization processing of the sub-board. On the other hand, the falling edge of the power-on reset signal can be delayed by a predetermined time shorter than the time Tinst after the instantaneous power failure, and the time between the rising edge delay time and the initialization processing time of the main board can be reduced. The total time exceeds the maximum initialization processing time of the sub-substrate.

Therefore, not only after the power is turned on but also after a momentary power failure, the command control by the graphic control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the firing control unit 11 is prevented from being missed. be able to.

[0041]

As described above, according to the present invention,
With the configuration described above, it is possible to prevent each sub-control unit from failing to take a command not only after power is turned on but also after a momentary power failure.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a delay circuit 201 in FIG.

FIG. 3 is a timing chart showing an example of the timing of each section of the delay circuit 201 of FIG.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing an example of the timing of each section of the delay circuit of FIG. 4;

FIG. 6 is a circuit diagram showing a conventional example of a delay circuit.

FIG. 7 is a timing chart showing an example of the timing of each section of the delay circuit of FIG. 6;

[Explanation of symbols]

Reference Signs List 1 power supply unit 2 main control unit 3 graphic control unit 4 audio control unit 7 lamp control unit 9 payout control unit 11 firing control unit 21, 24 resistor 22 capacitor 23 Schmitt trigger buffer 25 diode 41 counter 42 inverter 43 AND gate 101 regulator 102 power ON reset circuit 201 Delay circuit 202, 301, 501, 701, 901 and 1101
CPU

Continued on the front page F-term (reference) 2C088 AA31 BC58 DA24 EA09 EA10 5J055 AX21 AX57 AX58 BX41 CX00 DX01 EY01 EY10 EY12 EZ07 EZ25 EZ34 EZ39 EZ50 FX20 FX24 GX01 GX02 GX04 GX05

Claims (2)

[Claims] 1. A main control means, a plurality of sub-control means for performing a predetermined control according to a control command from the main control means, and an active to inactive state after a predetermined time has elapsed since the power was turned on. Supply means for supplying to the main control means and the plurality of sub-control means a power-on reset signal which becomes inactive after holding an active state for a predetermined holding time shorter than the time after the instantaneous interruption The main control means comprises: a first resistor, a second resistor having a smaller resistance value than the first resistor, a capacitor, a diode, and a Schmitt trigger buffer. Delay means for delaying the supplied power-on reset signal, wherein the first resistor and the capacitor are charged via the first resistor. The time required for the voltage between the terminals of the capacitor to rise to the threshold voltage of the Schmitt trigger buffer and the initialization processing time of the main control means is the maximum initialization time of the plurality of sub-control means. A terminal of the capacitor having a resistance value and a capacitance equal to a predetermined time exceeding a processing time, wherein the second resistor is discharged through a circuit in which the diode and the second resistor are connected in series. A gaming machine comprising: delay means having a resistance value such that a time required for an inter-voltage to fall to a threshold voltage of the Schmitt trigger buffer becomes equal to a predetermined time shorter than the holding time. 2. A main control means, a plurality of sub-control means for performing a predetermined control according to a control command from the main control means, and an active to inactive state after a predetermined time has elapsed since the power was turned on. Supply means for supplying to the main control means and the plurality of sub-control means a power-on reset signal which becomes inactive after holding an active state for a predetermined holding time shorter than the time after the instantaneous interruption In the gaming machine having: the main control means comprises: a clock generation means for generating a clock; and a delay means for delaying a power-on reset signal supplied by the supply means, wherein Reset to activate the output, while resetting by the inactive power-on reset signal. A counter that releases the clock and makes the output inactive, and resets the clock generated by the clock generation means and the maximum initialization of the plurality of sub-control means when the reset is released. A gaming machine comprising: a delay unit having a counter for inactivating the output when a predetermined number is counted from a processing time.