JP2002359558A - Digital-to-analog conversion circuit - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To output a desired analog voltage with high accuracy monotonicity even when the number of conversion bits is large, and to realize a digital analog (D) which can be realized with a small chip area when integrated.
A) Provide a conversion circuit. SOLUTION: Upper bits D5 to D5 of a digital input code are provided.
2 for alternately adding 1 to D2 for DA conversion
And two R-2R DA converters 210 and 220.
And an upper DA conversion circuit for outputting the second DA conversion voltages Va and Vb to a first output node 1001 and a second output node 1002 via two buffers 240 and 250 having the same characteristics, respectively. And the lower-order bits D1 and D0 of the digital input code using the voltage of both output nodes as the reference voltage of the resistor string type DA converter.
L of the upper input bit for the selection of the resistance divided voltage according to
Lower DA conversion circuit unit 2 for outputting to analog voltage output terminal unit 300 while switching the selection order based on SB value D2
000.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog (DA) converter formed on a semiconductor integrated circuit, and more particularly to an R-2R ladder resistor type DA converter and a resistor string type DA converter. Composite DA with
It relates to a conversion circuit.

[0002]

2. Description of the Related Art Generally, a DA conversion circuit is used to convert a digital input code into an analog quantity. The integrated DA conversion circuit mainly includes a resistor string type,
There is an R-2R ladder resistance type. It is difficult to use the R-2R ladder resistance DA conversion circuit from the viewpoint of monotonicity and pattern area when the number of bits n of the digital input code is large. On the other hand, the resistor string type DA conversion circuit is excellent in monotonicity, but it is difficult to use the DA conversion circuit from the viewpoint of the pattern area and the conversion accuracy when the number of bits n of the digital input code is large.

[0003]

For example, when applied to a tester for inspecting another semiconductor device, a DA converter is required to have a plurality of DA converters, not to mention high conversion accuracy. Accordingly, there is a strong demand for minimizing the pattern area necessary for one DA conversion circuit, and more recently for DA conversion of a multi-bit configuration having a large number of conversion bits. Any method is effective as a D / A conversion circuit with a small number of conversion bits, but when a D / A conversion circuit with a large number of conversion bits is configured, it is difficult to achieve high-precision conversion and the pattern area increases. Become.

As described above, there is a problem that it is difficult to use the conventional R-2R ladder resistance type or resistance string type DA conversion circuit when the number of conversion bits is large.

An object of the present invention is to provide a DA conversion circuit which can output a desired analog voltage with high accuracy without requiring device accuracy even when the number of conversion bits is large, and which can be integrated with a small pattern area. It is in.

[0006]

According to the digital-to-analog conversion circuit of the present invention, a high-order i (i <n) bit signal of an n-bit digital input code is input and 1 is added alternately. And two R-2R DA converters for performing D / A conversion, and a first D / A conversion voltage and a second D / D converter.
An upper DA conversion circuit for outputting the A-converted voltage to the first output node and the second output node via two buffers each having the same characteristic, and the voltages of these two output nodes The reference voltage of the resistor string type DA conversion circuit is used as a reference voltage for the resistance division voltage selection in accordance with the remaining lower j bits (j <n, j = ni) of the n-bit digital input code. And a lower DA conversion circuit section for outputting to the analog voltage output terminal section while switching the selection order according to the LSB value.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an external connection of a composite digital-to-analog (DA) conversion circuit according to an embodiment of the present invention. Composite DA conversion circuit (DAC) 3 shown in FIG.
000 is for converting an n-bit (n = 6 in this example) digital input code from DA to DA to generate an analog output voltage VOUT. 100 is a digital input terminal, 300
Is an analog voltage output terminal, VRT is a reference voltage on the high voltage side, and VRB is a reference voltage on the low voltage side. Of the input bit signals D5, D4, D3, D2, D1, D0, D5 to D
2 are received by the upper bit input terminal unit 101, and D2 to D0 are received by the lower bit input terminal unit 102, respectively. In the following description, the reference voltages VRT and VRB are assumed to be VDD (= 5V) and VSS (= 0V), respectively.

FIG. 2 is a block diagram of the composite DA converter 300 shown in FIG.
0 shows the basic configuration. DA conversion circuit 3 shown in FIG.
000 includes an upper D / A conversion circuit unit 1000 and a lower D / A conversion circuit unit 2000.

The high-order DA conversion circuit section 1000 outputs the high-order i (1 ≦ i <n, in this example, i =
4) When a bit is input and DA-converted, a first DA-converted voltage is output to a first output node 1001 and at the same time, a second DA-converted voltage is output to a second output node 1002, The first reference voltage VDD and the second reference voltage
First and second R-2R DA converters 210 and 220 for performing D / A conversion by 4 bits with respect to reference voltage VSS.
And the output voltage Va of the first R-2R DA converter 210
To the first output node 1001 and the second buffer for outputting the output voltage Vb of the second R-2R DA converter 220 to the second output node 1002. 250 and the upper bit input terminal 1
And an adder 230 for adding 1 to the digital value input to 01. D5a, D4a, D3a, D
2a is a higher-order input bit signal modified by the addition circuit unit 230. The lower DA conversion circuit unit 2000
And using the output voltages of the second buffers 240 and 250 as reference voltages for the remaining j (j = ni, j = 2 in this example) bits of the n bits of the digital input code.
First and second buffers 240,2 to perform the conversion.
Four resistors r0 to divide between 50 output voltages
r3, a decoder 280 for generating decode signals (MOS switch control signals) NS0 to NS4 according to a digital value input to the lower bit input terminal unit 102, and a generated MOS switch control MOS switches S0 are provided by signals NS0 to NS4.
Switch section 270 in which one of S4 to S4 is turned on
And a third buffer 290 for outputting the output of the MOS switch unit 270 to the analog voltage output terminal unit 300.

FIG. 3 shows a detailed configuration of the adder 230, and FIG. 4 shows a truth table thereof. Addition circuit 2
Numeral 30 is composed of EX-OR gates 1, 2, 7, and 8, an OR gate 3, and AND gates 4, 5, and 6. Two bits D2 and D3 on the LSB side of the upper input bit signal
Are input to the first EX-OR gate 1 and the first AND gate 4, respectively, and the output of the first AND gate 4 and the intermediate bit D4 of the upper input bit signal are respectively applied to the second EX-OR gate 2 And the second AND gate 5, and the output of the second AND gate 5 and D5 which is the MSB of the higher-order input bit signal are input to the OR gate 3, and D5
And the output of the second AND gate 5 are input to the third AND gate 6, and the output of the third AND gate 6 and the first E
The output of the X-OR gate 1 and the third EX-OR gate 7
And the output of the third AND gate 6 and the second EX
The output of the OR gate 2 is input to the fourth EX-OR gate 8, the output D2a of the third AND gate 6 is used as an all 1 detection signal (ALL1), and the third and fourth EX-Os are output.
The outputs D3a and D4a of the R gates 7 and 8 are transmitted as intermediate bit signals, and the output D5a of the OR gate 3 is transmitted as MSB.

FIG. 5 shows a first R-2R type DA converter 210.
FIG. 6 shows a detailed configuration of the second R-2R DA converter 22.
0 shows the detailed configuration. The first R-2R DA converter 210 includes a first R-2R unit 201 and a first bit switch unit 216, and the second R-2R DA converter 220 includes a second R-R DA converter 220. 2R unit 202 and a second bit switch unit 226, and the first and second R units
The -2R units 201 and 202 have the same circuit configuration.

As shown in FIG. 6, the second bit switch section 226 is a MOS switch 2 for 5 bits from the MSB.
MSB with 21, 222, 223, 224, 225
The three MOS switches 221, 222, and 223 on the side switch the reference voltages VDD and VSS according to the input bit signals D 5, D 4, and D 3, respectively (for example, when the input bit signal is 1, VDD is set, and when the input bit signal is 0, VSS is set). 2 R-2R part 20
2 on the 2R side terminal and the LSB side MOS switch 2
24 is always VD connected to the 2R side terminal of the second R-2R unit 202.
D, and another MOS switch 225 on the LSB side.
Supplies VSS to the 2R side terminal of the second R-2R unit 202 at all times.

On the other hand, as shown in FIG. 5, the first bit switch section 216 includes MOS switches 211, 212, 213, 214, and 215 for 5 bits from the MSB.
Three MOS switches 211, 212, 21 on the MSB side
Reference numeral 3 denotes D5a and D5a obtained by adding D2 to the digital values of the input bit signals D5, D4 and D3 by the adding circuit unit 230.
4a and D3a to switch the reference voltages VDD and VSS (for example, when the input bit signal is 1, VDD is applied, and when the input bit signal is 0, VSS is applied).
) To the 2R side terminal of the first R-2R unit 201, and
The remaining two MOS switches 214 and 215 on the SB side are connected to the 2Rs of the first R-2R unit 201 in response to an all 1 detection signal (ALL1) which is another output of the adding circuit unit 230.
VDD or VSS is supplied to the side terminal. That is,
If D2 is 0, [D5a, D4a, D3a] = [D
5, D4, D3], and if D2 is 1, [D5a,
D4a, D3a] = [[D5, D4, D3] +1]. Therefore, when the input codes D5, D4, D3, and D2 are all other than 1, the MOS switches 214 and 215 supply VSS to the 2R side terminal of the first R-2R unit 201. If all 1, the MOS switches 214 and 215
Supplies VDD to the 2R side terminal of the first R-2R unit 201, and the MOS switches 211, 212, and 213 also
VDD is supplied to the 2R side terminal of the R-2R unit 201 of FIG.
214 and 215 are the first R-2R unit 201
Is supplied to the 2R side terminal of.

FIG. 7 shows a detailed configuration of the decoder 280, and FIG.
Indicates the respective truth tables. In FIG.
11 is an inverter unit, 12 is a NAND gate unit, 13 is a first NOR gate unit, 14 is a second NOR gate unit,
Reference numeral 15 denotes an output unit. D00, D01, D10,
D11 represents the result of decoding the two bits D1 and D0. The lower DA conversion circuit unit 2000 has input bits D1,
Although the resistance division voltage by the resistance string unit 260 between Va and Vb is selected and DA-converted by the two bits D0, the decoder 280 is also supplied with D2 which is the LSB of the higher-order input bit signal, and the MOS switch MOS of part 270
If one of the switches S0 to S4 is turned on and D2 is 0, the switches are turned on in the order of S0 → S1 → S2 → S3 according to the binary values 00, 01, 10, and 11 of D1 and D0, and if D2 is 1, For example, binary values 00, 01, 10, and 11 of D1 and D0
Are turned on in the order of S4 → S3 → S2 → S1. For example, [D2, D1, D0] = [0, 1,
1], S3 is turned on, and [D2, D1, D0] = [1,
[0,0], the decoder 280 decodes D2, D1, and D0 so that S4 is turned on.

Here, an example of the operation of the high-order DA converter 1000 will be described with reference to FIG. When the input code [D5, D4, D3, D2] = [0, 1, 1, 0] of “A” shown in the figure is DA-converted by the high-order DA conversion circuit 1000, D2 of the high-order input code A is 0. Therefore, the addition circuit unit 230
In D5, D4 and D3, 1 is not added, and [D5a, D
4a, D3a] = [D5, D4, D3], and naturally all 1 is not detected, so the first R-2R DA
The conversion unit 210 calculates [D5, D4, D3, D2] as Va.
= DA conversion voltage value of [0, 1, 1, 0]. On the other hand, since the bit switch 224 corresponding to the LSB corresponds to D2 = 1 in the second R-2R DA converter 220, [D5, D4, D3, D2] = [0, 1, 1, 1] Is output as Vb. That is, Vb
Is higher than Va by 1 LSB of the upper input bit, and Vb−Va is changed to D by the remaining lower bit input.
A conversion.

Next, the input code [D5, D4,
The operation in the case where the D3, D2] = [0, 1, 1, 1] is DA-converted by the high-order DA converter 1000 will be described. Since D2 of the high-order input code B is 1, the addition circuit 230
Then, 1 is added to D5, D4, and D3, and [D5a, D4
a, D3a] = [[D5, D4, D3] +1] = [1,
0,0], and naturally all-ones are not detected. Therefore, the first R-2R DA converter 210 sets the D [D5, D4, D3, D2] = [1,0,0,0] as Va.
An A-converted voltage value is output. On the other hand, the second R-2R type DA
The conversion unit 220 is a bit switch 224 corresponding to LSB.
Corresponds to D2 = 1, so [D5, D4, D3, D
2] = [0,1,1,1] is output as Vb. That is, Va becomes a voltage value higher than Vb by 1 LSB of the upper input bit, and Va-Vb is DA-converted by the remaining lower bit input.

Here, the voltage value Vb is determined by the upper input code A,
Same for upper input code B [D5, D4, D3, D2] =
[0,1,1,1] (= B), and similarly, the voltage value Va is the same for the upper input code B and the upper input code C [D5, D4, D3, D2] = [1, 0, 0,0] (=
C).

FIG. 10 shows the order of turning on the MOS switch unit 270 in the case of the upper input code A and FIG. In the case of the higher-order input code A in which D2 is 0, the binary values of [D1, D0] are 00, 01,
It turns on in the order of S0 → S3 in accordance with 10, 11 and, in the case of the upper input code B in which D2 is 1, turns on in the order of S4 → S1 in accordance with the binary values 00, 01, 10, and 11 of [D1, D0]. When the higher-order input code transitions from A to B by 1 LSB, Vb keeps outputting the same voltage, and only Va switches, so that the occurrence of the differential error can be avoided. Since Va continuously outputs the same voltage value and only Vb is switched, the occurrence of a differential error can be similarly avoided, and therefore, monotonicity is ensured. When the upper input code is all 1s, that is, when [D5, D4, D3, D2] = [1, 1, 1, 1], Vb is the DA conversion voltage value of this code, and Va is [1, 1, 1] [1,1] requires a voltage value corresponding to a code obtained by adding 1 to the code.
D (= VRT) and an all 1 detection signal (ALL1)
Outputs all the outputs of the first bit switch section 216 to VD
D is easily obtained. Therefore, the 6-bit input code [D5, D4, D3, D
2, D1, D0], the analog output voltage VOUT excellent in monotonicity can be continuously obtained from all 0 to all 1.

FIG. 12 is a graph showing the relationship between the Va and the upper input code.
And the state of change of Vb. As shown in FIG. 12, when the value of the least significant bit D2 is 0 as in the case of the upper input code A, Va is the low voltage reference and Vb is the high voltage reference for the lower DA conversion. . On the other hand, when the value of the least significant bit D2 is 1, as in the case of the upper input code B, Vb is the low voltage reference and Va is the high voltage reference for the lower DA conversion. That is,
For a 1/0 change of D2, ie, a change of 1 LSB, V
a or Vb is always the same voltage, but the MOS switch unit 270 using the lower input bits D1 and D0
Are switched in accordance with the value of D2 by the decoder 280, so that lower DA conversion can be performed.

In the above example, n = 6, i = 4 and j
= 2, for example, when n = 13, i = 8, j
If = 5, two 8-bit R-2R DA converters and one 5-bit resistor string DA converter can constitute a high-accuracy composite DA converter.

[0022]

As described above, in the digital-to-analog conversion circuit of the present invention, even when the number of conversion bits is large, the high-order DA conversion circuit section is constituted by two R-2R ladder resistance types, and The conversion circuit section is formed of a resistor string type to avoid an increase in the pattern area, and the lower DA reference voltage by the upper R-2R ladder resistance type DA conversion is alternately switched with respect to the LSB of the upper input code. With high accuracy and monotonicity
A conversion circuit is provided.

[Brief description of the drawings]

FIG. 1 is an external connection diagram of a composite DA conversion circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic configuration of the composite DA converter of FIG. 1;

FIG. 3 is a circuit diagram illustrating a detailed configuration of an adding circuit unit in FIG. 2;

FIG. 4 is a diagram illustrating a truth table of the addition circuit unit of FIG. 3;

FIG. 5 is a circuit diagram illustrating a detailed configuration of a first R-2R DA converter in FIG. 2;

FIG. 6 is a circuit diagram showing a detailed configuration of a second R-2R DA converter in FIG. 2;

FIG. 7 is a circuit diagram showing a detailed configuration of a decoder in FIG. 2;

FIG. 8 is a diagram illustrating a truth table of the decoder of FIG. 7;

9 is an operation explanatory diagram of an upper DA conversion circuit section in FIG. 2;

10 is an operation explanatory diagram of the MOS switch unit in FIG. 2 corresponding to the upper input code A in FIG. 9 where D2 = 0.

11 is an operation explanatory diagram of the MOS switch unit in FIG. 2 corresponding to the upper input code B in FIG. 9 where D2 = 1;

12 is a diagram illustrating a relationship between an upper-order input code in an upper-order DA converter in FIG. 2 and output voltages of first and second R-2R DA converters; FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 digital input terminal unit 101 upper bit input terminal unit 102 lower bit input terminal unit 201, 202 first and second R-2R units 210, 220 first and second R-2R type DA converter units 216, 226 1st and 2nd bit switch part 230 Addition circuit part 240, 250 First and second buffer 260 Resistance string part 270 MOS switch part 280 Decoder 290 Third buffer 300 Analog voltage output terminal part 1000 Upper DA conversion circuit part 1001 , 1002 First and second output nodes 2000 Lower DA converter circuit 3000 Composite DA converter circuit A, B, C Upper input code ALL1 All 1 detection signal (D5 to D2) D5 to D0 Input bit signal D5a to D2a Modified upper input bit signal NS0-NS4 MOS switch Switch control signal (decode signal: negative logic) Va Output voltage of the first R-2R DA converter Vb Output voltage of the second R-2R DA converter VDD (VRT) First reference voltage VSS ( VRB) Second reference voltage VOUT Analog output voltage

Claims (5)

[Claims] 1. A digital-to-analog conversion circuit comprising an upper D / A conversion circuit section and a lower D / A conversion circuit section for converting an n-bit digital input code from digital to analog (DA) to generate an analog output voltage. The upper DA conversion circuit unit receives the upper i (1 ≦ i <n) bits of the digital input code, performs DA conversion on the input, and outputs a first DA conversion voltage to a first output node. And a second D / A conversion for i-bit conversion between the first reference voltage and the second reference voltage applied so as to output the second D / A conversion voltage to the second output node at the same time. 1st and 2nd R-2
An R-type DA converter; and an output voltage of the first R-2R-type DA converter.
A first buffer for outputting to an output node of the second R-2R type DA converter;
A second buffer for outputting to the output node, and an addition circuit for adding 1 to a digital value input to the upper bit input terminal unit, wherein the lower DA conversion circuit unit comprises: And the remaining j (j) of the n bits of the digital input code using the output voltage of the second buffer as a reference voltage, respectively.
= N−i) a resistor string portion for dividing the output voltage of the first and second buffers so as to perform DA conversion on the bits, and a digital value input to the lower bit input terminal portion A decoder for generating a decode signal in accordance with the following: a MOS switch unit for selecting one of the MOS switches to be turned on by the decode signal; and a MOS switch unit for outputting an output of the MOS switch unit to an analog voltage output terminal unit. 3. A digital-to-analog conversion circuit, comprising: 2. The digital-to-analog conversion circuit according to claim 1, wherein the first R-2R type DA conversion unit comprises a first R-2R unit and a first bit switch unit. R of 2
The -2R type DA converter comprises a second R-2R unit and a second bit switch unit, and the first and second R-
A digital / analog conversion circuit wherein the 2R units have the same circuit configuration. 3. The digital-to-analog conversion circuit according to claim 2, wherein said second bit switch section is a most significant bit (MSB).
And a MOS switch for i + 1 bits from the
A part of the S switch on the MSB side switches the reference voltage according to the input bit signal and supplies the reference voltage to the 2R side terminal of the second R-2R unit, and the other MOS switch on the least significant bit (LSB) side The first fixed potential is always supplied to the 2R side terminal of the second R-2R section, and the other MO on the LSB side is
The S switch is connected to the 2R side terminal of the second R-2R section by the second switch.
, And the first bit switch section includes a MOS switch for i + 1 bits from the MSB.
The part on the B side switches the reference voltage by a code obtained by adding the LSB of the higher-order input code to the digital value of the input bit signal in the adder circuit, and switches the reference voltage by the code of the first R-2R.
The two MOS switches on the LSB side are supplied to the R side terminal, and the remaining two MOS switches on the LSB side are all 1
The second fixed potential is simultaneously supplied to the 2R-side terminal of the first R-2R unit when the upper input code is not all 1 by the detection signal. The first terminal is connected to the 2R terminal of the R-2R section.
A digital-to-analog conversion circuit characterized by supplying a fixed potential of 4. The digital-to-analog conversion circuit according to claim 2, wherein said addition circuit section includes an EX-OR gate, an AND gate, and an O-gate.
And an R gate, and the two LSB sides of the upper input bit signal are the first
, And an output of the first AND gate and an intermediate bit of the higher-order input bit signal are input to a second EX-OR gate and a second AND gate, respectively. The output of the second AND gate and the MSB of the upper input bit signal are input to the first OR gate, and the MSB of the input bit signal and the output of the second AND gate are output to the third OR gate. An AND gate, and an output of the third AND gate and the first EX-OR
The output of the gate is input to a third EX-OR gate, and the output of the third AND gate and the second EX-OR
The output of the gate is input to a fourth EX-OR gate, the output of the third AND gate is an all-one detection signal, the output of the third and fourth EX-OR gates is an intermediate bit signal, MSB output from the first OR gate
A digital-to-analog conversion circuit, wherein the digital-to-analog conversion circuit transmits the data to the first bit switch unit. 5. The digital-to-analog conversion circuit according to claim 1, wherein a switch selection signal of said MOS switch section is decoded in 2j + 1 ways and according to an LSB value of an upper input bit. A digital-to-analog conversion circuit, wherein the switch selection order of the MOS switch unit is switched.