JP2002359342A - Intermediate substrate for multi-chip module - Google Patents

Abstract

(57) [Problem] To provide an intermediate substrate for a multi-chip module that enables an electronic device having excellent long-term reliability, high integration, small size and light weight, and the like. The pitch is in the range of 10 to 30 μm.
A wiring having a two-layer structure or a two-layer structure is formed on one surface of the base via an electrical insulating layer, and the base has a coefficient of thermal expansion of 10
By setting it to be less than ppm, an intermediate substrate for a face-down type multi-chip module on which a plurality of semiconductor chips are mounted is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an intermediate substrate for a multi-chip module on which a plurality of semiconductor chips are mounted, and more particularly to an intermediate substrate for use in a face-down type multi-chip module.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become higher in performance, higher in speed, smaller in size, and lighter in weight, it has become an important point how to increase the component mounting density. For a semiconductor device chip, which is one of these components, there is a package substrate in which an organic substrate is used and solder bumps are arranged in an area array type, in addition to a conventional package using a bonding wire and a lead frame.

The most frequently used package substrates are organic substrates made of a resin material such as glass fiber reinforced epoxy resin and polyimide resin. These organic substrates are inexpensive and relatively resistant to impact. , Is widely used in consumer devices. A conductive film pattern typified by a copper (Cu) film is formed on the organic substrate by printing or etching, and the connection terminals of semiconductor devices, chips and other components are formed at the ends of the conductive film pattern. It is mounted while being aligned with the connection pad portion.

On the other hand, a bare chip mounting method has been proposed in which a chip (bare chip) having no package is directly connected to a conductive film pattern on a mounting substrate. In the bare chip mounting method, bonding wires, bumps made of solder or metal spheres, anisotropic conductive films, conductive adhesives, light-shrinkable resins are formed on connection pad portions of a conductive film pattern formed on a mounting substrate in advance. The semiconductor device chip is mounted using connection means such as. Because the chip is not encapsulated in the package, the connection path between the chip and the conductive film pattern on the mounting board can be simplified and shortened, and the distance between the chip and other chips can be improved because the mounting density can be improved. Can also be shortened. Therefore, not only a reduction in size and weight but also an increase in the speed of signal processing can be expected.

In recent years, in a mounting structure, in order to transmit signals at a higher speed, a semiconductor device chip such as an LSI is mounted as a bare chip on an intermediate substrate including a wiring layer, and the intermediate substrate is mounted on a printed circuit board. A so-called multi-chip module to be joined has been proposed. Furthermore, in order to realize various functions in one module,
A system-in-package in which different types of semiconductors and electronic components are contained in one package has been proposed. As an intermediate substrate for such a multichip module, a ceramic substrate and an organic substrate have been conventionally proposed.

[0006]

However, in the method using an intermediate substrate made of a ceramic substrate, when the green sheet is fired, obstacles such as shrinkage, warpage, and cracks are generated, so that the conductor layer has an open defect. In order to prevent such a phenomenon, it is necessary to form a pattern under complicated firing conditions, which requires various steps and a long time for the manufacturing process.

On the other hand, in the case of a build-up substrate using an organic substrate, through-holes are required to be formed, conduction of the interior is required, and a hole filling process is required. Is difficult to form, resulting in an increase in the number of layers.

Further, when the pads of the semiconductor chip are miniaturized, there is a problem that the mounting stress is increased due to a mismatch in the coefficient of thermal expansion between the semiconductor chip and the organic substrate. For example, when the semiconductor device chip mounted on the bare chip is a silicon-based device chip, the thermal expansion coefficient of silicon is about 3 ppm, but the thermal expansion coefficient of the organic substrate is as large as about 10 to 15 ppm.
When a silicon-based semiconductor device chip is mounted on such an organic substrate, a tensile stress or a compressive stress occurs at the joint of the two members each time a large temperature change in the operating environment occurs due to a large mismatch between the two. Stress will work. As a result, fatigue accumulates at the joints, resulting in a loss of long-term reliability of the electronic device. The present invention has been made in view of the above circumstances, and provides an intermediate substrate for a multi-chip module that enables an electronic device having excellent long-term reliability, high integration, small size, and light weight. Aim.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an intermediate substrate for a face-down type multi-chip module on which a plurality of semiconductor chips are mounted. A wiring formed on one surface with an electrical insulating layer interposed therebetween, wherein the base has a coefficient of thermal expansion of 1
0 ppm or less, and the wiring has a pitch of 10 to 30 μm.
The configuration was such that the wiring had a one-layer structure or a two-layer structure in the range of m. In a preferred embodiment of the present invention,
A structure that covers a part of the wiring on the electric insulating layer, and includes an electric insulating pattern having a through hole for conducting with the wiring, the base and the electric insulating layer The configuration was such that a ground layer was provided between them.

In a preferred aspect of the present invention, a structure in which an adhesive layer is provided between the base and the electrical insulating layer, and a ground layer is provided between the adhesive layer and the electrical insulating layer. The configuration was adopted. In a preferred aspect of the present invention, the base has a desired circuit on the electric insulating layer side, and a desired portion of the wiring and the circuit are provided through a through hole provided in the electric insulating layer. A configuration in which conduction is provided, and a configuration in which a ground layer is provided in the electric insulating layer. Further, as a preferred embodiment of the present invention,
The base was made of silicon.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an embodiment of an intermediate substrate for a multichip module according to the present invention, and FIG. 2 is a longitudinal sectional view taken along line AA of the intermediate substrate shown in FIG. 1 and 2, an intermediate substrate 1 according to the present invention includes a base 2, an electric insulating layer 3 formed on one surface of the base 2, and a wiring 4 formed on the electric insulating layer 3. And

The base 2 forming the intermediate substrate 1 is made of a material having a coefficient of thermal expansion of 10 ppm or less, preferably in the range of 1 to 8 ppm. Examples of such a material having a low coefficient of thermal expansion include silicon, glass fiber reinforced epoxy resin, ceramics, glass, and metal.
In particular, it is preferable to use the same type of silicon for the base 2 as a semiconductor device chip such as an LSI. When the base 2 is made of silicon, the matching of the thermal expansion coefficient between the intermediate substrate 1 and the semiconductor device chip becomes higher, and even when a silicon-based semiconductor device chip having fine pads is mounted, The generation of stress at the joint due to a large temperature change in the use environment can be prevented, the accumulation of fatigue at the joint is reduced, and the long-term reliability is high. Further, since silicon has high thermal conductivity, the intermediate substrate of the present invention has excellent heat dissipation. The thickness of the base 2 made of such a material can be appropriately set, for example, in the range of 50 to 800 μm.

The electric insulating layer 3 constituting the intermediate substrate 1 can be formed using an inorganic insulating material such as silicon dioxide, alumina, aluminum nitride or the like, or an organic insulating material such as polyimide, benzocyclobutene or epoxy resin. it can.
In addition, the thickness of the electric insulating layer 3 can be appropriately set in the range of 0.1 to 10 μm when using the above-mentioned inorganic insulating material, and in the range of 1 to 20 μm when using the above-mentioned organic insulating material. .

The wiring 4 forming the intermediate substrate 1 includes chip-side pads 4a for mounting semiconductor devices and chips.
And a ball-side pad 4b for bonding to a terminal on a printed circuit board via a solder ball, and a lead-out lead 4c for connecting each chip-side pad 4a and the ball-side pad 4b. In the illustrated example, 32 chip-side pads 4a are formed in the center of the intermediate substrate 1 and 32 ball-side pads 4b are formed in the vicinity of the peripheral portion of the intermediate substrate in order to simplify the description and avoid complexity. There is
The wiring constituting the intermediate substrate of the present invention is not limited to the illustrated example, and the number of pads, pad arrangement, lead pattern shape, and the like can be appropriately set.

In the wiring 4 as described above, the smaller the pitch, the higher the density of the wiring, but the wiring width is 5 μm.
If the width is less than 5 μm, the electric resistance increases.
m or more, and therefore, the lower limit of the pitch of the wiring 4 is preferably 10 μm. In addition, the upper limit of the pitch of the wiring 4 is preferably 30 μm in consideration of higher density. Here, the pitch of the wiring in the present invention is:
It means the center distance between adjacent pads, the center distance between adjacent pads and leads, or the center distance between adjacent leads in a portion where wiring needs to be routed in the closest way for high density. For example, in the example shown in FIG. 1, the center distance between the chip-side pad 4a and the lead-out lead 4c in a portion where the lead-out lead 4c passes between the chip-side pads 4a, and the eight lead-out leads 4c are arranged in parallel. It means the center distance between adjacent lead leads 4c in the region. Therefore, in a portion where there is room for routing the wiring, the wiring pitch is 3
It may exceed 0 μm.

As described above, the pitch of the wiring 4 is set to 10 to 30.
When the thickness is in the range of μm, fine wiring can be achieved only by forming the wiring in a one-layer structure or a two-layer structure, and the conventional multilayer wiring becomes unnecessary, and the number of laminating steps can be greatly reduced. For example, when mounting a 481-pin semiconductor chip of 10 mm square, by forming wiring of a two-layer structure,
The outer dimensions of the intermediate substrate are approximately 20 mm square, and the size can be reduced. Such a wiring 4 can be formed using a conventional conductive material such as copper, silver, and gold.

In the intermediate substrate 1 as described above, the base 2 and the electric insulating layer are used to stabilize the functions of the semiconductor device chip to be mounted (reduce inductance, reduce crosstalk noise, control characteristic impedance, etc.). 3, a ground layer may be interposed. The ground layer can be formed using a conventionally known conductive material. When the ground layer is provided in this manner, for example, a through hole is formed in the electric insulating layer 3 or wire bonding is performed.
The ground layer and a predetermined pad of the wiring 4 can be connected.

FIG. 3 shows an intermediate substrate 1 according to the present invention as described above.
FIG. 3 is a diagram showing an aspect in which a semiconductor chip is mounted on the semiconductor device. In FIG. 3, the semiconductor chip 51 is mounted with its terminal portion 52 directly bonded to the chip-side pad 4 a of the wiring 4 of the intermediate substrate 1. On the other hand, solder balls 61 are formed on the ball-side pads 4b of the wiring 4 of the intermediate substrate 1. The intermediate substrate 1 of the present invention has a base 2 having a thermal expansion coefficient of 10
ppm or less, even if the semiconductor chip 51 is a silicon-based semiconductor chip having a small coefficient of thermal expansion, the mounting stress can be reduced, the fatigue accumulation at the junction is reduced, and the long-term reliability is high. . The intermediate board 1 on which the semiconductor chip 51 is mounted as described above can be joined to the printed board via the solder balls 61 such that the semiconductor chip 51 side is the printed board side (face-down type).

FIG. 4 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the intermediate substrate for a multichip module of the present invention. In FIG. 4, an intermediate substrate 11 of the present invention includes a base 12, an electric insulating layer 13 formed on one surface of the base 12, and a wiring 14 formed on the electric insulating layer 13.
And an electrical insulating pattern 15 formed so as to cover a part of the wiring 14. The base 12 and the electric insulating layer 13 constituting the intermediate substrate 11 can be the same as the base 2 and the electric insulating layer 3 constituting the above-described intermediate substrate 1, and the description thereof is omitted.

The wiring 14 forming the intermediate substrate 11
This is basically the same as the wiring 4 forming the intermediate substrate 1 described above. That is, the wiring 14 includes a chip-side pad 14a for mounting a semiconductor device chip or the like, a ball-side pad 14b for bonding to a terminal on a printed board via a solder ball, and an individual chip-side pad. 1
4a and lead-out leads 14c for connecting the ball-side pads 14b. The pitch of such wiring 14 is preferably in the range of 10 to 30 μm, and the wiring width is 5 μm.
μm or more is preferred.

The electrical insulating pattern 15 constituting the intermediate substrate 11 is formed in a corridor shape near the peripheral portion of the electrical insulating layer 13 so as to cover the ball-side pads 14b. The electric insulating pattern 15 is provided with a through-hole 16, and a surface 1 of the electric insulating pattern 15 is provided through a conductive layer 17 formed in the through-hole 16.
The 5a side is electrically connected to the ball side pad 14b. The above-mentioned electric insulation pattern 15 can be formed of a material such as polyimide, benzocyclobutene, or epoxy resin. The thickness of the electrically insulating pattern 15 can be appropriately set in the range of 1 to 20 μm.

When a semiconductor chip is mounted on the intermediate substrate 11 of the present invention as described above and mounted on a printed circuit board, the terminal portion of the semiconductor chip is directly joined to the chip-side pad 14a of the wiring 14 of the intermediate substrate 11. And mount the semiconductor chip. Further, a solder ball is formed on the conductive layer 17 located on the surface 15a side of the electrical insulating pattern 15 of the intermediate substrate 11. In the intermediate substrate 11 of the present invention, since the thermal expansion coefficient of the base 12 is 10 ppm or less, the mounting stress can be reduced even if the semiconductor chip is a silicon-based semiconductor chip having a small thermal expansion coefficient. And the long-term reliability is high.

Incidentally, even in such an intermediate substrate 11,
As with the intermediate substrate 1 described above,
In order to stabilize the function of the chip, the base 12 and the electric insulating layer 1
3, a ground layer may be interposed. The ground layer can be formed using a conventionally known conductive material. When the ground layer is provided in this manner, for example, a through hole is formed in the electric insulating layer 13 or a predetermined pad of the wiring 14 can be connected by wire bonding or the like.

The intermediate substrate 11 on which the semiconductor chip is mounted as described above is arranged such that the semiconductor chip side is the printed board side (face-down type), and the solder balls (wiring 1
4 which is electrically connected to the ball-side pad 14b). Here, the printed circuit board generally has a large coefficient of thermal expansion of about 10 to 15 ppm, and when a large temperature change occurs in the use environment, the printed circuit board expands and contracts. On the other hand, since the intermediate substrate 11 of the present invention includes the base 12 having a small coefficient of thermal expansion as described above, even if a large temperature change occurs in the use environment,
Maintain stable geometry. For this reason, a tensile stress or a compressive stress acts on the joint between the printed circuit board and the intermediate substrate 11 of the present invention. However, the intermediate substrate 11 of the present invention absorbs the above-mentioned stress by the electric insulating pattern 15, so Prevents fatigue accumulation.

FIG. 5 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the intermediate substrate for a multichip module of the present invention. In FIG. 5, an intermediate substrate 21 of the present invention is formed on a base 22, an electric insulating layer 23 formed on one surface of the base 22 via an adhesive layer 25, and formed on the electric insulating layer 23. Wiring 24. The base 22 and the electrical insulating layer 23 that constitute the intermediate substrate 21 are
Can be made the same as the base 2 and the electric insulating layer 3, and the description is omitted here.

The adhesive layer 25 constituting the intermediate substrate 21 is for bonding the base 22 and the electric insulating layer 23, and is formed by using a known adhesive such as thermoplastic polyimide or epoxy prepreg. Can be. This adhesive layer 2
The thickness of 5 can be appropriately set in the range of 1 to 20 μm.

The wiring 24 forming the intermediate substrate 21 is basically the same as the wiring 4 forming the intermediate substrate 1 described above.
That is, the wiring 24 includes a chip-side pad 24a for mounting a semiconductor device chip or the like, a ball-side pad 24b for joining a terminal on a printed board via a solder ball, and an individual chip-side pad. It comprises a lead 24c for connecting the ball 24a to the ball-side pad 24b. The pitch of such wirings 24 is preferably in the range of 10 to 30 μm, and the wiring width is preferably 5 μm or more.

Incidentally, even in such an intermediate substrate 21,
As with the intermediate substrate 1 described above,
A ground layer may be interposed between the adhesive layer 25 and the electric insulating layer 23 for stabilizing the function of the chip (reducing inductance, reducing crosstalk noise, controlling characteristic impedance, and the like). The ground layer can be formed using a conventionally known conductive material. When the ground layer is provided in this manner, for example, a through hole is formed in the electric insulating layer 23, or the ground layer and a predetermined pad of the wiring 24 can be connected by wire bonding or the like.

When a semiconductor chip is mounted on the intermediate substrate 21 of the present invention as described above and mounted on a printed circuit board, the terminal portion of the semiconductor chip is directly joined to the chip-side pad 24a of the wiring 24 of the intermediate substrate 21. And mount the semiconductor chip. Further, a solder ball is formed on the ball-side pad 24b of the wiring 24 of the intermediate substrate 21. In the intermediate substrate 21 of the present invention, since the thermal expansion coefficient of the base 22 is 10 ppm or less, even if the semiconductor chip is a silicon-based semiconductor chip having a small thermal expansion coefficient, the mounting stress can be reduced, Fatigue accumulation is reduced and long-term reliability is improved.

The intermediate board 21 on which the semiconductor chip is mounted as described above can be joined to the printed board via solder balls, with the semiconductor chip side facing the printed board (face-down type). Note that the wiring 2 is also provided on the intermediate substrate 21 similarly to the above-described intermediate substrate 11.
An electric insulating pattern may be provided so as to cover a part of the fourth.

FIG. 6 is a longitudinal sectional view corresponding to FIG. 2 showing another embodiment of the intermediate substrate for a multichip module of the present invention. In FIG. 6, an intermediate substrate 31 of the present invention includes a base 32, an electric insulating layer 33 formed on one surface of the base 32, and a wiring 34 formed on the electric insulating layer 33.
And The base 32 constituting the intermediate substrate 31 is
Similar to the base 2 constituting the above-mentioned intermediate substrate 1, the base 2 is made of a material having a thermal expansion coefficient of 10 ppm or less, preferably in a range of 1 to 8 ppm. The base 32 has a surface 32a.
A desired circuit 36 such as a semiconductor or an electronic component is provided on the side, and each circuit 36 is connected by a wiring (not shown) formed on the surface 32 a of the base 32. Through a through hole 37 formed in the layer 33,
It is connected to a predetermined pad of the wiring 34.

Electric insulating layer 33 constituting intermediate substrate 31
Is basically the same as the above-described electrical insulating layer 3 constituting the intermediate substrate 1, has a through hole 37 near the peripheral portion thereof, and a conductive layer (see FIG. A predetermined circuit 36 is connected to the wiring 34 via a not shown).
Are connected to predetermined pads.

The wiring 34 forming the intermediate substrate 31 is basically the same as the wiring 4 forming the intermediate substrate 1 described above.
That is, the wiring 34 includes a chip-side pad 34a for mounting a semiconductor device chip or the like, a ball-side pad 34b for bonding to a terminal on a printed board via a solder ball, and an individual chip-side pad. It comprises a lead 34c for connecting the ball-side pad 34b to the ball-side pad 34b. The pitch of such wirings 34 is preferably in the range of 10 to 30 μm, and the wiring width is preferably 5 μm or more.

Incidentally, even in such an intermediate substrate 31,
As with the intermediate substrate 1 described above,
A ground layer may be formed in the electric insulating layer 33 for stabilizing the function of the chip. The ground layer can be formed using a conventionally known conductive material. When the ground layer is provided in this manner, for example, a through hole is formed in the electrical insulating layer 33 to connect the ground layer to a predetermined pad of the wiring 34 or to connect the ground layer to a predetermined circuit 36. Can be.

When a semiconductor chip is mounted on the intermediate substrate 31 of the present invention as described above and mounted on a printed circuit board, the terminal portion of the semiconductor chip is directly joined to the chip-side pad 34a of the wiring 34 of the intermediate substrate 31. And mount the semiconductor chip. Further, a solder ball is formed on the ball-side pad 34b of the wiring 34 of the intermediate substrate 31. In the intermediate substrate 31 of the present invention, since the thermal expansion coefficient of the base 32 is 10 ppm or less, even if the semiconductor chip is a silicon-based semiconductor chip having a small thermal expansion coefficient, mounting stress can be reduced, and This reduces fatigue accumulation and increases long-term reliability.

The intermediate board 31 on which the semiconductor chip is mounted as described above can be joined to the printed board via solder balls, with the semiconductor chip side facing the printed board (face-down type). Note that the wiring 3 is also provided on the intermediate substrate 31 similarly to the above-described intermediate substrate 11.
An electric insulating pattern may be provided so as to cover a part of the fourth.

Next, a method of manufacturing an intermediate substrate according to the present invention will be described. FIG. 7 is a process chart showing an example of a method for manufacturing the intermediate substrate of the present invention shown in FIGS. In FIG. 7, first, the silicon base 2 is cleaned,
Is formed on one surface of the substrate. The electric insulating layer 3 is formed by using an inorganic insulating material such as silicon dioxide, alumina, or aluminum nitride, polyimide, benzocyclobutene,
Using an organic insulating material such as an epoxy resin, a thin film forming method such as a sputtering method, a coating method, or the like can be used. Next, a conductive thin film 4 'is formed on the electric insulating layer 3 (FIG. 7A). This conductive thin film 4 'is made of copper,
It can be formed by a known thin film forming method such as a sputtering method using silver, gold, or the like.

Next, a photosensitive resist is applied on the conductive thin film 4 ', and is exposed and developed through a desired wiring pattern mask to form a resist pattern 7 (FIG. 7B). Next, using the resist pattern 7 as a mask, a conductive pattern 4 ″ is formed on the conductive thin film 4 ′ by plating, and the resist pattern 7 is removed (FIG. 7C).

Thereafter, the conductive thin film 4 'is removed by etching using the conductive pattern 4 "as a mask.
The wiring 4 composed of a laminate of the conductive pattern 4 ″ and the conductive thin film 4 ′ located thereunder is formed, and the intermediate substrate 1 of the present invention is obtained (FIG. 7D).

Further, the intermediate substrate 11 of the present invention as shown in FIG.
The wiring 14 is formed on the substrate 2 via the electric insulating layer 13. Thereafter, a photosensitive electrical insulating material is applied so as to cover the wirings 14, exposed and developed through a predetermined mask, and a corridor-shaped electrical insulating pattern 15 is formed. Then, a through-hole 16 is formed by laser, and a conductive layer 17 is formed in the through-hole and on the surface 15a of the electrically insulating pattern by a sputtering method. Further, the through holes 16 can be formed simultaneously in the photolithography step.

FIG. 8 is a process chart showing an example of a method for manufacturing the intermediate substrate of the present invention shown in FIG. 8, first, an electric insulating film 23 made of an inorganic insulating material such as silicon dioxide, alumina, and aluminum nitride, and an organic insulating material such as polyimide, benzocyclobutene, and epoxy resin is formed. Then, a conductive thin film 24 'is formed (FIG. 8A). Conductive thin film 24 '
Can be formed by a known thin film forming method such as a sputtering method using copper, silver, gold or the like.

Next, a photosensitive resist is applied on the conductive thin film 24 'and exposed through a desired wiring pattern mask.
By developing, a resist pattern 27 is formed (FIG. 8B). Next, the above resist pattern 27
Is used as a mask to form a conductive pattern 24 ″ on the conductive thin film 24 ′ by a plating method.
Is removed (FIG. 8C).

Thereafter, the conductive thin film 24 'is removed by etching using the conductive pattern 24 "as a mask, thereby forming a wiring composed of a laminate of the conductive pattern 24" and the conductive thin film 24' located thereunder. 24 are formed (FIG. 8D). Next, the electrical insulating film 23 on which the wiring 24 is formed as described above is bonded to the silicon base 22 via the bonding layer 25. Thus, the intermediate substrate 21 of the present invention is obtained (FIG. 8E).

The intermediate substrate 31 of the present invention as shown in FIG. 6 is manufactured by first forming a base 32 on which a desired circuit 36 is formed in advance, and then forming the through hole 3 on the base 32.
7 is formed. Next, a wiring 34 can be formed on the electric insulating layer 33 to manufacture the wiring.

[0045]

Next, the present invention will be described in more detail with reference to specific examples.

Example A silicon substrate (coefficient of thermal expansion: 3.5 ppm, thickness: 500 μm) whose surface was cleaned was prepared as a base. An electric insulating layer (thickness: 1 μm) made of silicon dioxide was formed by sputtering over the entire surface of one side of the base.
m) was formed. Next, a copper thin film (having a thickness of 0.25) as a conductive thin film was formed on the electrical insulating layer by sputtering.
μm), a photosensitive resist (BCB manufactured by Dow Corning Co., Ltd.) was applied on the copper thin film, and exposed and developed through a photomask for wiring to form a resist pattern.

Thereafter, using this resist pattern as a mask, a copper plating layer (thickness: 5) is formed on the copper thin film by electrolytic plating.
μm), and the resist pattern was removed using acetone to form a conductive pattern. Next, using the conductive pattern as a mask, the conductive thin film (copper thin film) was etched using a soft etching solution to form a wiring. The wiring thus formed has a line width of 5 to 5.
The pitch was in the range of 15 μm and the pitch was in the range of 10 to 30 μm. As described above, 100 intermediate substrates of the present invention were produced.

[Comparative Example 1] A thermal expansion coefficient of 17
The same procedure as in Example 1 was repeated except that a glass fiber reinforced epoxy substrate having a thickness of 500 μm and a thickness of 500 μm was used.
00 pieces were produced.

[Comparative Example 2] A thermal expansion coefficient of 17
100 intermediate substrates were produced in the same manner as in Example 1 except that a metal (SUS) substrate having a thickness of 100 μm and a thickness of 100 ppm was used.

[Evaluation] A 300-pin, 10-mm square silicon semiconductor chip was mounted on each of the intermediate substrates produced as described above, and a heat cycle test was performed on the intermediate substrate under the following conditions. The joint was inspected for damage. As a result, no breakage was observed in all 100 intermediate substrates of the example. However, Comparative Example 1
Of 50 intermediate substrates were damaged, and Comparative Example 2
In 70 of the intermediate substrates, breakage was observed.

Heat cycle test conditions : Temperature fluctuation of one cycle: -65 ° C. to 200 ° C. Time of one cycle: 60 minutes Number of cycles: 3000 times

[0052]

As described above in detail, according to the present invention, since the wiring constituting the intermediate substrate has a one-layer structure or a two-layer structure composed of fine wirings having a pitch of 10 to 30 μm, it has a fine pad arrangement. Bonding with a semiconductor device chip is possible and the thermal expansion coefficient of the base is 10 ppm or less, so that mounting stress is reduced even when a silicon-based semiconductor device chip having a small thermal expansion coefficient is mounted, for example. As a result, a multi-chip module with excellent long-term reliability and high density and high integration can be realized. In addition, by using silicon as a base, when mounted on a printed circuit board in a face-down type, an effect of efficiently dissipating heat generated in a semiconductor device chip is exhibited. Further, since the number of laminating steps can be significantly reduced without the need for multilayer wiring, the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing an embodiment of an intermediate substrate for a multichip module of the present invention.

FIG. 2 is a vertical cross-sectional view taken along line AA of the intermediate substrate shown in FIG.

FIG. 3 is a diagram showing a mode in which a semiconductor chip is mounted on the intermediate substrate shown in FIG. 2;

FIG. 4 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of an intermediate substrate for a multichip module of the present invention.

5 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of an intermediate substrate for a multi-chip module of the present invention.

FIG. 6 is a longitudinal sectional view corresponding to FIG. 2, showing another embodiment of an intermediate substrate for a multi-chip module of the present invention.

FIG. 7 is a process chart illustrating an example of a method for manufacturing an intermediate substrate for a multichip module according to the present invention.

FIG. 8 is a process chart for explaining another example of the method of manufacturing an intermediate substrate for a multi-chip module according to the present invention.

[Explanation of symbols]

 1, 11, 21, 31 ... Intermediate substrate 2, 12, 22, 32 ... Base 3, 13, 23, 33 ... Electrical insulating layer 4, 14, 24, 34 ... Wiring 4a, 14a, 24a, 34a ... Chip side Pads 4b, 14b, 24b. 34b ... ball side pad 4c, 14c, 24c, 34c ... lead 15 ... electric insulating pattern 16 ... through hole 25 ... adhesive layer 36 ... circuit 4 ', 24' ... conductive thin film 4 ", 24" ... conductive pattern

Claims (8)

[Claims] An intermediate substrate for a face-down type multi-chip module on which a plurality of semiconductor chips are mounted, comprising: a base; and wiring formed on one surface of the base via an electrical insulating layer; The thermal expansion coefficient of the base is 10p
pm or less, and the wiring is a one-layer or two-layer wiring having a pitch in the range of 10 to 30 μm. 2. An electric insulating pattern according to claim 1, further comprising an electric insulating pattern covering a part of the wiring on the electric insulating layer and having a through hole for establishing conduction with the wiring. An intermediate substrate for a multichip module as described. 3. The intermediate substrate for a multi-chip module according to claim 1, further comprising a ground layer between the base and the electric insulating layer. 4. The intermediate substrate for a multi-chip module according to claim 1, further comprising an adhesive layer between the base and the electric insulating layer. 5. The intermediate substrate for a multi-chip module according to claim 4, further comprising a ground layer between said adhesive layer and said electric insulating layer. 6. The base has a desired circuit on the electric insulating layer side, and a desired portion of the wiring and the circuit are electrically connected to each other through a through hole provided in the electric insulating layer. The intermediate substrate for a multi-chip module according to claim 1 or 2, wherein: 7. The intermediate substrate for a multi-chip module according to claim 6, wherein a ground layer is provided in the electric insulating layer. 8. The intermediate substrate for a multi-chip module according to claim 1, wherein said base is made of silicon.