JP2002359284A - Signal line design method for scan test of semiconductor integrated circuit - Google Patents

Abstract

(57) [PROBLEMS] To reduce a hold time error caused by a short scan test signal line between registers without increasing the area of a semiconductor integrated circuit. SOLUTION: A scan test signal line is connected between registers, and a logic cell including the register is laid out.
Processing is performed so that the wiring length of the scan test signal line is the shortest as a result of the layout, the wiring delay time of the minimized scan test signal line is calculated, and the location where the hold time error occurs is specified. Then, the wiring is corrected so as to increase the wiring load on the specified scan test signal line, and the wiring delay time is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to an improvement in a wiring method of a scan test signal line for detecting a failure of a circuit using scan wiring.

[0002]

2. Description of the Related Art A scan test method, which is one method of inspecting a semiconductor integrated circuit, is such that a register having a scan input terminal is connected in an arbitrary order by a scan test signal line, and a logic is connected to the register in a predetermined order. This is a method for easily inspecting a semiconductor integrated circuit by applying a signal and comparing a logic result taken out from a signal output terminal with an input.

Conventional scan wiring methods include a method of connecting in alphabetical order of unique names added to registers in a logic circuit, and a method disclosed in, for example,
As disclosed in Japanese Patent Application Publication No. 96252, there are two methods of connecting by a method of minimizing scan wiring based on the register arrangement information after the cell arrangement step.

[0004] However, in the former method of connecting in alphabetical order of unique names added to registers, the distance between registers on a layout is not taken into account, and a signal used by a circuit for processing intended for the original purpose ( General signal)
Irrespective of this, the wiring path of the scan test signal line becomes complicated, and as a result, the area of the semiconductor integrated circuit may increase.

On the other hand, the method of minimizing the wiring of the scan test signal line based on the arrangement information of the register after the arrangement and wiring can avoid an increase in the area of the integrated circuit. Is not taken into account, and there is a possibility that a hold time error occurs due to reconnection so that the wiring between the registers becomes the shortest and a mislatch occurs.

[0006]

The conventional method of designing a signal line for a scan test of a semiconductor integrated circuit is configured as described above. There has been a problem that the register causes a hold time error due to the signal propagation time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor device capable of reducing the occurrence of a hold time error in a register without increasing the area of a semiconductor integrated circuit. An object of the present invention is to provide a method of designing a scan test signal line for an integrated circuit.

[0008]

According to a first aspect of the present invention, there is provided a method for designing a scan test signal line for a semiconductor integrated circuit, comprising the steps of: connecting a scan test signal line between registers; A cell arranging step of arranging a logic cell; a scan test wiring minimizing step of changing a connection order such that a wiring length of the scan test signal line is minimized after the logical cell arranging step; and a terminal of the logic cell. A wiring step for wiring between; a delay time calculating step for calculating a wiring delay time of the scan test signal line; and a wiring for correcting the wiring of the scan test signal line according to the result of the delay time calculating step. A correction process,
Is included.

Further, a method for designing a signal line for a scan test of a semiconductor integrated circuit according to a second aspect of the present invention is the first aspect.
In the method for designing a signal line for scan test of a semiconductor integrated circuit described above, the wiring correction step is performed by the delay time calculation step when there are two or more output terminals of a register to which the scan test signal line is connected. In consideration of the obtained delay information, the method includes a step of changing the output terminal of the register to which the scan test signal line is connected.

A third aspect of the present invention is a method for designing a scan test signal line for a semiconductor integrated circuit.
In the scan test signal line designing method described above, the wiring correction step is a step of changing the wiring of the scan test signal line to a wiring layer having a different resistance value in consideration of the delay information obtained in the delay time calculation step. Is included.

[0011]

Embodiment 1 Hereinafter, a method for designing a scan test signal line of a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a drawing describing a flowchart of a wiring method of a scan test signal line of a semiconductor integrated circuit according to the first embodiment. As shown in the drawing, a scan connection step 101 for connecting a scan test signal line between registers to a logic-designed circuit, a cell placement step 102 for placing a logic cell, and the scan test signal after the cell placement step. A scan wiring minimization step 103 for changing the connection order so that the wiring length of the line becomes the shortest, a wiring step 104 for wiring between the terminals of the logic cells, and a wiring delay time of the scan test signal line are calculated. It comprises a delay time calculation step 105 and a wiring correction step 106 for correcting the wiring of the scan test signal line.

Hereinafter, the above steps will be described in detail. FIG. 2 shows an example of a state where the scan connection in step 101 in FIG. 1 is completed. In FIG.
Reference numerals 204 denote registers, and a scan test signal line 205 connects the registers. In this state, the inter-register distance and the positional relationship on the layout are not taken into consideration, such as by connecting the unique names added to the registers in alphabetical order.

FIG. 3 shows the state of FIG.
2 is a diagram illustrating a state in which a logic cell is arranged by executing Step 2. Registers 301 to 304 in FIG. 3 correspond to the registers 201 to 204 in FIG. In the cell arranging step, the cell arrangement is performed so that the wiring of the general signal is optimized. Therefore, the wiring of the scan test signal line determined independently of the general signal is shown in FIG.
As in the order 301, 3
It can be seen that wiring such as 02, 303, and 304 results in a complicated wiring path, and the wiring length becomes long.

This state is shown in FIG.
The connection order is changed so that the wiring length between the registers becomes the shortest in the order of 01 to 303, 302, and 304. This step is Step 103.

Next, the wiring delay time of the wired scan test signal line is calculated. Since the wiring length between the registers of the scan test signal line is minimized in step 103, the wiring delay time has a small value. For this reason, the time required for the register to operate normally (hold time) cannot be held, and a mislatch occurs. Therefore, in order to hold the hold time, the wiring of the scan test signal line shown in step 106 of FIG. 1 is corrected.

FIG. 5 shows an example of connection of scan test signal lines between registers. As shown in the figure, the output pin Q of the register 501 is connected to the register 503 via the logic cell 502. On the other hand, the output pin Q of the register 501
The other output pin NQ is connected to a scan test signal line, and is connected to the input of the scan test signal line of the register 504 at the subsequent stage. At this time, as a result of calculating the wiring delay time in step 105 of FIG.
It is assumed that the wiring delay time of the wiring between the register 01 and the register 504 is too small, causing a hold time error in the register 504.

Here, the hold-dry error of the register will be described in detail. In FIG. 6, waveform CK is stored in register 5
This is the clock input to 04. A waveform NQ is an output waveform of the register 501, and a waveform SI is a scan test signal input to the register 504. In order to correctly latch data in response to a clock signal change, there must be no change in the data signal for a certain period of time (hold time). In this case, the periods in which the data signal changes occur overlap, and a sufficient hold time is not secured, and a hold time error occurs.

Here, when the wiring delay time is considered using a linear model as an example, the wiring delay time is expressed by the following equation: wiring delay time = wire resistance × (total pin capacitance + total wiring capacitance). Is done.

From this, it is understood that the wiring delay time of the scan test signal line can be increased by correcting the connection and increasing the capacitance. As an example, the pin capacitance of the register 504 is 1.5 [pF],
It is assumed that the pin capacitance of No. 1 is 3.5 [pF] and the wiring resistance from the register 501 to the register 504 is 0.1 [Ω]. Here, it is approximated that the wiring capacitance is as small as possible as compared with the pin capacitance. From the above equation 1, the wiring delay from the register 501 to the register 504 is 0.1
5 [psec]. Here, the scan test signal line connected from the output pin NQ of the register 501 to the register 504 is modified to be connected from the output pin Q of the register 501. Then, the pin capacitance of the register 501 affects the wiring delay time from the register 501 to the register 504.

The wiring delay time in this case is 0.45 [psec] according to the above equation 1, and the wiring delay time is increased by correcting the connection. FIG. 7 shows a connection example of a scan test signal line when the wiring is modified. By increasing the wiring delay time, the timing chart shows that, as shown in FIG.
The timing of the signal change of the scan test signal input to 04 changes, so that it is possible to prevent occurrence of a hold time error. The waveform Q in FIG.
1 shows the output waveform of FIG.

As described above, in addition to the method of changing the output terminal of the register to which the scan test signal line is connected, the scan test signal line may be changed to a wiring layer having a different resistance value. Similar effects can be obtained. FIG. 9 shows an example of sheet resistance and parallel plate capacitance of main materials used as a wiring layer of a semiconductor integrated circuit. Now, as an example,
A semiconductor integrated circuit has a two-layer wiring structure, in which one layer is made of aluminum (Al) and the other layer is made of polysilicon (PS). It is assumed that a hold time error as shown in FIG. 6 has occurred in a state where an Al layer is used as the wiring layer of the scan test signal line. At this time, by changing the wiring layer of the scan test signal line to PS, it is possible to prevent a hold time error from occurring due to an increase in capacitance. Here, the wiring length and the wiring width of the scan test signal line are 100
[Μm] and 1 [μm] are considered. The wiring delay time is obtained by the following equation. Wiring delay time = sheet resistance × wire length ÷ wiring width × parallel plate capacitance (Equation 2) From the value of FIG. It can be seen that the wiring delay time in the case of PS is 0.135 [psec]. Accordingly, by changing the wiring layer of the scan test signal line from Al to PS, the wiring delay time can be increased, and the occurrence of a hold time error can be prevented.

As described above, according to the present embodiment, the scan test signal line in which the hold time error has occurred is specified based on the delay time information obtained in the delay time calculation step, and the specified A wiring correction process is performed by changing the output terminal of the register to which the scan test signal line is connected to the location or changing the scan test signal line to a wiring layer having a different resistance value. Thus, the occurrence of the hold time error can be reduced by increasing the wiring resistance of the signal line with respect to the scan test signal line in which the hold time error has occurred and slowing down the signal propagation speed.

[0023]

As described above, according to the scan test signal line designing method according to the first aspect of the present invention, a scan test signal line connecting step of connecting a scan test signal line between registers, A cell arranging step of arranging cells; a scan test wiring minimizing step of changing a connection order such that a wiring length of the scan test signal line is minimized after the logical cell arranging step; Wiring, wiring delay of the scan test signal line, and wiring correction of the scan test signal line according to the result of the delay time calculation. The scan test signal in which a hold time error has occurred based on the delay time information obtained in the delay time calculation step By correcting the wiring of the scan test signal line at the specified location and increasing the wiring resistance of the signal line for the scan test signal line where a hold time error has occurred, The effect is obtained that the propagation speed is reduced and the occurrence of the hold time error can be reduced.

According to a second aspect of the present invention, in the method of designing a signal line for a scan test of a semiconductor integrated circuit according to the first aspect of the present invention, the step of correcting the wiring is performed by a scan test. When there are two or more output terminals of the register to which the signal line for connection is connected, the output terminal of the register to which the signal line for scan test is connected is changed in consideration of the delay information obtained in the delay time calculation step. Therefore, by correcting the connection to the output terminal with a large load capacitance to be driven and increasing the wiring resistance of the signal line for the scan test signal line in which the hold time error has occurred, This has the effect of reducing the signal propagation speed and reducing the occurrence of hold time errors.

According to a third aspect of the present invention, in the method of designing a scan test signal line according to the first aspect, the wiring correction step is performed by the delay time calculating step. In view of the obtained delay information, the method includes a step of changing the wiring of the scan test signal line to a wiring layer having a different resistance value. Therefore, it is specified that a hold time error has occurred in the delay time calculation step. The wiring layer used for the scan test signal line is made of a material with a different electrical resistance and a high electrical resistance value, and the wiring resistance is increased to reduce the signal propagation speed and reduce the hold time error. The effect of being able to reduce the occurrence of is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a flowchart of a method for designing a scan test signal line of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating an example of connection of a scan test signal line according to the first embodiment.

FIG. 3 is a diagram showing an example of a layout of a register to which a scan test signal line is connected in the first embodiment.

FIG. 4 is a diagram illustrating an example of a connection order of scan test signal lines that have been subjected to the wiring shorting process according to the first embodiment.

FIG. 5 is a diagram showing an example of connection of a scan test signal line between registers according to the first embodiment.

FIG. 6 is a diagram illustrating an example of a timing chart illustrating a situation in which a hold time error has occurred in a register.

FIG. 7 is a diagram showing an example of connection of a scan test signal line between registers after a wiring correction step in the first embodiment.

FIG. 8 is a diagram illustrating an example of a timing chart after a wiring correction step in the first embodiment.

FIG. 9 is a diagram showing an example of sheet resistance and parallel plate capacitance of main materials used as a wiring layer of a semiconductor integrated circuit.

[Explanation of symbols]

 201 to 204 register 205 scan test signal line 301 to 304 register 501 scan test signal line output side register 502 logic cell 503 register 504 scan test signal line input side register

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kenji Yokoyama 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F term (reference) 2G132 AA00 AB02 AC11 AC14 AD07 AK26 AK27 AL11 5F038 CA03 CD05 CD09 CD12 CD13 CD15 CD18 DT06 DT10 DT15 EZ20 5F064 BB31 DD25 DD39 EE03 EE08 EE22 EE33 EE36 EE42 EE43 EE47 FF05

Claims (3)

[Claims] A scan test signal line connecting step of connecting a scan test signal line between registers; a cell arranging step of arranging a logic cell; and a wiring length of the scan test signal line after the logical cell arranging step. A scan test wiring minimizing step of changing the connection order so as to make the shortest, a wiring step of wiring between terminals of the logic cell, and a delay time calculating step of calculating a wiring delay time of the scan test signal line And a wiring correction step of correcting the wiring of the scan test signal line according to the result of the delay time calculation step. A method of designing a scan test signal line for a semiconductor integrated circuit, the method comprising: 2. The method for designing a signal line for scan test of a semiconductor integrated circuit according to claim 1, wherein the wiring correction step is performed when there are two or more output terminals of a register to which the scan test signal line is connected. ,
A method of designing a scan test signal line for a semiconductor integrated circuit, comprising: changing an output terminal of the register connected to the scan test signal line in consideration of the delay information obtained in the delay time calculation step. . 3. The scan test signal line design method according to claim 1, wherein said wiring correction step includes setting a resistance value of the scan test signal line wiring to a resistance value in view of delay information obtained in said delay time calculation step. A signal line for scan test of a semiconductor integrated circuit, which includes a step of changing to a different wiring layer.